Lines Matching +full:0 +full:x2e00
43 if (max_carrier > 0x4000) in stv0900_check_signal_presence()
44 max_carrier = 0x4000; in stv0900_check_signal_presence()
46 if ((agc2_integr > 0x2000) in stv0900_check_signal_presence()
71 if (max_carrier > 0x4000) in stv0900_get_sw_loop_params()
72 max_carrier = 0x4000; in stv0900_get_sw_loop_params()
97 if ((freq_inc > max_carrier) || (freq_inc < 0)) in stv0900_get_sw_loop_params()
102 if (srate > 0) in stv0900_get_sw_loop_params()
105 if ((timeout > 100) || (timeout < 0)) in stv0900_get_sw_loop_params()
110 if ((max_steps > 100) || (max_steps < 0)) { in stv0900_get_sw_loop_params()
137 if (max_carrier > 0x4000) in stv0900_search_carr_sw_loop()
138 max_carrier = 0x4000; in stv0900_search_carr_sw_loop()
141 freqOffset = 0; in stv0900_search_carr_sw_loop()
145 stepCpt = 0; in stv0900_search_carr_sw_loop()
148 stv0900_write_reg(intp, DMDISTATE, 0x1c); in stv0900_search_carr_sw_loop()
149 stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff); in stv0900_search_carr_sw_loop()
150 stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff); in stv0900_search_carr_sw_loop()
151 stv0900_write_reg(intp, DMDISTATE, 0x18); in stv0900_search_carr_sw_loop()
154 if (intp->chip_id == 0x12) { in stv0900_search_carr_sw_loop()
156 stv0900_write_bits(intp, RST_HWARE, 0); in stv0900_search_carr_sw_loop()
160 if (freqOffset >= 0) in stv0900_search_carr_sw_loop()
177 stv0900_write_bits(intp, ALGOSWRST, 0); in stv0900_search_carr_sw_loop()
199 if (intp->chip_id >= 0x20) in stv0900_sw_algo()
200 stv0900_write_reg(intp, CARFREQ, 0x3b); in stv0900_sw_algo()
202 stv0900_write_reg(intp, CARFREQ, 0xef); in stv0900_sw_algo()
204 stv0900_write_reg(intp, DMDCFGMD, 0x49); in stv0900_sw_algo()
208 if (intp->chip_id >= 0x20) in stv0900_sw_algo()
209 stv0900_write_reg(intp, CORRELABS, 0x79); in stv0900_sw_algo()
211 stv0900_write_reg(intp, CORRELABS, 0x68); in stv0900_sw_algo()
213 stv0900_write_reg(intp, DMDCFGMD, 0x89); in stv0900_sw_algo()
219 if (intp->chip_id >= 0x20) { in stv0900_sw_algo()
220 stv0900_write_reg(intp, CARFREQ, 0x3b); in stv0900_sw_algo()
221 stv0900_write_reg(intp, CORRELABS, 0x79); in stv0900_sw_algo()
223 stv0900_write_reg(intp, CARFREQ, 0xef); in stv0900_sw_algo()
224 stv0900_write_reg(intp, CORRELABS, 0x68); in stv0900_sw_algo()
227 stv0900_write_reg(intp, DMDCFGMD, 0xc9); in stv0900_sw_algo()
232 trial_cntr = 0; in stv0900_sw_algo()
246 if (intp->chip_id >= 0x20) { in stv0900_sw_algo()
247 stv0900_write_reg(intp, CARFREQ, 0x49); in stv0900_sw_algo()
248 stv0900_write_reg(intp, CORRELABS, 0x9e); in stv0900_sw_algo()
250 stv0900_write_reg(intp, CARFREQ, 0xed); in stv0900_sw_algo()
251 stv0900_write_reg(intp, CORRELABS, 0x88); in stv0900_sw_algo()
260 if (s2fw < 0xd) { in stv0900_sw_algo()
266 if (s2fw < 0xd) { in stv0900_sw_algo()
270 if (intp->chip_id >= 0x20) in stv0900_sw_algo()
273 0x79); in stv0900_sw_algo()
277 0x68); in stv0900_sw_algo()
281 0x89); in stv0900_sw_algo()
304 dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n", in stv0900_get_symbol_rate()
313 rem1 = (mclk) % 0x10000; in stv0900_get_symbol_rate()
314 rem2 = (srate) % 0x10000; in stv0900_get_symbol_rate()
342 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f); in stv0900_set_symbol_rate()
343 stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff)); in stv0900_set_symbol_rate()
365 if (symb < 0x7fff) { in stv0900_set_max_symbol_rate()
366 stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f); in stv0900_set_max_symbol_rate()
367 stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff)); in stv0900_set_max_symbol_rate()
369 stv0900_write_reg(intp, SFRUP1, 0x7f); in stv0900_set_max_symbol_rate()
370 stv0900_write_reg(intp, SFRUP1 + 1, 0xff); in stv0900_set_max_symbol_rate()
394 stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff); in stv0900_set_min_symbol_rate()
395 stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff)); in stv0900_set_min_symbol_rate()
412 if (timingoffset == 0) in stv0900_get_timing_offst()
415 timingoffset = ((s32)srate * 10) / ((s32)0x1000000 / timingoffset); in stv0900_get_timing_offst()
426 if (intp->chip_id == 0x10) { in stv0900_set_dvbs2_rolloff()
428 rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03; in stv0900_set_dvbs2_rolloff()
430 } else if (intp->chip_id <= 0x20) in stv0900_set_dvbs2_rolloff()
431 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0); in stv0900_set_dvbs2_rolloff()
433 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0); in stv0900_set_dvbs2_rolloff()
461 timingcpt = 0; in stv0900_check_timing_lock()
469 stv0900_write_reg(intp, TMGTHRISE, 0x20); in stv0900_check_timing_lock()
470 stv0900_write_reg(intp, TMGTHFALL, 0x0); in stv0900_check_timing_lock()
471 stv0900_write_bits(intp, CFR_AUTOSCAN, 0); in stv0900_check_timing_lock()
472 stv0900_write_reg(intp, RTC, 0x80); in stv0900_check_timing_lock()
473 stv0900_write_reg(intp, RTCS2, 0x40); in stv0900_check_timing_lock()
474 stv0900_write_reg(intp, CARFREQ, 0x0); in stv0900_check_timing_lock()
475 stv0900_write_reg(intp, CFRINIT1, 0x0); in stv0900_check_timing_lock()
476 stv0900_write_reg(intp, CFRINIT0, 0x0); in stv0900_check_timing_lock()
477 stv0900_write_reg(intp, AGC2REF, 0x65); in stv0900_check_timing_lock()
478 stv0900_write_reg(intp, DMDISTATE, 0x18); in stv0900_check_timing_lock()
481 for (i = 0; i < 10; i++) { in stv0900_check_timing_lock()
491 stv0900_write_reg(intp, AGC2REF, 0x38); in stv0900_check_timing_lock()
492 stv0900_write_reg(intp, RTC, 0x88); in stv0900_check_timing_lock()
493 stv0900_write_reg(intp, RTCS2, 0x68); in stv0900_check_timing_lock()
535 stv0900_write_reg(intp, DMDISTATE, 0x1f); in stv0900_get_demod_cold_lock()
536 stv0900_write_reg(intp, DMDISTATE, 0x15); in stv0900_get_demod_cold_lock()
544 if (intp->chip_id <= 0x20) { in stv0900_get_demod_cold_lock()
570 if ((nb_steps % 2) != 0) in stv0900_get_demod_cold_lock()
573 if (nb_steps <= 0) in stv0900_get_demod_cold_lock()
581 if (intp->chip_id <= 0x20) { in stv0900_get_demod_cold_lock()
586 tuner_freq = 0; in stv0900_get_demod_cold_lock()
589 if (direction > 0) in stv0900_get_demod_cold_lock()
594 if (intp->chip_id <= 0x20) { in stv0900_get_demod_cold_lock()
601 stv0900_write_reg(intp, DMDISTATE, 0x1c); in stv0900_get_demod_cold_lock()
602 stv0900_write_reg(intp, CFRINIT1, 0); in stv0900_get_demod_cold_lock()
603 stv0900_write_reg(intp, CFRINIT0, 0); in stv0900_get_demod_cold_lock()
604 stv0900_write_reg(intp, DMDISTATE, 0x1f); in stv0900_get_demod_cold_lock()
605 stv0900_write_reg(intp, DMDISTATE, 0x15); in stv0900_get_demod_cold_lock()
607 stv0900_write_reg(intp, DMDISTATE, 0x1c); in stv0900_get_demod_cold_lock()
611 stv0900_write_reg(intp, DMDISTATE, 0x1f); in stv0900_get_demod_cold_lock()
612 stv0900_write_reg(intp, DMDISTATE, 0x05); in stv0900_get_demod_cold_lock()
680 stv0900_write_reg(intp, vth_reg++, 0xd0); in stv0900_set_viterbi_tracq()
681 stv0900_write_reg(intp, vth_reg++, 0x7d); in stv0900_set_viterbi_tracq()
682 stv0900_write_reg(intp, vth_reg++, 0x53); in stv0900_set_viterbi_tracq()
683 stv0900_write_reg(intp, vth_reg++, 0x2f); in stv0900_set_viterbi_tracq()
684 stv0900_write_reg(intp, vth_reg++, 0x24); in stv0900_set_viterbi_tracq()
685 stv0900_write_reg(intp, vth_reg++, 0x1f); in stv0900_set_viterbi_tracq()
698 stv0900_write_reg(intp, FECM, 0x10); in stv0900_set_viterbi_standard()
699 stv0900_write_reg(intp, PRVIT, 0x3f); in stv0900_set_viterbi_standard()
703 stv0900_write_reg(intp, FECM, 0x00); in stv0900_set_viterbi_standard()
707 stv0900_write_reg(intp, PRVIT, 0x2f); in stv0900_set_viterbi_standard()
710 stv0900_write_reg(intp, PRVIT, 0x01); in stv0900_set_viterbi_standard()
713 stv0900_write_reg(intp, PRVIT, 0x02); in stv0900_set_viterbi_standard()
716 stv0900_write_reg(intp, PRVIT, 0x04); in stv0900_set_viterbi_standard()
719 stv0900_write_reg(intp, PRVIT, 0x08); in stv0900_set_viterbi_standard()
722 stv0900_write_reg(intp, PRVIT, 0x20); in stv0900_set_viterbi_standard()
729 stv0900_write_reg(intp, FECM, 0x80); in stv0900_set_viterbi_standard()
733 stv0900_write_reg(intp, PRVIT, 0x13); in stv0900_set_viterbi_standard()
736 stv0900_write_reg(intp, PRVIT, 0x01); in stv0900_set_viterbi_standard()
739 stv0900_write_reg(intp, PRVIT, 0x02); in stv0900_set_viterbi_standard()
742 stv0900_write_reg(intp, PRVIT, 0x10); in stv0900_set_viterbi_standard()
788 if (intp->chip_id >= 0x30) { in stv0900_set_dvbs1_track_car_loop()
790 stv0900_write_reg(intp, ACLC, 0x2b); in stv0900_set_dvbs1_track_car_loop()
791 stv0900_write_reg(intp, BCLC, 0x1a); in stv0900_set_dvbs1_track_car_loop()
793 stv0900_write_reg(intp, ACLC, 0x0c); in stv0900_set_dvbs1_track_car_loop()
794 stv0900_write_reg(intp, BCLC, 0x1b); in stv0900_set_dvbs1_track_car_loop()
796 stv0900_write_reg(intp, ACLC, 0x2c); in stv0900_set_dvbs1_track_car_loop()
797 stv0900_write_reg(intp, BCLC, 0x1c); in stv0900_set_dvbs1_track_car_loop()
801 stv0900_write_reg(intp, ACLC, 0x1a); in stv0900_set_dvbs1_track_car_loop()
802 stv0900_write_reg(intp, BCLC, 0x09); in stv0900_set_dvbs1_track_car_loop()
818 i = 0, in stv0900_track_optimization()
821 blind_tun_sw = 0, in stv0900_track_optimization()
837 stv0900_write_bits(intp, DVBS2_ENABLE, 0); in stv0900_track_optimization()
843 if (intp->chip_id < 0x30) { in stv0900_track_optimization()
844 stv0900_write_reg(intp, ERRCTRL1, 0x75); in stv0900_track_optimization()
849 stv0900_write_reg(intp, GAUSSR0, 0x98); in stv0900_track_optimization()
850 stv0900_write_reg(intp, CCIR0, 0x18); in stv0900_track_optimization()
852 stv0900_write_reg(intp, GAUSSR0, 0x18); in stv0900_track_optimization()
853 stv0900_write_reg(intp, CCIR0, 0x18); in stv0900_track_optimization()
856 stv0900_write_reg(intp, ERRCTRL1, 0x75); in stv0900_track_optimization()
860 stv0900_write_bits(intp, DVBS1_ENABLE, 0); in stv0900_track_optimization()
862 stv0900_write_reg(intp, ACLC, 0); in stv0900_track_optimization()
863 stv0900_write_reg(intp, BCLC, 0); in stv0900_track_optimization()
866 pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01; in stv0900_track_optimization()
874 stv0900_write_reg(intp, ACLC2S2Q, 0x2a); in stv0900_track_optimization()
881 stv0900_write_reg(intp, ACLC2S2Q, 0x2a); in stv0900_track_optimization()
885 stv0900_write_reg(intp, ACLC2S2Q, 0x2a); in stv0900_track_optimization()
898 stv0900_write_reg(intp, ACLC2S2Q, 0x2a); in stv0900_track_optimization()
901 stv0900_write_reg(intp, ACLC2S2Q, 0x2a); in stv0900_track_optimization()
904 stv0900_write_reg(intp, ACLC2S2Q, 0x2a); in stv0900_track_optimization()
910 if (intp->chip_id <= 0x11) { in stv0900_track_optimization()
916 stv0900_write_reg(intp, ERRCTRL1, 0x67); in stv0900_track_optimization()
929 stv0900_write_reg(intp, SFRSTEP, 0x00); in stv0900_track_optimization()
930 stv0900_write_bits(intp, SCAN_ENABLE, 0); in stv0900_track_optimization()
931 stv0900_write_bits(intp, CFR_AUTOSCAN, 0); in stv0900_track_optimization()
932 stv0900_write_reg(intp, TMGCFG2, 0xc1); in stv0900_track_optimization()
940 if (intp->chip_id >= 0x20) { in stv0900_track_optimization()
946 stv0900_write_reg(intp, VAVSRVIT, 0x0a); in stv0900_track_optimization()
947 stv0900_write_reg(intp, VITSCALE, 0x0); in stv0900_track_optimization()
951 if (intp->chip_id < 0x20) in stv0900_track_optimization()
952 stv0900_write_reg(intp, CARHDR, 0x08); in stv0900_track_optimization()
954 if (intp->chip_id == 0x10) in stv0900_track_optimization()
955 stv0900_write_reg(intp, CORRELEXP, 0x0a); in stv0900_track_optimization()
957 stv0900_write_reg(intp, AGC2REF, 0x38); in stv0900_track_optimization()
959 if ((intp->chip_id >= 0x20) || in stv0900_track_optimization()
967 if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) { in stv0900_track_optimization()
990 stv0900_write_reg(intp, DMDISTATE, 0x1f); in stv0900_track_optimization()
993 stv0900_write_reg(intp, DMDISTATE, 0x18); in stv0900_track_optimization()
994 i = 0; in stv0900_track_optimization()
999 stv0900_write_reg(intp, DMDISTATE, 0x1f); in stv0900_track_optimization()
1002 stv0900_write_reg(intp, DMDISTATE, 0x18); in stv0900_track_optimization()
1009 if (intp->chip_id >= 0x20) in stv0900_track_optimization()
1010 stv0900_write_reg(intp, CARFREQ, 0x49); in stv0900_track_optimization()
1021 s32 timer = 0, lock = 0; in stv0900_get_fec_lock()
1029 while ((timer < time_out) && (lock == 0)) { in stv0900_get_fec_lock()
1034 lock = 0; in stv0900_get_fec_lock()
1044 if (lock == 0) { in stv0900_get_fec_lock()
1063 s32 timer = 0, lock = 0; in stv0900_wait_for_lock()
1073 lock = 0; in stv0900_wait_for_lock()
1078 while ((timer < fec_timeout) && (lock == 0)) { in stv0900_wait_for_lock()
1141 rem1 = mclk % 0x1000; in stv0900_get_carr_freq()
1142 rem2 = derot % 0x1000; in stv0900_get_carr_freq()
1154 u32 freq = 0; in stv0900_get_tuner_freq()
1160 if ((tuner_ops->get_frequency(fe, &freq)) < 0) in stv0900_get_tuner_freq()
1180 int i = 0, in stv0900_get_signal_params()
1188 i = 0; in stv0900_get_signal_params()
1189 stv0900_write_reg(intp, SFRSTEP, 0x5c); in stv0900_get_signal_params()
1191 while ((i <= 50) && (timing != 0) && (timing != 0xff)) { in stv0900_get_signal_params()
1211 result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01; in stv0900_get_signal_params()
1215 dprintk("%s: modcode=0x%x \n", __func__, result->modcode); in stv0900_get_signal_params()
1289 stv0900_write_bits(intp, CFR_AUTOSCAN, 0); in stv0900_dvbs1_acq_workaround()
1292 stv0900_write_reg(intp, DMDISTATE, 0x1c); in stv0900_dvbs1_acq_workaround()
1295 stv0900_write_reg(intp, DMDISTATE, 0x18); in stv0900_dvbs1_acq_workaround()
1304 stv0900_write_reg(intp, DMDISTATE, 0x1c); in stv0900_dvbs1_acq_workaround()
1307 stv0900_write_reg(intp, DMDISTATE, 0x18); in stv0900_dvbs1_acq_workaround()
1326 u32 minagc2level = 0xffff, in stv0900_blind_check_agc2_min_level()
1334 stv0900_write_reg(intp, AGC2REF, 0x38); in stv0900_blind_check_agc2_min_level()
1335 stv0900_write_bits(intp, SCAN_ENABLE, 0); in stv0900_blind_check_agc2_min_level()
1336 stv0900_write_bits(intp, CFR_AUTOSCAN, 0); in stv0900_blind_check_agc2_min_level()
1341 stv0900_write_reg(intp, DMDT0M, 0x0); in stv0900_blind_check_agc2_min_level()
1348 if (nb_steps < 0) in stv0900_blind_check_agc2_min_level()
1355 init_freq = 0; in stv0900_blind_check_agc2_min_level()
1357 for (i = 0; i < nb_steps; i++) { in stv0900_blind_check_agc2_min_level()
1358 if (direction > 0) in stv0900_blind_check_agc2_min_level()
1364 stv0900_write_reg(intp, DMDISTATE, 0x5C); in stv0900_blind_check_agc2_min_level()
1365 stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff); in stv0900_blind_check_agc2_min_level()
1366 stv0900_write_reg(intp, CFRINIT0, init_freq & 0xff); in stv0900_blind_check_agc2_min_level()
1367 stv0900_write_reg(intp, DMDISTATE, 0x58); in stv0900_blind_check_agc2_min_level()
1369 agc2level = 0; in stv0900_blind_check_agc2_min_level()
1371 for (j = 0; j < 10; j++) in stv0900_blind_check_agc2_min_level()
1391 s32 i, timingcpt = 0, in stv0900_search_srate_coarse()
1394 current_step = 0, in stv0900_search_srate_coarse()
1397 coarse_srate = 0, in stv0900_search_srate_coarse()
1398 agc2_integr = 0, in stv0900_search_srate_coarse()
1401 if (intp->chip_id >= 0x30) in stv0900_search_srate_coarse()
1402 agc2_th = 0x2e00; in stv0900_search_srate_coarse()
1404 agc2_th = 0x1f00; in stv0900_search_srate_coarse()
1406 stv0900_write_bits(intp, DEMOD_MODE, 0x1f); in stv0900_search_srate_coarse()
1407 stv0900_write_reg(intp, TMGCFG, 0x12); in stv0900_search_srate_coarse()
1408 stv0900_write_reg(intp, TMGTHRISE, 0xf0); in stv0900_search_srate_coarse()
1409 stv0900_write_reg(intp, TMGTHFALL, 0xe0); in stv0900_search_srate_coarse()
1412 stv0900_write_reg(intp, SFRUP1, 0x83); in stv0900_search_srate_coarse()
1413 stv0900_write_reg(intp, SFRUP0, 0xc0); in stv0900_search_srate_coarse()
1414 stv0900_write_reg(intp, SFRLOW1, 0x82); in stv0900_search_srate_coarse()
1415 stv0900_write_reg(intp, SFRLOW0, 0xa0); in stv0900_search_srate_coarse()
1416 stv0900_write_reg(intp, DMDT0M, 0x0); in stv0900_search_srate_coarse()
1417 stv0900_write_reg(intp, AGC2REF, 0x50); in stv0900_search_srate_coarse()
1419 if (intp->chip_id >= 0x30) { in stv0900_search_srate_coarse()
1420 stv0900_write_reg(intp, CARFREQ, 0x99); in stv0900_search_srate_coarse()
1421 stv0900_write_reg(intp, SFRSTEP, 0x98); in stv0900_search_srate_coarse()
1422 } else if (intp->chip_id >= 0x20) { in stv0900_search_srate_coarse()
1423 stv0900_write_reg(intp, CARFREQ, 0x6a); in stv0900_search_srate_coarse()
1424 stv0900_write_reg(intp, SFRSTEP, 0x95); in stv0900_search_srate_coarse()
1426 stv0900_write_reg(intp, CARFREQ, 0xed); in stv0900_search_srate_coarse()
1427 stv0900_write_reg(intp, SFRSTEP, 0x73); in stv0900_search_srate_coarse()
1443 if (nb_steps < 0) in stv0900_search_srate_coarse()
1450 current_step = 0; in stv0900_search_srate_coarse()
1456 stv0900_write_reg(intp, DMDISTATE, 0x5f); in stv0900_search_srate_coarse()
1457 stv0900_write_bits(intp, DEMOD_MODE, 0); in stv0900_search_srate_coarse()
1461 for (i = 0; i < 10; i++) { in stv0900_search_srate_coarse()
1474 …dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started. tuner freq=%d agc2=0x%x srate_coarse=%d tm… in stv0900_search_srate_coarse()
1483 if (direction > 0) in stv0900_search_srate_coarse()
1498 coarse_srate = 0; in stv0900_search_srate_coarse()
1548 coarse_srate = 0; in stv0900_search_srate_fine()
1550 stv0900_write_reg(intp, DMDISTATE, 0x1f); in stv0900_search_srate_fine()
1551 stv0900_write_reg(intp, TMGCFG2, 0xc1); in stv0900_search_srate_fine()
1552 stv0900_write_reg(intp, TMGTHRISE, 0x20); in stv0900_search_srate_fine()
1553 stv0900_write_reg(intp, TMGTHFALL, 0x00); in stv0900_search_srate_fine()
1554 stv0900_write_reg(intp, TMGCFG, 0xd2); in stv0900_search_srate_fine()
1555 stv0900_write_bits(intp, CFR_AUTOSCAN, 0); in stv0900_search_srate_fine()
1556 stv0900_write_reg(intp, AGC2REF, 0x38); in stv0900_search_srate_fine()
1558 if (intp->chip_id >= 0x30) in stv0900_search_srate_fine()
1559 stv0900_write_reg(intp, CARFREQ, 0x79); in stv0900_search_srate_fine()
1560 else if (intp->chip_id >= 0x20) in stv0900_search_srate_fine()
1561 stv0900_write_reg(intp, CARFREQ, 0x49); in stv0900_search_srate_fine()
1563 stv0900_write_reg(intp, CARFREQ, 0xed); in stv0900_search_srate_fine()
1565 stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f); in stv0900_search_srate_fine()
1566 stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff)); in stv0900_search_srate_fine()
1568 stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f); in stv0900_search_srate_fine()
1569 stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff)); in stv0900_search_srate_fine()
1571 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff); in stv0900_search_srate_fine()
1572 stv0900_write_reg(intp, SFRINIT0, (symb & 0xff)); in stv0900_search_srate_fine()
1574 stv0900_write_reg(intp, DMDT0M, 0x20); in stv0900_search_srate_fine()
1575 stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff); in stv0900_search_srate_fine()
1576 stv0900_write_reg(intp, CFRINIT0, coarse_freq & 0xff); in stv0900_search_srate_fine()
1577 stv0900_write_reg(intp, DMDISTATE, 0x15); in stv0900_search_srate_fine()
1605 if (intp->chip_id < 0x20) { in stv0900_blind_search_algo()
1613 if (intp->chip_id <= 0x20) in stv0900_blind_search_algo()
1624 if (intp->chip_id == 0x10) in stv0900_blind_search_algo()
1625 stv0900_write_reg(intp, CORRELEXP, 0xaa); in stv0900_blind_search_algo()
1627 if (intp->chip_id < 0x20) in stv0900_blind_search_algo()
1628 stv0900_write_reg(intp, CARHDR, 0x55); in stv0900_blind_search_algo()
1630 stv0900_write_reg(intp, CARHDR, 0x20); in stv0900_blind_search_algo()
1632 if (intp->chip_id <= 0x20) in stv0900_blind_search_algo()
1633 stv0900_write_reg(intp, CARCFG, 0xc4); in stv0900_blind_search_algo()
1635 stv0900_write_reg(intp, CARCFG, 0x6); in stv0900_blind_search_algo()
1637 stv0900_write_reg(intp, RTCS2, 0x44); in stv0900_blind_search_algo()
1639 if (intp->chip_id >= 0x20) { in stv0900_blind_search_algo()
1640 stv0900_write_reg(intp, EQUALCFG, 0x41); in stv0900_blind_search_algo()
1641 stv0900_write_reg(intp, FFECFG, 0x41); in stv0900_blind_search_algo()
1642 stv0900_write_reg(intp, VITSCALE, 0x82); in stv0900_blind_search_algo()
1643 stv0900_write_reg(intp, VAVSRVIT, 0x0); in stv0900_blind_search_algo()
1650 if (stv0900_search_srate_coarse(fe) != 0) { in stv0900_blind_search_algo()
1653 if (coarse_srate != 0) { in stv0900_blind_search_algo()
1664 fail_cpt = 0; in stv0900_blind_search_algo()
1665 agc2_overflow = 0; in stv0900_blind_search_algo()
1667 for (i = 0; i < 10; i++) { in stv0900_blind_search_algo()
1671 if (agc2_int >= 0xff00) in stv0900_blind_search_algo()
1676 if (((dstatus2 & 0x1) == 0x1) && in stv0900_blind_search_algo()
1701 stv0900_write_reg(intp, vth_reg++, 0x96); in stv0900_set_viterbi_acq()
1702 stv0900_write_reg(intp, vth_reg++, 0x64); in stv0900_set_viterbi_acq()
1703 stv0900_write_reg(intp, vth_reg++, 0x36); in stv0900_set_viterbi_acq()
1704 stv0900_write_reg(intp, vth_reg++, 0x23); in stv0900_set_viterbi_acq()
1705 stv0900_write_reg(intp, vth_reg++, 0x1e); in stv0900_set_viterbi_acq()
1706 stv0900_write_reg(intp, vth_reg++, 0x19); in stv0900_set_viterbi_acq()
1735 stv0900_write_bits(intp, DVBS2_ENABLE, 0); in stv0900_set_search_standard()
1736 stv0900_write_bits(intp, STOP_CLKVIT, 0); in stv0900_set_search_standard()
1740 stv0900_write_reg(intp, CAR2CFG, 0x22); in stv0900_set_search_standard()
1749 stv0900_write_bits(intp, DVBS1_ENABLE, 0); in stv0900_set_search_standard()
1752 stv0900_write_reg(intp, ACLC, 0x1a); in stv0900_set_search_standard()
1753 stv0900_write_reg(intp, BCLC, 0x09); in stv0900_set_search_standard()
1754 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/ in stv0900_set_search_standard()
1755 stv0900_write_reg(intp, CAR2CFG, 0x26); in stv0900_set_search_standard()
1757 stv0900_write_reg(intp, CAR2CFG, 0x66); in stv0900_set_search_standard()
1760 if (intp->chip_id <= 0x11) in stv0900_set_search_standard()
1775 stv0900_write_bits(intp, STOP_CLKVIT, 0); in stv0900_set_search_standard()
1776 stv0900_write_reg(intp, ACLC, 0x1a); in stv0900_set_search_standard()
1777 stv0900_write_reg(intp, BCLC, 0x09); in stv0900_set_search_standard()
1781 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/ in stv0900_set_search_standard()
1782 stv0900_write_reg(intp, CAR2CFG, 0x26); in stv0900_set_search_standard()
1784 stv0900_write_reg(intp, CAR2CFG, 0x66); in stv0900_set_search_standard()
1787 if (intp->chip_id <= 0x11) in stv0900_set_search_standard()
1823 stv0900_write_reg(intp, DMDISTATE, 0x5c); in stv0900_algo()
1824 if (intp->chip_id >= 0x20) { in stv0900_algo()
1826 stv0900_write_reg(intp, CORRELABS, 0x9e); in stv0900_algo()
1828 stv0900_write_reg(intp, CORRELABS, 0x82); in stv0900_algo()
1830 stv0900_write_reg(intp, CORRELABS, 0x88); in stv0900_algo()
1839 stv0900_write_reg(intp, TMGCFG2, 0xc0); in stv0900_algo()
1840 stv0900_write_reg(intp, CORRELMANT, 0x70); in stv0900_algo()
1844 stv0900_write_reg(intp, DMDT0M, 0x20); in stv0900_algo()
1845 stv0900_write_reg(intp, TMGCFG, 0xd2); in stv0900_algo()
1848 stv0900_write_reg(intp, CORRELMANT, 0x63); in stv0900_algo()
1850 stv0900_write_reg(intp, CORRELMANT, 0x70); in stv0900_algo()
1852 stv0900_write_reg(intp, AGC2REF, 0x38); in stv0900_algo()
1857 if (intp->chip_id >= 0x20) { in stv0900_algo()
1858 stv0900_write_reg(intp, KREFTMG, 0x5a); in stv0900_algo()
1868 stv0900_write_reg(intp, KREFTMG, 0xc1); in stv0900_algo()
1874 stv0900_write_reg(intp, TMGCFG2, 0xc1); in stv0900_algo()
1898 aq_power = 0; in stv0900_algo()
1900 if (agc1_power == 0) { in stv0900_algo()
1901 for (i = 0; i < 5; i++) in stv0900_algo()
1908 if ((agc1_power == 0) && (aq_power < IQPOWER_THRESHOLD)) { in stv0900_algo()
1915 if (intp->chip_id <= 0x20) /*cut 2.0*/ in stv0900_algo()
1929 if (intp->chip_id == 0x12) { in stv0900_algo()
1930 stv0900_write_bits(intp, RST_HWARE, 0); in stv0900_algo()
1933 stv0900_write_bits(intp, RST_HWARE, 0); in stv0900_algo()
1955 if (intp->chip_id <= 0x11) { in stv0900_algo()
1956 if ((stv0900_get_standard(fe, 0) == in stv0900_algo()
1961 stv0900_write_bits(intp, RST_HWARE, 0); in stv0900_algo()
1963 stv0900_write_bits(intp, RST_HWARE, 0); in stv0900_algo()
1966 stv0900_write_bits(intp, RST_HWARE, 0); in stv0900_algo()
1969 } else if (intp->chip_id >= 0x20) { in stv0900_algo()
1970 stv0900_write_bits(intp, RST_HWARE, 0); in stv0900_algo()
1973 stv0900_write_bits(intp, RST_HWARE, 0); in stv0900_algo()
1984 stv0900_write_bits(intp, RESET_UPKO_COUNT, 0); in stv0900_algo()
1985 stv0900_write_reg(intp, ERRCTRL1, 0x67); in stv0900_algo()
1987 stv0900_write_reg(intp, ERRCTRL1, 0x75); in stv0900_algo()
1990 stv0900_write_reg(intp, FBERCPT4, 0); in stv0900_algo()
1991 stv0900_write_reg(intp, ERRCTRL2, 0xc1); in stv0900_algo()
2004 if (intp->chip_id > 0x11) { in stv0900_algo()