1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * (C) 2018 MediaTek Inc. 4 * Copyright (C) 2022 BayLibre SAS 5 * Authors: Fabien Parent <fparent@baylibre.com> 6 * Bernhard Rosenkränzer <bero@baylibre.com> 7 * Alexandre Mergnat <amergnat@baylibre.com> 8 */ 9 10#include <dt-bindings/clock/mediatek,mt8365-clk.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/power/mediatek,mt8365-power.h> 15 16/ { 17 compatible = "mediatek,mt8365"; 18 interrupt-parent = <&sysirq>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cluster0_opp: opp-table-0 { 27 compatible = "operating-points-v2"; 28 opp-shared; 29 30 opp-850000000 { 31 opp-hz = /bits/ 64 <850000000>; 32 opp-microvolt = <650000>; 33 }; 34 35 opp-918000000 { 36 opp-hz = /bits/ 64 <918000000>; 37 opp-microvolt = <668750>; 38 }; 39 40 opp-987000000 { 41 opp-hz = /bits/ 64 <987000000>; 42 opp-microvolt = <687500>; 43 }; 44 45 opp-1056000000 { 46 opp-hz = /bits/ 64 <1056000000>; 47 opp-microvolt = <706250>; 48 }; 49 50 opp-1125000000 { 51 opp-hz = /bits/ 64 <1125000000>; 52 opp-microvolt = <725000>; 53 }; 54 55 opp-1216000000 { 56 opp-hz = /bits/ 64 <1216000000>; 57 opp-microvolt = <750000>; 58 }; 59 60 opp-1308000000 { 61 opp-hz = /bits/ 64 <1308000000>; 62 opp-microvolt = <775000>; 63 }; 64 65 opp-1400000000 { 66 opp-hz = /bits/ 64 <1400000000>; 67 opp-microvolt = <800000>; 68 }; 69 70 opp-1466000000 { 71 opp-hz = /bits/ 64 <1466000000>; 72 opp-microvolt = <825000>; 73 }; 74 75 opp-1533000000 { 76 opp-hz = /bits/ 64 <1533000000>; 77 opp-microvolt = <850000>; 78 }; 79 80 opp-1633000000 { 81 opp-hz = /bits/ 64 <1633000000>; 82 opp-microvolt = <887500>; 83 }; 84 85 opp-1700000000 { 86 opp-hz = /bits/ 64 <1700000000>; 87 opp-microvolt = <912500>; 88 }; 89 90 opp-1767000000 { 91 opp-hz = /bits/ 64 <1767000000>; 92 opp-microvolt = <937500>; 93 }; 94 95 opp-1834000000 { 96 opp-hz = /bits/ 64 <1834000000>; 97 opp-microvolt = <962500>; 98 }; 99 100 opp-1917000000 { 101 opp-hz = /bits/ 64 <1917000000>; 102 opp-microvolt = <993750>; 103 }; 104 105 opp-2001000000 { 106 opp-hz = /bits/ 64 <2001000000>; 107 opp-microvolt = <1025000>; 108 }; 109 }; 110 111 cpu-map { 112 cluster0 { 113 core0 { 114 cpu = <&cpu0>; 115 }; 116 core1 { 117 cpu = <&cpu1>; 118 }; 119 core2 { 120 cpu = <&cpu2>; 121 }; 122 core3 { 123 cpu = <&cpu3>; 124 }; 125 }; 126 }; 127 128 cpu0: cpu@0 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a53"; 131 reg = <0x0>; 132 #cooling-cells = <2>; 133 enable-method = "psci"; 134 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 135 i-cache-size = <0x8000>; 136 i-cache-line-size = <64>; 137 i-cache-sets = <256>; 138 d-cache-size = <0x8000>; 139 d-cache-line-size = <64>; 140 d-cache-sets = <256>; 141 next-level-cache = <&l2>; 142 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 143 <&apmixedsys CLK_APMIXED_MAINPLL>; 144 clock-names = "cpu", "intermediate"; 145 operating-points-v2 = <&cluster0_opp>; 146 }; 147 148 cpu1: cpu@1 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a53"; 151 reg = <0x1>; 152 #cooling-cells = <2>; 153 enable-method = "psci"; 154 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 155 i-cache-size = <0x8000>; 156 i-cache-line-size = <64>; 157 i-cache-sets = <256>; 158 d-cache-size = <0x8000>; 159 d-cache-line-size = <64>; 160 d-cache-sets = <256>; 161 next-level-cache = <&l2>; 162 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 163 <&apmixedsys CLK_APMIXED_MAINPLL>; 164 clock-names = "cpu", "intermediate", "armpll"; 165 operating-points-v2 = <&cluster0_opp>; 166 }; 167 168 cpu2: cpu@2 { 169 device_type = "cpu"; 170 compatible = "arm,cortex-a53"; 171 reg = <0x2>; 172 #cooling-cells = <2>; 173 enable-method = "psci"; 174 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 175 i-cache-size = <0x8000>; 176 i-cache-line-size = <64>; 177 i-cache-sets = <256>; 178 d-cache-size = <0x8000>; 179 d-cache-line-size = <64>; 180 d-cache-sets = <256>; 181 next-level-cache = <&l2>; 182 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 183 <&apmixedsys CLK_APMIXED_MAINPLL>; 184 clock-names = "cpu", "intermediate", "armpll"; 185 operating-points-v2 = <&cluster0_opp>; 186 }; 187 188 cpu3: cpu@3 { 189 device_type = "cpu"; 190 compatible = "arm,cortex-a53"; 191 reg = <0x3>; 192 #cooling-cells = <2>; 193 enable-method = "psci"; 194 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 195 i-cache-size = <0x8000>; 196 i-cache-line-size = <64>; 197 i-cache-sets = <256>; 198 d-cache-size = <0x8000>; 199 d-cache-line-size = <64>; 200 d-cache-sets = <256>; 201 next-level-cache = <&l2>; 202 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 203 <&apmixedsys CLK_APMIXED_MAINPLL>; 204 clock-names = "cpu", "intermediate", "armpll"; 205 operating-points-v2 = <&cluster0_opp>; 206 }; 207 208 idle-states { 209 entry-method = "psci"; 210 211 CPU_MCDI: cpu-mcdi { 212 compatible = "arm,idle-state"; 213 local-timer-stop; 214 arm,psci-suspend-param = <0x00010001>; 215 entry-latency-us = <300>; 216 exit-latency-us = <200>; 217 min-residency-us = <1000>; 218 }; 219 220 CLUSTER_MCDI: cluster-mcdi { 221 compatible = "arm,idle-state"; 222 local-timer-stop; 223 arm,psci-suspend-param = <0x01010001>; 224 entry-latency-us = <350>; 225 exit-latency-us = <250>; 226 min-residency-us = <1200>; 227 }; 228 229 CLUSTER_DPIDLE: cluster-dpidle { 230 compatible = "arm,idle-state"; 231 local-timer-stop; 232 arm,psci-suspend-param = <0x01010004>; 233 entry-latency-us = <300>; 234 exit-latency-us = <800>; 235 min-residency-us = <3300>; 236 }; 237 }; 238 239 l2: l2-cache { 240 compatible = "cache"; 241 cache-level = <2>; 242 cache-size = <0x80000>; 243 cache-line-size = <64>; 244 cache-sets = <512>; 245 cache-unified; 246 }; 247 }; 248 249 clk26m: oscillator { 250 compatible = "fixed-clock"; 251 #clock-cells = <0>; 252 clock-frequency = <26000000>; 253 clock-output-names = "clk26m"; 254 }; 255 256 psci { 257 compatible = "arm,psci-1.0"; 258 method = "smc"; 259 }; 260 261 soc { 262 #address-cells = <2>; 263 #size-cells = <2>; 264 compatible = "simple-bus"; 265 ranges; 266 267 gic: interrupt-controller@c000000 { 268 compatible = "arm,gic-v3"; 269 #interrupt-cells = <3>; 270 interrupt-parent = <&gic>; 271 interrupt-controller; 272 reg = <0 0x0c000000 0 0x10000>, /* GICD */ 273 <0 0x0c080000 0 0x80000>, /* GICR */ 274 <0 0x0c400000 0 0x2000>, /* GICC */ 275 <0 0x0c410000 0 0x1000>, /* GICH */ 276 <0 0x0c420000 0 0x2000>; /* GICV */ 277 278 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 279 }; 280 281 topckgen: syscon@10000000 { 282 compatible = "mediatek,mt8365-topckgen", "syscon"; 283 reg = <0 0x10000000 0 0x1000>; 284 #clock-cells = <1>; 285 }; 286 287 infracfg: syscon@10001000 { 288 compatible = "mediatek,mt8365-infracfg", "syscon"; 289 reg = <0 0x10001000 0 0x1000>; 290 #clock-cells = <1>; 291 }; 292 293 pericfg: syscon@10003000 { 294 compatible = "mediatek,mt8365-pericfg", "syscon"; 295 reg = <0 0x10003000 0 0x1000>; 296 #clock-cells = <1>; 297 }; 298 299 syscfg_pctl: syscfg-pctl@10005000 { 300 compatible = "mediatek,mt8365-syscfg", "syscon"; 301 reg = <0 0x10005000 0 0x1000>; 302 }; 303 304 scpsys: syscon@10006000 { 305 compatible = "mediatek,mt8365-scpsys", "syscon", "simple-mfd"; 306 reg = <0 0x10006000 0 0x1000>; 307 308 /* System Power Manager */ 309 spm: power-controller { 310 compatible = "mediatek,mt8365-power-controller"; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 #power-domain-cells = <1>; 314 315 /* power domains of the SoC */ 316 power-domain@MT8365_POWER_DOMAIN_MM { 317 reg = <MT8365_POWER_DOMAIN_MM>; 318 clocks = <&topckgen CLK_TOP_MM_SEL>, 319 <&mmsys CLK_MM_MM_SMI_COMMON>, 320 <&mmsys CLK_MM_MM_SMI_COMM0>, 321 <&mmsys CLK_MM_MM_SMI_COMM1>, 322 <&mmsys CLK_MM_MM_SMI_LARB0>; 323 clock-names = "mm", "mm-0", "mm-1", 324 "mm-2", "mm-3"; 325 #power-domain-cells = <0>; 326 mediatek,infracfg = <&infracfg>; 327 mediatek,infracfg-nao = <&infracfg_nao>; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 331 power-domain@MT8365_POWER_DOMAIN_CAM { 332 reg = <MT8365_POWER_DOMAIN_CAM>; 333 clocks = <&camsys CLK_CAM_LARB2>, 334 <&camsys CLK_CAM_SENIF>, 335 <&camsys CLK_CAMSV0>, 336 <&camsys CLK_CAMSV1>, 337 <&camsys CLK_CAM_FDVT>, 338 <&camsys CLK_CAM_WPE>; 339 clock-names = "cam-0", "cam-1", 340 "cam-2", "cam-3", 341 "cam-4", "cam-5"; 342 #power-domain-cells = <0>; 343 mediatek,infracfg = <&infracfg>; 344 mediatek,smi = <&smi_common>; 345 }; 346 347 power-domain@MT8365_POWER_DOMAIN_VDEC { 348 reg = <MT8365_POWER_DOMAIN_VDEC>; 349 #power-domain-cells = <0>; 350 mediatek,smi = <&smi_common>; 351 }; 352 353 power-domain@MT8365_POWER_DOMAIN_VENC { 354 reg = <MT8365_POWER_DOMAIN_VENC>; 355 #power-domain-cells = <0>; 356 mediatek,smi = <&smi_common>; 357 }; 358 359 power-domain@MT8365_POWER_DOMAIN_APU { 360 reg = <MT8365_POWER_DOMAIN_APU>; 361 clocks = <&infracfg CLK_IFR_APU_AXI>, 362 <&apu CLK_APU_IPU_CK>, 363 <&apu CLK_APU_AXI>, 364 <&apu CLK_APU_JTAG>, 365 <&apu CLK_APU_IF_CK>, 366 <&apu CLK_APU_EDMA>, 367 <&apu CLK_APU_AHB>; 368 clock-names = "apu", "apu-0", 369 "apu-1", "apu-2", 370 "apu-3", "apu-4", 371 "apu-5"; 372 #power-domain-cells = <0>; 373 mediatek,infracfg = <&infracfg>; 374 mediatek,smi = <&smi_common>; 375 }; 376 }; 377 378 power-domain@MT8365_POWER_DOMAIN_CONN { 379 reg = <MT8365_POWER_DOMAIN_CONN>; 380 clocks = <&topckgen CLK_TOP_CONN_32K>, 381 <&topckgen CLK_TOP_CONN_26M>; 382 clock-names = "conn", "conn1"; 383 #power-domain-cells = <0>; 384 mediatek,infracfg = <&infracfg>; 385 }; 386 387 power-domain@MT8365_POWER_DOMAIN_MFG { 388 reg = <MT8365_POWER_DOMAIN_MFG>; 389 clocks = <&topckgen CLK_TOP_MFG_SEL>; 390 clock-names = "mfg"; 391 #power-domain-cells = <0>; 392 mediatek,infracfg = <&infracfg>; 393 }; 394 395 power-domain@MT8365_POWER_DOMAIN_AUDIO { 396 reg = <MT8365_POWER_DOMAIN_AUDIO>; 397 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 398 <&infracfg CLK_IFR_AUDIO>, 399 <&infracfg CLK_IFR_AUD_26M_BK>; 400 clock-names = "audio", "audio1", "audio2"; 401 #power-domain-cells = <0>; 402 mediatek,infracfg = <&infracfg>; 403 }; 404 405 power-domain@MT8365_POWER_DOMAIN_DSP { 406 reg = <MT8365_POWER_DOMAIN_DSP>; 407 clocks = <&topckgen CLK_TOP_DSP_SEL>, 408 <&topckgen CLK_TOP_DSP_26M>; 409 clock-names = "dsp", "dsp1"; 410 #power-domain-cells = <0>; 411 mediatek,infracfg = <&infracfg>; 412 }; 413 }; 414 }; 415 416 watchdog: watchdog@10007000 { 417 compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt"; 418 reg = <0 0x10007000 0 0x100>; 419 #reset-cells = <1>; 420 }; 421 422 pio: pinctrl@1000b000 { 423 compatible = "mediatek,mt8365-pinctrl"; 424 reg = <0 0x1000b000 0 0x1000>; 425 mediatek,pctl-regmap = <&syscfg_pctl>; 426 gpio-controller; 427 #gpio-cells = <2>; 428 interrupt-controller; 429 #interrupt-cells = <2>; 430 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 431 }; 432 433 apmixedsys: syscon@1000c000 { 434 compatible = "mediatek,mt8365-apmixedsys", "syscon"; 435 reg = <0 0x1000c000 0 0x1000>; 436 #clock-cells = <1>; 437 }; 438 439 pwrap: pwrap@1000d000 { 440 compatible = "mediatek,mt8365-pwrap"; 441 reg = <0 0x1000d000 0 0x1000>; 442 reg-names = "pwrap"; 443 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&infracfg CLK_IFR_PWRAP_SPI>, 445 <&infracfg CLK_IFR_PMIC_AP>, 446 <&infracfg CLK_IFR_PWRAP_SYS>, 447 <&infracfg CLK_IFR_PWRAP_TMR>; 448 clock-names = "spi", "wrap", "sys", "tmr"; 449 }; 450 451 keypad: keypad@10010000 { 452 compatible = "mediatek,mt6779-keypad"; 453 reg = <0 0x10010000 0 0x1000>; 454 wakeup-source; 455 interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>; 456 clocks = <&clk26m>; 457 clock-names = "kpd"; 458 status = "disabled"; 459 }; 460 461 mcucfg: syscon@10200000 { 462 compatible = "mediatek,mt8365-mcucfg", "syscon"; 463 reg = <0 0x10200000 0 0x2000>; 464 #clock-cells = <1>; 465 }; 466 467 sysirq: interrupt-controller@10200a80 { 468 compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; 469 interrupt-controller; 470 #interrupt-cells = <3>; 471 interrupt-parent = <&gic>; 472 reg = <0 0x10200a80 0 0x20>; 473 }; 474 475 iommu: iommu@10205000 { 476 compatible = "mediatek,mt8365-m4u"; 477 reg = <0 0x10205000 0 0x1000>; 478 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>; 479 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>; 480 #iommu-cells = <1>; 481 }; 482 483 infracfg_nao: infracfg@1020e000 { 484 compatible = "mediatek,mt8365-infracfg", "syscon"; 485 reg = <0 0x1020e000 0 0x1000>; 486 #clock-cells = <1>; 487 }; 488 489 rng: rng@1020f000 { 490 compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng"; 491 reg = <0 0x1020f000 0 0x100>; 492 clocks = <&infracfg CLK_IFR_TRNG>; 493 clock-names = "rng"; 494 }; 495 496 apdma: dma-controller@11000280 { 497 compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; 498 reg = <0 0x11000280 0 0x80>, 499 <0 0x11000300 0 0x80>, 500 <0 0x11000380 0 0x80>, 501 <0 0x11000400 0 0x80>, 502 <0 0x11000580 0 0x80>, 503 <0 0x11000600 0 0x80>; 504 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>, 505 <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>, 506 <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>, 507 <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>, 508 <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>, 509 <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 510 dma-requests = <6>; 511 clocks = <&infracfg CLK_IFR_AP_DMA>; 512 clock-names = "apdma"; 513 #dma-cells = <1>; 514 }; 515 516 uart0: serial@11002000 { 517 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 518 reg = <0 0x11002000 0 0x1000>; 519 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>; 520 clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; 521 clock-names = "baud", "bus"; 522 dmas = <&apdma 0>, <&apdma 1>; 523 dma-names = "tx", "rx"; 524 status = "disabled"; 525 }; 526 527 uart1: serial@11003000 { 528 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 529 reg = <0 0x11003000 0 0x1000>; 530 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>; 531 clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; 532 clock-names = "baud", "bus"; 533 dmas = <&apdma 2>, <&apdma 3>; 534 dma-names = "tx", "rx"; 535 status = "disabled"; 536 }; 537 538 uart2: serial@11004000 { 539 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 540 reg = <0 0x11004000 0 0x1000>; 541 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>; 542 clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; 543 clock-names = "baud", "bus"; 544 dmas = <&apdma 4>, <&apdma 5>; 545 dma-names = "tx", "rx"; 546 status = "disabled"; 547 }; 548 549 pwm: pwm@11006000 { 550 compatible = "mediatek,mt8365-pwm"; 551 reg = <0 0x11006000 0 0x1000>; 552 #pwm-cells = <2>; 553 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 554 clocks = <&infracfg CLK_IFR_PWM_HCLK>, 555 <&infracfg CLK_IFR_PWM>, 556 <&infracfg CLK_IFR_PWM1>, 557 <&infracfg CLK_IFR_PWM2>, 558 <&infracfg CLK_IFR_PWM3>; 559 clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; 560 }; 561 562 i2c0: i2c@11007000 { 563 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 564 reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; 565 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>; 566 clock-div = <1>; 567 clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>; 568 clock-names = "main", "dma"; 569 #address-cells = <1>; 570 #size-cells = <0>; 571 status = "disabled"; 572 }; 573 574 i2c1: i2c@11008000 { 575 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 576 reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; 577 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>; 578 clock-div = <1>; 579 clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>; 580 clock-names = "main", "dma"; 581 #address-cells = <1>; 582 #size-cells = <0>; 583 status = "disabled"; 584 }; 585 586 i2c2: i2c@11009000 { 587 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 588 reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; 589 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>; 590 clock-div = <1>; 591 clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>; 592 clock-names = "main", "dma"; 593 #address-cells = <1>; 594 #size-cells = <0>; 595 status = "disabled"; 596 }; 597 598 spi: spi@1100a000 { 599 compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; 600 reg = <0 0x1100a000 0 0x100>; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>; 604 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 605 <&topckgen CLK_TOP_SPI_SEL>, 606 <&infracfg CLK_IFR_SPI0>; 607 clock-names = "parent-clk", "sel-clk", "spi-clk"; 608 status = "disabled"; 609 }; 610 611 i2c3: i2c@1100f000 { 612 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 613 reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; 614 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>; 615 clock-div = <1>; 616 clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>; 617 clock-names = "main", "dma"; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 status = "disabled"; 621 }; 622 623 ssusb: usb@11201000 { 624 compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; 625 reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; 626 reg-names = "mac", "ippc"; 627 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>; 628 phys = <&u2port0 PHY_TYPE_USB2>, 629 <&u2port1 PHY_TYPE_USB2>; 630 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 631 <&infracfg CLK_IFR_SSUSB_REF>, 632 <&infracfg CLK_IFR_SSUSB_SYS>, 633 <&infracfg CLK_IFR_ICUSB>; 634 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 635 #address-cells = <2>; 636 #size-cells = <2>; 637 ranges; 638 status = "disabled"; 639 640 usb_host: usb@11200000 { 641 compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; 642 reg = <0 0x11200000 0 0x1000>; 643 reg-names = "mac"; 644 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>; 645 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 646 <&infracfg CLK_IFR_SSUSB_REF>, 647 <&infracfg CLK_IFR_SSUSB_SYS>, 648 <&infracfg CLK_IFR_ICUSB>, 649 <&infracfg CLK_IFR_SSUSB_XHCI>; 650 clock-names = "sys_ck", "ref_ck", "mcu_ck", 651 "dma_ck", "xhci_ck"; 652 status = "disabled"; 653 }; 654 }; 655 656 mmc0: mmc@11230000 { 657 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 658 reg = <0 0x11230000 0 0x1000>, 659 <0 0x11cd0000 0 0x1000>; 660 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>; 661 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 662 <&infracfg CLK_IFR_MSDC0_HCLK>, 663 <&infracfg CLK_IFR_MSDC0_SRC>; 664 clock-names = "source", "hclk", "source_cg"; 665 status = "disabled"; 666 }; 667 668 mmc1: mmc@11240000 { 669 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 670 reg = <0 0x11240000 0 0x1000>, 671 <0 0x11c90000 0 0x1000>; 672 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>; 673 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 674 <&infracfg CLK_IFR_MSDC1_HCLK>, 675 <&infracfg CLK_IFR_MSDC1_SRC>; 676 clock-names = "source", "hclk", "source_cg"; 677 status = "disabled"; 678 }; 679 680 mmc2: mmc@11250000 { 681 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 682 reg = <0 0x11250000 0 0x1000>, 683 <0 0x11c60000 0 0x1000>; 684 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>; 685 clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>, 686 <&infracfg CLK_IFR_MSDC2_HCLK>, 687 <&infracfg CLK_IFR_MSDC2_SRC>, 688 <&infracfg CLK_IFR_MSDC2_BK>, 689 <&infracfg CLK_IFR_AP_MSDC0>; 690 clock-names = "source", "hclk", "source_cg", 691 "bus_clk", "sys_cg"; 692 status = "disabled"; 693 }; 694 695 ethernet: ethernet@112a0000 { 696 compatible = "mediatek,mt8365-eth"; 697 reg = <0 0x112a0000 0 0x1000>; 698 mediatek,pericfg = <&infracfg>; 699 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&topckgen CLK_TOP_ETH_SEL>, 701 <&infracfg CLK_IFR_NIC_AXI>, 702 <&infracfg CLK_IFR_NIC_SLV_AXI>; 703 clock-names = "core", "reg", "trans"; 704 status = "disabled"; 705 }; 706 707 u3phy: t-phy@11cc0000 { 708 compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; 709 #address-cells = <1>; 710 #size-cells = <1>; 711 ranges = <0 0 0x11cc0000 0x9000>; 712 713 u2port0: usb-phy@0 { 714 reg = <0x0 0x400>; 715 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 716 <&topckgen CLK_TOP_USB20_48M_EN>; 717 clock-names = "ref", "da_ref"; 718 #phy-cells = <1>; 719 }; 720 721 u2port1: usb-phy@1000 { 722 reg = <0x1000 0x400>; 723 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 724 <&topckgen CLK_TOP_USB20_48M_EN>; 725 clock-names = "ref", "da_ref"; 726 #phy-cells = <1>; 727 }; 728 }; 729 730 mmsys: syscon@14000000 { 731 compatible = "mediatek,mt8365-mmsys", "syscon"; 732 reg = <0 0x14000000 0 0x1000>; 733 #clock-cells = <1>; 734 }; 735 736 smi_common: smi@14002000 { 737 compatible = "mediatek,mt8365-smi-common"; 738 reg = <0 0x14002000 0 0x1000>; 739 clocks = <&mmsys CLK_MM_MM_SMI_COMMON>, 740 <&mmsys CLK_MM_MM_SMI_COMMON>, 741 <&mmsys CLK_MM_MM_SMI_COMM0>, 742 <&mmsys CLK_MM_MM_SMI_COMM1>; 743 clock-names = "apb", "smi", "gals0", "gals1"; 744 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 745 }; 746 747 larb0: larb@14003000 { 748 compatible = "mediatek,mt8365-smi-larb", 749 "mediatek,mt8186-smi-larb"; 750 reg = <0 0x14003000 0 0x1000>; 751 mediatek,smi = <&smi_common>; 752 clocks = <&mmsys CLK_MM_MM_SMI_LARB0>, 753 <&mmsys CLK_MM_MM_SMI_LARB0>; 754 clock-names = "apb", "smi"; 755 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 756 mediatek,larb-id = <0>; 757 }; 758 759 camsys: syscon@15000000 { 760 compatible = "mediatek,mt8365-imgsys", "syscon"; 761 reg = <0 0x15000000 0 0x1000>; 762 #clock-cells = <1>; 763 }; 764 765 larb2: larb@15001000 { 766 compatible = "mediatek,mt8365-smi-larb", 767 "mediatek,mt8186-smi-larb"; 768 reg = <0 0x15001000 0 0x1000>; 769 mediatek,smi = <&smi_common>; 770 clocks = <&mmsys CLK_MM_MM_SMI_IMG>, 771 <&camsys CLK_CAM_LARB2>; 772 clock-names = "apb", "smi"; 773 power-domains = <&spm MT8365_POWER_DOMAIN_CAM>; 774 mediatek,larb-id = <2>; 775 }; 776 777 vdecsys: syscon@16000000 { 778 compatible = "mediatek,mt8365-vdecsys", "syscon"; 779 reg = <0 0x16000000 0 0x1000>; 780 #clock-cells = <1>; 781 }; 782 783 larb3: larb@16010000 { 784 compatible = "mediatek,mt8365-smi-larb", 785 "mediatek,mt8186-smi-larb"; 786 reg = <0 0x16010000 0 0x1000>; 787 mediatek,smi = <&smi_common>; 788 clocks = <&vdecsys CLK_VDEC_LARB1>, 789 <&vdecsys CLK_VDEC_LARB1>; 790 clock-names = "apb", "smi"; 791 power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>; 792 mediatek,larb-id = <3>; 793 }; 794 795 vencsys: syscon@17000000 { 796 compatible = "mediatek,mt8365-vencsys", "syscon"; 797 reg = <0 0x17000000 0 0x1000>; 798 #clock-cells = <1>; 799 }; 800 801 larb1: larb@17010000 { 802 compatible = "mediatek,mt8365-smi-larb", 803 "mediatek,mt8186-smi-larb"; 804 reg = <0 0x17010000 0 0x1000>; 805 mediatek,smi = <&smi_common>; 806 clocks = <&vencsys CLK_VENC>, <&vencsys CLK_VENC>; 807 clock-names = "apb", "smi"; 808 power-domains = <&spm MT8365_POWER_DOMAIN_VENC>; 809 mediatek,larb-id = <1>; 810 }; 811 812 apu: syscon@19020000 { 813 compatible = "mediatek,mt8365-apu", "syscon"; 814 reg = <0 0x19020000 0 0x1000>; 815 #clock-cells = <1>; 816 }; 817 818 afe: audio-controller@11220000 { 819 compatible = "mediatek,mt8365-afe-pcm"; 820 reg = <0 0x11220000 0 0x1000>; 821 #sound-dai-cells = <0>; 822 clocks = <&clk26m>, 823 <&topckgen CLK_TOP_AUDIO_SEL>, 824 <&topckgen CLK_TOP_AUD_I2S0_M>, 825 <&topckgen CLK_TOP_AUD_I2S1_M>, 826 <&topckgen CLK_TOP_AUD_I2S2_M>, 827 <&topckgen CLK_TOP_AUD_I2S3_M>, 828 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, 829 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, 830 <&topckgen CLK_TOP_AUD_1_SEL>, 831 <&topckgen CLK_TOP_AUD_2_SEL>, 832 <&topckgen CLK_TOP_APLL_I2S0_SEL>, 833 <&topckgen CLK_TOP_APLL_I2S1_SEL>, 834 <&topckgen CLK_TOP_APLL_I2S2_SEL>, 835 <&topckgen CLK_TOP_APLL_I2S3_SEL>; 836 clock-names = "top_clk26m_clk", 837 "top_audio_sel", 838 "audio_i2s0_m", 839 "audio_i2s1_m", 840 "audio_i2s2_m", 841 "audio_i2s3_m", 842 "engen1", 843 "engen2", 844 "aud1", 845 "aud2", 846 "i2s0_m_sel", 847 "i2s1_m_sel", 848 "i2s2_m_sel", 849 "i2s3_m_sel"; 850 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>; 851 power-domains = <&spm MT8365_POWER_DOMAIN_AUDIO>; 852 status = "disabled"; 853 }; 854 }; 855 856 timer { 857 compatible = "arm,armv8-timer"; 858 interrupt-parent = <&gic>; 859 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 860 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 861 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 862 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 863 }; 864 865 system_clk: dummy13m { 866 compatible = "fixed-clock"; 867 clock-frequency = <13000000>; 868 #clock-cells = <0>; 869 }; 870 871 systimer: timer@10017000 { 872 compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer"; 873 reg = <0 0x10017000 0 0x100>; 874 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&system_clk>; 876 clock-names = "clk13m"; 877 }; 878}; 879