Lines Matching +full:0 +full:x2e00
30 .l_reg = 0x3164,
31 .m_reg = 0x3168,
32 .n_reg = 0x316c,
33 .config_reg = 0x3174,
34 .mode_reg = 0x3160,
35 .status_reg = 0x3178,
48 .enable_reg = 0x34c0,
61 .l_reg = 0x3144,
62 .m_reg = 0x3148,
63 .n_reg = 0x314c,
64 .config_reg = 0x3154,
65 .mode_reg = 0x3140,
66 .status_reg = 0x3158,
79 .enable_reg = 0x34c0,
92 .mode_reg = 0x3200,
93 .l_reg = 0x3208,
94 .m_reg = 0x320c,
95 .n_reg = 0x3210,
96 .config_reg = 0x3204,
97 .status_reg = 0x321c,
98 .config_val = 0x7845c665,
99 .droop_reg = 0x3214,
100 .droop_val = 0x0108c000,
120 .mode_reg = 0x3240,
121 .l_reg = 0x3248,
122 .m_reg = 0x324c,
123 .n_reg = 0x3250,
124 .config_reg = 0x3244,
125 .status_reg = 0x325c,
126 .config_val = 0x7845c665,
127 .droop_reg = 0x3254,
128 .droop_val = 0x0108c000,
134 .mode_reg = 0x3300,
135 .l_reg = 0x3308,
136 .m_reg = 0x330c,
137 .n_reg = 0x3310,
138 .config_reg = 0x3304,
139 .status_reg = 0x331c,
140 .config_val = 0x7845c665,
141 .droop_reg = 0x3314,
142 .droop_val = 0x0108c000,
162 .mode_reg = 0x3280,
163 .l_reg = 0x3288,
164 .m_reg = 0x328c,
165 .n_reg = 0x3290,
166 .config_reg = 0x3284,
167 .status_reg = 0x329c,
168 .config_val = 0x7845c665,
169 .droop_reg = 0x3294,
170 .droop_val = 0x0108c000,
190 .mode_reg = 0x32c0,
191 .l_reg = 0x32c8,
192 .m_reg = 0x32cc,
193 .n_reg = 0x32d0,
194 .config_reg = 0x32c4,
195 .status_reg = 0x32dc,
196 .config_val = 0x7845c665,
197 .droop_reg = 0x32d4,
198 .droop_val = 0x0108c000,
218 .mode_reg = 0x3300,
219 .l_reg = 0x3308,
220 .m_reg = 0x330c,
221 .n_reg = 0x3310,
222 .config_reg = 0x3304,
223 .status_reg = 0x331c,
224 .config_val = 0x7845c665,
225 .droop_reg = 0x3314,
226 .droop_val = 0x0108c000,
232 .mode_reg = 0x3400,
233 .l_reg = 0x3408,
234 .m_reg = 0x340c,
235 .n_reg = 0x3410,
236 .config_reg = 0x3404,
237 .status_reg = 0x341c,
238 .config_val = 0x7845c665,
239 .droop_reg = 0x3414,
240 .droop_val = 0x0108c000,
260 .l_reg = 0x31c4,
261 .m_reg = 0x31c8,
262 .n_reg = 0x31cc,
263 .config_reg = 0x31d4,
264 .mode_reg = 0x31c0,
265 .status_reg = 0x31d8,
278 .enable_reg = 0x34c0,
298 { P_PXO, 0 },
308 { P_PXO, 0 },
320 { P_PXO, 0 },
350 .ns_reg = 0x29d4,
351 .md_reg = 0x29d0,
365 .src_sel_shift = 0,
370 .enable_reg = 0x29d4,
383 .halt_reg = 0x2fcc,
386 .enable_reg = 0x29d4,
401 .ns_reg = 0x29f4,
402 .md_reg = 0x29f0,
416 .src_sel_shift = 0,
421 .enable_reg = 0x29f4,
434 .halt_reg = 0x2fcc,
437 .enable_reg = 0x29f4,
452 .ns_reg = 0x2a14,
453 .md_reg = 0x2a10,
467 .src_sel_shift = 0,
472 .enable_reg = 0x2a14,
485 .halt_reg = 0x2fcc,
488 .enable_reg = 0x2a14,
503 .ns_reg = 0x2a34,
504 .md_reg = 0x2a30,
518 .src_sel_shift = 0,
523 .enable_reg = 0x2a34,
536 .halt_reg = 0x2fd0,
539 .enable_reg = 0x2a34,
554 .ns_reg = 0x2a54,
555 .md_reg = 0x2a50,
569 .src_sel_shift = 0,
574 .enable_reg = 0x2a54,
587 .halt_reg = 0x2fd0,
590 .enable_reg = 0x2a54,
605 .ns_reg = 0x2a74,
606 .md_reg = 0x2a70,
620 .src_sel_shift = 0,
625 .enable_reg = 0x2a74,
638 .halt_reg = 0x2fd0,
641 .enable_reg = 0x2a74,
656 .ns_reg = 0x2a94,
657 .md_reg = 0x2a90,
671 .src_sel_shift = 0,
676 .enable_reg = 0x2a94,
689 .halt_reg = 0x2fd0,
692 .enable_reg = 0x2a94,
707 .ns_reg = 0x2ab4,
708 .md_reg = 0x2ab0,
722 .src_sel_shift = 0,
727 .enable_reg = 0x2ab4,
740 .halt_reg = 0x2fd0,
743 .enable_reg = 0x2ab4,
758 .ns_reg = 0x2ad4,
759 .md_reg = 0x2ad0,
773 .src_sel_shift = 0,
778 .enable_reg = 0x2ad4,
791 .halt_reg = 0x2fd0,
794 .enable_reg = 0x2ad4,
809 .ns_reg = 0x2af4,
810 .md_reg = 0x2af0,
824 .src_sel_shift = 0,
829 .enable_reg = 0x2af4,
842 .halt_reg = 0x2fd0,
845 .enable_reg = 0x2af4,
860 .ns_reg = 0x2b14,
861 .md_reg = 0x2b10,
875 .src_sel_shift = 0,
880 .enable_reg = 0x2b14,
893 .halt_reg = 0x2fd4,
896 .enable_reg = 0x2b14,
911 .ns_reg = 0x2b34,
912 .md_reg = 0x2b30,
926 .src_sel_shift = 0,
931 .enable_reg = 0x2b34,
944 .halt_reg = 0x2fd4,
947 .enable_reg = 0x2b34,
968 { 27000000, P_PXO, 1, 0, 0 },
975 .ns_reg = 0x29cc,
976 .md_reg = 0x29c8,
990 .src_sel_shift = 0,
995 .enable_reg = 0x29cc,
1008 .halt_reg = 0x2fcc,
1011 .enable_reg = 0x29cc,
1026 .ns_reg = 0x29ec,
1027 .md_reg = 0x29e8,
1041 .src_sel_shift = 0,
1046 .enable_reg = 0x29ec,
1059 .halt_reg = 0x2fcc,
1062 .enable_reg = 0x29ec,
1077 .ns_reg = 0x2a0c,
1078 .md_reg = 0x2a08,
1092 .src_sel_shift = 0,
1097 .enable_reg = 0x2a0c,
1110 .halt_reg = 0x2fcc,
1111 .halt_bit = 0,
1113 .enable_reg = 0x2a0c,
1128 .ns_reg = 0x2a2c,
1129 .md_reg = 0x2a28,
1143 .src_sel_shift = 0,
1148 .enable_reg = 0x2a2c,
1161 .halt_reg = 0x2fd0,
1164 .enable_reg = 0x2a2c,
1179 .ns_reg = 0x2a4c,
1180 .md_reg = 0x2a48,
1194 .src_sel_shift = 0,
1199 .enable_reg = 0x2a4c,
1212 .halt_reg = 0x2fd0,
1215 .enable_reg = 0x2a4c,
1230 .ns_reg = 0x2a6c,
1231 .md_reg = 0x2a68,
1245 .src_sel_shift = 0,
1250 .enable_reg = 0x2a6c,
1263 .halt_reg = 0x2fd0,
1266 .enable_reg = 0x2a6c,
1281 .ns_reg = 0x2a8c,
1282 .md_reg = 0x2a88,
1296 .src_sel_shift = 0,
1301 .enable_reg = 0x2a8c,
1314 .halt_reg = 0x2fd0,
1317 .enable_reg = 0x2a8c,
1332 .ns_reg = 0x2aac,
1333 .md_reg = 0x2aa8,
1347 .src_sel_shift = 0,
1352 .enable_reg = 0x2aac,
1365 .halt_reg = 0x2fd0,
1368 .enable_reg = 0x2aac,
1383 .ns_reg = 0x2acc,
1384 .md_reg = 0x2ac8,
1398 .src_sel_shift = 0,
1403 .enable_reg = 0x2acc,
1416 .halt_reg = 0x2fd0,
1419 .enable_reg = 0x2acc,
1434 .ns_reg = 0x2aec,
1435 .md_reg = 0x2ae8,
1449 .src_sel_shift = 0,
1454 .enable_reg = 0x2aec,
1467 .halt_reg = 0x2fd0,
1468 .halt_bit = 0,
1470 .enable_reg = 0x2aec,
1485 .ns_reg = 0x2b0c,
1486 .md_reg = 0x2b08,
1500 .src_sel_shift = 0,
1505 .enable_reg = 0x2b0c,
1518 .halt_reg = 0x2fd4,
1521 .enable_reg = 0x2b0c,
1536 .ns_reg = 0x2b2c,
1537 .md_reg = 0x2b28,
1551 .src_sel_shift = 0,
1556 .enable_reg = 0x2b2c,
1569 .halt_reg = 0x2fd4,
1572 .enable_reg = 0x2b2c,
1587 { 9600000, P_CXO, 2, 0, 0 },
1588 { 13500000, P_PXO, 2, 0, 0 },
1589 { 19200000, P_CXO, 1, 0, 0 },
1590 { 27000000, P_PXO, 1, 0, 0 },
1593 { 96000000, P_PLL8, 4, 0, 0 },
1594 { 128000000, P_PLL8, 3, 0, 0 },
1595 { 192000000, P_PLL8, 2, 0, 0 },
1600 .ns_reg = 0x2d24,
1601 .md_reg = 0x2d00,
1615 .src_sel_shift = 0,
1620 .enable_reg = 0x2d24,
1633 .halt_reg = 0x2fd8,
1636 .enable_reg = 0x2d24,
1651 .ns_reg = 0x2d44,
1652 .md_reg = 0x2d40,
1666 .src_sel_shift = 0,
1671 .enable_reg = 0x2d44,
1684 .halt_reg = 0x2fd8,
1687 .enable_reg = 0x2d44,
1702 .ns_reg = 0x2d64,
1703 .md_reg = 0x2d60,
1717 .src_sel_shift = 0,
1722 .enable_reg = 0x2d64,
1735 .halt_reg = 0x2fd8,
1738 .enable_reg = 0x2d64,
1753 .hwcg_reg = 0x25a0,
1755 .halt_reg = 0x2fc8,
1758 .enable_reg = 0x25a0,
1768 .ns_reg = 0x2e80,
1774 .src_sel_shift = 0,
1788 .halt_reg = 0x2fd8,
1792 .enable_reg = 0x3080,
1814 { 96000000, P_PLL8, 4, 0, 0 },
1815 { 192000000, P_PLL8, 2, 0, 0 },
1820 .ns_reg = 0x282c,
1821 .md_reg = 0x2828,
1835 .src_sel_shift = 0,
1840 .enable_reg = 0x282c,
1852 .halt_reg = 0x2fc8,
1855 .enable_reg = 0x282c,
1870 .ns_reg = 0x284c,
1871 .md_reg = 0x2848,
1885 .src_sel_shift = 0,
1890 .enable_reg = 0x284c,
1902 .halt_reg = 0x2fc8,
1905 .enable_reg = 0x284c,
1920 .ns_reg = 0x286c,
1921 .md_reg = 0x2868,
1935 .src_sel_shift = 0,
1940 .enable_reg = 0x286c,
1952 .halt_reg = 0x2fc8,
1955 .enable_reg = 0x286c,
1970 .ns_reg = 0x288c,
1971 .md_reg = 0x2888,
1985 .src_sel_shift = 0,
1990 .enable_reg = 0x288c,
2002 .halt_reg = 0x2fc8,
2005 .enable_reg = 0x288c,
2020 .ns_reg = 0x28ac,
2021 .md_reg = 0x28a8,
2035 .src_sel_shift = 0,
2040 .enable_reg = 0x28ac,
2052 .halt_reg = 0x2fc8,
2055 .enable_reg = 0x28ac,
2075 .ns_reg = 0x2710,
2076 .md_reg = 0x270c,
2090 .src_sel_shift = 0,
2095 .enable_reg = 0x2710,
2108 .halt_reg = 0x2fd4,
2111 .enable_reg = 0x2710,
2131 .ns_reg = 0x290c,
2132 .md_reg = 0x2908,
2146 .src_sel_shift = 0,
2151 .enable_reg = 0x290c,
2164 .halt_reg = 0x2fc8,
2165 .halt_bit = 0,
2167 .enable_reg = 0x290c,
2182 .ns_reg = 0x370c,
2183 .md_reg = 0x3708,
2197 .src_sel_shift = 0,
2202 .enable_reg = 0x370c,
2215 .halt_reg = 0x2fc8,
2218 .enable_reg = 0x370c,
2233 .ns_reg = 0x372c,
2234 .md_reg = 0x3728,
2248 .src_sel_shift = 0,
2253 .enable_reg = 0x372c,
2266 .halt_reg = 0x2fc8,
2269 .enable_reg = 0x372c,
2284 .ns_reg = 0x2928,
2285 .md_reg = 0x2924,
2299 .src_sel_shift = 0,
2304 .enable_reg = 0x2928,
2317 .halt_reg = 0x2fc8,
2320 .enable_reg = 0x2928,
2335 .halt_reg = 0x2fcc,
2338 .enable_reg = 0x292c,
2353 .halt_reg = 0x2fcc,
2356 .enable_reg = 0x2b44,
2357 .enable_mask = BIT(0),
2370 .halt_reg = 0x2fcc,
2373 .enable_reg = 0x2b48,
2374 .enable_mask = BIT(0),
2383 .ns_reg = 0x2968,
2384 .md_reg = 0x2964,
2398 .src_sel_shift = 0,
2403 .enable_reg = 0x2968,
2416 .halt_reg = 0x2fcc,
2419 .enable_reg = 0x2968,
2434 .halt_reg = 0x2fcc,
2437 .enable_reg = 0x296c,
2452 .ns_reg = 0x2988,
2453 .md_reg = 0x2984,
2467 .src_sel_shift = 0,
2472 .enable_reg = 0x2988,
2485 .halt_reg = 0x2fcc,
2488 .enable_reg = 0x2988,
2503 .halt_reg = 0x2fcc,
2506 .enable_reg = 0x298c,
2521 .hwcg_reg = 0x2724,
2523 .halt_reg = 0x2fd4,
2526 .enable_reg = 0x2724,
2536 .halt_reg = 0x2fd4,
2539 .enable_reg = 0x2720,
2549 .hwcg_reg = 0x25c0,
2551 .halt_reg = 0x2fc8,
2554 .enable_reg = 0x25c0,
2564 .hwcg_reg = 0x29c0,
2566 .halt_reg = 0x2fcc,
2569 .enable_reg = 0x29c0,
2579 .hwcg_reg = 0x29e0,
2581 .halt_reg = 0x2fcc,
2584 .enable_reg = 0x29e0,
2594 .hwcg_reg = 0x2a00,
2596 .halt_reg = 0x2fcc,
2599 .enable_reg = 0x2a00,
2609 .hwcg_reg = 0x2a20,
2611 .halt_reg = 0x2fd0,
2614 .enable_reg = 0x2a20,
2624 .hwcg_reg = 0x2a40,
2626 .halt_reg = 0x2fd0,
2629 .enable_reg = 0x2a40,
2639 .hwcg_reg = 0x2a60,
2641 .halt_reg = 0x2fd0,
2644 .enable_reg = 0x2a60,
2654 .hwcg_reg = 0x2a80,
2656 .halt_reg = 0x2fd0,
2659 .enable_reg = 0x2a80,
2669 .hwcg_reg = 0x2aa0,
2671 .halt_reg = 0x2fd0,
2674 .enable_reg = 0x2aa0,
2684 .hwcg_reg = 0x2ac0,
2686 .halt_reg = 0x2fd0,
2689 .enable_reg = 0x2ac0,
2699 .hwcg_reg = 0x2ae0,
2701 .halt_reg = 0x2fd0,
2704 .enable_reg = 0x2ae0,
2714 .hwcg_reg = 0x2b00,
2716 .halt_reg = 0x2fd4,
2719 .enable_reg = 0x2b00,
2729 .hwcg_reg = 0x2b20,
2731 .halt_reg = 0x2fd4,
2734 .enable_reg = 0x2b20,
2744 .hwcg_reg = 0x2700,
2746 .halt_reg = 0x2fd4,
2749 .enable_reg = 0x2700,
2759 .halt_reg = 0x2fcc,
2762 .enable_reg = 0x2960,
2772 .halt_reg = 0x2fcc,
2775 .enable_reg = 0x2980,
2785 .hwcg_reg = 0x2900,
2787 .halt_reg = 0x2fc8,
2790 .enable_reg = 0x2900,
2800 .halt_reg = 0x2fc8,
2803 .enable_reg = 0x3700,
2813 .halt_reg = 0x2fc8,
2816 .enable_reg = 0x3720,
2826 .halt_reg = 0x2fcc,
2829 .enable_reg = 0x2920,
2839 .hwcg_reg = 0x2820,
2841 .halt_reg = 0x2fc8,
2844 .enable_reg = 0x2820,
2854 .hwcg_reg = 0x2840,
2856 .halt_reg = 0x2fc8,
2859 .enable_reg = 0x2840,
2869 .hwcg_reg = 0x2860,
2871 .halt_reg = 0x2fc8,
2874 .enable_reg = 0x2860,
2884 .hwcg_reg = 0x2880,
2886 .halt_reg = 0x2fc8,
2889 .enable_reg = 0x2880,
2899 .hwcg_reg = 0x28a0,
2901 .halt_reg = 0x2fc8,
2904 .enable_reg = 0x28a0,
2914 .halt_reg = 0x2fdc,
2918 .enable_reg = 0x3080,
2928 .hwcg_reg = 0x2208,
2930 .halt_reg = 0x2fdc,
2934 .enable_reg = 0x3080,
2951 .ns_reg = 0x36c0,
2957 .src_sel_shift = 0,
2962 .enable_reg = 0x36c0,
2975 .halt_reg = 0x2fdc,
2978 .enable_reg = 0x36cc,
2993 .halt_reg = 0x2fc4,
2996 .enable_reg = 0x36c4,
3011 { 48000000, P_PLL8, 8, 0, 0 },
3012 { 100000000, P_PLL3, 12, 0, 0 },
3017 .ns_reg = 0x2c08,
3023 .src_sel_shift = 0,
3028 .enable_reg = 0x2c08,
3041 .halt_reg = 0x2fdc,
3044 .enable_reg = 0x2c0c,
3059 .halt_reg = 0x2fdc,
3062 .enable_reg = 0x2c10,
3077 .halt_reg = 0x2fdc,
3080 .enable_reg = 0x2c14,
3094 .halt_reg = 0x2fc0,
3097 .enable_reg = 0x2c20,
3107 .halt_reg = 0x2fdc,
3110 .enable_reg = 0x2c00,
3120 .halt_reg = 0x2fc4,
3123 .enable_reg = 0x2480,
3133 .halt_reg = 0x2fcc,
3136 .enable_reg = 0x2c40,
3146 .halt_reg = 0x2fdc,
3149 .enable_reg = 0x22d0,
3159 .halt_reg = 0x2fd4,
3162 .enable_reg = 0x22cc,
3172 .halt_reg = 0x2fc0,
3175 .enable_reg = 0x22c0,
3185 .halt_reg = 0x2fd8,
3189 .enable_reg = 0x3080,
3199 .halt_reg = 0x2fd8,
3203 .enable_reg = 0x3080,
3213 .halt_reg = 0x2fd8,
3217 .enable_reg = 0x3080,
3227 .hwcg_reg = 0x27e0,
3229 .halt_reg = 0x2fd8,
3233 .enable_reg = 0x3080,
3368 [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
3369 [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
3370 [QDSS_STM_RESET] = { 0x2060, 6 },
3371 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3372 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3373 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3374 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3375 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3376 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3377 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3378 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3379 [ADM0_C2_RESET] = { 0x220c, 4},
3380 [ADM0_C1_RESET] = { 0x220c, 3},
3381 [ADM0_C0_RESET] = { 0x220c, 2},
3382 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3383 [ADM0_RESET] = { 0x220c },
3384 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3385 [QDSS_POR_RESET] = { 0x2260, 4 },
3386 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3387 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3388 [QDSS_AXI_RESET] = { 0x2260, 1 },
3389 [QDSS_DBG_RESET] = { 0x2260 },
3390 [PCIE_A_RESET] = { 0x22c0, 7 },
3391 [PCIE_AUX_RESET] = { 0x22c8, 7 },
3392 [PCIE_H_RESET] = { 0x22d0, 7 },
3393 [SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
3394 [SFAB_PCIE_S_RESET] = { 0x22d4 },
3395 [SFAB_MSS_M_RESET] = { 0x2340, 7 },
3396 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3397 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3398 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3399 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3400 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3401 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3402 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3403 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3404 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3405 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3406 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3407 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3408 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3409 [PPSS_PROC_RESET] = { 0x2594, 1 },
3410 [PPSS_RESET] = { 0x2594},
3411 [DMA_BAM_RESET] = { 0x25c0, 7 },
3412 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3413 [SLIMBUS_H_RESET] = { 0x2620, 7 },
3414 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3415 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3416 [TSIF_H_RESET] = { 0x2700, 7 },
3417 [CE1_H_RESET] = { 0x2720, 7 },
3418 [CE1_CORE_RESET] = { 0x2724, 7 },
3419 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3420 [CE2_H_RESET] = { 0x2740, 7 },
3421 [CE2_CORE_RESET] = { 0x2744, 7 },
3422 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3423 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3424 [RPM_PROC_RESET] = { 0x27c0, 7 },
3425 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3426 [SDC1_RESET] = { 0x2830 },
3427 [SDC2_RESET] = { 0x2850 },
3428 [SDC3_RESET] = { 0x2870 },
3429 [SDC4_RESET] = { 0x2890 },
3430 [SDC5_RESET] = { 0x28b0 },
3431 [DFAB_A2_RESET] = { 0x28c0, 7 },
3432 [USB_HS1_RESET] = { 0x2910 },
3433 [USB_HSIC_RESET] = { 0x2934 },
3434 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3435 [USB_FS1_RESET] = { 0x2974 },
3436 [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
3437 [USB_FS2_RESET] = { 0x2994 },
3438 [GSBI1_RESET] = { 0x29dc },
3439 [GSBI2_RESET] = { 0x29fc },
3440 [GSBI3_RESET] = { 0x2a1c },
3441 [GSBI4_RESET] = { 0x2a3c },
3442 [GSBI5_RESET] = { 0x2a5c },
3443 [GSBI6_RESET] = { 0x2a7c },
3444 [GSBI7_RESET] = { 0x2a9c },
3445 [GSBI8_RESET] = { 0x2abc },
3446 [GSBI9_RESET] = { 0x2adc },
3447 [GSBI10_RESET] = { 0x2afc },
3448 [GSBI11_RESET] = { 0x2b1c },
3449 [GSBI12_RESET] = { 0x2b3c },
3450 [SPDM_RESET] = { 0x2b6c },
3451 [TLMM_H_RESET] = { 0x2ba0, 7 },
3452 [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
3453 [MSS_SLP_RESET] = { 0x2c60, 7 },
3454 [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
3455 [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
3456 [MSS_RESET] = { 0x2c64 },
3457 [SATA_H_RESET] = { 0x2c80, 7 },
3458 [SATA_RXOOB_RESE] = { 0x2c8c, 7 },
3459 [SATA_PMALIVE_RESET] = { 0x2c90, 7 },
3460 [SATA_SFAB_M_RESET] = { 0x2c98, 7 },
3461 [TSSC_RESET] = { 0x2ca0, 7 },
3462 [PDM_RESET] = { 0x2cc0, 12 },
3463 [MPM_H_RESET] = { 0x2da0, 7 },
3464 [MPM_RESET] = { 0x2da4 },
3465 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3466 [PRNG_RESET] = { 0x2e80, 12 },
3467 [RIVA_RESET] = { 0x35e0 },
3584 [QDSS_STM_RESET] = { 0x2060, 6 },
3585 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3586 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3587 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3588 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3589 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3590 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3591 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3592 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3593 [ADM0_C2_RESET] = { 0x220c, 4},
3594 [ADM0_C1_RESET] = { 0x220c, 3},
3595 [ADM0_C0_RESET] = { 0x220c, 2},
3596 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3597 [ADM0_RESET] = { 0x220c },
3598 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3599 [QDSS_POR_RESET] = { 0x2260, 4 },
3600 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3601 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3602 [QDSS_AXI_RESET] = { 0x2260, 1 },
3603 [QDSS_DBG_RESET] = { 0x2260 },
3604 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3605 [SFAB_PCIE_S_RESET] = { 0x22d8 },
3606 [PCIE_EXT_PCI_RESET] = { 0x22dc, 6 },
3607 [PCIE_PHY_RESET] = { 0x22dc, 5 },
3608 [PCIE_PCI_RESET] = { 0x22dc, 4 },
3609 [PCIE_POR_RESET] = { 0x22dc, 3 },
3610 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
3611 [PCIE_ACLK_RESET] = { 0x22dc },
3612 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3613 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3614 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3615 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3616 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3617 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3618 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3619 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3620 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3621 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3622 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3623 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3624 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3625 [PPSS_PROC_RESET] = { 0x2594, 1 },
3626 [PPSS_RESET] = { 0x2594},
3627 [DMA_BAM_RESET] = { 0x25c0, 7 },
3628 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3629 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3630 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3631 [TSIF_H_RESET] = { 0x2700, 7 },
3632 [CE1_H_RESET] = { 0x2720, 7 },
3633 [CE1_CORE_RESET] = { 0x2724, 7 },
3634 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3635 [CE2_H_RESET] = { 0x2740, 7 },
3636 [CE2_CORE_RESET] = { 0x2744, 7 },
3637 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3638 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3639 [RPM_PROC_RESET] = { 0x27c0, 7 },
3640 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3641 [SDC1_RESET] = { 0x2830 },
3642 [SDC2_RESET] = { 0x2850 },
3643 [SDC3_RESET] = { 0x2870 },
3644 [SDC4_RESET] = { 0x2890 },
3645 [USB_HS1_RESET] = { 0x2910 },
3646 [USB_HSIC_RESET] = { 0x2934 },
3647 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3648 [USB_FS1_RESET] = { 0x2974 },
3649 [GSBI1_RESET] = { 0x29dc },
3650 [GSBI2_RESET] = { 0x29fc },
3651 [GSBI3_RESET] = { 0x2a1c },
3652 [GSBI4_RESET] = { 0x2a3c },
3653 [GSBI5_RESET] = { 0x2a5c },
3654 [GSBI6_RESET] = { 0x2a7c },
3655 [GSBI7_RESET] = { 0x2a9c },
3656 [SPDM_RESET] = { 0x2b6c },
3657 [TLMM_H_RESET] = { 0x2ba0, 7 },
3658 [SATA_SFAB_M_RESET] = { 0x2c18 },
3659 [SATA_RESET] = { 0x2c1c },
3660 [GSS_SLP_RESET] = { 0x2c60, 7 },
3661 [GSS_RESET] = { 0x2c64 },
3662 [TSSC_RESET] = { 0x2ca0, 7 },
3663 [PDM_RESET] = { 0x2cc0, 12 },
3664 [MPM_H_RESET] = { 0x2da0, 7 },
3665 [MPM_RESET] = { 0x2da4 },
3666 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3667 [PRNG_RESET] = { 0x2e80, 12 },
3668 [RIVA_RESET] = { 0x35e0 },
3669 [CE3_H_RESET] = { 0x36c4, 7 },
3670 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3671 [SFAB_CE3_S_RESET] = { 0x36c8 },
3672 [CE3_RESET] = { 0x36cc, 7 },
3673 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
3674 [USB_HS3_RESET] = { 0x3710 },
3675 [USB_HS4_RESET] = { 0x3730 },
3682 .max_register = 0x3660,
3690 .max_register = 0x3880,
3741 if (of_get_available_child_count(pdev->dev.of_node) != 0) in gcc_msm8960_probe()
3745 NULL, 0); in gcc_msm8960_probe()
3751 return 0; in gcc_msm8960_probe()