Lines Matching +full:0 +full:x2e00
42 } while (0)
50 { S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, },
51 { S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, },
52 { S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, },
53 { S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, },
54 { S5H1411_I2C_TOP_ADDR, 0x1f, 0x342c, },
55 { S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, },
56 { S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, },
57 { S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, },
58 { S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, },
59 { S5H1411_I2C_TOP_ADDR, 0x28, 0x070f, },
60 { S5H1411_I2C_TOP_ADDR, 0x29, 0x2820, },
61 { S5H1411_I2C_TOP_ADDR, 0x2a, 0x102e, },
62 { S5H1411_I2C_TOP_ADDR, 0x2b, 0x0220, },
63 { S5H1411_I2C_TOP_ADDR, 0x2e, 0x0d0e, },
64 { S5H1411_I2C_TOP_ADDR, 0x2f, 0x1013, },
65 { S5H1411_I2C_TOP_ADDR, 0x31, 0x171b, },
66 { S5H1411_I2C_TOP_ADDR, 0x32, 0x0e0f, },
67 { S5H1411_I2C_TOP_ADDR, 0x33, 0x0f10, },
68 { S5H1411_I2C_TOP_ADDR, 0x34, 0x170e, },
69 { S5H1411_I2C_TOP_ADDR, 0x35, 0x4b10, },
70 { S5H1411_I2C_TOP_ADDR, 0x36, 0x0f17, },
71 { S5H1411_I2C_TOP_ADDR, 0x3c, 0x1577, },
72 { S5H1411_I2C_TOP_ADDR, 0x3d, 0x081a, },
73 { S5H1411_I2C_TOP_ADDR, 0x3e, 0x77ee, },
74 { S5H1411_I2C_TOP_ADDR, 0x40, 0x1e09, },
75 { S5H1411_I2C_TOP_ADDR, 0x41, 0x0f0c, },
76 { S5H1411_I2C_TOP_ADDR, 0x42, 0x1f10, },
77 { S5H1411_I2C_TOP_ADDR, 0x4d, 0x0509, },
78 { S5H1411_I2C_TOP_ADDR, 0x4e, 0x0a00, },
79 { S5H1411_I2C_TOP_ADDR, 0x50, 0x0000, },
80 { S5H1411_I2C_TOP_ADDR, 0x5b, 0x0000, },
81 { S5H1411_I2C_TOP_ADDR, 0x5c, 0x0008, },
82 { S5H1411_I2C_TOP_ADDR, 0x57, 0x1101, },
83 { S5H1411_I2C_TOP_ADDR, 0x65, 0x007c, },
84 { S5H1411_I2C_TOP_ADDR, 0x68, 0x0512, },
85 { S5H1411_I2C_TOP_ADDR, 0x69, 0x0258, },
86 { S5H1411_I2C_TOP_ADDR, 0x70, 0x0004, },
87 { S5H1411_I2C_TOP_ADDR, 0x71, 0x0007, },
88 { S5H1411_I2C_TOP_ADDR, 0x76, 0x00a9, },
89 { S5H1411_I2C_TOP_ADDR, 0x78, 0x3141, },
90 { S5H1411_I2C_TOP_ADDR, 0x7a, 0x3141, },
91 { S5H1411_I2C_TOP_ADDR, 0xb3, 0x8003, },
92 { S5H1411_I2C_TOP_ADDR, 0xb5, 0xa6bb, },
93 { S5H1411_I2C_TOP_ADDR, 0xb6, 0x0609, },
94 { S5H1411_I2C_TOP_ADDR, 0xb7, 0x2f06, },
95 { S5H1411_I2C_TOP_ADDR, 0xb8, 0x003f, },
96 { S5H1411_I2C_TOP_ADDR, 0xb9, 0x2700, },
97 { S5H1411_I2C_TOP_ADDR, 0xba, 0xfac8, },
98 { S5H1411_I2C_TOP_ADDR, 0xbe, 0x1003, },
99 { S5H1411_I2C_TOP_ADDR, 0xbf, 0x103f, },
100 { S5H1411_I2C_TOP_ADDR, 0xce, 0x2000, },
101 { S5H1411_I2C_TOP_ADDR, 0xcf, 0x0800, },
102 { S5H1411_I2C_TOP_ADDR, 0xd0, 0x0800, },
103 { S5H1411_I2C_TOP_ADDR, 0xd1, 0x0400, },
104 { S5H1411_I2C_TOP_ADDR, 0xd2, 0x0800, },
105 { S5H1411_I2C_TOP_ADDR, 0xd3, 0x2000, },
106 { S5H1411_I2C_TOP_ADDR, 0xd4, 0x3000, },
107 { S5H1411_I2C_TOP_ADDR, 0xdb, 0x4a9b, },
108 { S5H1411_I2C_TOP_ADDR, 0xdc, 0x1000, },
109 { S5H1411_I2C_TOP_ADDR, 0xde, 0x0001, },
110 { S5H1411_I2C_TOP_ADDR, 0xdf, 0x0000, },
111 { S5H1411_I2C_TOP_ADDR, 0xe3, 0x0301, },
112 { S5H1411_I2C_QAM_ADDR, 0xf3, 0x0000, },
113 { S5H1411_I2C_QAM_ADDR, 0xf3, 0x0001, },
114 { S5H1411_I2C_QAM_ADDR, 0x08, 0x0600, },
115 { S5H1411_I2C_QAM_ADDR, 0x18, 0x4201, },
116 { S5H1411_I2C_QAM_ADDR, 0x1e, 0x6476, },
117 { S5H1411_I2C_QAM_ADDR, 0x21, 0x0830, },
118 { S5H1411_I2C_QAM_ADDR, 0x0c, 0x5679, },
119 { S5H1411_I2C_QAM_ADDR, 0x0d, 0x579b, },
120 { S5H1411_I2C_QAM_ADDR, 0x24, 0x0102, },
121 { S5H1411_I2C_QAM_ADDR, 0x31, 0x7488, },
122 { S5H1411_I2C_QAM_ADDR, 0x32, 0x0a08, },
123 { S5H1411_I2C_QAM_ADDR, 0x3d, 0x8689, },
124 { S5H1411_I2C_QAM_ADDR, 0x49, 0x0048, },
125 { S5H1411_I2C_QAM_ADDR, 0x57, 0x2012, },
126 { S5H1411_I2C_QAM_ADDR, 0x5d, 0x7676, },
127 { S5H1411_I2C_QAM_ADDR, 0x04, 0x0400, },
128 { S5H1411_I2C_QAM_ADDR, 0x58, 0x00c0, },
129 { S5H1411_I2C_QAM_ADDR, 0x5b, 0x0100, },
137 { 0x39f, 300, },
138 { 0x39b, 295, },
139 { 0x397, 290, },
140 { 0x394, 285, },
141 { 0x38f, 280, },
142 { 0x38b, 275, },
143 { 0x387, 270, },
144 { 0x382, 265, },
145 { 0x37d, 260, },
146 { 0x377, 255, },
147 { 0x370, 250, },
148 { 0x36a, 245, },
149 { 0x364, 240, },
150 { 0x35b, 235, },
151 { 0x353, 230, },
152 { 0x349, 225, },
153 { 0x340, 220, },
154 { 0x337, 215, },
155 { 0x327, 210, },
156 { 0x31b, 205, },
157 { 0x310, 200, },
158 { 0x302, 195, },
159 { 0x2f3, 190, },
160 { 0x2e4, 185, },
161 { 0x2d7, 180, },
162 { 0x2cd, 175, },
163 { 0x2bb, 170, },
164 { 0x2a9, 165, },
165 { 0x29e, 160, },
166 { 0x284, 155, },
167 { 0x27a, 150, },
168 { 0x260, 145, },
169 { 0x23a, 140, },
170 { 0x224, 135, },
171 { 0x213, 130, },
172 { 0x204, 125, },
173 { 0x1fe, 120, },
174 { 0, 0, },
182 { 0x0001, 0, },
183 { 0x0af0, 300, },
184 { 0x0d80, 290, },
185 { 0x10a0, 280, },
186 { 0x14b5, 270, },
187 { 0x1590, 268, },
188 { 0x1680, 266, },
189 { 0x17b0, 264, },
190 { 0x18c0, 262, },
191 { 0x19b0, 260, },
192 { 0x1ad0, 258, },
193 { 0x1d00, 256, },
194 { 0x1da0, 254, },
195 { 0x1ef0, 252, },
196 { 0x2050, 250, },
197 { 0x20f0, 249, },
198 { 0x21d0, 248, },
199 { 0x22b0, 247, },
200 { 0x23a0, 246, },
201 { 0x2470, 245, },
202 { 0x24f0, 244, },
203 { 0x25a0, 243, },
204 { 0x26c0, 242, },
205 { 0x27b0, 241, },
206 { 0x28d0, 240, },
207 { 0x29b0, 239, },
208 { 0x2ad0, 238, },
209 { 0x2ba0, 237, },
210 { 0x2c80, 236, },
211 { 0x2d20, 235, },
212 { 0x2e00, 234, },
213 { 0x2f10, 233, },
214 { 0x3050, 232, },
215 { 0x3190, 231, },
216 { 0x3300, 230, },
217 { 0x3340, 229, },
218 { 0x3200, 228, },
219 { 0x3550, 227, },
220 { 0x3610, 226, },
221 { 0x3600, 225, },
222 { 0x3700, 224, },
223 { 0x3800, 223, },
224 { 0x3920, 222, },
225 { 0x3a20, 221, },
226 { 0x3b30, 220, },
227 { 0x3d00, 219, },
228 { 0x3e00, 218, },
229 { 0x4000, 217, },
230 { 0x4100, 216, },
231 { 0x4300, 215, },
232 { 0x4400, 214, },
233 { 0x4600, 213, },
234 { 0x4700, 212, },
235 { 0x4800, 211, },
236 { 0x4a00, 210, },
237 { 0x4b00, 209, },
238 { 0x4d00, 208, },
239 { 0x4f00, 207, },
240 { 0x5050, 206, },
241 { 0x5200, 205, },
242 { 0x53c0, 204, },
243 { 0x5450, 203, },
244 { 0x5650, 202, },
245 { 0x5820, 201, },
246 { 0x6000, 200, },
247 { 0xffff, 0, },
255 { 0x0001, 0, },
256 { 0x0970, 400, },
257 { 0x0a90, 390, },
258 { 0x0b90, 380, },
259 { 0x0d90, 370, },
260 { 0x0ff0, 360, },
261 { 0x1240, 350, },
262 { 0x1345, 348, },
263 { 0x13c0, 346, },
264 { 0x14c0, 344, },
265 { 0x1500, 342, },
266 { 0x1610, 340, },
267 { 0x1700, 338, },
268 { 0x1800, 336, },
269 { 0x18b0, 334, },
270 { 0x1900, 332, },
271 { 0x1ab0, 330, },
272 { 0x1bc0, 328, },
273 { 0x1cb0, 326, },
274 { 0x1db0, 324, },
275 { 0x1eb0, 322, },
276 { 0x2030, 320, },
277 { 0x2200, 318, },
278 { 0x2280, 316, },
279 { 0x2410, 314, },
280 { 0x25b0, 312, },
281 { 0x27a0, 310, },
282 { 0x2840, 308, },
283 { 0x29d0, 306, },
284 { 0x2b10, 304, },
285 { 0x2d30, 302, },
286 { 0x2f20, 300, },
287 { 0x30c0, 298, },
288 { 0x3260, 297, },
289 { 0x32c0, 296, },
290 { 0x3300, 295, },
291 { 0x33b0, 294, },
292 { 0x34b0, 293, },
293 { 0x35a0, 292, },
294 { 0x3650, 291, },
295 { 0x3800, 290, },
296 { 0x3900, 289, },
297 { 0x3a50, 288, },
298 { 0x3b30, 287, },
299 { 0x3cb0, 286, },
300 { 0x3e20, 285, },
301 { 0x3fa0, 284, },
302 { 0x40a0, 283, },
303 { 0x41c0, 282, },
304 { 0x42f0, 281, },
305 { 0x44a0, 280, },
306 { 0x4600, 279, },
307 { 0x47b0, 278, },
308 { 0x4900, 277, },
309 { 0x4a00, 276, },
310 { 0x4ba0, 275, },
311 { 0x4d00, 274, },
312 { 0x4f00, 273, },
313 { 0x5000, 272, },
314 { 0x51f0, 272, },
315 { 0x53a0, 270, },
316 { 0x5520, 269, },
317 { 0x5700, 268, },
318 { 0x5800, 267, },
319 { 0x5a00, 266, },
320 { 0x5c00, 265, },
321 { 0x5d00, 264, },
322 { 0x5f00, 263, },
323 { 0x6000, 262, },
324 { 0x6200, 261, },
325 { 0x6400, 260, },
326 { 0xffff, 0, },
334 u8 buf[] = { reg, data >> 8, data & 0xff }; in s5h1411_writereg()
336 struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = 3 }; in s5h1411_writereg()
341 printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, ret == %i)\n", in s5h1411_writereg()
344 return (ret != 1) ? -1 : 0; in s5h1411_writereg()
351 u8 b1[] = { 0, 0 }; in s5h1411_readreg()
354 { .addr = addr, .flags = 0, .buf = b0, .len = 1 }, in s5h1411_readreg()
362 return (b1[0] << 8) | b1[1]; in s5h1411_readreg()
371 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 0); in s5h1411_softreset()
372 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 1); in s5h1411_softreset()
373 return 0; in s5h1411_softreset()
384 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x10d5); in s5h1411_set_if_freq()
385 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x5342); in s5h1411_set_if_freq()
386 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x10d9); in s5h1411_set_if_freq()
389 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1225); in s5h1411_set_if_freq()
390 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x1e96); in s5h1411_set_if_freq()
391 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1225); in s5h1411_set_if_freq()
394 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x14bc); in s5h1411_set_if_freq()
395 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0xb53e); in s5h1411_set_if_freq()
396 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x14bd); in s5h1411_set_if_freq()
404 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1be4); in s5h1411_set_if_freq()
405 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x3655); in s5h1411_set_if_freq()
406 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1be4); in s5h1411_set_if_freq()
412 return 0; in s5h1411_set_if_freq()
422 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbe) & 0xcfff; in s5h1411_set_mpeg_timing()
425 val |= 0x0000; in s5h1411_set_mpeg_timing()
429 val |= 0x1000; in s5h1411_set_mpeg_timing()
432 val |= 0x2000; in s5h1411_set_mpeg_timing()
435 val |= 0x3000; in s5h1411_set_mpeg_timing()
442 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbe, val); in s5h1411_set_mpeg_timing()
451 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x24) & ~0x1000; in s5h1411_set_spectralinversion()
454 val |= 0x1000; /* Inverted */ in s5h1411_set_spectralinversion()
457 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x24, val); in s5h1411_set_spectralinversion()
466 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbd) & ~0x100; in s5h1411_set_serialmode()
469 val |= 0x100; in s5h1411_set_serialmode()
471 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbd, val); in s5h1411_set_serialmode()
479 dprintk("%s(0x%08x)\n", __func__, m); in s5h1411_enable_modulation()
481 if ((state->first_tune == 0) && (m == state->current_modulation)) { in s5h1411_enable_modulation()
484 return 0; in s5h1411_enable_modulation()
491 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x71); in s5h1411_enable_modulation()
492 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x00); in s5h1411_enable_modulation()
493 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0xf1); in s5h1411_enable_modulation()
500 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x0171); in s5h1411_enable_modulation()
501 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x0001); in s5h1411_enable_modulation()
502 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x16, 0x1101); in s5h1411_enable_modulation()
503 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0x00f0); in s5h1411_enable_modulation()
511 state->first_tune = 0; in s5h1411_enable_modulation()
514 return 0; in s5h1411_enable_modulation()
524 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1); in s5h1411_i2c_gate_ctrl()
526 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 0); in s5h1411_i2c_gate_ctrl()
536 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xe0) & ~0x02; in s5h1411_set_gpio()
539 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0, in s5h1411_set_gpio()
540 val | 0x02); in s5h1411_set_gpio()
542 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0, val); in s5h1411_set_gpio()
552 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 1); in s5h1411_set_powerstate()
554 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 0); in s5h1411_set_powerstate()
558 return 0; in s5h1411_set_powerstate()
572 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf3, 0); in s5h1411_register_reset()
596 fe->ops.i2c_gate_ctrl(fe, 0); in s5h1411_set_frontend()
603 return 0; in s5h1411_set_frontend()
615 s5h1411_set_powerstate(fe, 0); in s5h1411_init()
618 for (i = 0; i < ARRAY_SIZE(init_tab); i++) in s5h1411_init()
636 s5h1411_set_serialmode(fe, 0); in s5h1411_init()
645 s5h1411_i2c_gate_ctrl(fe, 0); in s5h1411_init()
647 return 0; in s5h1411_init()
654 u32 tuner_status = 0; in s5h1411_read_status()
656 *status = 0; in s5h1411_read_status()
663 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf0); in s5h1411_read_status()
664 if (reg & 0x10) /* QAM FEC Lock */ in s5h1411_read_status()
666 if (reg & 0x100) /* QAM EQ Lock */ in s5h1411_read_status()
671 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf2); in s5h1411_read_status()
672 if (reg & 0x1000) /* FEC Lock */ in s5h1411_read_status()
674 if (reg & 0x2000) /* EQ Lock */ in s5h1411_read_status()
677 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x53); in s5h1411_read_status()
678 if (reg & 0x1) /* AFC Lock */ in s5h1411_read_status()
700 fe->ops.i2c_gate_ctrl(fe, 0); in s5h1411_read_status()
707 dprintk("%s() status 0x%08x\n", __func__, *status); in s5h1411_read_status()
709 return 0; in s5h1411_read_status()
717 for (i = 0; i < ARRAY_SIZE(qam256_snr_tab); i++) { in s5h1411_qam256_lookup_snr()
720 ret = 0; in s5h1411_qam256_lookup_snr()
732 for (i = 0; i < ARRAY_SIZE(qam64_snr_tab); i++) { in s5h1411_qam64_lookup_snr()
735 ret = 0; in s5h1411_qam64_lookup_snr()
747 for (i = 0; i < ARRAY_SIZE(vsb_snr_tab); i++) { in s5h1411_vsb_lookup_snr()
750 ret = 0; in s5h1411_vsb_lookup_snr()
766 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1); in s5h1411_read_snr()
769 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1); in s5h1411_read_snr()
773 0xf2) & 0x3ff; in s5h1411_read_snr()
796 *signal_strength = 0; in s5h1411_read_signal_strength()
798 if (0 == ret) { in s5h1411_read_signal_strength()
807 * scale the range 0 - 35*2^24 into 0 - 65535*/ in s5h1411_read_signal_strength()
808 if (tmp >= 8960 * 0x10000) in s5h1411_read_signal_strength()
809 *signal_strength = 0xffff; in s5h1411_read_signal_strength()
821 *ucblocks = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xc9); in s5h1411_read_ucblocks()
823 return 0; in s5h1411_read_ucblocks()
839 return 0; in s5h1411_get_frontend()
846 return 0; in s5h1411_get_tune_settings()
875 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x05); in s5h1411_attach()
876 if (reg != 0x0066) in s5h1411_attach()
885 if (s5h1411_init(&state->frontend) != 0) { in s5h1411_attach()
892 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1); in s5h1411_attach()