| 3a52d587 | 23-Sep-2026 |
Timur Kristóf <timur.kristof@gmail.com> |
drm/amd/display: Mark DCE 6.4 as not APU
DCE 6.4 is found in Oland chips, which were advertised as low-end gaming GPUs in 2013~2015 and then have been sold as low-end workstation GPUs until 2017~201
drm/amd/display: Mark DCE 6.4 as not APU
DCE 6.4 is found in Oland chips, which were advertised as low-end gaming GPUs in 2013~2015 and then have been sold as low-end workstation GPUs until 2017~2019.
These are not APUs.
Fixes: 7c15fd86aaec ("drm/amd/display: dc/dce: add initial DCE6 support (v10)") Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://patch.msgid.link/20260923122033.1046651-3-timur.kristof@gmail.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 1072aa811ea1e61d5f763e4ec1bc6d24bb61f14a) Cc: stable@vger.kernel.org
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| 687d31ea | 23-Sep-2026 |
Timur Kristóf <timur.kristof@gmail.com> |
drm/amd/display: Fix fast updates on DCE 8.1
DCE8 should use legacy fast updates. This was already set for DCE 8.0 and 8.3, but it seems that DCE 8.1 (found in Kaveri chips) was forgotten.
This fix
drm/amd/display: Fix fast updates on DCE 8.1
DCE8 should use legacy fast updates. This was already set for DCE 8.0 and 8.3, but it seems that DCE 8.1 (found in Kaveri chips) was forgotten.
This fix should be backported to all kernel versions that have "Refactor fast update to use new HWSS build sequence", but this patch won't apply cleanly to older kernels due to another refactor in "Remove dc param from check_update".
Fixes: 0baae6246307 ("drm/amd/display: Refactor fast update to use new HWSS build sequence") Fixes: 9ec11bb842b6 ("drm/amd/display: Remove dc param from check_update") Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://patch.msgid.link/20260923122033.1046651-2-timur.kristof@gmail.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 57605379559e3b5044c8274a1010ec658e5e73af) Cc: stable@vger.kernel.org
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| 28ec6494 | 10-Jul-2026 |
Andriy Korud <a.korud@gmail.com> |
drm/amd/display: dce100: skip non-DP stream encoders for DP MST
On DCE8-class ASICs (e.g. Bonaire), the resource pool contains digital DIG stream encoders plus one analog DAC encoder. When assigning
drm/amd/display: dce100: skip non-DP stream encoders for DP MST
On DCE8-class ASICs (e.g. Bonaire), the resource pool contains digital DIG stream encoders plus one analog DAC encoder. When assigning a stream encoder for a second DisplayPort MST stream, if the preferred digital encoder is already acquired, dce100_find_first_free_match_stream_enc_for_link() falls back to the first free pool entry. That entry may be the analog encoder, whose funcs table lacks DP hooks such as dp_set_stream_attribute. The subsequent atomic commit then dereferences NULL function pointers in link_set_dpms_on() and crashes.
Skip encoders without dp_set_stream_attribute when the stream uses a DP signal (including MST). Use dc_is_dp_signal(stream->signal) for the MST fallback path instead of checking only the link connector signal.
Tested on: - GPU: AMD Radeon R7 260X (Bonaire / DCE8) - Board: Supermicro C9X299-PG300 - Setup: DP MST daisy chain, hotplug second monitor or have it connected on boot - Kernel: 7.1.3 (issue observed since 6.19) - Result: kernel oops without patch; dual monitors stable with patch
Signed-off-by: Andriy Korud <a.korud@gmail.com> Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5162 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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| 183bbded | 03-Jul-2026 |
Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> |
drm/amd/display: fix dcn42b det allocation order
set_pipe_unlock_order needs to be set to true for the pipes to be unlocked in correct order to avoid det overallocation
Reviewed-by: Charlene Liu <c
drm/amd/display: fix dcn42b det allocation order
set_pipe_unlock_order needs to be set to true for the pipes to be unlocked in correct order to avoid det overallocation
Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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| 4fb6f596 | 29-Jun-2026 |
Leo Chen <leo.chen@amd.com> |
drm/amd/display: Enable HUBP/DPP Driver PG for DCN42
[Why & How] The related corruption issue is now resolved, HUBP/DPP driver PG can be enabled for DCN42.
Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.b
drm/amd/display: Enable HUBP/DPP Driver PG for DCN42
[Why & How] The related corruption issue is now resolved, HUBP/DPP driver PG can be enabled for DCN42.
Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Leo Chen <leo.chen@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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| cee2f77c | 24-Jun-2026 |
James Lin <PingLei.Lin@amd.com> |
drm/amd/display: Add MALL status readback support for DCN 4.0.1
[why] The IGT test igt@amdgpu/amd_mall@static-screen always fails on DCN 4.0.1 because debugfs reports "mall enabled: no" even when M
drm/amd/display: Add MALL status readback support for DCN 4.0.1
[why] The IGT test igt@amdgpu/amd_mall@static-screen always fails on DCN 4.0.1 because debugfs reports "mall enabled: no" even when MALL is actually active. This is because the DCN 4.0.1 hubbub function table is missing the .get_mall_en callback, so capabilities_show() always sees mall_in_use as false.
[how] Reuse hubbub32_get_mall_en() for DCN 4.0.1 since the DCHUBBUB_ARB_MALL_CNTL register layout is identical to DCN 3.2: - Register the DCHUBBUB_ARB_MALL_CNTL register offset in dcn401_resource.h - Add MALL_PREFETCH_COMPLETE and MALL_IN_USE mask/shift definitions in dcn401_hubbub.h - Wire up .get_mall_en = hubbub32_get_mall_en in hubbub4_01_funcs
Reviewed-by: ChiaHsuan (Tom) Chung <chiahsuan.chung@amd.com> Signed-off-by: James Lin <PingLei.Lin@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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| 219fb1f4 | 10-Jun-2026 |
Gabe Teeger <gabe.teeger@amd.com> |
drm/amd/display: Enable zstate support and fix seamless boot
[Why & How] Port seamless boot fix from DCN42 to DCN42B and enable zstate support for DCN42B.
Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bu
drm/amd/display: Enable zstate support and fix seamless boot
[Why & How] Port seamless boot fix from DCN42 to DCN42B and enable zstate support for DCN42B.
Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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| b7d69145 | 04-Jun-2026 |
Matthew Stewart <Matthew.Stewart2@amd.com> |
drm/amd/display: Fix DCN42B null registers & register masks
[why]
DCN42B is missing some register masks, which are causing errors in dmesg.
[how]
Make DCN42B reuse the DCN42 register lists, and a
drm/amd/display: Fix DCN42B null registers & register masks
[why]
DCN42B is missing some register masks, which are causing errors in dmesg.
[how]
Make DCN42B reuse the DCN42 register lists, and add the missing defines manually.
Fixes: 64142f9d51af ("drm/amd/display: Fix DCN42 null registers & register masks") Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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