1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2024 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 #include <drm/drm_drv.h> 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "mes_userqueue.h" 28 #include "amdgpu_userq_fence.h" 29 #include "amdgpu_trace.h" 30 31 #define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE 32 #define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE 33 34 static int 35 mes_userq_create_wptr_mapping(struct amdgpu_device *adev, 36 struct amdgpu_userq_mgr *uq_mgr, 37 struct amdgpu_usermode_queue *queue, 38 uint64_t wptr) 39 { 40 struct amdgpu_bo_va_mapping *wptr_mapping; 41 struct amdgpu_userq_obj *wptr_obj = &queue->wptr_obj; 42 struct amdgpu_bo *obj; 43 struct amdgpu_vm *vm = queue->vm; 44 struct drm_exec exec; 45 int ret; 46 47 wptr &= AMDGPU_GMC_HOLE_MASK; 48 49 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 2); 50 drm_exec_until_all_locked(&exec) { 51 ret = amdgpu_vm_lock_pd(vm, &exec, 1); 52 drm_exec_retry_on_contention(&exec); 53 if (unlikely(ret)) 54 goto fail_lock; 55 56 wptr_mapping = amdgpu_vm_bo_lookup_mapping(vm, wptr >> PAGE_SHIFT); 57 if (!wptr_mapping) { 58 ret = -EINVAL; 59 goto fail_lock; 60 } 61 62 obj = wptr_mapping->bo_va->base.bo; 63 ret = drm_exec_lock_obj(&exec, &obj->tbo.base); 64 drm_exec_retry_on_contention(&exec); 65 if (unlikely(ret)) 66 goto fail_lock; 67 } 68 69 wptr_obj->obj = amdgpu_bo_ref(wptr_mapping->bo_va->base.bo); 70 if (wptr_obj->obj->tbo.base.size > PAGE_SIZE) { 71 ret = -EINVAL; 72 goto fail_map; 73 } 74 /* Keep WPTR BO under eviction-fence control instead of pinning. */ 75 ret = amdgpu_evf_mgr_attach_fence(&uq_mgr_to_fpriv(uq_mgr)->evf_mgr, wptr_obj->obj); 76 if (ret) { 77 DRM_ERROR("Failed to attach eviction fence to wptr bo. ret %d\n", ret); 78 goto fail_map; 79 } 80 81 ret = amdgpu_ttm_alloc_gart(&wptr_obj->obj->tbo); 82 if (ret) { 83 DRM_ERROR("Failed to bind wptr bo to GART. ret %d\n", ret); 84 goto fail_map; 85 } 86 87 queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset(wptr_obj->obj); 88 89 drm_exec_fini(&exec); 90 return 0; 91 fail_map: 92 amdgpu_bo_unref(&wptr_obj->obj); 93 fail_lock: 94 drm_exec_fini(&exec); 95 return ret; 96 97 } 98 99 static int convert_to_mes_priority(int priority) 100 { 101 switch (priority) { 102 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW: 103 default: 104 return AMDGPU_MES_PRIORITY_LEVEL_NORMAL; 105 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW: 106 return AMDGPU_MES_PRIORITY_LEVEL_LOW; 107 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH: 108 return AMDGPU_MES_PRIORITY_LEVEL_MEDIUM; 109 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH: 110 return AMDGPU_MES_PRIORITY_LEVEL_HIGH; 111 } 112 } 113 114 static int mes_userq_map(struct amdgpu_usermode_queue *queue) 115 { 116 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 117 struct amdgpu_device *adev = uq_mgr->adev; 118 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 119 struct amdgpu_mqd_prop *userq_props = queue->userq_prop; 120 struct mes_add_queue_input queue_input; 121 struct amdgpu_mes *mes = &adev->mes; 122 int r; 123 124 memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input)); 125 126 queue_input.process_va_start = 0; 127 queue_input.process_va_end = adev->vm_manager.max_pfn - 1; 128 129 /* set process quantum to 10 ms and gang quantum to 1 ms as default */ 130 queue_input.process_quantum = 100000; 131 queue_input.gang_quantum = 10000; 132 queue_input.paging = false; 133 134 queue_input.process_context_addr = uq_mgr->proc_ctx_obj.gpu_addr; 135 queue_input.gang_context_addr = ctx->gpu_addr; 136 queue_input.inprocess_gang_priority = AMDGPU_MES_PRIORITY_LEVEL_NORMAL; 137 queue_input.gang_global_priority_level = convert_to_mes_priority(queue->priority); 138 139 queue_input.process_id = queue->vm->pasid; 140 queue_input.queue_type = queue->queue_type; 141 queue_input.mqd_addr = queue->mqd.gpu_addr; 142 queue_input.wptr_addr = userq_props->wptr_gpu_addr; 143 queue_input.queue_size = userq_props->queue_size >> 2; 144 queue_input.doorbell_offset = userq_props->doorbell_index; 145 queue_input.page_table_base_addr = amdgpu_gmc_pd_addr(queue->vm->root.bo); 146 queue_input.wptr_mc_addr = queue->wptr_obj.gpu_addr; 147 if (mes->use_rs64mem) { 148 amdgpu_mes_alloc_proc_ctx_index(mes, queue); 149 queue_input.process_context_array_index = queue->proc_ctx_array_index; 150 amdgpu_mes_alloc_gang_ctx_index(mes, queue); 151 queue_input.gang_context_array_index = queue->gang_ctx_array_index; 152 } 153 amdgpu_mes_lock(&adev->mes); 154 r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input); 155 amdgpu_mes_unlock(&adev->mes); 156 if (r) { 157 DRM_ERROR("Failed to map queue in HW, err (%d)\n", r); 158 return r; 159 } 160 161 DRM_DEBUG_DRIVER("Queue (doorbell:%d) mapped successfully\n", userq_props->doorbell_index); 162 return 0; 163 } 164 165 static int mes_userq_unmap(struct amdgpu_usermode_queue *queue) 166 { 167 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 168 struct amdgpu_device *adev = uq_mgr->adev; 169 struct mes_remove_queue_input queue_input; 170 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 171 struct amdgpu_mes *mes = &adev->mes; 172 int r; 173 174 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input)); 175 queue_input.gang_context_array_index = queue->gang_ctx_array_index; 176 queue_input.doorbell_offset = queue->doorbell_index; 177 queue_input.gang_context_addr = ctx->gpu_addr; 178 queue_input.queue_type = queue->queue_type; 179 180 amdgpu_mes_lock(&adev->mes); 181 r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input); 182 amdgpu_mes_unlock(&adev->mes); 183 if (mes->use_rs64mem) { 184 amdgpu_mes_free_proc_ctx_index(mes, queue); 185 amdgpu_mes_free_gang_ctx_index(mes, queue); 186 } 187 if (r) 188 DRM_ERROR("Failed to unmap queue in HW, err (%d)\n", r); 189 return r; 190 } 191 192 int mes_userq_reset(struct amdgpu_usermode_queue *queue) 193 { 194 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 195 struct amdgpu_device *adev = uq_mgr->adev; 196 struct mes_reset_queue_input queue_input; 197 int r; 198 199 /* XXX: add a FW version check for SDMA per queue reset */ 200 memset(&queue_input, 0x0, sizeof(struct mes_reset_queue_input)); 201 queue_input.doorbell_offset = queue->doorbell_index; 202 queue_input.queue_type = queue->queue_type; 203 204 amdgpu_mes_lock(&adev->mes); 205 r = adev->mes.funcs->reset_hw_queue(&adev->mes, &queue_input); 206 amdgpu_mes_unlock(&adev->mes); 207 if (r) 208 return r; 209 210 /* mes_userq_unmap() does not update queue->state; mark it UNMAPPED so the 211 * destroy path does not issue a second REMOVE_QUEUE for the removed queue. 212 */ 213 r = mes_userq_unmap(queue); 214 if (!r) { 215 trace_amdgpu_userq_state_changed(queue, AMDGPU_USERQ_STATE_UNMAPPED); 216 queue->state = AMDGPU_USERQ_STATE_UNMAPPED; 217 } 218 return r; 219 } 220 221 int mes_userq_reset_queue(struct amdgpu_device *adev, 222 struct amdgpu_usermode_queue *guilty_uq, 223 int queue_type, 224 unsigned int pipe, 225 unsigned int queue, 226 unsigned int db) 227 { 228 struct amdgpu_usermode_queue *uq; 229 bool use_mmio = adev->gfx.mec.use_mmio_for_reset; 230 unsigned long uq_id; 231 int r; 232 233 xa_for_each(&adev->userq_doorbell_xa, uq_id, uq) { 234 if (uq->queue_type == queue_type) { 235 if (uq == guilty_uq) 236 continue; 237 if (uq->doorbell_index == db) { 238 uq->state = AMDGPU_USERQ_STATE_HUNG; 239 if (use_mmio) 240 r = amdgpu_mes_reset_queue_mmio(adev, queue_type, 0, 1, pipe, queue, 0); 241 else 242 r = amdgpu_mes_reset_user_queue(adev, queue_type, db, 0); 243 if (r) 244 return r; 245 r = mes_userq_unmap(uq); 246 if (r) 247 return r; 248 amdgpu_userq_fence_driver_force_completion(uq); 249 break; 250 } 251 } 252 } 253 return 0; 254 } 255 256 static int mes_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr, 257 struct amdgpu_usermode_queue *queue, 258 struct drm_amdgpu_userq_in *mqd_user) 259 { 260 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 261 int r, size; 262 263 /* The FW expects at least one page space allocated for gang ctx. */ 264 size = AMDGPU_USERQ_GANG_CTX_SZ; 265 r = amdgpu_bo_create_kernel(uq_mgr->adev, size, 0, 266 AMDGPU_GEM_DOMAIN_GTT, 267 &ctx->obj, &ctx->gpu_addr, 268 &ctx->cpu_ptr); 269 if (r) { 270 DRM_ERROR("Failed to allocate ctx space bo for userqueue, err:%d\n", r); 271 return r; 272 } 273 274 memset(ctx->cpu_ptr, 0, size); 275 return 0; 276 } 277 278 static int mes_userq_create_proc_ctx_space(struct amdgpu_userq_mgr *uq_mgr) 279 { 280 int r = 0; 281 282 mutex_lock(&uq_mgr->proc_ctx_lock); 283 /* This check is a necessary because amdgpu_bo_create_kernel() 284 * calls helpers like amdgpu_bo_pin() and memset() unconditionally 285 */ 286 if (!uq_mgr->proc_ctx_obj.obj) { 287 r = amdgpu_bo_create_kernel(uq_mgr->adev, AMDGPU_USERQ_PROC_CTX_SZ, 288 0, AMDGPU_GEM_DOMAIN_GTT, 289 &uq_mgr->proc_ctx_obj.obj, 290 &uq_mgr->proc_ctx_obj.gpu_addr, 291 &uq_mgr->proc_ctx_obj.cpu_ptr); 292 293 if (!r) 294 memset(uq_mgr->proc_ctx_obj.cpu_ptr, 0, AMDGPU_USERQ_PROC_CTX_SZ); 295 } 296 297 mutex_unlock(&uq_mgr->proc_ctx_lock); 298 299 return r; 300 } 301 302 static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, 303 struct drm_amdgpu_userq_in *args_in) 304 { 305 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 306 struct amdgpu_device *adev = uq_mgr->adev; 307 struct amdgpu_mqd *mqd_hw_default = &adev->mqds[queue->queue_type]; 308 struct drm_amdgpu_userq_in *mqd_user = args_in; 309 struct amdgpu_mqd_prop *userq_props; 310 int r; 311 312 /* Structure to initialize MQD for userqueue using generic MQD init function */ 313 userq_props = kzalloc_obj(struct amdgpu_mqd_prop); 314 if (!userq_props) { 315 DRM_ERROR("Failed to allocate memory for userq_props\n"); 316 return -ENOMEM; 317 } 318 319 r = amdgpu_bo_create_kernel(adev, 320 AMDGPU_MQD_SIZE_ALIGN(mqd_hw_default->mqd_size), 321 0, AMDGPU_GEM_DOMAIN_GTT, 322 &queue->mqd.obj, &queue->mqd.gpu_addr, 323 &queue->mqd.cpu_ptr); 324 if (r) { 325 DRM_ERROR("Failed to create MQD object for userqueue\n"); 326 goto free_props; 327 } 328 329 memset(queue->mqd.cpu_ptr, 0, 330 AMDGPU_MQD_SIZE_ALIGN(mqd_hw_default->mqd_size)); 331 332 /* Initialize the MQD BO with user given values */ 333 userq_props->wptr_gpu_addr = mqd_user->wptr_va; 334 userq_props->rptr_gpu_addr = mqd_user->rptr_va; 335 userq_props->queue_size = mqd_user->queue_size; 336 userq_props->hqd_base_gpu_addr = mqd_user->queue_va; 337 userq_props->mqd_gpu_addr = queue->mqd.gpu_addr; 338 userq_props->use_doorbell = true; 339 userq_props->doorbell_index = queue->doorbell_index; 340 userq_props->fence_address = queue->fence_drv->gpu_addr; 341 342 if (queue->queue_type == AMDGPU_HW_IP_COMPUTE) { 343 struct drm_amdgpu_userq_mqd_compute_gfx11 *compute_mqd; 344 345 if (mqd_user->mqd_size != sizeof(*compute_mqd)) { 346 DRM_ERROR("Invalid compute IP MQD size\n"); 347 r = -EINVAL; 348 goto free_mqd; 349 } 350 351 compute_mqd = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 352 if (IS_ERR(compute_mqd)) { 353 DRM_ERROR("Failed to read user MQD\n"); 354 r = -ENOMEM; 355 goto free_mqd; 356 } 357 358 r = amdgpu_bo_reserve(queue->vm->root.bo, false); 359 if (r) { 360 kfree(compute_mqd); 361 goto free_mqd; 362 } 363 r = amdgpu_userq_input_va_validate(adev, queue, 364 compute_mqd->eop_va, 2048, 365 &queue->userq_vas.va.eop); 366 amdgpu_bo_unreserve(queue->vm->root.bo); 367 if (r) { 368 kfree(compute_mqd); 369 goto free_mqd; 370 } 371 372 userq_props->eop_gpu_addr = compute_mqd->eop_va; 373 userq_props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL; 374 userq_props->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM; 375 userq_props->hqd_active = false; 376 userq_props->tmz_queue = 377 mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; 378 kfree(compute_mqd); 379 } else if (queue->queue_type == AMDGPU_HW_IP_GFX) { 380 struct drm_amdgpu_userq_mqd_gfx11 *mqd_gfx_v11; 381 struct amdgpu_gfx_shadow_info shadow_info; 382 383 if (adev->gfx.funcs->get_gfx_shadow_info) { 384 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow_info, true); 385 } else { 386 r = -EINVAL; 387 goto free_mqd; 388 } 389 390 if (mqd_user->mqd_size != sizeof(*mqd_gfx_v11) || !mqd_user->mqd) { 391 DRM_ERROR("Invalid GFX MQD\n"); 392 r = -EINVAL; 393 goto free_mqd; 394 } 395 396 mqd_gfx_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 397 if (IS_ERR(mqd_gfx_v11)) { 398 DRM_ERROR("Failed to read user MQD\n"); 399 r = -ENOMEM; 400 goto free_mqd; 401 } 402 403 userq_props->shadow_addr = mqd_gfx_v11->shadow_va; 404 userq_props->csa_addr = mqd_gfx_v11->csa_va; 405 userq_props->tmz_queue = 406 mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; 407 408 r = amdgpu_bo_reserve(queue->vm->root.bo, false); 409 if (r) { 410 kfree(mqd_gfx_v11); 411 goto free_mqd; 412 } 413 r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->shadow_va, 414 shadow_info.shadow_size, 415 &queue->userq_vas.va.shadow); 416 if (r) { 417 amdgpu_bo_unreserve(queue->vm->root.bo); 418 kfree(mqd_gfx_v11); 419 goto free_mqd; 420 } 421 422 r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->csa_va, 423 shadow_info.csa_size, 424 &queue->userq_vas.va.csa); 425 amdgpu_bo_unreserve(queue->vm->root.bo); 426 if (r) { 427 kfree(mqd_gfx_v11); 428 goto free_mqd; 429 } 430 431 kfree(mqd_gfx_v11); 432 } else if (queue->queue_type == AMDGPU_HW_IP_DMA) { 433 struct drm_amdgpu_userq_mqd_sdma_gfx11 *mqd_sdma_v11; 434 435 if (mqd_user->mqd_size != sizeof(*mqd_sdma_v11) || !mqd_user->mqd) { 436 DRM_ERROR("Invalid SDMA MQD\n"); 437 r = -EINVAL; 438 goto free_mqd; 439 } 440 441 mqd_sdma_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 442 if (IS_ERR(mqd_sdma_v11)) { 443 DRM_ERROR("Failed to read sdma user MQD\n"); 444 r = -ENOMEM; 445 goto free_mqd; 446 } 447 448 r = amdgpu_bo_reserve(queue->vm->root.bo, false); 449 if (r) { 450 kfree(mqd_sdma_v11); 451 goto free_mqd; 452 } 453 r = amdgpu_userq_input_va_validate(adev, queue, mqd_sdma_v11->csa_va, 454 32, 455 &queue->userq_vas.va.csa); 456 amdgpu_bo_unreserve(queue->vm->root.bo); 457 if (r) { 458 kfree(mqd_sdma_v11); 459 goto free_mqd; 460 } 461 462 userq_props->csa_addr = mqd_sdma_v11->csa_va; 463 kfree(mqd_sdma_v11); 464 } 465 466 queue->userq_prop = userq_props; 467 468 r = mqd_hw_default->init_mqd(adev, (void *)queue->mqd.cpu_ptr, userq_props); 469 if (r) { 470 DRM_ERROR("Failed to initialize MQD for userqueue\n"); 471 goto free_mqd; 472 } 473 474 /* Create per-process MES process context BO */ 475 r = mes_userq_create_proc_ctx_space(uq_mgr); 476 if (r) { 477 DRM_ERROR("Failed to allocate MES process context space bo, error: %d\n", r); 478 goto free_mqd; 479 } 480 481 /* Create BO of a gang for FW operations */ 482 r = mes_userq_create_ctx_space(uq_mgr, queue, mqd_user); 483 if (r) { 484 DRM_ERROR("Failed to allocate BO for userqueue (%d)", r); 485 goto free_mqd; 486 } 487 488 /* FW expects WPTR BOs to be mapped into GART */ 489 r = mes_userq_create_wptr_mapping(adev, uq_mgr, queue, userq_props->wptr_gpu_addr); 490 if (r) { 491 DRM_ERROR("Failed to create WPTR mapping\n"); 492 goto free_ctx; 493 } 494 495 return 0; 496 497 free_ctx: 498 amdgpu_bo_free_kernel(&queue->fw_obj.obj, &queue->fw_obj.gpu_addr, 499 &queue->fw_obj.cpu_ptr); 500 501 free_mqd: 502 amdgpu_bo_free_kernel(&queue->mqd.obj, &queue->mqd.gpu_addr, 503 &queue->mqd.cpu_ptr); 504 505 free_props: 506 kfree(userq_props); 507 508 return r; 509 } 510 511 static void mes_userq_mqd_destroy(struct amdgpu_usermode_queue *queue) 512 { 513 514 amdgpu_bo_free_kernel(&queue->fw_obj.obj, &queue->fw_obj.gpu_addr, 515 &queue->fw_obj.cpu_ptr); 516 kfree(queue->userq_prop); 517 amdgpu_bo_free_kernel(&queue->mqd.obj, &queue->mqd.gpu_addr, 518 &queue->mqd.cpu_ptr); 519 520 amdgpu_bo_unref(&queue->wptr_obj.obj); 521 } 522 523 static int mes_userq_preempt(struct amdgpu_usermode_queue *queue) 524 { 525 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 526 struct amdgpu_device *adev = uq_mgr->adev; 527 struct mes_suspend_gang_input queue_input; 528 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 529 signed long timeout = 2100000; /* 2100 ms */ 530 u64 fence_gpu_addr; 531 u32 fence_offset; 532 u64 *fence_ptr; 533 int i, r; 534 535 if (queue->state != AMDGPU_USERQ_STATE_MAPPED) 536 return 0; 537 r = amdgpu_wb_get(adev, &fence_offset); 538 if (r) 539 return r; 540 541 fence_gpu_addr = adev->wb.gpu_addr + (fence_offset * 4); 542 fence_ptr = (u64 *)&adev->wb.wb[fence_offset]; 543 *fence_ptr = 0; 544 545 memset(&queue_input, 0x0, sizeof(struct mes_suspend_gang_input)); 546 queue_input.gang_context_addr = ctx->gpu_addr; 547 queue_input.suspend_fence_addr = fence_gpu_addr; 548 queue_input.suspend_fence_value = 1; 549 amdgpu_mes_lock(&adev->mes); 550 r = adev->mes.funcs->suspend_gang(&adev->mes, &queue_input); 551 amdgpu_mes_unlock(&adev->mes); 552 if (r) { 553 DRM_ERROR("Failed to suspend gang: %d\n", r); 554 goto out; 555 } 556 557 for (i = 0; i < timeout; i++) { 558 if (*fence_ptr == 1) 559 goto out; 560 udelay(1); 561 } 562 r = -ETIMEDOUT; 563 564 out: 565 amdgpu_wb_free(adev, fence_offset); 566 return r; 567 } 568 569 static int mes_userq_restore(struct amdgpu_usermode_queue *queue) 570 { 571 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 572 struct amdgpu_device *adev = uq_mgr->adev; 573 struct mes_resume_gang_input queue_input; 574 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 575 int r; 576 577 if (queue->state == AMDGPU_USERQ_STATE_HUNG) 578 return -EINVAL; 579 if (queue->state != AMDGPU_USERQ_STATE_PREEMPTED) 580 return 0; 581 582 memset(&queue_input, 0x0, sizeof(struct mes_resume_gang_input)); 583 queue_input.gang_context_addr = ctx->gpu_addr; 584 585 amdgpu_mes_lock(&adev->mes); 586 r = adev->mes.funcs->resume_gang(&adev->mes, &queue_input); 587 amdgpu_mes_unlock(&adev->mes); 588 if (r) 589 dev_err(adev->dev, "Failed to resume queue, err (%d)\n", r); 590 return r; 591 } 592 593 const struct amdgpu_userq_funcs userq_mes_funcs = { 594 .mqd_create = mes_userq_mqd_create, 595 .mqd_destroy = mes_userq_mqd_destroy, 596 .unmap = mes_userq_unmap, 597 .map = mes_userq_map, 598 .preempt = mes_userq_preempt, 599 .restore = mes_userq_restore, 600 .reset = mes_userq_reset, 601 }; 602