1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gfx_v11_0.h" 30 #include "gc/gc_11_0_0_offset.h" 31 #include "gc/gc_11_0_0_sh_mask.h" 32 #include "gc/gc_11_0_0_default.h" 33 #include "v11_structs.h" 34 #include "mes_v11_api_def.h" 35 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin"); 52 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin"); 53 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes_2.bin"); 54 MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); 55 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin"); 56 MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); 57 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes_2.bin"); 58 MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes1.bin"); 59 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes_2.bin"); 60 MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes1.bin"); 61 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes_2.bin"); 62 MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes1.bin"); 63 MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes_2.bin"); 64 MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes1.bin"); 65 MODULE_FIRMWARE("amdgpu/gc_11_7_1_mes_2.bin"); 66 MODULE_FIRMWARE("amdgpu/gc_11_7_1_mes1.bin"); 67 68 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block); 69 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block); 70 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); 71 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); 72 73 #define MES_EOP_SIZE 2048 74 #define GFX_MES_DRAM_SIZE 0x80000 75 #define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE) 76 77 #define MES11_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset, [4:7] = hqd info */ 78 #define MES11_HUNG_HQD_INFO_OFFSET 4 79 80 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 81 { 82 struct amdgpu_device *adev = ring->adev; 83 84 if (ring->use_doorbell) { 85 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 86 ring->wptr); 87 WDOORBELL64(ring->doorbell_index, ring->wptr); 88 } else { 89 dev_warn_once(adev->dev, "%s requires doorbell!\n", __func__); 90 } 91 } 92 93 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 94 { 95 return *ring->rptr_cpu_addr; 96 } 97 98 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 99 { 100 struct amdgpu_device *adev = ring->adev; 101 u64 wptr; 102 103 if (ring->use_doorbell) { 104 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 105 } else { 106 dev_warn_once(adev->dev, "%s requires doorbell!\n", __func__); 107 wptr = 0; 108 } 109 return wptr; 110 } 111 112 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 113 .type = AMDGPU_RING_TYPE_MES, 114 .align_mask = 1, 115 .nop = 0, 116 .support_64bit_ptrs = true, 117 .get_rptr = mes_v11_0_ring_get_rptr, 118 .get_wptr = mes_v11_0_ring_get_wptr, 119 .set_wptr = mes_v11_0_ring_set_wptr, 120 .insert_nop = amdgpu_ring_insert_nop, 121 }; 122 123 static const char *mes_v11_0_opcodes[] = { 124 "SET_HW_RSRC", 125 "SET_SCHEDULING_CONFIG", 126 "ADD_QUEUE", 127 "REMOVE_QUEUE", 128 "PERFORM_YIELD", 129 "SET_GANG_PRIORITY_LEVEL", 130 "SUSPEND", 131 "RESUME", 132 "RESET", 133 "SET_LOG_BUFFER", 134 "CHANGE_GANG_PRORITY", 135 "QUERY_SCHEDULER_STATUS", 136 "PROGRAM_GDS", 137 "SET_DEBUG_VMID", 138 "MISC", 139 "UPDATE_ROOT_PAGE_TABLE", 140 "AMD_LOG", 141 "unused", 142 "unused", 143 "SET_HW_RSRC_1", 144 }; 145 146 static const char *mes_v11_0_misc_opcodes[] = { 147 "WRITE_REG", 148 "INV_GART", 149 "QUERY_STATUS", 150 "READ_REG", 151 "WAIT_REG_MEM", 152 "SET_SHADER_DEBUGGER", 153 }; 154 155 static const char *mes_v11_0_get_op_string(union MESAPI__MISC *x_pkt) 156 { 157 const char *op_str = NULL; 158 159 if (x_pkt->header.opcode < ARRAY_SIZE(mes_v11_0_opcodes)) 160 op_str = mes_v11_0_opcodes[x_pkt->header.opcode]; 161 162 return op_str; 163 } 164 165 static const char *mes_v11_0_get_misc_op_string(union MESAPI__MISC *x_pkt) 166 { 167 const char *op_str = NULL; 168 169 if ((x_pkt->header.opcode == MES_SCH_API_MISC) && 170 (x_pkt->opcode < ARRAY_SIZE(mes_v11_0_misc_opcodes))) 171 op_str = mes_v11_0_misc_opcodes[x_pkt->opcode]; 172 173 return op_str; 174 } 175 176 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 177 void *pkt, int size, 178 int api_status_off) 179 { 180 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 181 signed long timeout = 2100000; /* 2100 ms */ 182 struct amdgpu_device *adev = mes->adev; 183 struct amdgpu_ring *ring = &mes->ring[0]; 184 struct MES_API_STATUS *api_status; 185 union MESAPI__MISC *x_pkt = pkt; 186 const char *op_str, *misc_op_str; 187 unsigned long flags; 188 u64 status_gpu_addr; 189 u32 seq, status_offset; 190 u64 *status_ptr; 191 signed long r; 192 int ret; 193 194 if (x_pkt->header.opcode >= MES_SCH_API_MAX) 195 return -EINVAL; 196 197 if (amdgpu_emu_mode) { 198 timeout *= 100; 199 } else if (amdgpu_sriov_vf(adev)) { 200 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 201 timeout = 15 * 600 * 1000; 202 } 203 204 ret = amdgpu_wb_get(adev, &status_offset); 205 if (ret) 206 return ret; 207 208 status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); 209 status_ptr = (u64 *)&adev->wb.wb[status_offset]; 210 *status_ptr = 0; 211 212 spin_lock_irqsave(&mes->ring_lock[0], flags); 213 r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); 214 if (r) 215 goto error_unlock_free; 216 217 seq = ++ring->fence_drv.sync_seq; 218 r = amdgpu_fence_wait_polling(ring, 219 seq - ring->fence_drv.num_fences_mask, 220 timeout); 221 if (r < 1) 222 goto error_undo; 223 224 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 225 api_status->api_completion_fence_addr = status_gpu_addr; 226 api_status->api_completion_fence_value = 1; 227 228 amdgpu_ring_write_multiple(ring, pkt, size / 4); 229 230 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 231 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 232 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 233 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 234 mes_status_pkt.api_status.api_completion_fence_addr = 235 ring->fence_drv.gpu_addr; 236 mes_status_pkt.api_status.api_completion_fence_value = seq; 237 238 amdgpu_ring_write_multiple(ring, &mes_status_pkt, 239 sizeof(mes_status_pkt) / 4); 240 241 amdgpu_ring_commit(ring); 242 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 243 244 op_str = mes_v11_0_get_op_string(x_pkt); 245 misc_op_str = mes_v11_0_get_misc_op_string(x_pkt); 246 247 if (misc_op_str) 248 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, 249 misc_op_str); 250 else if (op_str) 251 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str); 252 else 253 dev_dbg(adev->dev, "MES msg=%d was emitted\n", 254 x_pkt->header.opcode); 255 256 r = amdgpu_fence_wait_polling(ring, seq, timeout); 257 if (r < 1 || !*status_ptr) { 258 259 if (misc_op_str) 260 dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n", 261 op_str, misc_op_str); 262 else if (op_str) 263 dev_err(adev->dev, "MES failed to respond to msg=%s\n", 264 op_str); 265 else 266 dev_err(adev->dev, "MES failed to respond to msg=%d\n", 267 x_pkt->header.opcode); 268 269 while (halt_if_hws_hang) 270 schedule(); 271 272 r = -ETIMEDOUT; 273 goto error_wb_free; 274 } 275 276 amdgpu_wb_free(adev, status_offset); 277 return 0; 278 279 error_undo: 280 dev_err(adev->dev, "MES ring buffer is full.\n"); 281 amdgpu_ring_undo(ring); 282 283 error_unlock_free: 284 spin_unlock_irqrestore(&mes->ring_lock[0], flags); 285 286 error_wb_free: 287 amdgpu_wb_free(adev, status_offset); 288 return r; 289 } 290 291 static int convert_to_mes_queue_type(int queue_type) 292 { 293 if (queue_type == AMDGPU_RING_TYPE_GFX) 294 return MES_QUEUE_TYPE_GFX; 295 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 296 return MES_QUEUE_TYPE_COMPUTE; 297 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 298 return MES_QUEUE_TYPE_SDMA; 299 else 300 WARN(1, "Invalid queue type %d\n", queue_type); 301 return MES_QUEUE_TYPE_GFX; 302 } 303 304 static int convert_to_mes_priority_level(int priority_level) 305 { 306 switch (priority_level) { 307 case AMDGPU_MES_PRIORITY_LEVEL_LOW: 308 return AMD_PRIORITY_LEVEL_LOW; 309 case AMDGPU_MES_PRIORITY_LEVEL_NORMAL: 310 default: 311 return AMD_PRIORITY_LEVEL_NORMAL; 312 case AMDGPU_MES_PRIORITY_LEVEL_MEDIUM: 313 return AMD_PRIORITY_LEVEL_MEDIUM; 314 case AMDGPU_MES_PRIORITY_LEVEL_HIGH: 315 return AMD_PRIORITY_LEVEL_HIGH; 316 case AMDGPU_MES_PRIORITY_LEVEL_REALTIME: 317 return AMD_PRIORITY_LEVEL_REALTIME; 318 } 319 } 320 321 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 322 struct mes_add_queue_input *input) 323 { 324 struct amdgpu_device *adev = mes->adev; 325 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 326 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 327 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 328 329 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 330 331 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 332 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 333 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 334 335 mes_add_queue_pkt.process_id = input->process_id; 336 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 337 mes_add_queue_pkt.process_va_start = input->process_va_start; 338 mes_add_queue_pkt.process_va_end = input->process_va_end; 339 mes_add_queue_pkt.process_quantum = input->process_quantum; 340 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 341 mes_add_queue_pkt.process_context_array_index = input->process_context_array_index; 342 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 343 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 344 mes_add_queue_pkt.gang_context_array_index = input->gang_context_array_index; 345 mes_add_queue_pkt.inprocess_gang_priority = 346 convert_to_mes_priority_level(input->inprocess_gang_priority); 347 mes_add_queue_pkt.gang_global_priority_level = 348 convert_to_mes_priority_level(input->gang_global_priority_level); 349 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 350 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 351 352 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 353 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 354 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 355 else 356 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 357 358 mes_add_queue_pkt.queue_type = 359 convert_to_mes_queue_type(input->queue_type); 360 mes_add_queue_pkt.paging = input->paging; 361 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 362 mes_add_queue_pkt.gws_base = input->gws_base; 363 mes_add_queue_pkt.gws_size = input->gws_size; 364 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 365 mes_add_queue_pkt.tma_addr = input->tma_addr; 366 mes_add_queue_pkt.trap_en = input->trap_en; 367 mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; 368 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 369 370 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 371 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 372 mes_add_queue_pkt.gds_size = input->queue_size; 373 374 mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled; 375 376 return mes_v11_0_submit_pkt_and_poll_completion(mes, 377 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 378 offsetof(union MESAPI__ADD_QUEUE, api_status)); 379 } 380 381 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 382 struct mes_remove_queue_input *input) 383 { 384 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 385 uint32_t mes_rev = mes->sched_version & AMDGPU_MES_VERSION_MASK; 386 387 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 388 389 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 390 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 391 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 392 393 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 394 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 395 mes_remove_queue_pkt.gang_context_array_index = input->gang_context_array_index; 396 mes_remove_queue_pkt.queue_type = 397 convert_to_mes_queue_type(input->queue_type); 398 399 if (mes_rev >= 0x60) 400 mes_remove_queue_pkt.remove_queue_after_reset = input->remove_queue_after_reset; 401 402 return mes_v11_0_submit_pkt_and_poll_completion(mes, 403 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 404 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 405 } 406 407 static bool mes_v11_0_pipe_reset_support(struct amdgpu_device *adev) 408 { 409 /* Disable the pipe reset until the CPFW fully support it.*/ 410 dev_warn_once(adev->dev, "The CPFW hasn't support pipe reset yet.\n"); 411 return false; 412 } 413 static int mes_v11_0_reset_gfx_pipe_mmio(struct amdgpu_device *adev, 414 u32 me, u32 pipe, u32 queue) 415 { 416 uint32_t reset_pipe = 0, clean_pipe = 0; 417 int r; 418 419 if (!mes_v11_0_pipe_reset_support(adev)) 420 return -EOPNOTSUPP; 421 422 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 423 mutex_lock(&adev->srbm_mutex); 424 soc21_grbm_select(adev, me, pipe, queue, 0); 425 426 switch (pipe) { 427 case 0: 428 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 429 PFP_PIPE0_RESET, 1); 430 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 431 ME_PIPE0_RESET, 1); 432 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 433 PFP_PIPE0_RESET, 0); 434 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 435 ME_PIPE0_RESET, 0); 436 break; 437 case 1: 438 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 439 PFP_PIPE1_RESET, 1); 440 reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL, 441 ME_PIPE1_RESET, 1); 442 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 443 PFP_PIPE1_RESET, 0); 444 clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL, 445 ME_PIPE1_RESET, 0); 446 break; 447 default: 448 break; 449 } 450 451 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe); 452 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe); 453 454 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) - 455 RS64_FW_UC_START_ADDR_LO; 456 soc21_grbm_select(adev, 0, 0, 0, 0); 457 mutex_unlock(&adev->srbm_mutex); 458 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 459 460 dev_info(adev->dev, "The gfx pipe reset to the ME firmware start PC: %s\n", 461 r == 0 ? "successfully" : "failed"); 462 /* FIXME: Sometimes driver can't cache the ME firmware start PC correctly, 463 * so the pipe reset status relies on the later gfx ring test result. 464 */ 465 return 0; 466 } 467 468 /* 469 * With MEC pipe reset asserted, clear CP_HQD_ACTIVE / CP_HQD_DEQUEUE_REQUEST for 470 * every queue on (me, pipe). HQDs must be torn down while pipe reset stays 471 * asserted; only then clear the pipe reset bit. 472 * Caller must hold adev->srbm_mutex. 473 */ 474 static void mes_v11_0_clear_hqds_on_mec_pipe(struct amdgpu_device *adev, u32 me, 475 u32 pipe) 476 { 477 unsigned int q; 478 479 for (q = 0; q < adev->gfx.mec.num_queue_per_pipe; q++) { 480 soc21_grbm_select(adev, me, pipe, q, 0); 481 /* Start from a clean HQD dequeue state before forcing HQD inactive. */ 482 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); 483 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0); 484 } 485 } 486 487 static int mes_v11_0_reset_compute_pipe_mmio(struct amdgpu_device *adev, 488 u32 me, u32 pipe, u32 queue) 489 { 490 uint32_t reset_val, clean_val; 491 int r; 492 493 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 494 mutex_lock(&adev->srbm_mutex); 495 soc21_grbm_select(adev, me, pipe, queue, 0); 496 497 if (adev->gfx.rs64_enable) { 498 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); 499 clean_val = reset_val; 500 501 switch (pipe) { 502 case 0: 503 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 504 MEC_PIPE0_RESET, 1); 505 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 506 MEC_PIPE0_RESET, 0); 507 break; 508 case 1: 509 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 510 MEC_PIPE1_RESET, 1); 511 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 512 MEC_PIPE1_RESET, 0); 513 break; 514 case 2: 515 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 516 MEC_PIPE2_RESET, 1); 517 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 518 MEC_PIPE2_RESET, 0); 519 break; 520 case 3: 521 reset_val = REG_SET_FIELD(reset_val, CP_MEC_RS64_CNTL, 522 MEC_PIPE3_RESET, 1); 523 clean_val = REG_SET_FIELD(clean_val, CP_MEC_RS64_CNTL, 524 MEC_PIPE3_RESET, 0); 525 break; 526 default: 527 break; 528 } 529 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_val); 530 mes_v11_0_clear_hqds_on_mec_pipe(adev, me, pipe); 531 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_val); 532 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) - 533 RS64_FW_UC_START_ADDR_LO; 534 } else { 535 reset_val = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); 536 clean_val = reset_val; 537 538 if (me == 1) { 539 switch (pipe) { 540 case 0: 541 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 542 MEC_ME1_PIPE0_RESET, 1); 543 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 544 MEC_ME1_PIPE0_RESET, 0); 545 break; 546 case 1: 547 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 548 MEC_ME1_PIPE1_RESET, 1); 549 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 550 MEC_ME1_PIPE1_RESET, 0); 551 break; 552 case 2: 553 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 554 MEC_ME1_PIPE2_RESET, 1); 555 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 556 MEC_ME1_PIPE2_RESET, 0); 557 break; 558 case 3: 559 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 560 MEC_ME1_PIPE3_RESET, 1); 561 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 562 MEC_ME1_PIPE3_RESET, 0); 563 break; 564 default: 565 break; 566 } 567 /* mec1 fw pc: CP_MEC1_INSTR_PNTR */ 568 } else { 569 switch (pipe) { 570 case 0: 571 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 572 MEC_ME2_PIPE0_RESET, 1); 573 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 574 MEC_ME2_PIPE0_RESET, 0); 575 break; 576 case 1: 577 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 578 MEC_ME2_PIPE1_RESET, 1); 579 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 580 MEC_ME2_PIPE1_RESET, 0); 581 break; 582 case 2: 583 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 584 MEC_ME2_PIPE2_RESET, 1); 585 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 586 MEC_ME2_PIPE2_RESET, 0); 587 break; 588 case 3: 589 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, 590 MEC_ME2_PIPE3_RESET, 1); 591 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, 592 MEC_ME2_PIPE3_RESET, 0); 593 break; 594 default: 595 break; 596 } 597 /* mec2 fw pc: CP:CP_MEC2_INSTR_PNTR */ 598 } 599 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_val); 600 mes_v11_0_clear_hqds_on_mec_pipe(adev, me, pipe); 601 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_val); 602 r = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC1_INSTR_PNTR)); 603 } 604 605 soc21_grbm_select(adev, 0, 0, 0, 0); 606 mutex_unlock(&adev->srbm_mutex); 607 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 608 609 dev_dbg(adev->dev, "MEC pipe me%u pipe%u queue%u resets to MEC FW start PC: %s\n", 610 me, pipe, queue, r == 0 ? "successfully" : "failed"); 611 /*FIXME:Sometimes driver can't cache the MEC firmware start PC correctly, so the pipe 612 * reset status relies on the compute ring test result. 613 */ 614 return 0; 615 } 616 617 static int mes_v11_0_reset_pipe_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 618 uint32_t me_id, uint32_t pipe_id, 619 uint32_t queue_id, uint32_t vmid) 620 { 621 struct amdgpu_device *adev = mes->adev; 622 623 if (queue_type == AMDGPU_RING_TYPE_GFX) 624 return mes_v11_0_reset_gfx_pipe_mmio(adev, me_id, pipe_id, queue_id); 625 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 626 return mes_v11_0_reset_compute_pipe_mmio(adev, me_id, pipe_id, queue_id); 627 else 628 return -EOPNOTSUPP; 629 } 630 631 static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, 632 uint32_t me_id, uint32_t pipe_id, 633 uint32_t queue_id, uint32_t vmid) 634 { 635 struct amdgpu_device *adev = mes->adev; 636 uint32_t value, reg; 637 int i, r = 0; 638 639 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 640 641 if (queue_type == AMDGPU_RING_TYPE_GFX) { 642 dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", 643 me_id, pipe_id, queue_id, vmid); 644 645 mutex_lock(&adev->gfx.reset_sem_mutex); 646 gfx_v11_0_request_gfx_index_mutex(adev, true); 647 /* all se allow writes */ 648 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, 649 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 650 value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); 651 if (pipe_id == 0) 652 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); 653 else 654 value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); 655 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); 656 gfx_v11_0_request_gfx_index_mutex(adev, false); 657 mutex_unlock(&adev->gfx.reset_sem_mutex); 658 659 mutex_lock(&adev->srbm_mutex); 660 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 661 /* wait till dequeue take effects */ 662 for (i = 0; i < adev->usec_timeout; i++) { 663 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) 664 break; 665 udelay(1); 666 } 667 if (i >= adev->usec_timeout) { 668 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); 669 r = -ETIMEDOUT; 670 } 671 672 soc21_grbm_select(adev, 0, 0, 0, 0); 673 mutex_unlock(&adev->srbm_mutex); 674 } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 675 dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", 676 me_id, pipe_id, queue_id); 677 mutex_lock(&adev->srbm_mutex); 678 soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); 679 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); 680 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); 681 682 /* wait till dequeue take effects */ 683 for (i = 0; i < adev->usec_timeout; i++) { 684 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 685 break; 686 udelay(1); 687 } 688 if (i >= adev->usec_timeout) { 689 dev_err(adev->dev, "failed to wait on hqd deactivate\n"); 690 r = -ETIMEDOUT; 691 } 692 soc21_grbm_select(adev, 0, 0, 0, 0); 693 mutex_unlock(&adev->srbm_mutex); 694 } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { 695 dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n", 696 me_id, pipe_id, queue_id); 697 switch (me_id) { 698 case 1: 699 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); 700 break; 701 case 0: 702 default: 703 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); 704 break; 705 } 706 707 value = 1 << queue_id; 708 WREG32(reg, value); 709 /* wait for queue reset done */ 710 for (i = 0; i < adev->usec_timeout; i++) { 711 if (!(RREG32(reg) & value)) 712 break; 713 udelay(1); 714 } 715 if (i >= adev->usec_timeout) { 716 dev_err(adev->dev, "failed to wait on sdma queue reset done\n"); 717 r = -ETIMEDOUT; 718 } 719 } 720 721 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 722 return r; 723 } 724 725 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, 726 struct mes_map_legacy_queue_input *input) 727 { 728 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 729 730 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 731 732 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 733 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 734 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 735 736 mes_add_queue_pkt.pipe_id = input->pipe_id; 737 mes_add_queue_pkt.queue_id = input->queue_id; 738 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 739 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 740 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 741 mes_add_queue_pkt.queue_type = 742 convert_to_mes_queue_type(input->queue_type); 743 mes_add_queue_pkt.map_legacy_kq = 1; 744 745 return mes_v11_0_submit_pkt_and_poll_completion(mes, 746 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 747 offsetof(union MESAPI__ADD_QUEUE, api_status)); 748 } 749 750 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 751 struct mes_unmap_legacy_queue_input *input) 752 { 753 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 754 755 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 756 757 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 758 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 759 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 760 761 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 762 mes_remove_queue_pkt.gang_context_addr = 0; 763 764 mes_remove_queue_pkt.pipe_id = input->pipe_id; 765 mes_remove_queue_pkt.queue_id = input->queue_id; 766 767 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 768 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 769 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 770 mes_remove_queue_pkt.tf_data = 771 lower_32_bits(input->trail_fence_data); 772 } else { 773 mes_remove_queue_pkt.unmap_legacy_queue = 1; 774 mes_remove_queue_pkt.queue_type = 775 convert_to_mes_queue_type(input->queue_type); 776 } 777 778 if (input->action == RESET_QUEUES && 779 (mes->sched_version & AMDGPU_MES_VERSION_MASK) >= 0x60) 780 mes_remove_queue_pkt.remove_queue_after_reset = 1; 781 782 783 return mes_v11_0_submit_pkt_and_poll_completion(mes, 784 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 785 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 786 } 787 788 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 789 struct mes_suspend_gang_input *input) 790 { 791 union MESAPI__SUSPEND mes_suspend_gang_pkt; 792 793 memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 794 795 mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 796 mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 797 mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 798 799 mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 800 mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 801 mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 802 mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 803 mes_suspend_gang_pkt.doorbell_offset = input->doorbell_offset; 804 805 return mes_v11_0_submit_pkt_and_poll_completion(mes, 806 &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 807 offsetof(union MESAPI__SUSPEND, api_status)); 808 } 809 810 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 811 struct mes_resume_gang_input *input) 812 { 813 union MESAPI__RESUME mes_resume_gang_pkt; 814 815 memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 816 817 mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 818 mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 819 mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 820 821 mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 822 mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 823 mes_resume_gang_pkt.doorbell_offset = input->doorbell_offset; 824 825 return mes_v11_0_submit_pkt_and_poll_completion(mes, 826 &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 827 offsetof(union MESAPI__RESUME, api_status)); 828 } 829 830 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 831 { 832 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 833 834 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 835 836 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 837 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 838 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 839 840 return mes_v11_0_submit_pkt_and_poll_completion(mes, 841 &mes_status_pkt, sizeof(mes_status_pkt), 842 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 843 } 844 845 /* 846 * QUERY_SCHEDULER_STATUS: get proc/gang context array sizes 847 */ 848 static int mes_v11_0_query_ctx_array_sizes(struct amdgpu_mes *mes) 849 { 850 struct amdgpu_device *adev = mes->adev; 851 union MESAPI__QUERY_MES_STATUS mes_query_pkt; 852 int r; 853 854 if (!mes->ctx_array_size_cpu_ptr) 855 return -EINVAL; 856 857 /* Clear the output buffer */ 858 mes->ctx_array_size_cpu_ptr[0] = 0; /* proc_ctx_array_size */ 859 mes->ctx_array_size_cpu_ptr[1] = 0; /* gang_ctx_array_size */ 860 861 memset(&mes_query_pkt, 0, sizeof(mes_query_pkt)); 862 863 mes_query_pkt.header.type = MES_API_TYPE_SCHEDULER; 864 mes_query_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 865 mes_query_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 866 867 mes_query_pkt.subopcode = MES_API_QUERY_MES__GET_CTX_ARRAY_SIZE; 868 869 /* 870 * MES FW will write the array sizes to these GPU addresses: 871 * proc_ctx_array_size_addr -> uint32_t N (e.g., 50) 872 * gang_ctx_array_size_addr -> uint32_t M (e.g., 300) 873 */ 874 mes_query_pkt.ctx_array_size.proc_ctx_array_size_addr = 875 mes->ctx_array_size_gpu_addr; 876 mes_query_pkt.ctx_array_size.gang_ctx_array_size_addr = 877 mes->ctx_array_size_gpu_addr + sizeof(uint32_t); 878 879 mes_query_pkt.api_status.api_completion_fence_addr = 880 mes->ring[0].fence_drv.gpu_addr; 881 mes_query_pkt.api_status.api_completion_fence_value = 882 ++mes->ring[0].fence_drv.sync_seq; 883 884 r = mes_v11_0_submit_pkt_and_poll_completion(mes, 885 &mes_query_pkt, sizeof(mes_query_pkt), 886 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 887 if (r) { 888 dev_err(adev->dev, 889 "MES QUERY_SCHEDULER_STATUS (GET_CTX_ARRAY_SIZE) failed, r=%d\n", r); 890 return r; 891 } 892 893 /* MES has written the sizes - now set up bitmaps */ 894 return amdgpu_mes_rs64mem_setup_bitmaps(mes); 895 } 896 897 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 898 struct mes_misc_op_input *input) 899 { 900 union MESAPI__MISC misc_pkt; 901 902 memset(&misc_pkt, 0, sizeof(misc_pkt)); 903 904 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 905 misc_pkt.header.opcode = MES_SCH_API_MISC; 906 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 907 908 switch (input->op) { 909 case MES_MISC_OP_READ_REG: 910 misc_pkt.opcode = MESAPI_MISC__READ_REG; 911 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 912 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 913 break; 914 case MES_MISC_OP_WRITE_REG: 915 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 916 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 917 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 918 break; 919 case MES_MISC_OP_WRM_REG_WAIT: 920 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 921 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 922 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 923 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 924 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 925 misc_pkt.wait_reg_mem.reg_offset2 = 0; 926 break; 927 case MES_MISC_OP_WRM_REG_WR_WAIT: 928 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 929 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 930 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 931 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 932 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 933 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 934 break; 935 case MES_MISC_OP_SET_SHADER_DEBUGGER: 936 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; 937 misc_pkt.set_shader_debugger.process_context_addr = 938 input->set_shader_debugger.process_context_addr; 939 misc_pkt.set_shader_debugger.flags.u32all = 940 input->set_shader_debugger.flags.u32all; 941 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = 942 input->set_shader_debugger.spi_gdbg_per_vmid_cntl; 943 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, 944 input->set_shader_debugger.tcp_watch_cntl, 945 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); 946 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; 947 break; 948 case MES_MISC_OP_CHANGE_CONFIG: 949 if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) < 0x63) { 950 dev_warn_once(mes->adev->dev, 951 "MES FW version must be larger than 0x63 to support limit single process feature.\n"); 952 return 0; 953 } 954 misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; 955 misc_pkt.change_config.opcode = 956 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; 957 misc_pkt.change_config.option.bits.limit_single_process = 958 input->change_config.option.limit_single_process; 959 break; 960 961 default: 962 drm_err(adev_to_drm(mes->adev), "unsupported misc op (%d)\n", input->op); 963 return -EINVAL; 964 } 965 966 return mes_v11_0_submit_pkt_and_poll_completion(mes, 967 &misc_pkt, sizeof(misc_pkt), 968 offsetof(union MESAPI__MISC, api_status)); 969 } 970 971 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 972 { 973 int i; 974 struct amdgpu_device *adev = mes->adev; 975 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 976 977 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 978 979 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 980 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 981 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 982 983 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 984 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 985 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 986 mes_set_hw_res_pkt.paging_vmid = 0; 987 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0]; 988 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 989 mes->query_status_fence_gpu_addr[0]; 990 991 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 992 mes_set_hw_res_pkt.compute_hqd_mask[i] = 993 mes->compute_hqd_mask[i]; 994 995 for (i = 0; i < MAX_GFX_PIPES; i++) 996 mes_set_hw_res_pkt.gfx_hqd_mask[i] = 997 mes->gfx_hqd_mask[i]; 998 999 for (i = 0; i < MAX_SDMA_PIPES; i++) 1000 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 1001 1002 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 1003 mes_set_hw_res_pkt.aggregated_doorbells[i] = 1004 mes->aggregated_doorbells[i]; 1005 1006 for (i = 0; i < 5; i++) { 1007 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 1008 mes_set_hw_res_pkt.mmhub_base[i] = 1009 adev->reg_offset[MMHUB_HWIP][0][i]; 1010 mes_set_hw_res_pkt.osssys_base[i] = 1011 adev->reg_offset[OSSSYS_HWIP][0][i]; 1012 } 1013 1014 mes_set_hw_res_pkt.disable_reset = 1; 1015 mes_set_hw_res_pkt.disable_mes_log = 1; 1016 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 1017 mes_set_hw_res_pkt.enable_reg_active_poll = 1; 1018 mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; 1019 mes_set_hw_res_pkt.oversubscription_timer = 50; 1020 1021 if (amdgpu_mes_log_enable) { 1022 mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; 1023 mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = 1024 mes->event_log_gpu_addr; 1025 } 1026 1027 if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) 1028 mes_set_hw_res_pkt.limit_single_process = 1; 1029 1030 return mes_v11_0_submit_pkt_and_poll_completion(mes, 1031 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 1032 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 1033 } 1034 1035 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) 1036 { 1037 union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt; 1038 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 1039 1040 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 1041 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; 1042 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 1043 mes_set_hw_res_pkt.enable_mes_info_ctx = 1; 1044 1045 mes_set_hw_res_pkt.cleaner_shader_fence_mc_addr = mes->resource_1_gpu_addr[0]; 1046 if (amdgpu_sriov_is_mes_info_enable(mes->adev)) { 1047 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = 1048 mes->resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE; 1049 mes_set_hw_res_pkt.mes_info_ctx_size = MES11_HW_RESOURCE_1_SIZE; 1050 } 1051 1052 return mes_v11_0_submit_pkt_and_poll_completion(mes, 1053 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 1054 offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); 1055 } 1056 1057 static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes, 1058 struct mes_reset_queue_input *input) 1059 { 1060 union MESAPI__RESET mes_reset_queue_pkt; 1061 1062 if (input->use_mmio) { 1063 int r = mes_v11_0_reset_queue_mmio(mes, input->queue_type, 1064 input->me_id, input->pipe_id, 1065 input->queue_id, input->vmid); 1066 if (r) 1067 return mes_v11_0_reset_pipe_mmio(mes, input->queue_type, 1068 input->me_id, input->pipe_id, 1069 input->queue_id, input->vmid); 1070 return 0; 1071 } 1072 1073 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 1074 1075 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 1076 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 1077 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 1078 1079 mes_reset_queue_pkt.queue_type = 1080 convert_to_mes_queue_type(input->queue_type); 1081 1082 if (input->legacy_gfx) { 1083 mes_reset_queue_pkt.reset_legacy_gfx = 1; 1084 mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; 1085 mes_reset_queue_pkt.queue_id_lp = input->queue_id; 1086 mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; 1087 mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; 1088 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; 1089 mes_reset_queue_pkt.vmid_id_lp = input->vmid; 1090 } else { 1091 mes_reset_queue_pkt.reset_queue_only = 1; 1092 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; 1093 } 1094 1095 return mes_v11_0_submit_pkt_and_poll_completion(mes, 1096 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 1097 offsetof(union MESAPI__RESET, api_status)); 1098 } 1099 1100 static int mes_v11_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, 1101 struct mes_detect_and_reset_queue_input *input) 1102 { 1103 union MESAPI__RESET mes_reset_queue_pkt; 1104 1105 memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 1106 1107 mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 1108 mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 1109 mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 1110 1111 mes_reset_queue_pkt.queue_type = 1112 convert_to_mes_queue_type(input->queue_type); 1113 mes_reset_queue_pkt.doorbell_offset_addr = 1114 mes->hung_queue_db_array_gpu_addr[0]; 1115 1116 if (input->detect_only) 1117 mes_reset_queue_pkt.hang_detect_only = 1; 1118 else 1119 mes_reset_queue_pkt.hang_detect_then_reset = 1; 1120 1121 return mes_v11_0_submit_pkt_and_poll_completion(mes, 1122 &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 1123 offsetof(union MESAPI__RESET, api_status)); 1124 } 1125 1126 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 1127 .add_hw_queue = mes_v11_0_add_hw_queue, 1128 .remove_hw_queue = mes_v11_0_remove_hw_queue, 1129 .map_legacy_queue = mes_v11_0_map_legacy_queue, 1130 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 1131 .suspend_gang = mes_v11_0_suspend_gang, 1132 .resume_gang = mes_v11_0_resume_gang, 1133 .misc_op = mes_v11_0_misc_op, 1134 .reset_hw_queue = mes_v11_0_reset_hw_queue, 1135 .detect_and_reset_hung_queues = mes_v11_0_detect_and_reset_hung_queues, 1136 }; 1137 1138 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 1139 enum amdgpu_mes_pipe pipe) 1140 { 1141 int r; 1142 const struct mes_firmware_header_v1_0 *mes_hdr; 1143 const __le32 *fw_data; 1144 unsigned fw_size; 1145 1146 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1147 adev->mes.fw[pipe]->data; 1148 1149 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1150 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1151 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1152 1153 r = amdgpu_bo_create_reserved(adev, fw_size, 1154 PAGE_SIZE, 1155 AMDGPU_GEM_DOMAIN_VRAM | 1156 AMDGPU_GEM_DOMAIN_GTT, 1157 &adev->mes.ucode_fw_obj[pipe], 1158 &adev->mes.ucode_fw_gpu_addr[pipe], 1159 (void **)&adev->mes.ucode_fw_ptr[pipe]); 1160 if (r) { 1161 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 1162 return r; 1163 } 1164 1165 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 1166 1167 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 1168 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 1169 1170 return 0; 1171 } 1172 1173 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 1174 enum amdgpu_mes_pipe pipe) 1175 { 1176 int r; 1177 const struct mes_firmware_header_v1_0 *mes_hdr; 1178 const __le32 *fw_data; 1179 unsigned fw_size; 1180 1181 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1182 adev->mes.fw[pipe]->data; 1183 1184 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1185 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1186 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1187 1188 if (fw_size > GFX_MES_DRAM_SIZE) { 1189 dev_err(adev->dev, "PIPE%d ucode data fw size (%d) is greater than dram size (%d)\n", 1190 pipe, fw_size, GFX_MES_DRAM_SIZE); 1191 return -EINVAL; 1192 } 1193 1194 r = amdgpu_bo_create_reserved(adev, GFX_MES_DRAM_SIZE, 1195 64 * 1024, 1196 AMDGPU_GEM_DOMAIN_VRAM | 1197 AMDGPU_GEM_DOMAIN_GTT, 1198 &adev->mes.data_fw_obj[pipe], 1199 &adev->mes.data_fw_gpu_addr[pipe], 1200 (void **)&adev->mes.data_fw_ptr[pipe]); 1201 if (r) { 1202 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 1203 return r; 1204 } 1205 1206 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 1207 1208 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 1209 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 1210 1211 return 0; 1212 } 1213 1214 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 1215 enum amdgpu_mes_pipe pipe) 1216 { 1217 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 1218 &adev->mes.data_fw_gpu_addr[pipe], 1219 (void **)&adev->mes.data_fw_ptr[pipe]); 1220 1221 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 1222 &adev->mes.ucode_fw_gpu_addr[pipe], 1223 (void **)&adev->mes.ucode_fw_ptr[pipe]); 1224 } 1225 1226 static void mes_v11_0_get_fw_version(struct amdgpu_device *adev) 1227 { 1228 int pipe; 1229 1230 /* return early if we have already fetched these */ 1231 if (adev->mes.sched_version && adev->mes.kiq_version) 1232 return; 1233 1234 /* get MES scheduler/KIQ versions */ 1235 mutex_lock(&adev->srbm_mutex); 1236 1237 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1238 soc21_grbm_select(adev, 3, pipe, 0, 0); 1239 1240 if (pipe == AMDGPU_MES_SCHED_PIPE) 1241 adev->mes.sched_version = 1242 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1243 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 1244 adev->mes.kiq_version = 1245 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 1246 } 1247 1248 soc21_grbm_select(adev, 0, 0, 0, 0); 1249 mutex_unlock(&adev->srbm_mutex); 1250 } 1251 1252 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 1253 { 1254 uint64_t ucode_addr; 1255 uint32_t pipe, data = 0; 1256 1257 if (enable) { 1258 if (amdgpu_mes_log_enable) { 1259 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO, 1260 lower_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 1261 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI, 1262 upper_32_bits(adev->mes.event_log_gpu_addr + AMDGPU_MES_LOG_BUFFER_SIZE)); 1263 dev_info(adev->dev, "Setup CP MES MSCRATCH address : 0x%x. 0x%x\n", 1264 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI), 1265 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO)); 1266 } 1267 1268 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1269 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1270 data = REG_SET_FIELD(data, CP_MES_CNTL, 1271 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 1272 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1273 1274 mutex_lock(&adev->srbm_mutex); 1275 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1276 if (!adev->enable_mes_kiq && 1277 pipe == AMDGPU_MES_KIQ_PIPE) 1278 continue; 1279 1280 soc21_grbm_select(adev, 3, pipe, 0, 0); 1281 1282 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1283 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1284 lower_32_bits(ucode_addr)); 1285 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1286 upper_32_bits(ucode_addr)); 1287 } 1288 soc21_grbm_select(adev, 0, 0, 0, 0); 1289 mutex_unlock(&adev->srbm_mutex); 1290 1291 /* unhalt MES and activate pipe0 */ 1292 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 1293 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1294 adev->enable_mes_kiq ? 1 : 0); 1295 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1296 1297 if (amdgpu_emu_mode) 1298 msleep(100); 1299 else 1300 udelay(500); 1301 } else { 1302 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 1303 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 1304 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 1305 data = REG_SET_FIELD(data, CP_MES_CNTL, 1306 MES_INVALIDATE_ICACHE, 1); 1307 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 1308 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1309 adev->enable_mes_kiq ? 1 : 0); 1310 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 1311 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 1312 } 1313 } 1314 1315 /* This function is for backdoor MES firmware */ 1316 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 1317 enum amdgpu_mes_pipe pipe, bool prime_icache) 1318 { 1319 int r; 1320 uint32_t data; 1321 uint64_t ucode_addr; 1322 1323 mes_v11_0_enable(adev, false); 1324 1325 if (!adev->mes.fw[pipe]) 1326 return -EINVAL; 1327 1328 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 1329 if (r) 1330 return r; 1331 1332 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 1333 if (r) { 1334 mes_v11_0_free_ucode_buffers(adev, pipe); 1335 return r; 1336 } 1337 1338 mutex_lock(&adev->srbm_mutex); 1339 /* me=3, pipe=0, queue=0 */ 1340 soc21_grbm_select(adev, 3, pipe, 0, 0); 1341 1342 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 1343 1344 /* set ucode start address */ 1345 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 1346 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 1347 lower_32_bits(ucode_addr)); 1348 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 1349 upper_32_bits(ucode_addr)); 1350 1351 /* set ucode fimrware address */ 1352 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 1353 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1354 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 1355 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 1356 1357 /* set ucode instruction cache boundary to 2M-1 */ 1358 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 1359 1360 /* set ucode data firmware address */ 1361 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 1362 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1363 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 1364 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 1365 1366 /* Set 0x7FFFF (512K-1) to CP_MES_MDBOUND_LO */ 1367 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); 1368 1369 if (prime_icache) { 1370 /* invalidate ICACHE */ 1371 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1372 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 1373 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 1374 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1375 1376 /* prime the ICACHE. */ 1377 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 1378 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 1379 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 1380 } 1381 1382 soc21_grbm_select(adev, 0, 0, 0, 0); 1383 mutex_unlock(&adev->srbm_mutex); 1384 1385 return 0; 1386 } 1387 1388 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 1389 enum amdgpu_mes_pipe pipe) 1390 { 1391 int r; 1392 u32 *eop; 1393 1394 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 1395 AMDGPU_GEM_DOMAIN_GTT, 1396 &adev->mes.eop_gpu_obj[pipe], 1397 &adev->mes.eop_gpu_addr[pipe], 1398 (void **)&eop); 1399 if (r) { 1400 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 1401 return r; 1402 } 1403 1404 memset(eop, 0, 1405 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 1406 1407 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 1408 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 1409 1410 return 0; 1411 } 1412 1413 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 1414 { 1415 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1416 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1417 uint32_t tmp; 1418 1419 memset(mqd, 0, sizeof(*mqd)); 1420 1421 mqd->header = 0xC0310800; 1422 mqd->compute_pipelinestat_enable = 0x00000001; 1423 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1424 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1425 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1426 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1427 mqd->compute_misc_reserved = 0x00000007; 1428 1429 eop_base_addr = ring->eop_gpu_addr >> 8; 1430 1431 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1432 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 1433 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1434 (order_base_2(MES_EOP_SIZE / 4) - 1)); 1435 1436 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 1437 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1438 mqd->cp_hqd_eop_control = tmp; 1439 1440 /* disable the queue if it's active */ 1441 ring->wptr = 0; 1442 mqd->cp_hqd_pq_rptr = 0; 1443 mqd->cp_hqd_pq_wptr_lo = 0; 1444 mqd->cp_hqd_pq_wptr_hi = 0; 1445 1446 /* set the pointer to the MQD */ 1447 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1448 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1449 1450 /* set MQD vmid to 0 */ 1451 tmp = regCP_MQD_CONTROL_DEFAULT; 1452 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1453 mqd->cp_mqd_control = tmp; 1454 1455 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1456 hqd_gpu_addr = ring->gpu_addr >> 8; 1457 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 1458 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1459 1460 /* set the wb address whether it's enabled or not */ 1461 wb_gpu_addr = ring->rptr_gpu_addr; 1462 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1463 mqd->cp_hqd_pq_rptr_report_addr_hi = 1464 upper_32_bits(wb_gpu_addr) & 0xffff; 1465 1466 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1467 wb_gpu_addr = ring->wptr_gpu_addr; 1468 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 1469 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1470 1471 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1472 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 1473 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1474 (order_base_2(ring->ring_size / 4) - 1)); 1475 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1476 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1477 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 1478 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 1479 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1480 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1481 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 1482 mqd->cp_hqd_pq_control = tmp; 1483 1484 /* enable doorbell */ 1485 tmp = 0; 1486 if (ring->use_doorbell) { 1487 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1488 DOORBELL_OFFSET, ring->doorbell_index); 1489 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1490 DOORBELL_EN, 1); 1491 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1492 DOORBELL_SOURCE, 0); 1493 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1494 DOORBELL_HIT, 0); 1495 } else 1496 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1497 DOORBELL_EN, 0); 1498 mqd->cp_hqd_pq_doorbell_control = tmp; 1499 1500 mqd->cp_hqd_vmid = 0; 1501 /* activate the queue */ 1502 mqd->cp_hqd_active = 1; 1503 1504 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 1505 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 1506 PRELOAD_SIZE, 0x55); 1507 mqd->cp_hqd_persistent_state = tmp; 1508 1509 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 1510 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 1511 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 1512 1513 amdgpu_device_flush_hdp(ring->adev, NULL); 1514 return 0; 1515 } 1516 1517 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 1518 { 1519 struct v11_compute_mqd *mqd = ring->mqd_ptr; 1520 struct amdgpu_device *adev = ring->adev; 1521 uint32_t data = 0; 1522 1523 mutex_lock(&adev->srbm_mutex); 1524 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1525 1526 /* set CP_HQD_VMID.VMID = 0. */ 1527 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 1528 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 1529 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 1530 1531 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 1532 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1533 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1534 DOORBELL_EN, 0); 1535 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1536 1537 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 1538 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 1539 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 1540 1541 /* set CP_MQD_CONTROL.VMID=0 */ 1542 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1543 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 1544 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 1545 1546 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 1547 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 1548 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 1549 1550 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 1551 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1552 mqd->cp_hqd_pq_rptr_report_addr_lo); 1553 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1554 mqd->cp_hqd_pq_rptr_report_addr_hi); 1555 1556 /* set CP_HQD_PQ_CONTROL */ 1557 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 1558 1559 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 1560 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 1561 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1562 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1563 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1564 1565 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 1566 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 1567 mqd->cp_hqd_pq_doorbell_control); 1568 1569 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 1570 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 1571 1572 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 1573 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 1574 1575 soc21_grbm_select(adev, 0, 0, 0, 0); 1576 mutex_unlock(&adev->srbm_mutex); 1577 } 1578 1579 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 1580 { 1581 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 1582 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 1583 int r; 1584 1585 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 1586 return -EINVAL; 1587 1588 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 1589 if (r) { 1590 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 1591 return r; 1592 } 1593 1594 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); 1595 1596 return amdgpu_ring_test_helper(kiq_ring); 1597 } 1598 1599 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 1600 enum amdgpu_mes_pipe pipe) 1601 { 1602 struct amdgpu_ring *ring; 1603 int r; 1604 1605 if (pipe == AMDGPU_MES_KIQ_PIPE) { 1606 ring = &adev->gfx.kiq[0].ring; 1607 } else if (pipe == AMDGPU_MES_SCHED_PIPE) { 1608 ring = &adev->mes.ring[0]; 1609 } else { 1610 WARN(1, "Invalid MES pipe %d\n", pipe); 1611 return -EINVAL; 1612 } 1613 1614 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 1615 (amdgpu_in_reset(adev) || adev->in_suspend)) { 1616 *(ring->wptr_cpu_addr) = 0; 1617 *(ring->rptr_cpu_addr) = 0; 1618 amdgpu_ring_clear_ring(ring); 1619 } 1620 1621 r = mes_v11_0_mqd_init(ring); 1622 if (r) 1623 return r; 1624 1625 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1626 r = mes_v11_0_kiq_enable_queue(adev); 1627 if (r) 1628 return r; 1629 } else { 1630 mes_v11_0_queue_init_register(ring); 1631 } 1632 1633 return 0; 1634 } 1635 1636 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1637 { 1638 struct amdgpu_ring *ring; 1639 1640 ring = &adev->mes.ring[0]; 1641 1642 ring->funcs = &mes_v11_0_ring_funcs; 1643 1644 ring->me = 3; 1645 ring->pipe = 0; 1646 ring->queue = 0; 1647 1648 ring->ring_obj = NULL; 1649 ring->use_doorbell = true; 1650 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1651 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1652 ring->no_scheduler = true; 1653 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1654 1655 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1656 AMDGPU_RING_PRIO_DEFAULT, NULL); 1657 } 1658 1659 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1660 { 1661 struct amdgpu_ring *ring; 1662 1663 spin_lock_init(&adev->gfx.kiq[0].ring_lock); 1664 1665 ring = &adev->gfx.kiq[0].ring; 1666 1667 ring->me = 3; 1668 ring->pipe = 1; 1669 ring->queue = 0; 1670 1671 ring->adev = NULL; 1672 ring->ring_obj = NULL; 1673 ring->use_doorbell = true; 1674 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1675 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1676 ring->no_scheduler = true; 1677 sprintf(ring->name, "mes_kiq_%d.%d.%d", 1678 ring->me, ring->pipe, ring->queue); 1679 1680 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1681 AMDGPU_RING_PRIO_DEFAULT, NULL); 1682 } 1683 1684 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1685 enum amdgpu_mes_pipe pipe) 1686 { 1687 int r, mqd_size = sizeof(struct v11_compute_mqd); 1688 struct amdgpu_ring *ring; 1689 1690 if (pipe == AMDGPU_MES_KIQ_PIPE) 1691 ring = &adev->gfx.kiq[0].ring; 1692 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1693 ring = &adev->mes.ring[0]; 1694 else 1695 return -EINVAL; 1696 1697 if (ring->mqd_obj) 1698 return 0; 1699 1700 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1701 AMDGPU_GEM_DOMAIN_VRAM | 1702 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1703 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1704 if (r) { 1705 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1706 return r; 1707 } 1708 1709 memset(ring->mqd_ptr, 0, mqd_size); 1710 1711 /* prepare MQD backup */ 1712 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1713 if (!adev->mes.mqd_backup[pipe]) { 1714 dev_warn(adev->dev, 1715 "no memory to create MQD backup for ring %s\n", 1716 ring->name); 1717 return -ENOMEM; 1718 } 1719 1720 return 0; 1721 } 1722 1723 static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 1724 { 1725 struct amdgpu_device *adev = ip_block->adev; 1726 int pipe, r, bo_size; 1727 1728 adev->mes.funcs = &mes_v11_0_funcs; 1729 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1730 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1731 1732 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE; 1733 1734 r = amdgpu_mes_init(adev); 1735 if (r) 1736 return r; 1737 1738 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1739 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1740 continue; 1741 1742 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1743 if (r) 1744 return r; 1745 1746 r = mes_v11_0_mqd_sw_init(adev, pipe); 1747 if (r) 1748 return r; 1749 } 1750 1751 if (adev->enable_mes_kiq) { 1752 r = mes_v11_0_kiq_ring_init(adev); 1753 if (r) 1754 return r; 1755 } 1756 1757 r = mes_v11_0_ring_init(adev); 1758 if (r) 1759 return r; 1760 1761 bo_size = AMDGPU_GPU_PAGE_SIZE; 1762 if (amdgpu_sriov_is_mes_info_enable(adev)) 1763 bo_size += MES11_HW_RESOURCE_1_SIZE; 1764 1765 /* Only needed for AMDGPU_MES_SCHED_PIPE on MES 11*/ 1766 r = amdgpu_bo_create_kernel(adev, 1767 bo_size, 1768 PAGE_SIZE, 1769 AMDGPU_GEM_DOMAIN_VRAM, 1770 &adev->mes.resource_1[0], 1771 &adev->mes.resource_1_gpu_addr[0], 1772 &adev->mes.resource_1_addr[0]); 1773 if (r) { 1774 dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", r); 1775 return r; 1776 } 1777 1778 return 0; 1779 } 1780 1781 static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 1782 { 1783 struct amdgpu_device *adev = ip_block->adev; 1784 int pipe; 1785 1786 amdgpu_bo_free_kernel(&adev->mes.resource_1[0], &adev->mes.resource_1_gpu_addr[0], 1787 &adev->mes.resource_1_addr[0]); 1788 1789 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1790 kfree(adev->mes.mqd_backup[pipe]); 1791 1792 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1793 &adev->mes.eop_gpu_addr[pipe], 1794 NULL); 1795 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1796 } 1797 1798 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj, 1799 &adev->gfx.kiq[0].ring.mqd_gpu_addr, 1800 &adev->gfx.kiq[0].ring.mqd_ptr); 1801 1802 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj, 1803 &adev->mes.ring[0].mqd_gpu_addr, 1804 &adev->mes.ring[0].mqd_ptr); 1805 1806 amdgpu_ring_fini(&adev->gfx.kiq[0].ring); 1807 amdgpu_ring_fini(&adev->mes.ring[0]); 1808 1809 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1810 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1811 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1812 } 1813 1814 amdgpu_mes_fini(adev); 1815 return 0; 1816 } 1817 1818 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring) 1819 { 1820 uint32_t data; 1821 int i; 1822 struct amdgpu_device *adev = ring->adev; 1823 1824 mutex_lock(&adev->srbm_mutex); 1825 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 1826 1827 /* disable the queue if it's active */ 1828 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1829 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1830 for (i = 0; i < adev->usec_timeout; i++) { 1831 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1832 break; 1833 udelay(1); 1834 } 1835 } 1836 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1837 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1838 DOORBELL_EN, 0); 1839 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1840 DOORBELL_HIT, 1); 1841 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1842 1843 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1844 1845 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1846 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1847 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1848 1849 soc21_grbm_select(adev, 0, 0, 0, 0); 1850 mutex_unlock(&adev->srbm_mutex); 1851 } 1852 1853 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1854 { 1855 uint32_t tmp; 1856 struct amdgpu_device *adev = ring->adev; 1857 1858 /* tell RLC which is KIQ queue */ 1859 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1860 tmp &= 0xffffff00; 1861 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1862 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 1863 } 1864 1865 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) 1866 { 1867 uint32_t tmp; 1868 1869 /* tell RLC which is KIQ dequeue */ 1870 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1871 tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK; 1872 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1873 } 1874 1875 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) 1876 { 1877 int r = 0; 1878 struct amdgpu_ip_block *ip_block; 1879 1880 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1881 1882 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1883 if (r) { 1884 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1885 return r; 1886 } 1887 1888 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1889 if (r) { 1890 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1891 return r; 1892 } 1893 1894 } 1895 1896 mes_v11_0_enable(adev, true); 1897 1898 mes_v11_0_get_fw_version(adev); 1899 1900 mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); 1901 1902 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); 1903 if (unlikely(!ip_block)) { 1904 dev_err(adev->dev, "Failed to get MES handle\n"); 1905 return -EINVAL; 1906 } 1907 1908 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1909 if (r) 1910 goto failure; 1911 1912 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47) 1913 adev->mes.enable_legacy_queue_map = true; 1914 else 1915 adev->mes.enable_legacy_queue_map = false; 1916 1917 if (adev->mes.enable_legacy_queue_map) { 1918 r = mes_v11_0_hw_init(ip_block); 1919 if (r) 1920 goto failure; 1921 } 1922 1923 return r; 1924 1925 failure: 1926 mes_v11_0_hw_fini(ip_block); 1927 return r; 1928 } 1929 1930 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) 1931 { 1932 if (adev->mes.ring[0].sched.ready) { 1933 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]); 1934 adev->mes.ring[0].sched.ready = false; 1935 } 1936 1937 if (amdgpu_sriov_vf(adev)) { 1938 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring); 1939 mes_v11_0_kiq_clear(adev); 1940 } 1941 1942 mes_v11_0_enable(adev, false); 1943 1944 return 0; 1945 } 1946 1947 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 1948 { 1949 int r; 1950 struct amdgpu_device *adev = ip_block->adev; 1951 1952 if (adev->mes.ring[0].sched.ready) 1953 goto out; 1954 1955 if (!adev->enable_mes_kiq) { 1956 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1957 r = mes_v11_0_load_microcode(adev, 1958 AMDGPU_MES_SCHED_PIPE, true); 1959 if (r) { 1960 DRM_ERROR("failed to MES fw, r=%d\n", r); 1961 return r; 1962 } 1963 } 1964 1965 mes_v11_0_enable(adev, true); 1966 } 1967 1968 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1969 if (r) 1970 goto failure; 1971 1972 /* Allocate GPU buffer for array size query results */ 1973 r = amdgpu_mes_rs64mem_init(&adev->mes); 1974 if (r) 1975 dev_warn(adev->dev, 1976 "RS64 local memory init failed (%d)," 1977 "falling back to system memory path\n", r); 1978 1979 r = mes_v11_0_set_hw_resources(&adev->mes); 1980 1981 if (r) 1982 goto failure; 1983 1984 /* 1985 * QUERY_SCHEDULER_STATUS to get array sizes (N, M). 1986 * MES writes the sizes to the GPU buffer, then we allocate bitmaps. 1987 */ 1988 if (adev->mes.use_rs64mem) { 1989 r = mes_v11_0_query_ctx_array_sizes(&adev->mes); 1990 if (r) { 1991 dev_warn(adev->dev, 1992 "Failed to query ctx array sizes (%d)," 1993 "disabling RS64 local memory\n", r); 1994 /* Continue without optimization - not fatal */ 1995 } 1996 } 1997 1998 1999 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x52) { 2000 r = mes_v11_0_set_hw_resources_1(&adev->mes); 2001 if (r) { 2002 DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r); 2003 goto failure; 2004 } 2005 } 2006 2007 r = mes_v11_0_query_sched_status(&adev->mes); 2008 if (r) { 2009 DRM_ERROR("MES is busy\n"); 2010 goto failure; 2011 } 2012 2013 r = amdgpu_mes_update_enforce_isolation(adev); 2014 if (r) 2015 goto failure; 2016 2017 amdgpu_mes_validate_fw_version(adev); 2018 out: 2019 /* 2020 * Disable KIQ ring usage from the driver once MES is enabled. 2021 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 2022 * with MES enabled. 2023 */ 2024 adev->gfx.kiq[0].ring.sched.ready = false; 2025 adev->mes.ring[0].sched.ready = true; 2026 2027 return 0; 2028 2029 failure: 2030 mes_v11_0_hw_fini(ip_block); 2031 return r; 2032 } 2033 2034 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 2035 { 2036 struct amdgpu_device *adev = ip_block->adev; 2037 2038 if (adev->mes.use_rs64mem) 2039 amdgpu_mes_rs64mem_fini(&adev->mes); 2040 return 0; 2041 } 2042 2043 static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block) 2044 { 2045 return mes_v11_0_hw_fini(ip_block); 2046 } 2047 2048 static int mes_v11_0_resume(struct amdgpu_ip_block *ip_block) 2049 { 2050 return mes_v11_0_hw_init(ip_block); 2051 } 2052 2053 static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) 2054 { 2055 struct amdgpu_device *adev = ip_block->adev; 2056 int pipe, r; 2057 2058 adev->mes.hung_queue_db_array_size = MES11_HUNG_DB_OFFSET_ARRAY_SIZE; 2059 adev->mes.hung_queue_hqd_info_offset = MES11_HUNG_HQD_INFO_OFFSET; 2060 2061 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 2062 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 2063 continue; 2064 r = amdgpu_mes_init_microcode(adev, pipe); 2065 if (r) 2066 return r; 2067 } 2068 2069 return 0; 2070 } 2071 2072 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 2073 .name = "mes_v11_0", 2074 .early_init = mes_v11_0_early_init, 2075 .late_init = NULL, 2076 .sw_init = mes_v11_0_sw_init, 2077 .sw_fini = mes_v11_0_sw_fini, 2078 .hw_init = mes_v11_0_hw_init, 2079 .hw_fini = mes_v11_0_hw_fini, 2080 .suspend = mes_v11_0_suspend, 2081 .resume = mes_v11_0_resume, 2082 }; 2083 2084 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 2085 .type = AMD_IP_BLOCK_TYPE_MES, 2086 .major = 11, 2087 .minor = 0, 2088 .rev = 0, 2089 .funcs = &mes_v11_0_ip_funcs, 2090 }; 2091