1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * I3C master driver for the AMD I3C controller. 4 * 5 * Copyright (C) 2026, Advanced Micro Devices, Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/cleanup.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/err.h> 14 #include <linux/i3c/master.h> 15 #include <linux/io.h> 16 #include <linux/iopoll.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/mutex.h> 20 #include <linux/of.h> 21 #include <linux/platform_device.h> 22 #include <linux/slab.h> 23 #include <linux/time.h> 24 #include <linux/unaligned.h> 25 26 #define XI3C_VERSION_OFFSET 0x00 /* Version Register */ 27 #define XI3C_RESET_OFFSET 0x04 /* Soft Reset Register */ 28 #define XI3C_CR_OFFSET 0x08 /* Control Register */ 29 #define XI3C_ADDRESS_OFFSET 0x0C /* Target Address Register */ 30 #define XI3C_SR_OFFSET 0x10 /* Status Register */ 31 #define XI3C_CMD_FIFO_OFFSET 0x20 /* I3C Command FIFO Register */ 32 #define XI3C_WR_FIFO_OFFSET 0x24 /* I3C Write Data FIFO Register */ 33 #define XI3C_RD_FIFO_OFFSET 0x28 /* I3C Read Data FIFO Register */ 34 #define XI3C_RESP_STATUS_FIFO_OFFSET 0x2C /* I3C Response status FIFO Register */ 35 #define XI3C_FIFO_LVL_STATUS_OFFSET 0x30 /* CMD slots free | WR-FIFO free (words) */ 36 #define XI3C_FIFO_LVL_STATUS_1_OFFSET 0x34 /* RESP fill | RD-FIFO fill level (words) */ 37 #define XI3C_SCL_HIGH_TIME_OFFSET 0x38 /* I3C SCL HIGH Register */ 38 #define XI3C_SCL_LOW_TIME_OFFSET 0x3C /* I3C SCL LOW Register */ 39 #define XI3C_SDA_HOLD_TIME_OFFSET 0x40 /* I3C SDA HOLD Register */ 40 #define XI3C_TSU_START_OFFSET 0x48 /* I3C START SETUP Register */ 41 #define XI3C_THD_START_OFFSET 0x4C /* I3C START HOLD Register */ 42 #define XI3C_TSU_STOP_OFFSET 0x50 /* I3C STOP Setup Register */ 43 #define XI3C_OD_SCL_HIGH_TIME_OFFSET 0x54 /* I3C OD SCL HIGH Register */ 44 #define XI3C_OD_SCL_LOW_TIME_OFFSET 0x58 /* I3C OD SCL LOW Register */ 45 #define XI3C_PID0_OFFSET 0x6C /* LSB 4 bytes of the PID */ 46 #define XI3C_PID1_BCR_DCR 0x70 /* MSB 2 bytes of the PID, BCR and DCR */ 47 48 #define XI3C_CR_EN_MASK BIT(0) /* Core Enable */ 49 #define XI3C_CR_RESUME_MASK BIT(2) /* Core Resume */ 50 #define XI3C_SR_RESP_NOT_EMPTY_MASK BIT(4) /* Resp Fifo not empty status mask */ 51 #define XI3C_RD_FIFO_NOT_EMPTY_MASK BIT(15) /* Read Fifo not empty status mask */ 52 53 #define XI3C_BCR_MASK GENMASK(23, 16) 54 #define XI3C_DCR_MASK GENMASK(31, 24) 55 #define XI3C_PID_MASK GENMASK_ULL(63, 16) 56 #define XI3C_TIMING_MASK GENMASK(17, 0) 57 #define XI3C_REV_NUM_MASK GENMASK(15, 8) 58 #define XI3C_PID1_MASK GENMASK(15, 0) 59 #define XI3C_FIFO_LEVEL_MASK GENMASK(15, 0) 60 #define XI3C_RESP_CODE_MASK GENMASK(8, 5) 61 62 /* Controller response codes; PG439 page 34, Table 46 */ 63 #define XI3C_RESP_CODE_SUCCESS 0 /* Transfer completed OK */ 64 #define XI3C_RESP_CODE_NO_TARGET 2 /* 7E NACK: no target on bus */ 65 #define XI3C_RESP_CODE_NACK 3 /* Target NACK / DAA end */ 66 #define XI3C_RESP_CODE_READ_EARLY_TERM 5 /* Target ended read early (T-bit), short read */ 67 68 /* xi3c_get_response() private return: read ended early with valid data; resume needed */ 69 #define XI3C_XFER_SHORT_READ 1 70 71 #define XI3C_RESP_BYTES_MASK GENMASK(20, 9) /* NUM_BYTES processed */ 72 #define XI3C_ADDR_MASK GENMASK(6, 0) 73 #define XI3C_FIFOS_RST_MASK GENMASK(4, 1) 74 75 /* Command FIFO word layout (bit ranges encoded in the GENMASK/BIT args) */ 76 #define XI3C_CMD_TYPE GENMASK(3, 0) /* command type */ 77 #define XI3C_CMD_TERMINATE BIT(4) /* terminate (last cmd of xfer) */ 78 #define XI3C_CMD_ADDR GENMASK(15, 8) /* target address << 1 | RnW */ 79 #define XI3C_CMD_LEN GENMASK(27, 16) /* payload length in bytes */ 80 #define XI3C_CMD_TID GENMASK(31, 28) /* transfer ID */ 81 82 /* tLOW_OD open-drain SCL low; MIPI I3C v1.1.1 Table 74 min 200 ns, 500 ns chosen conservatively */ 83 #define XI3C_OD_TLOW_NS 500 84 /* Open-drain SCL high (tHIGH) max; MIPI I3C v1.1.1 Table 74 (41 ns) */ 85 #define XI3C_OD_THIGH_NS 41 86 /* 87 * tSU_STA/tHD_STA/tSU_STO min, 400 kHz/Fm; MIPI I3C v1.1.1 Table 73 88 * (mixed bus with legacy I2C device) 89 */ 90 #define XI3C_I2C_TCASMIN_NS 600 91 /* tSU_STA/tHD_STA/tSU_STO min, 1 MHz/Fm+; MIPI I3C v1.1.1 Table 73 (pure I3C bus) */ 92 #define XI3C_TCASMIN_NS 260 93 /* Max payload per transfer: 12-bit CMD length field (XI3C_CMD_LEN); PG439 page 32, Table 42 */ 94 #define XI3C_MAXDATA_LENGTH 4095 95 /* Max enumerated devices; PG439 page 27, AXI_I3C_IBI_TARGET_ADDR register detail */ 96 #define XI3C_MAX_DEVS 128 97 /* DAA target response = 48-bit PID + BCR + DCR = 8 bytes; PG439 page 28 */ 98 #define XI3C_DAA_SLAVEINFO_READ_BYTECOUNT 8 99 100 /* 101 * Min SDA hold cycles, rev 0 IP. Revision-specific value, PG439 page 24, 102 * AXI_I3C_SDA_HOLD_TIME register detail 103 */ 104 #define XI3C_THOLD_MIN_REV0 5 105 /* 106 * Min SDA hold cycles, rev >= 1 IP. Revision-specific value, PG439 page 24, 107 * AXI_I3C_SDA_HOLD_TIME register detail 108 */ 109 #define XI3C_THOLD_MIN_REV1 6 110 /* 111 * SCL/SDA pre-bias to account for the HW pipeline. PG439 page 24, 112 * AXI_I3C_SDA_HOLD_TIME register detail 113 */ 114 #define XI3C_CYCLE_ADJUST 2 115 /* Short settling delay so the FIFO reset assert/de-assert takes effect before the FIFOs are used */ 116 #define XI3C_FIFO_RESET_DELAY_US 10 117 /* 118 * Poll/sleep slice for FIFO and response waits: small enough to stay 119 * responsive, avoids busy-waiting 120 */ 121 #define XI3C_POLL_INTERVAL_US 10 122 123 #define XI3C_I2C_MODE 0 124 #define XI3C_I2C_TID 0 125 #define XI3C_SDR_MODE 1 126 #define XI3C_SDR_TID 1 127 128 #define XI3C_WORD_LEN 4 129 130 /* Software guard: 500 ms (us, for readl_poll_timeout) to bail out if no response word arrives */ 131 #define XI3C_RESP_TIMEOUT_US 500000 132 /* Software guard: 1 s (ms, for msecs_to_jiffies) to bail out if a transfer never completes */ 133 #define XI3C_XFER_TIMEOUT_MS 1000 134 135 struct xi3c_cmd { 136 const void *tx_buf; 137 void *rx_buf; 138 u16 tx_len; 139 u16 rx_len; 140 u16 rx_actual; 141 u8 addr; 142 u8 type; 143 u8 tid; 144 bool rnw; 145 bool is_daa; 146 bool continued; 147 enum i3c_error_code err; 148 }; 149 150 struct xi3c_xfer { 151 unsigned int ncmds; 152 unsigned int nissued; 153 struct xi3c_cmd cmds[] __counted_by(ncmds); 154 }; 155 156 /** 157 * struct xi3c_master - I3C master controller state. 158 * @base: I3C master controller embedded by the framework. 159 * @dev: Pointer to the backing device structure. 160 * @membase: Memory base of the HW registers. 161 * @pclk: Input clock driving the controller. 162 * @lock: Serializes transfers and CCC submission. 163 * @daa: ENTDAA enumeration state. 164 * @daa.addrs: Dynamic addresses assigned in enumeration order. 165 * @daa.index: Number of responders enumerated so far. 166 */ 167 struct xi3c_master { 168 struct i3c_master_controller base; 169 struct device *dev; 170 void __iomem *membase; 171 struct clk *pclk; 172 struct mutex lock; /* serializes transfers and CCC submission */ 173 struct { 174 u8 addrs[XI3C_MAX_DEVS]; 175 u8 index; 176 } daa; 177 }; 178 179 static inline struct xi3c_master * 180 to_xi3c_master(struct i3c_master_controller *master) 181 { 182 return container_of(master, struct xi3c_master, base); 183 } 184 185 static inline u8 xi3c_get_revision_number(struct xi3c_master *master) 186 { 187 return FIELD_GET(XI3C_REV_NUM_MASK, 188 ioread32(master->membase + XI3C_VERSION_OFFSET)); 189 } 190 191 static inline u16 xi3c_wr_fifo_level(struct xi3c_master *master) 192 { 193 return ioread32(master->membase + XI3C_FIFO_LVL_STATUS_OFFSET) & 194 XI3C_FIFO_LEVEL_MASK; 195 } 196 197 static inline u16 xi3c_rd_fifo_level(struct xi3c_master *master) 198 { 199 return ioread32(master->membase + XI3C_FIFO_LVL_STATUS_1_OFFSET) & 200 XI3C_FIFO_LEVEL_MASK; 201 } 202 203 static inline bool xi3c_is_resp_available(struct xi3c_master *master) 204 { 205 return FIELD_GET(XI3C_SR_RESP_NOT_EMPTY_MASK, 206 ioread32(master->membase + XI3C_SR_OFFSET)); 207 } 208 209 static int xi3c_get_response(struct xi3c_master *master, struct xi3c_cmd *cmd) 210 { 211 u32 response_data; 212 u32 resp_reg; 213 u8 code; 214 int ret; 215 216 ret = readl_poll_timeout(master->membase + XI3C_SR_OFFSET, 217 resp_reg, 218 resp_reg & XI3C_SR_RESP_NOT_EMPTY_MASK, 219 XI3C_POLL_INTERVAL_US, XI3C_RESP_TIMEOUT_US); 220 if (ret) { 221 dev_err(master->dev, "XI3C response timeout\n"); 222 return ret; 223 } 224 225 response_data = ioread32(master->membase + XI3C_RESP_STATUS_FIFO_OFFSET); 226 code = FIELD_GET(XI3C_RESP_CODE_MASK, response_data); 227 228 switch (code) { 229 case XI3C_RESP_CODE_SUCCESS: 230 cmd->err = I3C_ERROR_UNKNOWN; 231 cmd->rx_actual = FIELD_GET(XI3C_RESP_BYTES_MASK, response_data); 232 return 0; 233 case XI3C_RESP_CODE_READ_EARLY_TERM: 234 /* Short read: valid data, but controller parked in STOP and must be resumed */ 235 cmd->err = I3C_ERROR_UNKNOWN; 236 cmd->rx_actual = FIELD_GET(XI3C_RESP_BYTES_MASK, response_data); 237 return XI3C_XFER_SHORT_READ; 238 case XI3C_RESP_CODE_NO_TARGET: 239 case XI3C_RESP_CODE_NACK: 240 cmd->err = I3C_ERROR_M2; 241 return cmd->is_daa ? -ENODEV : -EIO; 242 default: 243 cmd->err = I3C_ERROR_M0; 244 dev_err(master->dev, "XI3C transfer error, response code %u\n", 245 code); 246 return -EIO; 247 } 248 } 249 250 static inline void xi3c_writesl_be(void __iomem *addr, const void *buffer, 251 unsigned int count) 252 { 253 const u32 *buf = buffer; 254 255 while (count--) 256 iowrite32be(get_unaligned(buf++), addr); 257 } 258 259 static inline void xi3c_readsl_be(const void __iomem *addr, void *buffer, 260 unsigned int count) 261 { 262 u32 *buf = buffer; 263 264 while (count--) 265 put_unaligned(ioread32be(addr), buf++); 266 } 267 268 static inline void xi3c_writel_fifo(void __iomem *addr, const void *buf, 269 int nbytes) 270 { 271 xi3c_writesl_be(addr, buf, nbytes / 4); 272 if (nbytes & 3) { 273 u32 tmp = 0; 274 275 memcpy(&tmp, (const u8 *)buf + (nbytes & ~3), nbytes & 3); 276 xi3c_writesl_be(addr, &tmp, 1); 277 } 278 } 279 280 static inline void xi3c_readl_fifo(const void __iomem *addr, void *buf, 281 int nbytes) 282 { 283 xi3c_readsl_be(addr, buf, nbytes / 4); 284 if (nbytes & 3) { 285 u32 tmp; 286 287 xi3c_readsl_be(addr, &tmp, 1); 288 memcpy((u8 *)buf + (nbytes & ~3), &tmp, nbytes & 3); 289 } 290 } 291 292 static void xi3c_master_write_to_cmdfifo(struct xi3c_master *master, 293 struct xi3c_cmd *cmd, u16 len) 294 { 295 u32 transfer_cmd; 296 u8 addr; 297 298 addr = ((cmd->addr & XI3C_ADDR_MASK) << 1) | (u8)cmd->rnw; 299 300 transfer_cmd = FIELD_PREP(XI3C_CMD_TYPE, cmd->type); 301 transfer_cmd |= FIELD_PREP(XI3C_CMD_TERMINATE, !cmd->continued); 302 transfer_cmd |= FIELD_PREP(XI3C_CMD_ADDR, addr); 303 transfer_cmd |= FIELD_PREP(XI3C_CMD_TID, cmd->tid); 304 305 /* 306 * For dynamic addressing, an additional 1-byte length must be added 307 * to the command FIFO to account for the address present in the TX FIFO 308 */ 309 if (cmd->is_daa) { 310 xi3c_writel_fifo(master->membase + XI3C_WR_FIFO_OFFSET, 311 cmd->tx_buf, cmd->tx_len); 312 313 len++; 314 } 315 316 transfer_cmd |= FIELD_PREP(XI3C_CMD_LEN, len); 317 iowrite32(transfer_cmd, master->membase + XI3C_CMD_FIFO_OFFSET); 318 } 319 320 static inline void xi3c_master_enable(struct xi3c_master *master) 321 { 322 iowrite32(ioread32(master->membase + XI3C_CR_OFFSET) | XI3C_CR_EN_MASK, 323 master->membase + XI3C_CR_OFFSET); 324 } 325 326 static inline void xi3c_master_disable(struct xi3c_master *master) 327 { 328 iowrite32(ioread32(master->membase + XI3C_CR_OFFSET) & ~XI3C_CR_EN_MASK, 329 master->membase + XI3C_CR_OFFSET); 330 } 331 332 static inline void xi3c_master_resume(struct xi3c_master *master) 333 { 334 iowrite32(ioread32(master->membase + XI3C_CR_OFFSET) | 335 XI3C_CR_RESUME_MASK, master->membase + XI3C_CR_OFFSET); 336 } 337 338 static void xi3c_master_reset_fifos(struct xi3c_master *master) 339 { 340 u32 data; 341 342 /* Assert FIFO reset. */ 343 data = ioread32(master->membase + XI3C_RESET_OFFSET); 344 data |= XI3C_FIFOS_RST_MASK; 345 iowrite32(data, master->membase + XI3C_RESET_OFFSET); 346 /* Read-back flushes the posted write before the settling delay below. */ 347 ioread32(master->membase + XI3C_RESET_OFFSET); 348 fsleep(XI3C_FIFO_RESET_DELAY_US); 349 350 /* De-assert FIFO reset, then wait for the FIFOs to come back up. */ 351 data &= ~XI3C_FIFOS_RST_MASK; 352 iowrite32(data, master->membase + XI3C_RESET_OFFSET); 353 ioread32(master->membase + XI3C_RESET_OFFSET); 354 fsleep(XI3C_FIFO_RESET_DELAY_US); 355 } 356 357 static inline void xi3c_master_init(struct xi3c_master *master) 358 { 359 /* Reset fifos */ 360 xi3c_master_reset_fifos(master); 361 362 /* Enable controller */ 363 xi3c_master_enable(master); 364 } 365 366 static inline void xi3c_master_reinit(struct xi3c_master *master) 367 { 368 /* Reset fifos */ 369 xi3c_master_reset_fifos(master); 370 371 /* Resume controller */ 372 xi3c_master_resume(master); 373 } 374 375 static struct xi3c_xfer *xi3c_master_alloc_xfer(unsigned int ncmds) 376 { 377 struct xi3c_xfer *xfer; 378 379 xfer = kzalloc_flex(*xfer, cmds, ncmds); 380 if (!xfer) 381 return NULL; 382 383 xfer->ncmds = ncmds; 384 385 return xfer; 386 } 387 388 static void xi3c_master_rd_from_rx_fifo(struct xi3c_master *master, 389 struct xi3c_cmd *cmd) 390 { 391 u16 rx_data_available; 392 u16 copy_len; 393 u16 len; 394 395 rx_data_available = xi3c_rd_fifo_level(master); 396 len = rx_data_available * XI3C_WORD_LEN; 397 398 if (!len) 399 return; 400 401 copy_len = min(len, cmd->rx_len); 402 xi3c_readl_fifo(master->membase + XI3C_RD_FIFO_OFFSET, 403 (u8 *)cmd->rx_buf, copy_len); 404 405 cmd->rx_buf = (u8 *)cmd->rx_buf + copy_len; 406 cmd->rx_len -= copy_len; 407 } 408 409 static int xi3c_master_read(struct xi3c_master *master, struct xi3c_cmd *cmd) 410 { 411 unsigned long timeout; 412 u32 status_reg; 413 int ret; 414 415 if (cmd->rx_len > XI3C_MAXDATA_LENGTH) 416 return -EINVAL; 417 /* 418 * Zero-length probes (e.g. i2cdetect) legitimately pass a NULL 419 * buffer; only a non-zero length requires one. 420 */ 421 if (cmd->rx_len && !cmd->rx_buf) 422 return -EINVAL; 423 424 /* Fill command fifo */ 425 xi3c_master_write_to_cmdfifo(master, cmd, cmd->rx_len); 426 427 if (!cmd->rx_len) 428 return 0; 429 430 ret = readl_poll_timeout(master->membase + XI3C_SR_OFFSET, 431 status_reg, 432 status_reg & (XI3C_RD_FIFO_NOT_EMPTY_MASK | 433 XI3C_SR_RESP_NOT_EMPTY_MASK), 434 XI3C_POLL_INTERVAL_US, XI3C_RESP_TIMEOUT_US); 435 if (ret) { 436 dev_err(master->dev, "XI3C read timeout\n"); 437 return ret; 438 } 439 440 if (!(status_reg & XI3C_RD_FIFO_NOT_EMPTY_MASK)) 441 return 0; 442 443 timeout = jiffies + msecs_to_jiffies(XI3C_XFER_TIMEOUT_MS); 444 445 /* Read data from rx fifo */ 446 while (cmd->rx_len > 0 && !xi3c_is_resp_available(master)) { 447 if (time_after(jiffies, timeout)) { 448 dev_err(master->dev, "XI3C read timeout\n"); 449 return -EIO; 450 } 451 xi3c_master_rd_from_rx_fifo(master, cmd); 452 usleep_range(XI3C_POLL_INTERVAL_US, 2 * XI3C_POLL_INTERVAL_US); 453 } 454 455 /* Read remaining data */ 456 xi3c_master_rd_from_rx_fifo(master, cmd); 457 458 return 0; 459 } 460 461 static void xi3c_master_wr_to_tx_fifo(struct xi3c_master *master, 462 struct xi3c_cmd *cmd) 463 { 464 u16 wrfifo_space; 465 u16 len; 466 467 wrfifo_space = xi3c_wr_fifo_level(master); 468 if (cmd->tx_len > wrfifo_space * XI3C_WORD_LEN) 469 len = wrfifo_space * XI3C_WORD_LEN; 470 else 471 len = cmd->tx_len; 472 473 if (len) { 474 xi3c_writel_fifo(master->membase + XI3C_WR_FIFO_OFFSET, cmd->tx_buf, 475 len); 476 477 cmd->tx_buf = (const u8 *)cmd->tx_buf + len; 478 cmd->tx_len -= len; 479 } 480 } 481 482 static int xi3c_master_write(struct xi3c_master *master, struct xi3c_cmd *cmd) 483 { 484 unsigned long timeout; 485 u16 cmd_len; 486 487 if (cmd->tx_len > XI3C_MAXDATA_LENGTH) 488 return -EINVAL; 489 /* 490 * Zero-length probes (e.g. i2cdetect) legitimately pass a NULL 491 * buffer; only a non-zero length requires one. 492 */ 493 if (cmd->tx_len && !cmd->tx_buf) 494 return -EINVAL; 495 496 cmd_len = cmd->tx_len; 497 498 /* Fill Tx fifo */ 499 xi3c_master_wr_to_tx_fifo(master, cmd); 500 501 /* Write to command fifo */ 502 xi3c_master_write_to_cmdfifo(master, cmd, cmd_len); 503 504 timeout = jiffies + msecs_to_jiffies(XI3C_XFER_TIMEOUT_MS); 505 /* Fill if any remaining data to tx fifo */ 506 while (cmd->tx_len > 0 && !xi3c_is_resp_available(master)) { 507 if (time_after(jiffies, timeout)) { 508 dev_err(master->dev, "XI3C write timeout\n"); 509 return -EIO; 510 } 511 512 xi3c_master_wr_to_tx_fifo(master, cmd); 513 usleep_range(XI3C_POLL_INTERVAL_US, 2 * XI3C_POLL_INTERVAL_US); 514 } 515 516 return 0; 517 } 518 519 static int xi3c_master_xfer(struct xi3c_master *master, struct xi3c_cmd *cmd) 520 { 521 int ret; 522 523 if (cmd->rnw) 524 ret = xi3c_master_read(master, cmd); 525 else 526 ret = xi3c_master_write(master, cmd); 527 528 if (ret) 529 goto err_xfer_out; 530 531 ret = xi3c_get_response(master, cmd); 532 if (ret < 0) 533 goto err_xfer_out; 534 535 /* Short read leaves the controller parked in STOP; resume it for the next command */ 536 if (ret == XI3C_XFER_SHORT_READ) 537 xi3c_master_resume(master); 538 539 return 0; 540 541 err_xfer_out: 542 xi3c_master_reinit(master); 543 return ret; 544 } 545 546 static int xi3c_master_common_xfer(struct xi3c_master *master, 547 struct xi3c_xfer *xfer) 548 { 549 unsigned int i; 550 int ret; 551 552 guard(mutex)(&master->lock); 553 554 for (i = 0; i < xfer->ncmds; i++) { 555 ret = xi3c_master_xfer(master, &xfer->cmds[i]); 556 if (ret) { 557 /* Count commands sent on the bus; the rest never ran */ 558 xfer->nissued = i + 1; 559 return ret; 560 } 561 } 562 563 xfer->nissued = xfer->ncmds; 564 565 return 0; 566 } 567 568 static int xi3c_master_do_daa(struct i3c_master_controller *m) 569 { 570 u8 (*pid_bufs)[XI3C_DAA_SLAVEINFO_READ_BYTECOUNT]; 571 struct xi3c_master *master = to_xi3c_master(m); 572 struct xi3c_cmd *daa_cmd; 573 struct xi3c_xfer *xfer; 574 int addr, ret, i; 575 u8 last_addr = 0; 576 u8 *pid_buf; 577 u8 ccc_id; 578 579 xfer = xi3c_master_alloc_xfer(1); 580 if (!xfer) 581 return -ENOMEM; 582 583 pid_bufs = kcalloc(XI3C_MAX_DEVS, XI3C_DAA_SLAVEINFO_READ_BYTECOUNT, 584 GFP_KERNEL); 585 if (!pid_bufs) { 586 ret = -ENOMEM; 587 goto out; 588 } 589 590 /* Fill ENTDAA CCC */ 591 ccc_id = I3C_CCC_ENTDAA; 592 daa_cmd = &xfer->cmds[0]; 593 daa_cmd->addr = I3C_BROADCAST_ADDR; 594 daa_cmd->rnw = false; 595 daa_cmd->tx_buf = &ccc_id; 596 daa_cmd->tx_len = 1; 597 daa_cmd->type = XI3C_SDR_MODE; 598 daa_cmd->tid = XI3C_SDR_TID; 599 daa_cmd->continued = true; 600 601 ret = xi3c_master_common_xfer(master, xfer); 602 if (ret) { 603 /* NACK on ENTDAA broadcast means no devices to enumerate */ 604 if (daa_cmd->err == I3C_ERROR_M2) 605 ret = 0; 606 goto err_daa; 607 } 608 609 master->daa.index = 0; 610 611 while (true) { 612 struct xi3c_cmd *cmd = &xfer->cmds[0]; 613 u8 daa_byte; 614 615 /* Out of device slots; stop and keep what was enumerated */ 616 if (master->daa.index >= XI3C_MAX_DEVS) { 617 dev_warn(master->dev, 618 "DAA: reached %d devices, stopping enumeration\n", 619 XI3C_MAX_DEVS); 620 xi3c_master_reinit(master); 621 break; 622 } 623 624 addr = i3c_master_get_free_addr(m, last_addr + 1); 625 if (addr < 0) { 626 dev_warn(master->dev, 627 "DAA: no free dynamic address, stopping enumeration\n"); 628 xi3c_master_reinit(master); 629 break; 630 } 631 632 pid_buf = pid_bufs[master->daa.index]; 633 634 daa_byte = (addr << 1) | (parity8(addr) ^ 1); 635 636 cmd->tx_buf = &daa_byte; 637 cmd->tx_len = 1; 638 cmd->addr = I3C_BROADCAST_ADDR; 639 cmd->rnw = true; 640 cmd->rx_buf = pid_buf; 641 cmd->rx_len = XI3C_DAA_SLAVEINFO_READ_BYTECOUNT; 642 cmd->is_daa = true; 643 cmd->type = XI3C_SDR_MODE; 644 cmd->tid = XI3C_SDR_TID; 645 cmd->continued = true; 646 647 ret = xi3c_master_common_xfer(master, xfer); 648 649 /* -ENODEV: no more responders, enumeration complete */ 650 if (ret == -ENODEV) { 651 ret = 0; 652 break; 653 } 654 if (ret) 655 goto err_daa; 656 657 master->daa.addrs[master->daa.index] = addr; 658 last_addr = addr; 659 master->daa.index++; 660 } 661 662 for (i = 0; i < master->daa.index; i++) { 663 u64 pid; 664 665 /* Ignore per-device add errors so one failure doesn't abort the rest */ 666 i3c_master_add_i3c_dev_locked(m, master->daa.addrs[i]); 667 668 pid = FIELD_GET(XI3C_PID_MASK, 669 get_unaligned_be64(pid_bufs[i])); 670 dev_dbg(master->dev, "Client %d: PID: 0x%llx\n", i, pid); 671 } 672 673 ret = 0; 674 goto out; 675 676 err_daa: 677 xi3c_master_reinit(master); 678 out: 679 kfree(pid_bufs); 680 kfree(xfer); 681 return ret; 682 } 683 684 static bool 685 xi3c_master_supports_ccc_cmd(struct i3c_master_controller *master, 686 const struct i3c_ccc_cmd *cmd) 687 { 688 if (cmd->ndests > 1) 689 return false; 690 691 switch (cmd->id) { 692 case I3C_CCC_ENEC(true): 693 case I3C_CCC_ENEC(false): 694 case I3C_CCC_DISEC(true): 695 case I3C_CCC_DISEC(false): 696 case I3C_CCC_ENTAS(0, true): 697 case I3C_CCC_ENTAS(0, false): 698 case I3C_CCC_RSTDAA(true): 699 case I3C_CCC_RSTDAA(false): 700 case I3C_CCC_ENTDAA: 701 case I3C_CCC_SETMWL(true): 702 case I3C_CCC_SETMWL(false): 703 case I3C_CCC_SETMRL(true): 704 case I3C_CCC_SETMRL(false): 705 case I3C_CCC_SETDASA: 706 case I3C_CCC_SETNEWDA: 707 case I3C_CCC_GETMWL: 708 case I3C_CCC_GETMRL: 709 case I3C_CCC_GETPID: 710 case I3C_CCC_GETBCR: 711 case I3C_CCC_GETDCR: 712 case I3C_CCC_GETSTATUS: 713 case I3C_CCC_GETMXDS: 714 return true; 715 default: 716 return false; 717 } 718 } 719 720 static int xi3c_master_send_bdcast_ccc_cmd(struct xi3c_master *master, 721 struct i3c_ccc_cmd *ccc) 722 { 723 struct xi3c_xfer *xfer __free(kfree) = NULL; 724 u8 *buf __free(kfree) = NULL; 725 struct xi3c_cmd *cmd; 726 u16 xfer_len; 727 int ret; 728 729 if (ccc->dests[0].payload.len >= XI3C_MAXDATA_LENGTH) 730 return -EINVAL; 731 732 xfer_len = ccc->dests[0].payload.len + 1; 733 734 xfer = xi3c_master_alloc_xfer(1); 735 if (!xfer) 736 return -ENOMEM; 737 738 buf = kmalloc_objs(*buf, xfer_len); 739 if (!buf) 740 return -ENOMEM; 741 742 buf[0] = ccc->id; 743 memcpy(&buf[1], ccc->dests[0].payload.data, ccc->dests[0].payload.len); 744 745 cmd = &xfer->cmds[0]; 746 cmd->addr = ccc->dests[0].addr; 747 cmd->rnw = ccc->rnw; 748 cmd->tx_buf = buf; 749 cmd->tx_len = xfer_len; 750 cmd->type = XI3C_SDR_MODE; 751 cmd->tid = XI3C_SDR_TID; 752 cmd->continued = false; 753 754 ret = xi3c_master_common_xfer(master, xfer); 755 ccc->err = cmd->err; 756 757 return ret; 758 } 759 760 static int xi3c_master_send_direct_ccc_cmd(struct xi3c_master *master, 761 struct i3c_ccc_cmd *ccc) 762 { 763 struct xi3c_xfer *xfer __free(kfree) = NULL; 764 struct xi3c_cmd *cmd; 765 int ret; 766 767 if (ccc->dests[0].payload.len > XI3C_MAXDATA_LENGTH) 768 return -EINVAL; 769 770 xfer = xi3c_master_alloc_xfer(2); 771 if (!xfer) 772 return -ENOMEM; 773 774 /* Broadcasted message */ 775 cmd = &xfer->cmds[0]; 776 cmd->addr = I3C_BROADCAST_ADDR; 777 cmd->rnw = false; 778 cmd->tx_buf = &ccc->id; 779 cmd->tx_len = 1; 780 cmd->type = XI3C_SDR_MODE; 781 cmd->tid = XI3C_SDR_TID; 782 cmd->continued = true; 783 784 /* Directed message */ 785 cmd = &xfer->cmds[1]; 786 cmd->addr = ccc->dests[0].addr; 787 cmd->rnw = ccc->rnw; 788 if (cmd->rnw) { 789 cmd->rx_buf = ccc->dests[0].payload.data; 790 cmd->rx_len = ccc->dests[0].payload.len; 791 } else { 792 cmd->tx_buf = ccc->dests[0].payload.data; 793 cmd->tx_len = ccc->dests[0].payload.len; 794 } 795 cmd->type = XI3C_SDR_MODE; 796 cmd->tid = XI3C_SDR_TID; 797 cmd->continued = false; 798 799 ret = xi3c_master_common_xfer(master, xfer); 800 801 /* 802 * Report broadcast error if any, else the directed one, so either 803 * NACK reaches the caller 804 */ 805 ccc->err = xfer->cmds[0].err ? xfer->cmds[0].err : xfer->cmds[1].err; 806 807 /* Report actual byte count so the core sees the right length on short reads */ 808 if (!ret && ccc->rnw) 809 ccc->dests[0].payload.len = min(xfer->cmds[1].rx_actual, 810 ccc->dests[0].payload.len); 811 812 return ret; 813 } 814 815 static int xi3c_master_send_ccc_cmd(struct i3c_master_controller *m, 816 struct i3c_ccc_cmd *cmd) 817 { 818 struct xi3c_master *master = to_xi3c_master(m); 819 820 if (cmd->id & I3C_CCC_DIRECT) 821 return xi3c_master_send_direct_ccc_cmd(master, cmd); 822 823 return xi3c_master_send_bdcast_ccc_cmd(master, cmd); 824 } 825 826 static int xi3c_master_i3c_xfers(struct i3c_dev_desc *dev, 827 struct i3c_xfer *xfers, 828 int nxfers, enum i3c_xfer_mode mode) 829 { 830 struct i3c_master_controller *m = i3c_dev_get_master(dev); 831 struct xi3c_master *master = to_xi3c_master(m); 832 struct xi3c_xfer *xfer __free(kfree) = NULL; 833 int i, ret; 834 835 if (!nxfers) 836 return 0; 837 838 if (mode != I3C_SDR) 839 return -EOPNOTSUPP; 840 841 for (i = 0; i < nxfers; i++) 842 if (xfers[i].len > XI3C_MAXDATA_LENGTH) 843 return -EINVAL; 844 845 xfer = xi3c_master_alloc_xfer(nxfers); 846 if (!xfer) 847 return -ENOMEM; 848 849 for (i = 0; i < nxfers; i++) { 850 struct xi3c_cmd *cmd = &xfer->cmds[i]; 851 852 cmd->addr = dev->info.dyn_addr; 853 cmd->rnw = xfers[i].rnw; 854 855 if (cmd->rnw) { 856 cmd->rx_buf = xfers[i].data.in; 857 cmd->rx_len = xfers[i].len; 858 } else { 859 cmd->tx_buf = xfers[i].data.out; 860 cmd->tx_len = xfers[i].len; 861 } 862 863 cmd->type = XI3C_SDR_MODE; 864 cmd->tid = XI3C_SDR_TID; 865 cmd->continued = (i + 1) < nxfers; 866 } 867 868 ret = xi3c_master_common_xfer(master, xfer); 869 870 for (i = 0; i < xfer->nissued; i++) { 871 xfers[i].err = xfer->cmds[i].err; 872 if (xfers[i].rnw) 873 xfers[i].actual_len = min(xfer->cmds[i].rx_actual, 874 xfers[i].len); 875 } 876 877 return ret; 878 } 879 880 static int xi3c_master_i2c_xfers(struct i2c_dev_desc *dev, 881 struct i2c_msg *xfers, 882 int nxfers) 883 { 884 struct i3c_master_controller *m = i2c_dev_get_master(dev); 885 struct xi3c_master *master = to_xi3c_master(m); 886 struct xi3c_xfer *xfer __free(kfree) = NULL; 887 int i; 888 889 if (!nxfers) 890 return 0; 891 892 for (i = 0; i < nxfers; i++) 893 if (xfers[i].len > XI3C_MAXDATA_LENGTH) 894 return -EINVAL; 895 896 xfer = xi3c_master_alloc_xfer(nxfers); 897 if (!xfer) 898 return -ENOMEM; 899 900 for (i = 0; i < nxfers; i++) { 901 struct xi3c_cmd *cmd = &xfer->cmds[i]; 902 903 cmd->addr = xfers[i].addr & XI3C_ADDR_MASK; 904 cmd->rnw = !!(xfers[i].flags & I2C_M_RD); 905 906 if (cmd->rnw) { 907 cmd->rx_buf = xfers[i].buf; 908 cmd->rx_len = xfers[i].len; 909 } else { 910 cmd->tx_buf = xfers[i].buf; 911 cmd->tx_len = xfers[i].len; 912 } 913 914 cmd->type = XI3C_I2C_MODE; 915 cmd->tid = XI3C_I2C_TID; 916 cmd->continued = (i + 1) < nxfers; 917 } 918 919 return xi3c_master_common_xfer(master, xfer); 920 } 921 922 static int xi3c_clk_cfg(struct xi3c_master *master, unsigned long sclhz, u8 mode) 923 { 924 unsigned long core_rate, core_periodns; 925 u32 tcasmin, tsustart, tsustop, thdstart; 926 u32 thigh, tlow, thold; 927 u32 odthigh, odtlow; 928 929 core_rate = clk_get_rate(master->pclk); 930 if (!core_rate) 931 return -EINVAL; 932 933 if (!sclhz) 934 return -EINVAL; 935 936 core_periodns = DIV_ROUND_UP(NSEC_PER_SEC, core_rate); 937 938 thigh = DIV_ROUND_UP(core_rate, sclhz) >> 1; 939 tlow = thigh; 940 941 /* Reject rates whose timing exceeds the 18-bit registers (would wrap) */ 942 if (thigh <= XI3C_CYCLE_ADJUST || 943 (thigh - XI3C_CYCLE_ADJUST) > XI3C_TIMING_MASK) 944 return -EINVAL; 945 946 /* Hold time : 40% of tlow time */ 947 thold = (tlow * 4) / 10; 948 949 if (xi3c_get_revision_number(master) == 0) 950 thold = max_t(u32, thold, XI3C_THOLD_MIN_REV0); 951 else 952 thold = max_t(u32, thold, XI3C_THOLD_MIN_REV1); 953 954 iowrite32((thigh - XI3C_CYCLE_ADJUST) & XI3C_TIMING_MASK, 955 master->membase + XI3C_SCL_HIGH_TIME_OFFSET); 956 iowrite32((tlow - XI3C_CYCLE_ADJUST) & XI3C_TIMING_MASK, 957 master->membase + XI3C_SCL_LOW_TIME_OFFSET); 958 iowrite32((thold - XI3C_CYCLE_ADJUST) & XI3C_TIMING_MASK, 959 master->membase + XI3C_SDA_HOLD_TIME_OFFSET); 960 961 if (mode == XI3C_I2C_MODE) { 962 iowrite32((thigh - XI3C_CYCLE_ADJUST) & XI3C_TIMING_MASK, 963 master->membase + XI3C_OD_SCL_HIGH_TIME_OFFSET); 964 iowrite32((tlow - XI3C_CYCLE_ADJUST) & XI3C_TIMING_MASK, 965 master->membase + XI3C_OD_SCL_LOW_TIME_OFFSET); 966 967 tcasmin = DIV_ROUND_UP(XI3C_I2C_TCASMIN_NS, core_periodns); 968 } else { 969 odtlow = DIV_ROUND_UP(XI3C_OD_TLOW_NS, core_periodns); 970 odthigh = DIV_ROUND_UP(XI3C_OD_THIGH_NS, core_periodns); 971 972 odtlow = max(tlow, odtlow); 973 odthigh = min(thigh, odthigh); 974 975 if (odthigh <= XI3C_CYCLE_ADJUST) 976 return -EINVAL; 977 978 iowrite32((odthigh - XI3C_CYCLE_ADJUST) & XI3C_TIMING_MASK, 979 master->membase + XI3C_OD_SCL_HIGH_TIME_OFFSET); 980 iowrite32((odtlow - XI3C_CYCLE_ADJUST) & XI3C_TIMING_MASK, 981 master->membase + XI3C_OD_SCL_LOW_TIME_OFFSET); 982 983 tcasmin = DIV_ROUND_UP(XI3C_TCASMIN_NS, core_periodns); 984 } 985 986 thdstart = max(thigh, tcasmin); 987 tsustart = max(tlow, tcasmin); 988 tsustop = max(tlow, tcasmin); 989 990 iowrite32((tsustart - XI3C_CYCLE_ADJUST) & XI3C_TIMING_MASK, 991 master->membase + XI3C_TSU_START_OFFSET); 992 iowrite32((thdstart - XI3C_CYCLE_ADJUST) & XI3C_TIMING_MASK, 993 master->membase + XI3C_THD_START_OFFSET); 994 iowrite32((tsustop - XI3C_CYCLE_ADJUST) & XI3C_TIMING_MASK, 995 master->membase + XI3C_TSU_STOP_OFFSET); 996 997 return 0; 998 } 999 1000 static int xi3c_master_bus_init(struct i3c_master_controller *m) 1001 { 1002 struct xi3c_master *master = to_xi3c_master(m); 1003 struct i3c_bus *bus = i3c_master_get_bus(m); 1004 struct i3c_device_info info = {}; 1005 unsigned long sclhz; 1006 u32 pid1_bcr_dcr; 1007 u8 mode; 1008 int ret; 1009 1010 switch (bus->mode) { 1011 case I3C_BUS_MODE_MIXED_FAST: 1012 case I3C_BUS_MODE_MIXED_LIMITED: 1013 case I3C_BUS_MODE_MIXED_SLOW: 1014 mode = XI3C_I2C_MODE; 1015 sclhz = bus->scl_rate.i2c; 1016 break; 1017 case I3C_BUS_MODE_PURE: 1018 mode = XI3C_SDR_MODE; 1019 sclhz = bus->scl_rate.i3c; 1020 break; 1021 default: 1022 return -EINVAL; 1023 } 1024 1025 ret = xi3c_clk_cfg(master, sclhz, mode); 1026 if (ret) 1027 return ret; 1028 1029 xi3c_master_init(master); 1030 1031 /* Get an address for the master. */ 1032 ret = i3c_master_get_free_addr(m, 0); 1033 if (ret < 0) 1034 return ret; 1035 1036 info.dyn_addr = ret; 1037 1038 /* Write the dynamic address value to the address register. */ 1039 iowrite32(info.dyn_addr, master->membase + XI3C_ADDRESS_OFFSET); 1040 1041 /* Read PID, BCR and DCR values, and assign to i3c device info. */ 1042 pid1_bcr_dcr = ioread32(master->membase + XI3C_PID1_BCR_DCR); 1043 info.pid = ((u64)FIELD_GET(XI3C_PID1_MASK, pid1_bcr_dcr) << 32) | 1044 ioread32(master->membase + XI3C_PID0_OFFSET); 1045 info.bcr = FIELD_GET(XI3C_BCR_MASK, pid1_bcr_dcr); 1046 info.dcr = FIELD_GET(XI3C_DCR_MASK, pid1_bcr_dcr); 1047 1048 return i3c_master_set_info(&master->base, &info); 1049 } 1050 1051 static void xi3c_master_bus_cleanup(struct i3c_master_controller *m) 1052 { 1053 struct xi3c_master *master = to_xi3c_master(m); 1054 1055 xi3c_master_disable(master); 1056 } 1057 1058 static const struct i3c_master_controller_ops xi3c_master_ops = { 1059 .bus_init = xi3c_master_bus_init, 1060 .bus_cleanup = xi3c_master_bus_cleanup, 1061 .do_daa = xi3c_master_do_daa, 1062 .supports_ccc_cmd = xi3c_master_supports_ccc_cmd, 1063 .send_ccc_cmd = xi3c_master_send_ccc_cmd, 1064 .i3c_xfers = xi3c_master_i3c_xfers, 1065 .i2c_xfers = xi3c_master_i2c_xfers, 1066 }; 1067 1068 static int xi3c_master_probe(struct platform_device *pdev) 1069 { 1070 struct xi3c_master *master; 1071 int ret; 1072 1073 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); 1074 if (!master) 1075 return -ENOMEM; 1076 1077 master->dev = &pdev->dev; 1078 1079 master->membase = devm_platform_ioremap_resource(pdev, 0); 1080 if (IS_ERR(master->membase)) 1081 return dev_err_probe(master->dev, PTR_ERR(master->membase), 1082 "Failed to map registers\n"); 1083 1084 master->pclk = devm_clk_get_enabled(master->dev, NULL); 1085 if (IS_ERR(master->pclk)) 1086 return dev_err_probe(master->dev, PTR_ERR(master->pclk), 1087 "Failed to get and enable clock\n"); 1088 1089 ret = devm_mutex_init(master->dev, &master->lock); 1090 if (ret) 1091 return ret; 1092 1093 platform_set_drvdata(pdev, master); 1094 1095 return i3c_master_register(&master->base, master->dev, 1096 &xi3c_master_ops, false); 1097 } 1098 1099 static void xi3c_master_remove(struct platform_device *pdev) 1100 { 1101 struct xi3c_master *master = platform_get_drvdata(pdev); 1102 1103 i3c_master_unregister(&master->base); 1104 } 1105 1106 static const struct of_device_id xi3c_master_of_ids[] = { 1107 { .compatible = "xlnx,axi-i3c-1.0" }, 1108 { }, 1109 }; 1110 MODULE_DEVICE_TABLE(of, xi3c_master_of_ids); 1111 1112 static struct platform_driver xi3c_master_driver = { 1113 .probe = xi3c_master_probe, 1114 .remove = xi3c_master_remove, 1115 .driver = { 1116 .name = "axi-i3c-master", 1117 .of_match_table = xi3c_master_of_ids, 1118 }, 1119 }; 1120 module_platform_driver(xi3c_master_driver); 1121 1122 MODULE_AUTHOR("Manikanta Guntupalli <manikanta.guntupalli@amd.com>"); 1123 MODULE_DESCRIPTION("AMD AXI I3C master driver"); 1124 MODULE_LICENSE("GPL"); 1125