1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2015-2026 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 /* The caprices of the preprocessor require that this be declared right here */ 28 #define CREATE_TRACE_POINTS 29 30 #include "dm_services_types.h" 31 #include "dc.h" 32 #include "link_enc_cfg.h" 33 #include "dc/inc/core_types.h" 34 #include "dal_asic_id.h" 35 #include "dmub/dmub_srv.h" 36 #include "dc/inc/hw/dmcu.h" 37 #include "dc/inc/hw/abm.h" 38 #include "dc/dc_dmub_srv.h" 39 #include "dc/dc_edid_parser.h" 40 #include "dc/dc_stat.h" 41 #include "dc/dc_state.h" 42 #include "amdgpu_dm_trace.h" 43 #include "link/protocols/link_dpcd.h" 44 #include "link_service_types.h" 45 #include "link/protocols/link_dp_capability.h" 46 #include "link/protocols/link_ddc.h" 47 48 #include "amdgpu.h" 49 #include "amdgpu_display.h" 50 #include "amdgpu_ucode.h" 51 #include "atom.h" 52 #include "amdgpu_dm.h" 53 #include "amdgpu_dm_plane.h" 54 #include "amdgpu_dm_crtc.h" 55 #include "amdgpu_dm_hdcp.h" 56 #include <drm/display/drm_hdcp_helper.h> 57 #include "amdgpu_dm_wb.h" 58 #include "amdgpu_atombios.h" 59 60 #include "amd_shared.h" 61 #include "amdgpu_dm_irq.h" 62 #include "dm_helpers.h" 63 #include "amdgpu_dm_mst_types.h" 64 #if defined(CONFIG_DEBUG_FS) 65 #include "amdgpu_dm_debugfs.h" 66 #endif 67 #include "amdgpu_dm_psr.h" 68 #include "amdgpu_dm_replay.h" 69 #include "amdgpu_dm_backlight.h" 70 #include "amdgpu_dm_audio.h" 71 #include "amdgpu_dm_dmub.h" 72 #include "amdgpu_dm_connector.h" 73 #include "amdgpu_dm_pp_smu.h" 74 #include "amdgpu_dm_freesync.h" 75 #include "amdgpu_dm_cursor.h" 76 77 #include "ivsrcid/ivsrcid_vislands30.h" 78 79 #include <linux/backlight.h> 80 #include <linux/module.h> 81 #include <linux/moduleparam.h> 82 #include <linux/types.h> 83 #include <linux/pm_runtime.h> 84 #include <linux/pci.h> 85 #include <linux/power_supply.h> 86 #include <linux/firmware.h> 87 #include <linux/component.h> 88 #include <linux/sort.h> 89 90 #include <drm/drm_privacy_screen_consumer.h> 91 #include <drm/display/drm_dp_mst_helper.h> 92 #include <drm/display/drm_hdmi_helper.h> 93 #include <drm/drm_atomic.h> 94 #include <drm/drm_atomic_uapi.h> 95 #include <drm/drm_atomic_helper.h> 96 #include <drm/drm_blend.h> 97 #include <drm/drm_fixed.h> 98 #include <drm/drm_fourcc.h> 99 #include <drm/drm_edid.h> 100 #include <drm/drm_eld.h> 101 #include <drm/drm_mode.h> 102 #include <drm/drm_utils.h> 103 #include <drm/drm_vblank.h> 104 #include <drm/drm_colorop.h> 105 #include <drm/drm_gem_atomic_helper.h> 106 107 #include <media/cec-notifier.h> 108 #include <acpi/video.h> 109 110 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 111 112 #include "modules/inc/mod_freesync.h" 113 #include "modules/inc/mod_power.h" 114 #include "modules/power/power_helpers.h" 115 116 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 117 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 118 119 /** 120 * DOC: overview 121 * 122 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 123 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM 124 * requests into DC requests, and DC responses into DRM responses. 125 * 126 * The root control structure is &struct amdgpu_display_manager. 127 */ 128 129 /* basic init/fini API */ 130 static int amdgpu_dm_init(struct amdgpu_device *adev); 131 static void amdgpu_dm_fini(struct amdgpu_device *adev); 132 133 /* 134 * initializes drm_device display related structures, based on the information 135 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 136 * drm_encoder, drm_mode_config 137 * 138 * Returns 0 on success 139 */ 140 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 141 /* removes and deallocates the drm structures, created by the above function */ 142 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 143 144 static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_commit *state); 145 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_commit *state); 146 STATIC_IFN_KUNIT void dm_enable_per_frame_crtc_master_sync(struct dc_state *context); 147 148 static int amdgpu_dm_atomic_check(struct drm_device *dev, 149 struct drm_atomic_commit *state); 150 151 static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc) 152 { 153 if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter) 154 dc_exit_ips_for_hw_access(dc); 155 } 156 157 /* 158 * dm_vblank_get_counter 159 * 160 * @brief 161 * Get counter for number of vertical blanks 162 * 163 * @param 164 * struct amdgpu_device *adev - [in] desired amdgpu device 165 * int disp_idx - [in] which CRTC to get the counter from 166 * 167 * @return 168 * Counter for vertical blanks 169 */ 170 STATIC_IFN_KUNIT u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 171 { 172 struct amdgpu_crtc *acrtc = NULL; 173 174 if (crtc >= adev->mode_info.num_crtc) 175 return 0; 176 177 acrtc = adev->mode_info.crtcs[crtc]; 178 179 if (!acrtc->dm_irq_params.stream) { 180 drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n", 181 crtc); 182 return 0; 183 } 184 185 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); 186 } 187 EXPORT_IF_KUNIT(dm_vblank_get_counter); 188 189 STATIC_IFN_KUNIT int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 190 u32 *vbl, u32 *position) 191 { 192 u32 v_blank_start = 0, v_blank_end = 0, h_position = 0, v_position = 0; 193 struct amdgpu_crtc *acrtc = NULL; 194 struct dc *dc = adev->dm.dc; 195 196 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 197 return -EINVAL; 198 199 acrtc = adev->mode_info.crtcs[crtc]; 200 201 if (!acrtc->dm_irq_params.stream) { 202 drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n", 203 crtc); 204 return 0; 205 } 206 207 if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed) 208 dc_allow_idle_optimizations(dc, false); 209 210 /* 211 * TODO rework base driver to use values directly. 212 * for now parse it back into reg-format 213 */ 214 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, 215 &v_blank_start, 216 &v_blank_end, 217 &h_position, 218 &v_position); 219 220 *position = v_position | (h_position << 16); 221 *vbl = v_blank_start | (v_blank_end << 16); 222 223 return 0; 224 } 225 EXPORT_IF_KUNIT(dm_crtc_get_scanoutpos); 226 227 STATIC_IFN_KUNIT bool dm_is_idle(struct amdgpu_ip_block *ip_block) 228 { 229 /* XXX todo */ 230 return true; 231 } 232 EXPORT_IF_KUNIT(dm_is_idle); 233 234 STATIC_IFN_KUNIT int dm_wait_for_idle(struct amdgpu_ip_block *ip_block) 235 { 236 /* XXX todo */ 237 return 0; 238 } 239 EXPORT_IF_KUNIT(dm_wait_for_idle); 240 241 STATIC_IFN_KUNIT int dm_soft_reset(struct amdgpu_ip_block *ip_block) 242 { 243 /* XXX todo */ 244 return 0; 245 } 246 EXPORT_IF_KUNIT(dm_soft_reset); 247 248 /* 249 * DC will program planes with their z-order determined by their ordering 250 * in the dc_surface_updates array. This comparator is used to sort them 251 * by descending zpos. 252 */ 253 STATIC_IFN_KUNIT int dm_plane_layer_index_cmp(const void *a, const void *b) 254 { 255 const struct dc_surface_update *sa = (struct dc_surface_update *)a; 256 const struct dc_surface_update *sb = (struct dc_surface_update *)b; 257 258 /* Sort by descending dc_plane layer_index (i.e. normalized_zpos) */ 259 return sb->surface->layer_index - sa->surface->layer_index; 260 } 261 EXPORT_IF_KUNIT(dm_plane_layer_index_cmp); 262 263 /** 264 * update_planes_and_stream_adapter() - Send planes to be updated in DC 265 * 266 * DC has a generic way to update planes and stream via 267 * dc_update_planes_and_stream function; however, DM might need some 268 * adjustments and preparation before calling it. This function is a wrapper 269 * for the dc_update_planes_and_stream that does any required configuration 270 * before passing control to DC. 271 * 272 * @dc: Display Core control structure 273 * @update_type: specify whether it is FULL/MEDIUM/FAST update 274 * @planes_count: planes count to update 275 * @stream: stream state 276 * @stream_update: stream update 277 * @array_of_surface_update: dc surface update pointer 278 * 279 */ 280 static inline bool update_planes_and_stream_adapter(struct dc *dc, 281 int update_type, 282 int planes_count, 283 struct dc_stream_state *stream, 284 struct dc_stream_update *stream_update, 285 struct dc_surface_update *array_of_surface_update) 286 { 287 sort(array_of_surface_update, planes_count, 288 sizeof(*array_of_surface_update), dm_plane_layer_index_cmp, NULL); 289 290 /* 291 * Previous frame finished and HW is ready for optimization. 292 */ 293 dc_post_update_surfaces_to_stream(dc); 294 295 return dc_update_planes_and_stream(dc, 296 array_of_surface_update, 297 planes_count, 298 stream, 299 stream_update); 300 } 301 302 STATIC_IFN_KUNIT int dm_set_clockgating_state(struct amdgpu_ip_block *ip_block, 303 enum amd_clockgating_state state) 304 { 305 return 0; 306 } 307 EXPORT_IF_KUNIT(dm_set_clockgating_state); 308 309 STATIC_IFN_KUNIT int dm_set_powergating_state(struct amdgpu_ip_block *ip_block, 310 enum amd_powergating_state state) 311 { 312 return 0; 313 } 314 EXPORT_IF_KUNIT(dm_set_powergating_state); 315 316 /* Prototypes of private functions */ 317 static int dm_early_init(struct amdgpu_ip_block *ip_block); 318 319 /* Allocate memory for FBC compressed data */ 320 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) 321 { 322 u64 pt_base; 323 u32 logical_addr_low; 324 u32 logical_addr_high; 325 u32 agp_base, agp_bot, agp_top; 326 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; 327 328 memset(pa_config, 0, sizeof(*pa_config)); 329 330 agp_base = 0; 331 agp_bot = adev->gmc.agp_start >> 24; 332 agp_top = adev->gmc.agp_end >> 24; 333 334 /* AGP aperture is disabled */ 335 if (agp_bot > agp_top) { 336 logical_addr_low = adev->gmc.fb_start >> 18; 337 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 338 AMD_APU_IS_RENOIR | 339 AMD_APU_IS_GREEN_SARDINE)) 340 /* 341 * Raven2 has a HW issue that it is unable to use the vram which 342 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 343 * workaround that increase system aperture high address (add 1) 344 * to get rid of the VM fault and hardware hang. 345 */ 346 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; 347 else 348 logical_addr_high = adev->gmc.fb_end >> 18; 349 } else { 350 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 351 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 352 AMD_APU_IS_RENOIR | 353 AMD_APU_IS_GREEN_SARDINE)) 354 /* 355 * Raven2 has a HW issue that it is unable to use the vram which 356 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 357 * workaround that increase system aperture high address (add 1) 358 * to get rid of the VM fault and hardware hang. 359 */ 360 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 361 else 362 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 363 } 364 365 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 366 367 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> 368 AMDGPU_GPU_PAGE_SHIFT); 369 page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >> 370 AMDGPU_GPU_PAGE_SHIFT); 371 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> 372 AMDGPU_GPU_PAGE_SHIFT); 373 page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >> 374 AMDGPU_GPU_PAGE_SHIFT); 375 page_table_base.high_part = upper_32_bits(pt_base); 376 page_table_base.low_part = lower_32_bits(pt_base); 377 378 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 379 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 380 381 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; 382 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 383 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 384 385 pa_config->system_aperture.fb_base = adev->gmc.fb_start; 386 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; 387 pa_config->system_aperture.fb_top = adev->gmc.fb_end; 388 389 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; 390 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; 391 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; 392 393 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; 394 395 } 396 397 static int amdgpu_dm_init_power_module(struct amdgpu_display_manager *dm) 398 { 399 struct mod_power_init_params init_data[MAX_NUM_EDP]; 400 401 if (dm->num_of_edps == 0) { 402 drm_dbg_driver( 403 dm->ddev, 404 "amdgpu: No eDP detected, skip initializing power module\n"); 405 return 0; 406 } 407 408 /* Initialize all the power module parameters */ 409 for (int i = 0; i < dm->num_of_edps; i++) { 410 init_data[i].allow_psr_smu_optimizations = 411 !!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT); 412 init_data[i].allow_psr_multi_disp_optimizations = 413 !!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT); 414 /* See dm_late_init */ 415 init_data[i].backlight_ramping_override = false; 416 init_data[i].backlight_ramping_start = 0xCCCC; 417 init_data[i].backlight_ramping_reduction = 0xCCCCCCCC; 418 init_data[i].def_varibright_level = 0; 419 init_data[i].abm_config_setting = 0; 420 init_data[i].num_backlight_levels = 101; 421 init_data[i].use_nits_based_brightness = false; 422 init_data[i].panel_max_millinits = 0; 423 init_data[i].panel_min_millinits = 0; 424 init_data[i].disable_fractional_pwm = 425 !(amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK); 426 init_data[i].use_custom_backlight_caps = false; 427 init_data[i].custom_backlight_caps_config_no = 0; 428 init_data[i].use_linear_backlight_curve = false; 429 init_data[i].def_varibright_enable = 0; 430 init_data[i].varibright_level = 0; 431 /* 432 * Power module uses 16-bit backlight levels (0xFFFF max) rather 433 * than 8-bit(0XFF max) 434 */ 435 init_data[i].min_backlight_pwm = 436 dm->backlight_caps[i].min_input_signal * 0x101; 437 init_data[i].max_backlight_pwm = 438 dm->backlight_caps[i].max_input_signal * 0x101; 439 init_data[i].min_abm_backlight = 440 dm->backlight_caps[i].min_input_signal * 0x101; 441 442 /* Min backlight level after ABM reduction, Don't allow below 1% 443 * 0xFFFF x 0.01 = 0x28F 444 */ 445 init_data[i].min_abm_backlight = (init_data[i].min_abm_backlight < 0x28F) ? 446 0x28F : init_data[i].min_abm_backlight; 447 } 448 449 dm->power_module = mod_power_create(dm->dc, init_data, dm->num_of_edps); 450 if (!dm->power_module) { 451 drm_err(dm->ddev, "amdgpu: Error allocating memory for power module\n"); 452 return -ENOMEM; 453 } 454 455 mod_power_hw_init(dm->power_module); 456 drm_dbg_driver(dm->ddev, "amdgpu: Power module init done\n"); 457 458 return 0; 459 } 460 461 static int amdgpu_dm_init(struct amdgpu_device *adev) 462 { 463 struct dc_init_data init_data; 464 struct dc_callback_init init_params; 465 int r; 466 467 adev->dm.ddev = adev_to_drm(adev); 468 adev->dm.adev = adev; 469 470 /* Zero all the fields */ 471 memset(&init_data, 0, sizeof(init_data)); 472 memset(&init_params, 0, sizeof(init_params)); 473 474 mutex_init(&adev->dm.dpia_aux_lock); 475 mutex_init(&adev->dm.dc_lock); 476 mutex_init(&adev->dm.audio_lock); 477 478 spin_lock_init(&adev->dm.dmub_lock); 479 480 if (amdgpu_dm_irq_init(adev)) { 481 drm_err(adev_to_drm(adev), "failed to initialize DM IRQ support.\n"); 482 goto error; 483 } 484 485 /* special handling for early revisions of GC 11.5.4 */ 486 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 4)) 487 init_data.asic_id.chip_family = AMDGPU_FAMILY_GC_11_5_4; 488 else 489 init_data.asic_id.chip_family = adev->family; 490 491 init_data.asic_id.pci_revision_id = adev->pdev->revision; 492 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 493 init_data.asic_id.chip_id = adev->pdev->device; 494 495 init_data.asic_id.vram_width = adev->gmc.vram_width; 496 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 497 init_data.asic_id.atombios_base_address = 498 adev->mode_info.atom_context->bios; 499 500 init_data.driver = adev; 501 502 /* cgs_device was created in dm_sw_init() */ 503 init_data.cgs_device = adev->dm.cgs_device; 504 505 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 506 507 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 508 case IP_VERSION(2, 1, 0): 509 switch (adev->dm.dmcub_fw_version) { 510 case 0: /* development */ 511 case 0x1: /* linux-firmware.git hash 6d9f399 */ 512 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ 513 init_data.flags.disable_dmcu = false; 514 break; 515 default: 516 init_data.flags.disable_dmcu = true; 517 } 518 break; 519 case IP_VERSION(2, 0, 3): 520 init_data.flags.disable_dmcu = true; 521 break; 522 default: 523 break; 524 } 525 526 /* APU support S/G display by default except: 527 * ASICs before Carrizo, 528 * RAVEN1 (Users reported stability issue) 529 */ 530 531 if (adev->asic_type < CHIP_CARRIZO) { 532 init_data.flags.gpu_vm_support = false; 533 } else if (adev->asic_type == CHIP_RAVEN) { 534 if (adev->apu_flags & AMD_APU_IS_RAVEN) 535 init_data.flags.gpu_vm_support = false; 536 else 537 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0); 538 } else { 539 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(2, 0, 3)) 540 init_data.flags.gpu_vm_support = (amdgpu_sg_display == 1); 541 else 542 init_data.flags.gpu_vm_support = 543 (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU); 544 } 545 546 adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support; 547 548 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 549 init_data.flags.fbc_support = true; 550 551 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 552 init_data.flags.multi_mon_pp_mclk_switch = true; 553 554 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 555 init_data.flags.disable_fractional_pwm = true; 556 557 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) 558 init_data.flags.edp_no_power_sequencing = true; 559 560 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) 561 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; 562 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) 563 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; 564 565 if (amdgpu_dc_feature_mask & DC_FRL_MASK) 566 init_data.flags.enable_frl = true; 567 568 init_data.flags.seamless_boot_edp_requested = false; 569 570 if (amdgpu_device_seamless_boot_supported(adev)) { 571 init_data.flags.seamless_boot_edp_requested = true; 572 init_data.flags.allow_seamless_boot_optimization = true; 573 drm_dbg(adev->dm.ddev, "Seamless boot requested\n"); 574 } 575 576 init_data.flags.enable_mipi_converter_optimization = true; 577 578 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; 579 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; 580 init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0]; 581 582 if (amdgpu_dc_debug_mask & DC_DISABLE_IPS) 583 init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; 584 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS_DYNAMIC) 585 init_data.flags.disable_ips = DMUB_IPS_DISABLE_DYNAMIC; 586 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS2_DYNAMIC) 587 init_data.flags.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; 588 else if (amdgpu_dc_debug_mask & DC_FORCE_IPS_ENABLE) 589 init_data.flags.disable_ips = DMUB_IPS_ENABLE; 590 else 591 init_data.flags.disable_ips = dm_get_default_ips_mode(adev); 592 593 init_data.flags.disable_ips_in_vpb = 0; 594 595 /* DCN35 and above supports dynamic DTBCLK switch */ 596 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0)) 597 init_data.flags.allow_0_dtb_clk = true; 598 599 /* Enable DWB for tested platforms only */ 600 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) 601 init_data.num_virtual_links = 1; 602 603 /* DCN42 and above dpia switch to unified link training path */ 604 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 2, 0)) { 605 init_data.flags.consolidated_dpia_dp_lt = true; 606 init_data.flags.enable_dpia_pre_training = true; 607 init_data.flags.unify_link_enc_assignment = true; 608 init_data.flags.usb4_bw_alloc_support = true; 609 } 610 611 /* DCN201 audio desyncs using DP SS */ 612 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 613 init_data.flags.ignore_dpref_ss = true; 614 615 retrieve_dmi_info(&adev->dm); 616 if (adev->dm.edp0_on_dp1_quirk) 617 init_data.flags.support_edp0_on_dp1 = true; 618 619 if (adev->dm.bb_from_dmub) 620 init_data.bb_from_dmub = adev->dm.bb_from_dmub; 621 else 622 init_data.bb_from_dmub = NULL; 623 624 /* Display Core create. */ 625 adev->dm.dc = dc_create(&init_data); 626 627 if (adev->dm.dc) { 628 drm_info(adev_to_drm(adev), "Display Core v%s initialized on %s\n", DC_VER, 629 dce_version_to_string(adev->dm.dc->ctx->dce_version)); 630 } else { 631 drm_info(adev_to_drm(adev), "Display Core failed to initialize with v%s!\n", DC_VER); 632 goto error; 633 } 634 635 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { 636 adev->dm.dc->debug.force_single_disp_pipe_split = false; 637 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 638 } 639 640 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 641 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 642 if (dm_should_disable_stutter(adev->pdev)) 643 adev->dm.dc->debug.disable_stutter = true; 644 645 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 646 adev->dm.dc->debug.disable_stutter = true; 647 648 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 649 adev->dm.dc->debug.disable_dsc = true; 650 651 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 652 adev->dm.dc->debug.disable_clock_gate = true; 653 654 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) 655 adev->dm.dc->debug.force_subvp_mclk_switch = true; 656 657 if (amdgpu_dc_debug_mask & DC_DISABLE_SUBVP_FAMS) { 658 adev->dm.dc->debug.force_disable_subvp = true; 659 adev->dm.dc->debug.fams2_config.bits.enable = false; 660 } 661 662 if (amdgpu_dc_debug_mask & DC_ENABLE_DML2) { 663 adev->dm.dc->debug.using_dml2 = true; 664 adev->dm.dc->debug.using_dml21 = true; 665 } 666 667 if (amdgpu_dc_debug_mask & DC_HDCP_LC_FORCE_FW_ENABLE) 668 adev->dm.dc->debug.hdcp_lc_force_fw_enable = true; 669 670 if (amdgpu_dc_debug_mask & DC_HDCP_LC_ENABLE_SW_FALLBACK) 671 adev->dm.dc->debug.hdcp_lc_enable_sw_fallback = true; 672 673 if (amdgpu_dc_debug_mask & DC_SKIP_DETECTION_LT) 674 adev->dm.dc->debug.skip_detection_link_training = true; 675 676 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; 677 678 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ 679 adev->dm.dc->debug.ignore_cable_id = true; 680 681 if (adev->dm.dc->caps.dp_hdmi21_pcon_support) 682 drm_info(adev_to_drm(adev), "DP-HDMI FRL PCON supported\n"); 683 684 r = dm_dmub_hw_init(adev); 685 if (r) { 686 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r); 687 goto error; 688 } 689 690 dc_hardware_init(adev->dm.dc); 691 692 /* GOP/vBIOS may leave an OPTC enabled for a display present at power-on 693 * but no longer driven (e.g. an external DP unplugged at boot). Such a 694 * dangling pipe keeps DCN out of idle and blocks s0i3. Power it down 695 * here when nothing needs to be preserved. 696 */ 697 if (adev->flags & AMD_IS_APU) 698 dc_disable_dangling_timing_generators(adev->dm.dc); 699 700 adev->dm.hpd_rx_offload_wq = amdgpu_dm_hpd_rx_irq_create_workqueue(adev); 701 if (!adev->dm.hpd_rx_offload_wq) { 702 drm_err(adev_to_drm(adev), "failed to create hpd rx offload workqueue.\n"); 703 goto error; 704 } 705 706 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { 707 struct dc_phy_addr_space_config pa_config; 708 709 mmhub_read_system_context(adev, &pa_config); 710 711 // Call the DC init_memory func 712 dc_setup_system_context(adev->dm.dc, &pa_config); 713 } 714 715 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 716 if (!adev->dm.freesync_module) { 717 drm_err(adev_to_drm(adev), 718 "failed to initialize freesync_module.\n"); 719 } else 720 drm_dbg_driver(adev_to_drm(adev), "freesync_module init done %p.\n", 721 adev->dm.freesync_module); 722 723 amdgpu_dm_init_color_mod(); 724 725 if (adev->dm.dc->caps.max_links > 0) { 726 adev->dm.vblank_control_workqueue = 727 create_singlethread_workqueue("dm_vblank_control_workqueue"); 728 if (!adev->dm.vblank_control_workqueue) 729 drm_err(adev_to_drm(adev), "failed to initialize vblank_workqueue.\n"); 730 } 731 732 if (adev->dm.dc->caps.ips_support && 733 adev->dm.dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) 734 adev->dm.idle_workqueue = idle_create_workqueue(adev); 735 736 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { 737 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); 738 739 if (!adev->dm.hdcp_workqueue) 740 drm_err(adev_to_drm(adev), "failed to initialize hdcp_workqueue.\n"); 741 else 742 drm_dbg_driver(adev_to_drm(adev), 743 "hdcp_workqueue init done %p.\n", 744 adev->dm.hdcp_workqueue); 745 746 dc_init_callbacks(adev->dm.dc, &init_params); 747 } 748 if (adev->dm.dc->caps.max_links > 0) { 749 adev->dm.hdmi_frl_status_polling_wq = 750 create_singlethread_workqueue("hdmi_frl_status_polling_wq"); 751 if (!adev->dm.hdmi_frl_status_polling_wq) 752 drm_err(adev_to_drm(adev), "failed to initialize hdmi_frl_status_polling_wq\n"); 753 } 754 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 755 init_completion(&adev->dm.dmub_aux_transfer_done); 756 adev->dm.dmub_notify = kzalloc_obj(struct dmub_notification); 757 if (!adev->dm.dmub_notify) { 758 drm_info(adev_to_drm(adev), "fail to allocate adev->dm.dmub_notify"); 759 goto error; 760 } 761 762 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); 763 if (!adev->dm.delayed_hpd_wq) { 764 drm_err(adev_to_drm(adev), "failed to create hpd offload workqueue.\n"); 765 goto error; 766 } 767 768 amdgpu_dm_outbox_init(adev); 769 if (!dm_register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, 770 dm_dmub_aux_setconfig_callback, false)) { 771 drm_err(adev_to_drm(adev), "fail to register dmub aux callback"); 772 goto error; 773 } 774 775 for (size_t i = 0; i < ARRAY_SIZE(adev->dm.fused_io); i++) 776 init_completion(&adev->dm.fused_io[i].replied); 777 778 if (!dm_register_dmub_notify_callback(adev, DMUB_NOTIFICATION_FUSED_IO, 779 dm_dmub_aux_fused_io_callback, false)) { 780 drm_err(adev_to_drm(adev), "fail to register dmub fused io callback"); 781 goto error; 782 } 783 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. 784 * It is expected that DMUB will resend any pending notifications at this point. Note 785 * that hpd and hpd_irq handler registration are deferred to 786 * amdgpu_dm_register_hpd_handlers() to align legacy interface initialization 787 * sequence. Connection status will be proactivly detected once in the 788 * amdgpu_dm_initialize_drm_device. 789 */ 790 dc_enable_dmub_outbox(adev->dm.dc); 791 792 /* DPIA trace goes to dmesg logs only if outbox is enabled */ 793 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE) 794 dc_dmub_srv_enable_dpia_trace(adev->dm.dc); 795 } 796 797 if (amdgpu_dm_initialize_drm_device(adev)) { 798 drm_err(adev_to_drm(adev), 799 "failed to initialize sw for display support.\n"); 800 goto error; 801 } 802 803 if (amdgpu_dm_init_power_module(&adev->dm)) 804 goto error; 805 806 /* create fake encoders for MST */ 807 dm_dp_create_fake_mst_encoders(adev); 808 809 /* TODO: Add_display_info? */ 810 811 /* TODO use dynamic cursor width */ 812 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 813 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 814 815 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 816 drm_err(adev_to_drm(adev), 817 "failed to initialize vblank for display support.\n"); 818 goto error; 819 } 820 821 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 822 amdgpu_dm_crtc_secure_display_create_contexts(adev); 823 if (!adev->dm.secure_display_ctx.crtc_ctx) 824 drm_err(adev_to_drm(adev), "failed to initialize secure display contexts.\n"); 825 826 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 0, 1)) 827 adev->dm.secure_display_ctx.support_mul_roi = true; 828 829 #endif 830 831 drm_dbg_driver(adev_to_drm(adev), "KMS initialized.\n"); 832 833 return 0; 834 error: 835 amdgpu_dm_fini(adev); 836 837 return -EINVAL; 838 } 839 840 static int amdgpu_dm_early_fini(struct amdgpu_ip_block *ip_block) 841 { 842 struct amdgpu_device *adev = ip_block->adev; 843 844 amdgpu_dm_audio_fini(adev); 845 846 return 0; 847 } 848 849 static void amdgpu_dm_fini(struct amdgpu_device *adev) 850 { 851 int i; 852 853 if (adev->dm.vblank_control_workqueue) { 854 destroy_workqueue(adev->dm.vblank_control_workqueue); 855 adev->dm.vblank_control_workqueue = NULL; 856 } 857 858 if (adev->dm.idle_workqueue) { 859 if (adev->dm.idle_workqueue->running) { 860 adev->dm.idle_workqueue->enable = false; 861 flush_work(&adev->dm.idle_workqueue->work); 862 } 863 864 kfree(adev->dm.idle_workqueue); 865 adev->dm.idle_workqueue = NULL; 866 } 867 868 /* 869 * Disable ISM before dc_destroy() invalidates dm->dc. 870 * 871 * Quiesce workers first without dc_lock (they take dc_lock 872 * themselves, so syncing under it would deadlock), then drive the 873 * FSM back to FULL_POWER_RUNNING under dc_lock. 874 */ 875 amdgpu_dm_ism_disable(&adev->dm); 876 scoped_guard(mutex, &adev->dm.dc_lock) 877 amdgpu_dm_ism_force_full_power(&adev->dm); 878 879 amdgpu_dm_destroy_drm_device(&adev->dm); 880 881 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 882 if (adev->dm.secure_display_ctx.crtc_ctx) { 883 for (i = 0; i < adev->mode_info.num_crtc; i++) { 884 if (adev->dm.secure_display_ctx.crtc_ctx[i].crtc) { 885 flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].notify_ta_work); 886 flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].forward_roi_work); 887 } 888 } 889 kfree(adev->dm.secure_display_ctx.crtc_ctx); 890 adev->dm.secure_display_ctx.crtc_ctx = NULL; 891 } 892 #endif 893 if (adev->dm.hdcp_workqueue) { 894 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); 895 adev->dm.hdcp_workqueue = NULL; 896 } 897 898 if (adev->dm.dc) { 899 dc_deinit_callbacks(adev->dm.dc); 900 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 901 if (dc_enable_dmub_notifications(adev->dm.dc)) { 902 kfree(adev->dm.dmub_notify); 903 adev->dm.dmub_notify = NULL; 904 destroy_workqueue(adev->dm.delayed_hpd_wq); 905 adev->dm.delayed_hpd_wq = NULL; 906 } 907 } 908 909 if (adev->dm.dmub_bo) 910 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 911 &adev->dm.dmub_bo_gpu_addr, 912 &adev->dm.dmub_bo_cpu_addr); 913 914 if (adev->dm.boot_time_crc_info.bo_ptr) 915 amdgpu_bo_free_kernel(&adev->dm.boot_time_crc_info.bo_ptr, 916 &adev->dm.boot_time_crc_info.gpu_addr, 917 &adev->dm.boot_time_crc_info.cpu_addr); 918 919 if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) { 920 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { 921 if (adev->dm.hpd_rx_offload_wq[i].wq) { 922 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); 923 adev->dm.hpd_rx_offload_wq[i].wq = NULL; 924 } 925 } 926 927 kfree(adev->dm.hpd_rx_offload_wq); 928 adev->dm.hpd_rx_offload_wq = NULL; 929 } 930 931 amdgpu_dm_irq_fini(adev); 932 933 /* DC Destroy TODO: Replace destroy DAL */ 934 if (adev->dm.dc) 935 dc_destroy(&adev->dm.dc); 936 937 if (adev->dm.cgs_device) { 938 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 939 adev->dm.cgs_device = NULL; 940 } 941 if (adev->dm.freesync_module) { 942 mod_freesync_destroy(adev->dm.freesync_module); 943 adev->dm.freesync_module = NULL; 944 } 945 946 if (adev->dm.power_module) { 947 mod_power_destroy(adev->dm.power_module); 948 adev->dm.power_module = NULL; 949 } 950 mutex_destroy(&adev->dm.audio_lock); 951 mutex_destroy(&adev->dm.dc_lock); 952 mutex_destroy(&adev->dm.dpia_aux_lock); 953 } 954 955 static int load_dmcu_fw(struct amdgpu_device *adev) 956 { 957 const char *fw_name_dmcu = NULL; 958 int r; 959 const struct dmcu_firmware_header_v1_0 *hdr; 960 961 switch (adev->asic_type) { 962 #if defined(CONFIG_DRM_AMD_DC_SI) 963 case CHIP_TAHITI: 964 case CHIP_PITCAIRN: 965 case CHIP_VERDE: 966 case CHIP_OLAND: 967 #endif 968 case CHIP_BONAIRE: 969 case CHIP_HAWAII: 970 case CHIP_KAVERI: 971 case CHIP_KABINI: 972 case CHIP_MULLINS: 973 case CHIP_TONGA: 974 case CHIP_FIJI: 975 case CHIP_CARRIZO: 976 case CHIP_STONEY: 977 case CHIP_POLARIS11: 978 case CHIP_POLARIS10: 979 case CHIP_POLARIS12: 980 case CHIP_VEGAM: 981 case CHIP_VEGA10: 982 case CHIP_VEGA12: 983 case CHIP_VEGA20: 984 return 0; 985 case CHIP_NAVI12: 986 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; 987 break; 988 case CHIP_RAVEN: 989 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 990 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 991 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 992 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 993 else 994 return 0; 995 break; 996 default: 997 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 998 case IP_VERSION(2, 0, 2): 999 case IP_VERSION(2, 0, 3): 1000 case IP_VERSION(2, 0, 0): 1001 case IP_VERSION(2, 1, 0): 1002 case IP_VERSION(3, 0, 0): 1003 case IP_VERSION(3, 0, 2): 1004 case IP_VERSION(3, 0, 3): 1005 case IP_VERSION(3, 0, 1): 1006 case IP_VERSION(3, 1, 2): 1007 case IP_VERSION(3, 1, 3): 1008 case IP_VERSION(3, 1, 4): 1009 case IP_VERSION(3, 1, 5): 1010 case IP_VERSION(3, 1, 6): 1011 case IP_VERSION(3, 2, 0): 1012 case IP_VERSION(3, 2, 1): 1013 case IP_VERSION(3, 5, 0): 1014 case IP_VERSION(3, 5, 1): 1015 case IP_VERSION(3, 6, 0): 1016 case IP_VERSION(4, 0, 1): 1017 case IP_VERSION(4, 2, 0): 1018 case IP_VERSION(4, 2, 1): 1019 case IP_VERSION(6, 0, 0): 1020 return 0; 1021 default: 1022 break; 1023 } 1024 drm_err(adev_to_drm(adev), "Unsupported ASIC type: 0x%X\n", adev->asic_type); 1025 return -EINVAL; 1026 } 1027 1028 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1029 drm_dbg_kms(adev_to_drm(adev), "dm: DMCU firmware not supported on direct or SMU loading\n"); 1030 return 0; 1031 } 1032 1033 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, AMDGPU_UCODE_REQUIRED, 1034 "%s", fw_name_dmcu); 1035 if (r == -ENODEV) { 1036 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 1037 drm_dbg_kms(adev_to_drm(adev), "dm: DMCU firmware not found\n"); 1038 adev->dm.fw_dmcu = NULL; 1039 return 0; 1040 } 1041 if (r) { 1042 drm_err(adev_to_drm(adev), "amdgpu_dm: Can't validate firmware \"%s\"\n", 1043 fw_name_dmcu); 1044 amdgpu_ucode_release(&adev->dm.fw_dmcu); 1045 return r; 1046 } 1047 1048 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 1049 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 1050 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 1051 adev->firmware.fw_size += 1052 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1053 1054 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 1055 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 1056 adev->firmware.fw_size += 1057 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1058 1059 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 1060 1061 drm_dbg_kms(adev_to_drm(adev), "PSP loading DMCU firmware\n"); 1062 1063 return 0; 1064 } 1065 1066 static int dm_sw_init(struct amdgpu_ip_block *ip_block) 1067 { 1068 struct amdgpu_device *adev = ip_block->adev; 1069 int r; 1070 1071 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 1072 1073 if (!adev->dm.cgs_device) { 1074 drm_err(adev_to_drm(adev), "failed to create cgs device.\n"); 1075 return -EINVAL; 1076 } 1077 1078 /* Moved from dm init since we need to use allocations for storing bounding box data */ 1079 INIT_LIST_HEAD(&adev->dm.da_list); 1080 1081 r = dm_dmub_sw_init(adev); 1082 if (r) 1083 return r; 1084 1085 return load_dmcu_fw(adev); 1086 } 1087 1088 static int dm_sw_fini(struct amdgpu_ip_block *ip_block) 1089 { 1090 struct amdgpu_device *adev = ip_block->adev; 1091 struct dal_allocation *da; 1092 1093 list_for_each_entry(da, &adev->dm.da_list, list) { 1094 if (adev->dm.bb_from_dmub == (void *) da->cpu_ptr) { 1095 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 1096 list_del(&da->list); 1097 kfree(da); 1098 adev->dm.bb_from_dmub = NULL; 1099 break; 1100 } 1101 } 1102 1103 1104 kfree(adev->dm.dmub_fb_info); 1105 adev->dm.dmub_fb_info = NULL; 1106 1107 if (adev->dm.dmub_srv) { 1108 dmub_srv_destroy(adev->dm.dmub_srv); 1109 kfree(adev->dm.dmub_srv); 1110 adev->dm.dmub_srv = NULL; 1111 } 1112 1113 amdgpu_ucode_release(&adev->dm.dmub_fw); 1114 amdgpu_ucode_release(&adev->dm.fw_dmcu); 1115 1116 return 0; 1117 } 1118 1119 1120 static void amdgpu_dm_boot_time_crc_init(struct amdgpu_device *adev) 1121 { 1122 struct dm_boot_time_crc_info *bootcrc_info = NULL; 1123 struct dmub_srv *dmub = NULL; 1124 union dmub_fw_boot_options option = {0}; 1125 int ret = 0; 1126 const uint32_t fb_size = 3 * 1024 * 1024; /* 3MB for DCC pattern */ 1127 1128 if (!adev || !adev->dm.dc || !adev->dm.dc->ctx || 1129 !adev->dm.dc->ctx->dmub_srv) { 1130 return; 1131 } 1132 1133 dmub = adev->dm.dc->ctx->dmub_srv->dmub; 1134 bootcrc_info = &adev->dm.boot_time_crc_info; 1135 1136 if (!dmub || !dmub->hw_funcs.get_fw_boot_option) { 1137 drm_dbg(adev_to_drm(adev), "failed to init boot time crc buffer\n"); 1138 return; 1139 } 1140 1141 option = dmub->hw_funcs.get_fw_boot_option(dmub); 1142 1143 /* Return if boot time CRC is not enabled */ 1144 if (option.bits.bootcrc_en_at_S0i3 == 0) 1145 return; 1146 1147 /* Create a buffer for boot time CRC */ 1148 ret = amdgpu_bo_create_kernel(adev, fb_size, PAGE_SIZE, 1149 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT, 1150 &bootcrc_info->bo_ptr, 1151 &bootcrc_info->gpu_addr, 1152 &bootcrc_info->cpu_addr); 1153 1154 if (ret) { 1155 drm_dbg(adev_to_drm(adev), "failed to create boot time crc buffer\n"); 1156 } else { 1157 bootcrc_info->size = fb_size; 1158 1159 drm_dbg(adev_to_drm(adev), "boot time crc buffer created addr 0x%llx, size %u\n", 1160 bootcrc_info->gpu_addr, bootcrc_info->size); 1161 1162 /* Send the buffer info to DMUB */ 1163 dc_dmub_srv_boot_time_crc_init(adev->dm.dc, 1164 bootcrc_info->gpu_addr, bootcrc_info->size); 1165 } 1166 } 1167 1168 static int dm_late_init(struct amdgpu_ip_block *ip_block) 1169 { 1170 struct amdgpu_device *adev = ip_block->adev; 1171 1172 struct dmcu_iram_parameters params; 1173 unsigned int linear_lut[16]; 1174 int i; 1175 struct dmcu *dmcu = NULL; 1176 1177 dmcu = adev->dm.dc->res_pool->dmcu; 1178 1179 /* Init the boot time CRC (skip in resume) */ 1180 if ((adev->in_suspend == 0) && 1181 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 6, 0))) 1182 amdgpu_dm_boot_time_crc_init(adev); 1183 1184 for (i = 0; i < 16; i++) 1185 linear_lut[i] = 0xFFFF * i / 15; 1186 1187 params.set = 0; 1188 params.backlight_ramping_override = false; 1189 params.backlight_ramping_start = 0xCCCC; 1190 params.backlight_ramping_reduction = 0xCCCCCCCC; 1191 params.backlight_lut_array_size = 16; 1192 params.backlight_lut_array = linear_lut; 1193 1194 /* Min backlight level after ABM reduction, Don't allow below 1% 1195 * 0xFFFF x 0.01 = 0x28F 1196 */ 1197 params.min_abm_backlight = 0x28F; 1198 /* In the case where abm is implemented on dmcub, 1199 * dmcu object will be null. 1200 * ABM 2.4 and up are implemented on dmcub. 1201 */ 1202 if (dmcu) { 1203 if (!dmcu_load_iram(dmcu, params)) 1204 return -EINVAL; 1205 } else if (adev->dm.dc->ctx->dmub_srv) { 1206 struct dc_link *edp_links[MAX_NUM_EDP]; 1207 int edp_num; 1208 1209 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); 1210 for (i = 0; i < edp_num; i++) { 1211 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) 1212 return -EINVAL; 1213 } 1214 } 1215 1216 return amdgpu_dm_detect_mst_link_for_all_connectors(adev_to_drm(adev)); 1217 } 1218 1219 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) 1220 { 1221 u8 buf[UUID_SIZE]; 1222 guid_t guid; 1223 int ret; 1224 1225 mutex_lock(&mgr->lock); 1226 if (!mgr->mst_primary) 1227 goto out_fail; 1228 1229 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { 1230 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 1231 goto out_fail; 1232 } 1233 1234 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 1235 DP_MST_EN | 1236 DP_UP_REQ_EN | 1237 DP_UPSTREAM_IS_SRC); 1238 if (ret < 0) { 1239 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n"); 1240 goto out_fail; 1241 } 1242 1243 /* Some hubs forget their guids after they resume */ 1244 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, buf, sizeof(buf)); 1245 if (ret != sizeof(buf)) { 1246 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 1247 goto out_fail; 1248 } 1249 1250 import_guid(&guid, buf); 1251 1252 if (guid_is_null(&guid)) { 1253 guid_gen(&guid); 1254 export_guid(buf, &guid); 1255 1256 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, buf, sizeof(buf)); 1257 1258 if (ret != sizeof(buf)) { 1259 drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n"); 1260 goto out_fail; 1261 } 1262 } 1263 1264 guid_copy(&mgr->mst_primary->guid, &guid); 1265 1266 out_fail: 1267 mutex_unlock(&mgr->lock); 1268 } 1269 1270 static void s3_handle_mst(struct drm_device *dev, bool suspend) 1271 { 1272 struct amdgpu_dm_connector *aconnector; 1273 struct drm_connector *connector; 1274 struct drm_connector_list_iter iter; 1275 struct drm_dp_mst_topology_mgr *mgr; 1276 1277 drm_connector_list_iter_begin(dev, &iter); 1278 drm_for_each_connector_iter(connector, &iter) { 1279 1280 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 1281 continue; 1282 1283 aconnector = to_amdgpu_dm_connector(connector); 1284 if (aconnector->dc_link->type != dc_connection_mst_branch || 1285 aconnector->mst_root) 1286 continue; 1287 1288 mgr = &aconnector->mst_mgr; 1289 1290 if (suspend) { 1291 drm_dp_mst_topology_mgr_suspend(mgr); 1292 } else { 1293 /* if extended timeout is supported in hardware, 1294 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer 1295 * CTS 4.2.1.1 regression introduced by CTS specs requirement update. 1296 */ 1297 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); 1298 if (!dp_is_lttpr_present(aconnector->dc_link)) 1299 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); 1300 1301 /* TODO: move resume_mst_branch_status() into drm mst resume again 1302 * once topology probing work is pulled out from mst resume into mst 1303 * resume 2nd step. mst resume 2nd step should be called after old 1304 * state getting restored (i.e. drm_atomic_helper_resume()). 1305 */ 1306 resume_mst_branch_status(mgr); 1307 } 1308 } 1309 drm_connector_list_iter_end(&iter); 1310 } 1311 1312 static int dm_oem_i2c_hw_init(struct amdgpu_device *adev) 1313 { 1314 struct amdgpu_display_manager *dm = &adev->dm; 1315 struct amdgpu_i2c_adapter *oem_i2c; 1316 struct ddc_service *oem_ddc_service; 1317 int r; 1318 1319 oem_ddc_service = dc_get_oem_i2c_device(adev->dm.dc); 1320 if (oem_ddc_service) { 1321 oem_i2c = amdgpu_dm_create_i2c(oem_ddc_service, true); 1322 if (!oem_i2c) { 1323 drm_info(adev_to_drm(adev), "Failed to create oem i2c adapter data\n"); 1324 return -ENOMEM; 1325 } 1326 1327 r = devm_i2c_add_adapter(adev->dev, &oem_i2c->base); 1328 if (r) { 1329 drm_info(adev_to_drm(adev), "Failed to register oem i2c\n"); 1330 kfree(oem_i2c); 1331 return r; 1332 } 1333 dm->oem_i2c = oem_i2c; 1334 } 1335 1336 return 0; 1337 } 1338 1339 /** 1340 * dm_hw_init() - Initialize DC device 1341 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1342 * 1343 * Initialize the &struct amdgpu_display_manager device. This involves calling 1344 * the initializers of each DM component, then populating the struct with them. 1345 * 1346 * Although the function implies hardware initialization, both hardware and 1347 * software are initialized here. Splitting them out to their relevant init 1348 * hooks is a future TODO item. 1349 * 1350 * Some notable things that are initialized here: 1351 * 1352 * - Display Core, both software and hardware 1353 * - DC modules that we need (freesync and color management) 1354 * - DRM software states 1355 * - Interrupt sources and handlers 1356 * - Vblank support 1357 * - Debug FS entries, if enabled 1358 */ 1359 static int dm_hw_init(struct amdgpu_ip_block *ip_block) 1360 { 1361 struct amdgpu_device *adev = ip_block->adev; 1362 int r; 1363 1364 adev->dm.i2c_devres_group = devres_open_group(adev->dev, NULL, GFP_KERNEL); 1365 if (!adev->dm.i2c_devres_group) 1366 return -ENOMEM; 1367 1368 /* Create DAL display manager */ 1369 r = amdgpu_dm_init(adev); 1370 if (r) 1371 goto err_release_i2c; 1372 amdgpu_dm_hpd_init(adev); 1373 1374 r = dm_oem_i2c_hw_init(adev); 1375 if (r) 1376 drm_info(adev_to_drm(adev), "Failed to add OEM i2c bus\n"); 1377 1378 devres_close_group(adev->dev, adev->dm.i2c_devres_group); 1379 return 0; 1380 1381 err_release_i2c: 1382 devres_release_group(adev->dev, adev->dm.i2c_devres_group); 1383 return r; 1384 } 1385 1386 /** 1387 * dm_hw_fini() - Teardown DC device 1388 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1389 * 1390 * Teardown components within &struct amdgpu_display_manager that require 1391 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 1392 * were loaded. Also flush IRQ workqueues and disable them. 1393 */ 1394 static int dm_hw_fini(struct amdgpu_ip_block *ip_block) 1395 { 1396 struct amdgpu_device *adev = ip_block->adev; 1397 1398 if (adev->dm.i2c_devres_group) 1399 devres_release_group(adev->dev, adev->dm.i2c_devres_group); 1400 1401 amdgpu_dm_hpd_fini(adev); 1402 1403 amdgpu_dm_fini(adev); 1404 return 0; 1405 } 1406 1407 1408 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, 1409 struct dc_state *state, bool enable) 1410 { 1411 enum dc_irq_source irq_source; 1412 struct amdgpu_crtc *acrtc; 1413 int rc = -EBUSY; 1414 int i = 0; 1415 1416 for (i = 0; i < state->stream_count; i++) { 1417 acrtc = amdgpu_dm_get_crtc_by_otg_inst( 1418 adev, state->stream_status[i].primary_otg_inst); 1419 1420 if (acrtc && state->stream_status[i].plane_count != 0 && 1421 amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { 1422 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; 1423 rc = amdgpu_dm_irq_set(adev, irq_source, enable) ? 0 : -EBUSY; 1424 if (rc) 1425 drm_warn(adev_to_drm(adev), "Failed to %s pflip interrupts\n", 1426 enable ? "enable" : "disable"); 1427 1428 if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) { 1429 if (enable) { 1430 if (amdgpu_dm_crtc_vrr_active( 1431 to_dm_crtc_state(acrtc->base.state))) 1432 rc = amdgpu_dm_crtc_set_vupdate_irq( 1433 &acrtc->base, true); 1434 } else 1435 rc = amdgpu_dm_crtc_set_vupdate_irq( 1436 &acrtc->base, false); 1437 1438 if (rc) 1439 drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n", 1440 enable ? "en" : "dis"); 1441 } 1442 1443 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 1444 /* During gpu-reset we disable and then enable vblank irq, so 1445 * don't use amdgpu_irq_get/put() to avoid refcount change. 1446 */ 1447 if (!amdgpu_dm_irq_set(adev, irq_source, enable)) 1448 drm_warn(adev_to_drm(adev), "Failed to %sable vblank interrupt\n", enable ? "en" : "dis"); 1449 1450 } else if (acrtc && state->stream_status[i].plane_count != 0) { 1451 /* DCN only needs to toggle VUPDATE_NO_LOCK */ 1452 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, enable); 1453 if (rc) 1454 drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n", 1455 enable ? "en" : "dis"); 1456 } 1457 } 1458 1459 } 1460 1461 DEFINE_FREE(state_release, struct dc_state *, if (_T) dc_state_release(_T)) 1462 1463 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) 1464 { 1465 struct dc_state *context __free(state_release) = NULL; 1466 int i; 1467 struct dc_stream_state *del_streams[MAX_PIPES]; 1468 int del_streams_count = 0; 1469 struct dc_commit_streams_params params = {}; 1470 1471 memset(del_streams, 0, sizeof(del_streams)); 1472 1473 context = dc_state_create_current_copy(dc); 1474 if (context == NULL) 1475 return DC_ERROR_UNEXPECTED; 1476 1477 /* First remove from context all streams */ 1478 for (i = 0; i < context->stream_count; i++) { 1479 struct dc_stream_state *stream = context->streams[i]; 1480 1481 del_streams[del_streams_count++] = stream; 1482 } 1483 1484 /* Remove all planes for removed streams and then remove the streams */ 1485 for (i = 0; i < del_streams_count; i++) { 1486 enum dc_status res; 1487 1488 if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) 1489 return DC_FAIL_DETACH_SURFACES; 1490 1491 res = dc_state_remove_stream(dc, context, del_streams[i]); 1492 if (res != DC_OK) 1493 return res; 1494 } 1495 1496 params.streams = context->streams; 1497 params.stream_count = context->stream_count; 1498 1499 return dc_commit_streams(dc, ¶ms); 1500 } 1501 1502 static int dm_cache_state(struct amdgpu_device *adev) 1503 { 1504 int r; 1505 1506 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 1507 if (IS_ERR(adev->dm.cached_state)) { 1508 r = PTR_ERR(adev->dm.cached_state); 1509 adev->dm.cached_state = NULL; 1510 } 1511 1512 return adev->dm.cached_state ? 0 : r; 1513 } 1514 1515 static void dm_destroy_cached_state(struct amdgpu_device *adev) 1516 { 1517 struct amdgpu_display_manager *dm = &adev->dm; 1518 struct drm_device *ddev = adev_to_drm(adev); 1519 struct dm_plane_state *dm_new_plane_state; 1520 struct drm_plane_state *new_plane_state; 1521 struct dm_crtc_state *dm_new_crtc_state; 1522 struct drm_crtc_state *new_crtc_state; 1523 struct drm_plane *plane; 1524 struct drm_crtc *crtc; 1525 int i; 1526 1527 if (!dm->cached_state) 1528 return; 1529 1530 /* Force mode set in atomic commit */ 1531 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1532 new_crtc_state->active_changed = true; 1533 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1534 amdgpu_dm_reset_freesync_config_for_crtc(dm_new_crtc_state); 1535 } 1536 1537 /* 1538 * atomic_check is expected to create the dc states. We need to release 1539 * them here, since they were duplicated as part of the suspend 1540 * procedure. 1541 */ 1542 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1543 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1544 if (dm_new_crtc_state->stream) { 1545 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 1546 dc_stream_release(dm_new_crtc_state->stream); 1547 dm_new_crtc_state->stream = NULL; 1548 } 1549 dm_new_crtc_state->base.color_mgmt_changed = true; 1550 } 1551 1552 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 1553 dm_new_plane_state = to_dm_plane_state(new_plane_state); 1554 if (dm_new_plane_state->dc_state) { 1555 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 1556 dc_plane_state_release(dm_new_plane_state->dc_state); 1557 dm_new_plane_state->dc_state = NULL; 1558 } 1559 } 1560 1561 drm_atomic_helper_resume(ddev, dm->cached_state); 1562 1563 dm->cached_state = NULL; 1564 } 1565 1566 static int dm_suspend(struct amdgpu_ip_block *ip_block) 1567 { 1568 struct amdgpu_device *adev = ip_block->adev; 1569 struct amdgpu_display_manager *dm = &adev->dm; 1570 1571 if (amdgpu_in_reset(adev)) { 1572 enum dc_status res; 1573 1574 /* Quiesce ISM workers before taking dc_lock (workers take 1575 * dc_lock themselves; syncing under it would deadlock). 1576 */ 1577 amdgpu_dm_ism_disable(dm); 1578 1579 mutex_lock(&dm->dc_lock); 1580 1581 amdgpu_dm_ism_force_full_power(dm); 1582 dc_allow_idle_optimizations(adev->dm.dc, false); 1583 1584 dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state); 1585 if (!dm->cached_dc_state) { 1586 drm_err(adev_to_drm(adev), 1587 "Failed to allocate cached DC state during suspend\n"); 1588 mutex_unlock(&dm->dc_lock); 1589 return -ENOMEM; 1590 } 1591 1592 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); 1593 1594 res = amdgpu_dm_commit_zero_streams(dm->dc); 1595 if (res != DC_OK) { 1596 drm_err(adev_to_drm(adev), "Failed to commit zero streams: %d\n", res); 1597 dc_state_release(dm->cached_dc_state); 1598 dm->cached_dc_state = NULL; 1599 mutex_unlock(&dm->dc_lock); 1600 return -EINVAL; 1601 } 1602 1603 amdgpu_dm_irq_suspend(adev); 1604 1605 amdgpu_dm_hpd_rx_irq_work_suspend(dm); 1606 1607 return 0; 1608 } 1609 1610 if (!adev->dm.cached_state) { 1611 int r = dm_cache_state(adev); 1612 1613 if (r) 1614 return r; 1615 } 1616 1617 amdgpu_dm_s3_handle_hdmi_cec(adev_to_drm(adev), true); 1618 1619 s3_handle_mst(adev_to_drm(adev), true); 1620 1621 amdgpu_dm_irq_suspend(adev); 1622 1623 /* 1624 * Quiesce ISM workers before taking dc_lock (workers take dc_lock 1625 * themselves; syncing under it would deadlock). 1626 */ 1627 amdgpu_dm_ism_disable(dm); 1628 scoped_guard(mutex, &dm->dc_lock) 1629 amdgpu_dm_ism_force_full_power(dm); 1630 1631 amdgpu_dm_hpd_rx_irq_work_suspend(dm); 1632 1633 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 1634 1635 if (dm->dc->caps.ips_support && adev->in_s0ix) 1636 dc_allow_idle_optimizations(dm->dc, true); 1637 1638 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3); 1639 1640 return 0; 1641 } 1642 1643 void amdgpu_dm_emulated_link_detect(struct dc_link *link) 1644 { 1645 struct dc_sink_init_data sink_init_data = { 0 }; 1646 struct display_sink_capability sink_caps = { 0 }; 1647 enum dc_edid_status edid_status; 1648 struct dc_context *dc_ctx = link->ctx; 1649 struct drm_device *dev = adev_to_drm(dc_ctx->driver_context); 1650 struct dc_sink *sink = NULL; 1651 struct dc_sink *prev_sink = NULL; 1652 1653 link->type = dc_connection_none; 1654 prev_sink = link->local_sink; 1655 1656 if (prev_sink) 1657 dc_sink_release(prev_sink); 1658 1659 switch (link->connector_signal) { 1660 case SIGNAL_TYPE_HDMI_TYPE_A: { 1661 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1662 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 1663 break; 1664 } 1665 1666 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 1667 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1668 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1669 break; 1670 } 1671 1672 case SIGNAL_TYPE_DVI_DUAL_LINK: { 1673 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1674 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 1675 break; 1676 } 1677 1678 case SIGNAL_TYPE_LVDS: { 1679 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1680 sink_caps.signal = SIGNAL_TYPE_LVDS; 1681 break; 1682 } 1683 1684 case SIGNAL_TYPE_EDP: { 1685 sink_caps.transaction_type = 1686 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1687 sink_caps.signal = SIGNAL_TYPE_EDP; 1688 break; 1689 } 1690 1691 case SIGNAL_TYPE_DISPLAY_PORT: { 1692 sink_caps.transaction_type = 1693 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1694 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 1695 break; 1696 } 1697 1698 default: 1699 drm_err(dev, "Invalid connector type! signal:%d\n", 1700 link->connector_signal); 1701 return; 1702 } 1703 1704 sink_init_data.link = link; 1705 sink_init_data.sink_signal = sink_caps.signal; 1706 1707 sink = dc_sink_create(&sink_init_data); 1708 if (!sink) { 1709 drm_err(dev, "Failed to create sink!\n"); 1710 return; 1711 } 1712 1713 /* dc_sink_create returns a new reference */ 1714 link->local_sink = sink; 1715 1716 edid_status = dm_helpers_read_local_edid( 1717 link->ctx, 1718 link, 1719 sink); 1720 1721 if (edid_status != EDID_OK) 1722 drm_err(dev, "Failed to read EDID\n"); 1723 1724 } 1725 1726 static void dm_gpureset_commit_state(struct dc_state *dc_state, 1727 struct amdgpu_display_manager *dm) 1728 { 1729 struct { 1730 struct dc_surface_update surface_updates[MAX_SURFACES]; 1731 struct dc_plane_info plane_infos[MAX_SURFACES]; 1732 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 1733 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 1734 struct dc_stream_update stream_update; 1735 } *bundle __free(kfree); 1736 int k, m; 1737 1738 bundle = kzalloc_obj(*bundle); 1739 1740 if (!bundle) { 1741 drm_err(dm->ddev, "Failed to allocate update bundle\n"); 1742 return; 1743 } 1744 1745 for (k = 0; k < dc_state->stream_count; k++) { 1746 bundle->stream_update.stream = dc_state->streams[k]; 1747 1748 for (m = 0; m < dc_state->stream_status[k].plane_count; m++) { 1749 bundle->surface_updates[m].surface = 1750 dc_state->stream_status[k].plane_states[m]; 1751 bundle->surface_updates[m].surface->force_full_update = 1752 true; 1753 } 1754 1755 update_planes_and_stream_adapter(dm->dc, 1756 UPDATE_TYPE_FULL, 1757 dc_state->stream_status[k].plane_count, 1758 dc_state->streams[k], 1759 &bundle->stream_update, 1760 bundle->surface_updates); 1761 } 1762 } 1763 1764 void amdgpu_dm_apply_delay_after_dpcd_poweroff(struct amdgpu_device *adev, 1765 struct dc_sink *sink) 1766 { 1767 struct dc_panel_patch *ppatch = NULL; 1768 1769 if (!sink) 1770 return; 1771 1772 ppatch = &sink->edid_caps.panel_patch; 1773 if (ppatch->wait_after_dpcd_poweroff_ms) { 1774 msleep(ppatch->wait_after_dpcd_poweroff_ms); 1775 drm_dbg_driver(adev_to_drm(adev), 1776 "%s: adding a %ds delay as w/a for panel\n", 1777 __func__, 1778 ppatch->wait_after_dpcd_poweroff_ms / 1000); 1779 } 1780 } 1781 EXPORT_IF_KUNIT(amdgpu_dm_apply_delay_after_dpcd_poweroff); 1782 1783 /** 1784 * amdgpu_dm_dump_links_and_sinks - Debug dump of all DC links and their sinks 1785 * @adev: amdgpu device pointer 1786 * 1787 * Iterates through all DC links and dumps information about local and remote 1788 * (MST) sinks. Should be called after connector detection is complete to see 1789 * the final state of all links. 1790 */ 1791 static void amdgpu_dm_dump_links_and_sinks(struct amdgpu_device *adev) 1792 { 1793 struct dc *dc = adev->dm.dc; 1794 struct drm_device *dev = adev_to_drm(adev); 1795 int li; 1796 1797 if (!dc) 1798 return; 1799 1800 for (li = 0; li < dc->link_count; li++) { 1801 struct dc_link *l = dc->links[li]; 1802 const char *name = NULL; 1803 int rs; 1804 1805 if (!l) 1806 continue; 1807 if (l->local_sink && l->local_sink->edid_caps.display_name[0]) 1808 name = l->local_sink->edid_caps.display_name; 1809 else 1810 name = "n/a"; 1811 1812 drm_dbg_kms(dev, 1813 "LINK_DUMP[%d]: local_sink=%p type=%d sink_signal=%d sink_count=%u edid_name=%s mst_capable=%d mst_alloc_streams=%d\n", 1814 li, 1815 l->local_sink, 1816 l->type, 1817 l->local_sink ? l->local_sink->sink_signal : SIGNAL_TYPE_NONE, 1818 l->sink_count, 1819 name, 1820 l->dpcd_caps.is_mst_capable, 1821 l->mst_stream_alloc_table.stream_count); 1822 1823 /* Dump remote (MST) sinks if any */ 1824 for (rs = 0; rs < l->sink_count; rs++) { 1825 struct dc_sink *rsink = l->remote_sinks[rs]; 1826 const char *rname = NULL; 1827 1828 if (!rsink) 1829 continue; 1830 if (rsink->edid_caps.display_name[0]) 1831 rname = rsink->edid_caps.display_name; 1832 else 1833 rname = "n/a"; 1834 drm_dbg_kms(dev, 1835 " REMOTE_SINK[%d:%d]: sink=%p signal=%d edid_name=%s\n", 1836 li, rs, 1837 rsink, 1838 rsink->sink_signal, 1839 rname); 1840 } 1841 } 1842 } 1843 1844 static int dm_resume(struct amdgpu_ip_block *ip_block) 1845 { 1846 struct amdgpu_device *adev = ip_block->adev; 1847 struct drm_device *ddev = adev_to_drm(adev); 1848 struct amdgpu_display_manager *dm = &adev->dm; 1849 struct amdgpu_dm_connector *aconnector; 1850 struct drm_connector *connector; 1851 struct drm_connector_list_iter iter; 1852 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 1853 enum dc_connection_type new_connection_type = dc_connection_none; 1854 struct dc_state *dc_state; 1855 int i, r, j; 1856 struct dc_commit_streams_params commit_params = {}; 1857 1858 if (dm->dc->caps.ips_support) { 1859 if (!amdgpu_in_reset(adev)) 1860 mutex_lock(&dm->dc_lock); 1861 1862 /* Need to set POWER_STATE_D0 first or it will not execute 1863 * idle_power_optimizations command to DMUB. 1864 */ 1865 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 1866 dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false); 1867 1868 if (!amdgpu_in_reset(adev)) 1869 mutex_unlock(&dm->dc_lock); 1870 } 1871 1872 if (amdgpu_in_reset(adev)) { 1873 dc_state = dm->cached_dc_state; 1874 1875 /* 1876 * The dc->current_state is backed up into dm->cached_dc_state 1877 * before we commit 0 streams. 1878 * 1879 * DC will clear link encoder assignments on the real state 1880 * but the changes won't propagate over to the copy we made 1881 * before the 0 streams commit. 1882 * 1883 * DC expects that link encoder assignments are *not* valid 1884 * when committing a state, so as a workaround we can copy 1885 * off of the current state. 1886 * 1887 * We lose the previous assignments, but we had already 1888 * commit 0 streams anyway. 1889 */ 1890 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); 1891 1892 r = dm_dmub_hw_init(adev); 1893 if (r) { 1894 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r); 1895 dc_state_release(dm->cached_dc_state); 1896 dm->cached_dc_state = NULL; 1897 mutex_unlock(&dm->dc_lock); 1898 return r; 1899 } 1900 1901 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 1902 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 1903 1904 dc_resume(dm->dc); 1905 1906 amdgpu_dm_ism_enable(dm); 1907 amdgpu_dm_irq_resume_early(adev); 1908 1909 for (i = 0; i < dc_state->stream_count; i++) { 1910 dc_state->streams[i]->mode_changed = true; 1911 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { 1912 dc_pipe_update_bits_set_full(&dc_state->stream_status[i].plane_states[j]->update_bits); 1913 } 1914 } 1915 1916 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 1917 amdgpu_dm_outbox_init(adev); 1918 dc_enable_dmub_outbox(adev->dm.dc); 1919 } 1920 1921 commit_params.streams = dc_state->streams; 1922 commit_params.stream_count = dc_state->stream_count; 1923 dc_exit_ips_for_hw_access(dm->dc); 1924 WARN_ON(!dc_commit_streams(dm->dc, &commit_params)); 1925 1926 dm_gpureset_commit_state(dm->cached_dc_state, dm); 1927 1928 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); 1929 1930 dc_state_release(dm->cached_dc_state); 1931 dm->cached_dc_state = NULL; 1932 1933 amdgpu_dm_irq_resume_late(adev); 1934 1935 mutex_unlock(&dm->dc_lock); 1936 1937 /* set the backlight after a reset */ 1938 for (i = 0; i < dm->num_of_edps; i++) { 1939 if (dm->backlight_dev[i]) 1940 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 1941 } 1942 1943 return 0; 1944 } 1945 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 1946 dc_state_release(dm_state->context); 1947 dm_state->context = dc_state_create(dm->dc, NULL); 1948 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 1949 1950 /* Before powering on DC we need to re-initialize DMUB. */ 1951 dm_dmub_hw_resume(adev); 1952 1953 /* Re-enable outbox interrupts for DPIA. */ 1954 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 1955 amdgpu_dm_outbox_init(adev); 1956 dc_enable_dmub_outbox(adev->dm.dc); 1957 } 1958 1959 /* power on hardware */ 1960 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 1961 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 1962 1963 /* program HPD filter */ 1964 dc_resume(dm->dc); 1965 1966 scoped_guard(mutex, &dm->dc_lock) 1967 amdgpu_dm_ism_enable(dm); 1968 1969 /* 1970 * early enable HPD Rx IRQ, should be done before set mode as short 1971 * pulse interrupts are used for MST 1972 */ 1973 amdgpu_dm_irq_resume_early(adev); 1974 1975 amdgpu_dm_s3_handle_hdmi_cec(ddev, false); 1976 1977 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 1978 s3_handle_mst(ddev, false); 1979 1980 /* Exit IPS before the detection loop's first AUX/DDC access. */ 1981 scoped_guard(mutex, &dm->dc_lock) 1982 dc_exit_ips_for_hw_access(dm->dc); 1983 1984 /* Do detection*/ 1985 drm_connector_list_iter_begin(ddev, &iter); 1986 drm_for_each_connector_iter(connector, &iter) { 1987 bool ret; 1988 1989 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 1990 continue; 1991 1992 aconnector = to_amdgpu_dm_connector(connector); 1993 1994 if (!aconnector->dc_link) 1995 continue; 1996 1997 /* 1998 * this is the case when traversing through already created end sink 1999 * MST connectors, should be skipped 2000 */ 2001 if (aconnector->mst_root) 2002 continue; 2003 2004 /* Skip eDP detection, when there is no sink present */ 2005 if (aconnector->dc_link->connector_signal == SIGNAL_TYPE_EDP && 2006 !aconnector->dc_link->edp_sink_present) 2007 continue; 2008 2009 guard(mutex)(&aconnector->hpd_lock); 2010 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 2011 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 2012 2013 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2014 amdgpu_dm_emulated_link_detect(aconnector->dc_link); 2015 } else { 2016 guard(mutex)(&dm->dc_lock); 2017 dc_exit_ips_for_hw_access(dm->dc); 2018 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_RESUMEFROMS3S4); 2019 if (ret) { 2020 /* w/a delay for certain panels */ 2021 amdgpu_dm_apply_delay_after_dpcd_poweroff(adev, aconnector->dc_sink); 2022 } 2023 } 2024 2025 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 2026 aconnector->fake_enable = false; 2027 2028 if (aconnector->dc_sink) 2029 dc_sink_release(aconnector->dc_sink); 2030 aconnector->dc_sink = NULL; 2031 amdgpu_dm_update_connector_after_detect(aconnector); 2032 } 2033 drm_connector_list_iter_end(&iter); 2034 2035 dm_destroy_cached_state(adev); 2036 2037 /* Do mst topology probing after resuming cached state*/ 2038 drm_connector_list_iter_begin(ddev, &iter); 2039 drm_for_each_connector_iter(connector, &iter) { 2040 bool init = false; 2041 2042 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2043 continue; 2044 2045 aconnector = to_amdgpu_dm_connector(connector); 2046 if (aconnector->dc_link->type != dc_connection_mst_branch || 2047 aconnector->mst_root) 2048 continue; 2049 2050 scoped_guard(mutex, &aconnector->mst_mgr.lock) { 2051 init = !aconnector->mst_mgr.mst_primary; 2052 } 2053 if (init) 2054 dm_helpers_dp_mst_start_top_mgr(aconnector->dc_link->ctx, 2055 aconnector->dc_link, false); 2056 else 2057 drm_dp_mst_topology_queue_probe(&aconnector->mst_mgr); 2058 } 2059 drm_connector_list_iter_end(&iter); 2060 2061 /* Debug dump: list all DC links and their associated sinks after detection 2062 * is complete for all connectors. This provides a comprehensive view of the 2063 * final state without repeating the dump for each connector. 2064 */ 2065 amdgpu_dm_dump_links_and_sinks(adev); 2066 2067 amdgpu_dm_irq_resume_late(adev); 2068 2069 amdgpu_dm_smu_write_watermarks_table(adev); 2070 2071 drm_kms_helper_hotplug_event(ddev); 2072 2073 return 0; 2074 } 2075 2076 /** 2077 * DOC: DM Lifecycle 2078 * 2079 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 2080 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 2081 * the base driver's device list to be initialized and torn down accordingly. 2082 * 2083 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 2084 */ 2085 2086 static const struct amd_ip_funcs amdgpu_dm_funcs = { 2087 .name = "dm", 2088 .early_init = dm_early_init, 2089 .late_init = dm_late_init, 2090 .sw_init = dm_sw_init, 2091 .sw_fini = dm_sw_fini, 2092 .early_fini = amdgpu_dm_early_fini, 2093 .hw_init = dm_hw_init, 2094 .hw_fini = dm_hw_fini, 2095 .suspend = dm_suspend, 2096 .resume = dm_resume, 2097 .is_idle = dm_is_idle, 2098 .wait_for_idle = dm_wait_for_idle, 2099 .soft_reset = dm_soft_reset, 2100 .set_clockgating_state = dm_set_clockgating_state, 2101 .set_powergating_state = dm_set_powergating_state, 2102 }; 2103 2104 const struct amdgpu_ip_block_version dm_ip_block = { 2105 .type = AMD_IP_BLOCK_TYPE_DCE, 2106 .major = 1, 2107 .minor = 0, 2108 .rev = 0, 2109 .funcs = &amdgpu_dm_funcs, 2110 }; 2111 2112 2113 /** 2114 * DOC: atomic 2115 * 2116 * *WIP* 2117 */ 2118 2119 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 2120 .fb_create = amdgpu_display_user_framebuffer_create, 2121 .get_format_info = amdgpu_dm_plane_get_format_info, 2122 .atomic_check = amdgpu_dm_atomic_check, 2123 .atomic_commit = drm_atomic_helper_commit, 2124 }; 2125 2126 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 2127 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, 2128 .atomic_commit_setup = amdgpu_dm_atomic_setup_commit, 2129 }; 2130 2131 /* 2132 * Acquires the lock for the atomic state object and returns 2133 * the new atomic state. 2134 * 2135 * This should only be called during atomic check. 2136 */ 2137 int dm_atomic_get_state(struct drm_atomic_commit *state, 2138 struct dm_atomic_state **dm_state) 2139 { 2140 struct drm_device *dev = state->dev; 2141 struct amdgpu_device *adev = drm_to_adev(dev); 2142 struct amdgpu_display_manager *dm = &adev->dm; 2143 struct drm_private_state *priv_state; 2144 2145 if (*dm_state) 2146 return 0; 2147 2148 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 2149 if (IS_ERR(priv_state)) 2150 return PTR_ERR(priv_state); 2151 2152 *dm_state = to_dm_atomic_state(priv_state); 2153 2154 return 0; 2155 } 2156 2157 STATIC_IFN_KUNIT struct dm_atomic_state * 2158 dm_atomic_get_new_state(struct drm_atomic_commit *state) 2159 { 2160 struct drm_device *dev = state->dev; 2161 struct amdgpu_device *adev = drm_to_adev(dev); 2162 struct amdgpu_display_manager *dm = &adev->dm; 2163 struct drm_private_obj *obj; 2164 struct drm_private_state *new_obj_state; 2165 int i; 2166 2167 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 2168 if (obj->funcs == dm->atomic_obj.funcs) 2169 return to_dm_atomic_state(new_obj_state); 2170 } 2171 2172 return NULL; 2173 } 2174 EXPORT_IF_KUNIT(dm_atomic_get_new_state); 2175 2176 static struct drm_private_state * 2177 dm_atomic_duplicate_state(struct drm_private_obj *obj) 2178 { 2179 struct dm_atomic_state *old_state, *new_state; 2180 2181 new_state = kzalloc_obj(*new_state); 2182 if (!new_state) 2183 return NULL; 2184 2185 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 2186 2187 old_state = to_dm_atomic_state(obj->state); 2188 2189 if (old_state && old_state->context) 2190 new_state->context = dc_state_create_copy(old_state->context); 2191 2192 if (!new_state->context) { 2193 kfree(new_state); 2194 return NULL; 2195 } 2196 2197 return &new_state->base; 2198 } 2199 2200 STATIC_IFN_KUNIT void dm_atomic_destroy_state(struct drm_private_obj *obj, 2201 struct drm_private_state *state) 2202 { 2203 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 2204 2205 if (dm_state && dm_state->context) 2206 dc_state_release(dm_state->context); 2207 2208 kfree(dm_state); 2209 } 2210 EXPORT_IF_KUNIT(dm_atomic_destroy_state); 2211 2212 static struct drm_private_state * 2213 dm_atomic_create_state(struct drm_private_obj *obj) 2214 { 2215 struct amdgpu_device *adev = drm_to_adev(obj->dev); 2216 struct dm_atomic_state *dm_state; 2217 struct dc_state *context; 2218 2219 dm_state = kzalloc_obj(*dm_state); 2220 if (!dm_state) 2221 return ERR_PTR(-ENOMEM); 2222 2223 context = dc_state_create_current_copy(adev->dm.dc); 2224 if (!context) { 2225 kfree(dm_state); 2226 return ERR_PTR(-ENOMEM); 2227 } 2228 2229 __drm_atomic_helper_private_obj_create_state(obj, &dm_state->base); 2230 dm_state->context = context; 2231 2232 return &dm_state->base; 2233 } 2234 2235 static struct drm_private_state_funcs dm_atomic_state_funcs = { 2236 .atomic_create_state = dm_atomic_create_state, 2237 .atomic_duplicate_state = dm_atomic_duplicate_state, 2238 .atomic_destroy_state = dm_atomic_destroy_state, 2239 }; 2240 2241 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 2242 { 2243 int r; 2244 2245 adev->mode_info.mode_config_initialized = true; 2246 2247 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 2248 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 2249 2250 adev_to_drm(adev)->mode_config.max_width = 16384; 2251 adev_to_drm(adev)->mode_config.max_height = 16384; 2252 2253 adev_to_drm(adev)->mode_config.preferred_depth = 24; 2254 if (adev->asic_type == CHIP_HAWAII) 2255 /* disable prefer shadow for now due to hibernation issues */ 2256 adev_to_drm(adev)->mode_config.prefer_shadow = 0; 2257 else 2258 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 2259 /* indicates support for immediate flip */ 2260 adev_to_drm(adev)->mode_config.async_page_flip = true; 2261 2262 drm_atomic_private_obj_init(adev_to_drm(adev), 2263 &adev->dm.atomic_obj, 2264 &dm_atomic_state_funcs); 2265 2266 r = amdgpu_display_modeset_create_props(adev); 2267 if (r) 2268 return r; 2269 2270 #ifdef AMD_PRIVATE_COLOR 2271 if (amdgpu_dm_create_color_properties(adev)) 2272 return -ENOMEM; 2273 #endif 2274 2275 r = amdgpu_dm_audio_init(adev); 2276 if (r) 2277 return r; 2278 2279 return 0; 2280 } 2281 2282 static int initialize_plane(struct amdgpu_display_manager *dm, 2283 struct amdgpu_mode_info *mode_info, int plane_id, 2284 enum drm_plane_type plane_type, 2285 const struct dc_plane_cap *plane_cap) 2286 { 2287 struct drm_plane *plane; 2288 unsigned long possible_crtcs; 2289 int ret = 0; 2290 2291 plane = kzalloc_obj(struct drm_plane); 2292 if (!plane) { 2293 drm_err(adev_to_drm(dm->adev), "KMS: Failed to allocate plane\n"); 2294 return -ENOMEM; 2295 } 2296 plane->type = plane_type; 2297 2298 /* 2299 * HACK: IGT tests expect that the primary plane for a CRTC 2300 * can only have one possible CRTC. Only expose support for 2301 * any CRTC if they're not going to be used as a primary plane 2302 * for a CRTC - like overlay or underlay planes. 2303 */ 2304 possible_crtcs = 1 << plane_id; 2305 if (plane_id >= dm->dc->caps.max_streams) 2306 possible_crtcs = 0xff; 2307 2308 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 2309 2310 if (ret) { 2311 drm_err(adev_to_drm(dm->adev), "KMS: Failed to initialize plane\n"); 2312 kfree(plane); 2313 return ret; 2314 } 2315 2316 if (mode_info) 2317 mode_info->planes[plane_id] = plane; 2318 2319 return ret; 2320 } 2321 2322 2323 /* 2324 * In this architecture, the association 2325 * connector -> encoder -> crtc 2326 * id not really requried. The crtc and connector will hold the 2327 * display_index as an abstraction to use with DAL component 2328 * 2329 * Returns 0 on success 2330 */ 2331 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 2332 { 2333 struct amdgpu_display_manager *dm = &adev->dm; 2334 s32 i; 2335 struct amdgpu_dm_connector *aconnector = NULL; 2336 struct amdgpu_encoder *aencoder = NULL; 2337 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2338 u32 link_cnt; 2339 s32 primary_planes; 2340 enum dc_connection_type new_connection_type = dc_connection_none; 2341 const struct dc_plane_cap *plane; 2342 bool psr_feature_enabled = false; 2343 bool replay_feature_enabled = false; 2344 int max_overlay = dm->dc->caps.max_slave_planes; 2345 2346 dm->display_indexes_num = dm->dc->caps.max_streams; 2347 /* Update the actual used number of crtc */ 2348 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 2349 2350 amdgpu_dm_set_irq_funcs(adev); 2351 2352 link_cnt = dm->dc->caps.max_links; 2353 if (amdgpu_dm_mode_config_init(dm->adev)) { 2354 drm_err(adev_to_drm(adev), "DM: Failed to initialize mode config\n"); 2355 return -EINVAL; 2356 } 2357 2358 /* There is one primary plane per CRTC */ 2359 primary_planes = dm->dc->caps.max_streams; 2360 if (primary_planes > AMDGPU_MAX_PLANES) { 2361 drm_err(adev_to_drm(adev), "DM: Plane nums out of 6 planes\n"); 2362 return -EINVAL; 2363 } 2364 2365 /* 2366 * Initialize primary planes, implicit planes for legacy IOCTLS. 2367 * Order is reversed to match iteration order in atomic check. 2368 */ 2369 for (i = (primary_planes - 1); i >= 0; i--) { 2370 plane = &dm->dc->caps.planes[i]; 2371 2372 if (initialize_plane(dm, mode_info, i, 2373 DRM_PLANE_TYPE_PRIMARY, plane)) { 2374 drm_err(adev_to_drm(adev), "KMS: Failed to initialize primary plane\n"); 2375 goto fail; 2376 } 2377 } 2378 2379 /* 2380 * Initialize overlay planes, index starting after primary planes. 2381 * These planes have a higher DRM index than the primary planes since 2382 * they should be considered as having a higher z-order. 2383 * Order is reversed to match iteration order in atomic check. 2384 * 2385 * Only support DCN for now, and only expose one so we don't encourage 2386 * userspace to use up all the pipes. 2387 */ 2388 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 2389 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 2390 2391 /* Do not create overlay if MPO disabled */ 2392 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) 2393 break; 2394 2395 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 2396 continue; 2397 2398 if (!plane->pixel_format_support.argb8888) 2399 continue; 2400 2401 if (max_overlay-- == 0) 2402 break; 2403 2404 if (initialize_plane(dm, NULL, primary_planes + i, 2405 DRM_PLANE_TYPE_OVERLAY, plane)) { 2406 drm_err(adev_to_drm(adev), "KMS: Failed to initialize overlay plane\n"); 2407 goto fail; 2408 } 2409 } 2410 2411 for (i = 0; i < dm->dc->caps.max_streams; i++) 2412 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 2413 drm_err(adev_to_drm(adev), "KMS: Failed to initialize crtc\n"); 2414 goto fail; 2415 } 2416 2417 /* Use Outbox interrupt */ 2418 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2419 case IP_VERSION(3, 0, 0): 2420 case IP_VERSION(3, 1, 2): 2421 case IP_VERSION(3, 1, 3): 2422 case IP_VERSION(3, 1, 4): 2423 case IP_VERSION(3, 1, 5): 2424 case IP_VERSION(3, 1, 6): 2425 case IP_VERSION(3, 2, 0): 2426 case IP_VERSION(3, 2, 1): 2427 case IP_VERSION(2, 1, 0): 2428 case IP_VERSION(3, 5, 0): 2429 case IP_VERSION(3, 5, 1): 2430 case IP_VERSION(3, 6, 0): 2431 case IP_VERSION(4, 0, 1): 2432 case IP_VERSION(4, 2, 0): 2433 case IP_VERSION(4, 2, 1): 2434 case IP_VERSION(6, 0, 0): 2435 if (amdgpu_dm_register_outbox_irq_handlers(dm->adev)) { 2436 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2437 goto fail; 2438 } 2439 break; 2440 default: 2441 drm_dbg_kms(adev_to_drm(adev), "Unsupported DCN IP version for outbox: 0x%X\n", 2442 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2443 } 2444 2445 /* Determine whether to enable PSR support by default. */ 2446 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { 2447 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2448 case IP_VERSION(3, 1, 2): 2449 case IP_VERSION(3, 1, 3): 2450 case IP_VERSION(3, 1, 4): 2451 case IP_VERSION(3, 1, 5): 2452 case IP_VERSION(3, 1, 6): 2453 case IP_VERSION(3, 2, 0): 2454 case IP_VERSION(3, 2, 1): 2455 case IP_VERSION(3, 5, 0): 2456 case IP_VERSION(3, 5, 1): 2457 case IP_VERSION(3, 6, 0): 2458 case IP_VERSION(4, 0, 1): 2459 case IP_VERSION(4, 2, 0): 2460 case IP_VERSION(4, 2, 1): 2461 case IP_VERSION(6, 0, 0): 2462 psr_feature_enabled = true; 2463 break; 2464 default: 2465 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; 2466 break; 2467 } 2468 } 2469 2470 /* Determine whether to enable Replay support by default. */ 2471 if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { 2472 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2473 case IP_VERSION(3, 1, 4): 2474 case IP_VERSION(3, 2, 0): 2475 case IP_VERSION(3, 2, 1): 2476 case IP_VERSION(3, 5, 0): 2477 case IP_VERSION(3, 5, 1): 2478 case IP_VERSION(3, 6, 0): 2479 case IP_VERSION(4, 2, 0): 2480 case IP_VERSION(4, 2, 1): 2481 case IP_VERSION(6, 0, 0): 2482 replay_feature_enabled = true; 2483 break; 2484 2485 default: 2486 replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK; 2487 break; 2488 } 2489 } 2490 2491 if (link_cnt > MAX_LINKS) { 2492 drm_err(adev_to_drm(adev), 2493 "KMS: Cannot support more than %d display indexes\n", 2494 MAX_LINKS); 2495 goto fail; 2496 } 2497 2498 /* loops over all connectors on the board */ 2499 for (i = 0; i < link_cnt; i++) { 2500 struct dc_link *link = NULL; 2501 2502 link = dc_get_link_at_index(dm->dc, i); 2503 2504 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) { 2505 struct amdgpu_dm_wb_connector *wbcon = kzalloc_obj(*wbcon); 2506 2507 if (!wbcon) { 2508 drm_err(adev_to_drm(adev), "KMS: Failed to allocate writeback connector\n"); 2509 continue; 2510 } 2511 2512 if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) { 2513 drm_err(adev_to_drm(adev), "KMS: Failed to initialize writeback connector\n"); 2514 kfree(wbcon); 2515 continue; 2516 } 2517 2518 link->psr_settings.psr_feature_enabled = false; 2519 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; 2520 2521 continue; 2522 } 2523 2524 aconnector = kzalloc_obj(*aconnector); 2525 if (!aconnector) 2526 goto fail; 2527 2528 aencoder = kzalloc_obj(*aencoder); 2529 if (!aencoder) 2530 goto fail; 2531 2532 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 2533 drm_err(adev_to_drm(adev), "KMS: Failed to initialize encoder\n"); 2534 goto fail; 2535 } 2536 2537 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 2538 drm_err(adev_to_drm(adev), "KMS: Failed to initialize connector\n"); 2539 goto fail; 2540 } 2541 2542 if (dm->hpd_rx_offload_wq) 2543 dm->hpd_rx_offload_wq[aconnector->base.index].aconnector = 2544 aconnector; 2545 2546 if (!dc_link_detect_connection_type(link, &new_connection_type)) 2547 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 2548 2549 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2550 amdgpu_dm_emulated_link_detect(link); 2551 amdgpu_dm_update_connector_after_detect(aconnector); 2552 } else { 2553 bool ret = false; 2554 2555 mutex_lock(&dm->dc_lock); 2556 dc_exit_ips_for_hw_access(dm->dc); 2557 ret = dc_link_detect(link, DETECT_REASON_BOOT); 2558 mutex_unlock(&dm->dc_lock); 2559 2560 if (ret) { 2561 amdgpu_dm_update_connector_after_detect(aconnector); 2562 amdgpu_dm_setup_backlight_device(dm, aconnector); 2563 2564 /* Disable PSR if Replay can be enabled */ 2565 if (replay_feature_enabled) 2566 if (amdgpu_dm_set_replay_caps(link, aconnector)) 2567 psr_feature_enabled = false; 2568 2569 if (psr_feature_enabled) { 2570 amdgpu_dm_set_psr_caps(link, aconnector); 2571 drm_info(adev_to_drm(adev), "%s: PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n", 2572 aconnector->base.name, 2573 link->psr_settings.psr_feature_enabled, 2574 link->psr_settings.psr_version, 2575 link->dpcd_caps.psr_info.psr_version, 2576 link->dpcd_caps.psr_info.psr_dpcd_caps.raw, 2577 link->dpcd_caps.psr_info.psr2_su_y_granularity_cap); 2578 } 2579 } 2580 } 2581 amdgpu_set_panel_orientation(&aconnector->base); 2582 } 2583 2584 /* Debug dump: list all DC links and their associated sinks after detection 2585 * is complete for all connectors. This provides a comprehensive view of the 2586 * final state without repeating the dump for each connector. 2587 */ 2588 amdgpu_dm_dump_links_and_sinks(adev); 2589 2590 /* Software is initialized. Now we can register interrupt handlers. */ 2591 switch (adev->asic_type) { 2592 #if defined(CONFIG_DRM_AMD_DC_SI) 2593 case CHIP_TAHITI: 2594 case CHIP_PITCAIRN: 2595 case CHIP_VERDE: 2596 case CHIP_OLAND: 2597 #endif 2598 case CHIP_BONAIRE: 2599 case CHIP_HAWAII: 2600 case CHIP_KAVERI: 2601 case CHIP_KABINI: 2602 case CHIP_MULLINS: 2603 case CHIP_TONGA: 2604 case CHIP_FIJI: 2605 case CHIP_CARRIZO: 2606 case CHIP_STONEY: 2607 case CHIP_POLARIS11: 2608 case CHIP_POLARIS10: 2609 case CHIP_POLARIS12: 2610 case CHIP_VEGAM: 2611 case CHIP_VEGA10: 2612 case CHIP_VEGA12: 2613 case CHIP_VEGA20: 2614 if (amdgpu_dm_dce110_register_irq_handlers(dm->adev)) { 2615 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2616 goto fail; 2617 } 2618 break; 2619 default: 2620 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2621 case IP_VERSION(1, 0, 0): 2622 case IP_VERSION(1, 0, 1): 2623 case IP_VERSION(2, 0, 2): 2624 case IP_VERSION(2, 0, 3): 2625 case IP_VERSION(2, 0, 0): 2626 case IP_VERSION(2, 1, 0): 2627 case IP_VERSION(3, 0, 0): 2628 case IP_VERSION(3, 0, 2): 2629 case IP_VERSION(3, 0, 3): 2630 case IP_VERSION(3, 0, 1): 2631 case IP_VERSION(3, 1, 2): 2632 case IP_VERSION(3, 1, 3): 2633 case IP_VERSION(3, 1, 4): 2634 case IP_VERSION(3, 1, 5): 2635 case IP_VERSION(3, 1, 6): 2636 case IP_VERSION(3, 2, 0): 2637 case IP_VERSION(3, 2, 1): 2638 case IP_VERSION(3, 5, 0): 2639 case IP_VERSION(3, 5, 1): 2640 case IP_VERSION(3, 6, 0): 2641 case IP_VERSION(4, 0, 1): 2642 case IP_VERSION(4, 2, 0): 2643 case IP_VERSION(4, 2, 1): 2644 case IP_VERSION(6, 0, 0): 2645 if (amdgpu_dm_dcn10_register_irq_handlers(dm->adev)) { 2646 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2647 goto fail; 2648 } 2649 break; 2650 default: 2651 drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%X\n", 2652 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2653 goto fail; 2654 } 2655 break; 2656 } 2657 2658 return 0; 2659 fail: 2660 kfree(aencoder); 2661 kfree(aconnector); 2662 2663 return -EINVAL; 2664 } 2665 2666 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 2667 { 2668 if (dm->atomic_obj.state) 2669 drm_atomic_private_obj_fini(&dm->atomic_obj); 2670 } 2671 2672 /****************************************************************************** 2673 * amdgpu_display_funcs functions 2674 *****************************************************************************/ 2675 2676 /* 2677 * dm_bandwidth_update - program display watermarks 2678 * 2679 * @adev: amdgpu_device pointer 2680 * 2681 * Calculate and program the display watermarks and line buffer allocation. 2682 */ 2683 STATIC_IFN_KUNIT void dm_bandwidth_update(struct amdgpu_device *adev) 2684 { 2685 /* TODO: implement later */ 2686 } 2687 EXPORT_IF_KUNIT(dm_bandwidth_update); 2688 2689 static const struct amdgpu_display_funcs dm_display_funcs = { 2690 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 2691 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 2692 .backlight_set_level = NULL, /* never called for DC */ 2693 .backlight_get_level = NULL, /* never called for DC */ 2694 .hpd_sense = NULL,/* called unconditionally */ 2695 .hpd_set_polarity = NULL, /* called unconditionally */ 2696 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 2697 .page_flip_get_scanoutpos = 2698 dm_crtc_get_scanoutpos,/* called unconditionally */ 2699 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 2700 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 2701 }; 2702 2703 #if defined(CONFIG_DEBUG_KERNEL_DC) 2704 2705 static ssize_t s3_debug_store(struct device *device, 2706 struct device_attribute *attr, 2707 const char *buf, 2708 size_t count) 2709 { 2710 int ret; 2711 int s3_state; 2712 struct drm_device *drm_dev = dev_get_drvdata(device); 2713 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2714 struct amdgpu_ip_block *ip_block; 2715 2716 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_DCE); 2717 if (!ip_block) 2718 return -EINVAL; 2719 2720 ret = kstrtoint(buf, 0, &s3_state); 2721 2722 if (ret == 0) { 2723 if (s3_state) { 2724 dm_resume(ip_block); 2725 drm_kms_helper_hotplug_event(adev_to_drm(adev)); 2726 } else 2727 dm_suspend(ip_block); 2728 } 2729 2730 return ret == 0 ? count : 0; 2731 } 2732 2733 DEVICE_ATTR_WO(s3_debug); 2734 2735 #endif 2736 2737 static int dm_early_init(struct amdgpu_ip_block *ip_block) 2738 { 2739 struct amdgpu_device *adev = ip_block->adev; 2740 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2741 struct atom_context *ctx = mode_info->atom_context; 2742 int index = GetIndexIntoMasterTable(DATA, Object_Header); 2743 u16 data_offset; 2744 2745 /* if there is no object header, skip DM */ 2746 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 2747 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 2748 drm_info(adev_to_drm(adev), "No object header, skipping DM\n"); 2749 return -ENOENT; 2750 } 2751 2752 switch (adev->asic_type) { 2753 #if defined(CONFIG_DRM_AMD_DC_SI) 2754 case CHIP_TAHITI: 2755 case CHIP_PITCAIRN: 2756 case CHIP_VERDE: 2757 adev->mode_info.num_crtc = 6; 2758 adev->mode_info.num_hpd = 6; 2759 adev->mode_info.num_dig = 6; 2760 break; 2761 case CHIP_OLAND: 2762 adev->mode_info.num_crtc = 2; 2763 adev->mode_info.num_hpd = 2; 2764 adev->mode_info.num_dig = 2; 2765 break; 2766 #endif 2767 case CHIP_BONAIRE: 2768 case CHIP_HAWAII: 2769 adev->mode_info.num_crtc = 6; 2770 adev->mode_info.num_hpd = 6; 2771 adev->mode_info.num_dig = 6; 2772 break; 2773 case CHIP_KAVERI: 2774 adev->mode_info.num_crtc = 4; 2775 adev->mode_info.num_hpd = 6; 2776 adev->mode_info.num_dig = 7; 2777 break; 2778 case CHIP_KABINI: 2779 case CHIP_MULLINS: 2780 adev->mode_info.num_crtc = 2; 2781 adev->mode_info.num_hpd = 6; 2782 adev->mode_info.num_dig = 6; 2783 break; 2784 case CHIP_FIJI: 2785 case CHIP_TONGA: 2786 adev->mode_info.num_crtc = 6; 2787 adev->mode_info.num_hpd = 6; 2788 adev->mode_info.num_dig = 7; 2789 break; 2790 case CHIP_CARRIZO: 2791 adev->mode_info.num_crtc = 3; 2792 adev->mode_info.num_hpd = 6; 2793 adev->mode_info.num_dig = 9; 2794 break; 2795 case CHIP_STONEY: 2796 adev->mode_info.num_crtc = 2; 2797 adev->mode_info.num_hpd = 6; 2798 adev->mode_info.num_dig = 9; 2799 break; 2800 case CHIP_POLARIS11: 2801 case CHIP_POLARIS12: 2802 adev->mode_info.num_crtc = 5; 2803 adev->mode_info.num_hpd = 5; 2804 adev->mode_info.num_dig = 5; 2805 break; 2806 case CHIP_POLARIS10: 2807 case CHIP_VEGAM: 2808 adev->mode_info.num_crtc = 6; 2809 adev->mode_info.num_hpd = 6; 2810 adev->mode_info.num_dig = 6; 2811 break; 2812 case CHIP_VEGA10: 2813 case CHIP_VEGA12: 2814 case CHIP_VEGA20: 2815 adev->mode_info.num_crtc = 6; 2816 adev->mode_info.num_hpd = 6; 2817 adev->mode_info.num_dig = 6; 2818 break; 2819 default: 2820 2821 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2822 case IP_VERSION(2, 0, 2): 2823 case IP_VERSION(3, 0, 0): 2824 adev->mode_info.num_crtc = 6; 2825 adev->mode_info.num_hpd = 6; 2826 adev->mode_info.num_dig = 6; 2827 break; 2828 case IP_VERSION(2, 0, 0): 2829 case IP_VERSION(3, 0, 2): 2830 adev->mode_info.num_crtc = 5; 2831 adev->mode_info.num_hpd = 5; 2832 adev->mode_info.num_dig = 5; 2833 break; 2834 case IP_VERSION(2, 0, 3): 2835 case IP_VERSION(3, 0, 3): 2836 adev->mode_info.num_crtc = 2; 2837 adev->mode_info.num_hpd = 2; 2838 adev->mode_info.num_dig = 2; 2839 break; 2840 case IP_VERSION(1, 0, 0): 2841 case IP_VERSION(1, 0, 1): 2842 case IP_VERSION(3, 0, 1): 2843 case IP_VERSION(2, 1, 0): 2844 case IP_VERSION(3, 1, 2): 2845 case IP_VERSION(3, 1, 3): 2846 case IP_VERSION(3, 1, 4): 2847 case IP_VERSION(3, 1, 5): 2848 case IP_VERSION(3, 1, 6): 2849 case IP_VERSION(3, 2, 0): 2850 case IP_VERSION(3, 2, 1): 2851 case IP_VERSION(3, 5, 0): 2852 case IP_VERSION(3, 5, 1): 2853 case IP_VERSION(3, 6, 0): 2854 case IP_VERSION(4, 0, 1): 2855 case IP_VERSION(4, 2, 0): 2856 case IP_VERSION(4, 2, 1): 2857 case IP_VERSION(6, 0, 0): 2858 adev->mode_info.num_crtc = 4; 2859 adev->mode_info.num_hpd = 4; 2860 adev->mode_info.num_dig = 4; 2861 break; 2862 default: 2863 drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%x\n", 2864 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2865 return -EINVAL; 2866 } 2867 break; 2868 } 2869 2870 if (adev->mode_info.funcs == NULL) 2871 adev->mode_info.funcs = &dm_display_funcs; 2872 2873 /* 2874 * Note: Do NOT change adev->reg.audio_endpt.rreg and 2875 * adev->reg.audio_endpt.wreg because they are initialised in 2876 * amdgpu_device_init() 2877 */ 2878 #if defined(CONFIG_DEBUG_KERNEL_DC) 2879 device_create_file( 2880 adev_to_drm(adev)->dev, 2881 &dev_attr_s3_debug); 2882 #endif 2883 adev->dc_enabled = true; 2884 2885 return dm_init_microcode(adev); 2886 } 2887 2888 STATIC_IFN_KUNIT bool modereset_required(struct drm_crtc_state *crtc_state) 2889 { 2890 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 2891 } 2892 EXPORT_IF_KUNIT(modereset_required); 2893 2894 STATIC_IFN_KUNIT int 2895 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 2896 const enum surface_pixel_format format, 2897 enum dc_color_space *color_space) 2898 { 2899 bool full_range; 2900 2901 *color_space = COLOR_SPACE_SRGB; 2902 2903 /* Ignore properties when DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE is set */ 2904 if (plane_state->state && plane_state->state->plane_color_pipeline) 2905 return 0; 2906 2907 /* DRM color properties only affect non-RGB formats. */ 2908 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 2909 return 0; 2910 2911 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 2912 2913 switch (plane_state->color_encoding) { 2914 case DRM_COLOR_YCBCR_BT601: 2915 if (full_range) 2916 *color_space = COLOR_SPACE_YCBCR601; 2917 else 2918 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 2919 break; 2920 2921 case DRM_COLOR_YCBCR_BT709: 2922 if (full_range) 2923 *color_space = COLOR_SPACE_YCBCR709; 2924 else 2925 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 2926 break; 2927 2928 case DRM_COLOR_YCBCR_BT2020: 2929 if (full_range) 2930 *color_space = COLOR_SPACE_2020_YCBCR_FULL; 2931 else 2932 *color_space = COLOR_SPACE_2020_YCBCR_LIMITED; 2933 break; 2934 2935 default: 2936 return -EINVAL; 2937 } 2938 2939 return 0; 2940 } 2941 EXPORT_IF_KUNIT(fill_plane_color_attributes); 2942 2943 static int 2944 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 2945 const struct drm_plane_state *plane_state, 2946 struct dc_plane_info *plane_info, 2947 struct dc_plane_address *address, 2948 bool tmz_surface) 2949 { 2950 const struct drm_framebuffer *fb = plane_state->fb; 2951 const struct amdgpu_framebuffer *afb = 2952 to_amdgpu_framebuffer(plane_state->fb); 2953 int ret; 2954 2955 memset(plane_info, 0, sizeof(*plane_info)); 2956 2957 switch (fb->format->format) { 2958 case DRM_FORMAT_C8: 2959 plane_info->format = 2960 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 2961 break; 2962 case DRM_FORMAT_RGB565: 2963 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 2964 break; 2965 case DRM_FORMAT_XRGB8888: 2966 case DRM_FORMAT_ARGB8888: 2967 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 2968 break; 2969 case DRM_FORMAT_XRGB2101010: 2970 case DRM_FORMAT_ARGB2101010: 2971 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 2972 break; 2973 case DRM_FORMAT_XBGR2101010: 2974 case DRM_FORMAT_ABGR2101010: 2975 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 2976 break; 2977 case DRM_FORMAT_XBGR8888: 2978 case DRM_FORMAT_ABGR8888: 2979 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 2980 break; 2981 case DRM_FORMAT_NV21: 2982 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 2983 break; 2984 case DRM_FORMAT_NV12: 2985 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 2986 break; 2987 case DRM_FORMAT_P010: 2988 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; 2989 break; 2990 case DRM_FORMAT_XRGB16161616F: 2991 case DRM_FORMAT_ARGB16161616F: 2992 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; 2993 break; 2994 case DRM_FORMAT_XBGR16161616F: 2995 case DRM_FORMAT_ABGR16161616F: 2996 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; 2997 break; 2998 case DRM_FORMAT_XRGB16161616: 2999 case DRM_FORMAT_ARGB16161616: 3000 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; 3001 break; 3002 case DRM_FORMAT_XBGR16161616: 3003 case DRM_FORMAT_ABGR16161616: 3004 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; 3005 break; 3006 default: 3007 drm_err(adev_to_drm(adev), 3008 "Unsupported screen format %p4cc\n", 3009 &fb->format->format); 3010 return -EINVAL; 3011 } 3012 3013 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 3014 case DRM_MODE_ROTATE_0: 3015 plane_info->rotation = ROTATION_ANGLE_0; 3016 break; 3017 case DRM_MODE_ROTATE_90: 3018 plane_info->rotation = ROTATION_ANGLE_90; 3019 break; 3020 case DRM_MODE_ROTATE_180: 3021 plane_info->rotation = ROTATION_ANGLE_180; 3022 break; 3023 case DRM_MODE_ROTATE_270: 3024 plane_info->rotation = ROTATION_ANGLE_270; 3025 break; 3026 default: 3027 plane_info->rotation = ROTATION_ANGLE_0; 3028 break; 3029 } 3030 3031 3032 plane_info->visible = true; 3033 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 3034 3035 plane_info->layer_index = plane_state->normalized_zpos; 3036 3037 ret = fill_plane_color_attributes(plane_state, plane_info->format, 3038 &plane_info->color_space); 3039 if (ret) 3040 return ret; 3041 3042 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, 3043 plane_info->rotation, 3044 &plane_info->tiling_info, 3045 &plane_info->plane_size, 3046 &plane_info->dcc, address, 3047 tmz_surface); 3048 if (ret) 3049 return ret; 3050 3051 amdgpu_dm_plane_fill_blending_from_plane_state( 3052 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, 3053 &plane_info->global_alpha, &plane_info->global_alpha_value); 3054 3055 return 0; 3056 } 3057 3058 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 3059 struct dc_plane_state *dc_plane_state, 3060 struct drm_plane_state *plane_state, 3061 struct drm_crtc_state *crtc_state) 3062 { 3063 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 3064 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; 3065 struct dc_scaling_info scaling_info; 3066 struct dc_plane_info plane_info; 3067 int ret; 3068 3069 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); 3070 if (ret) 3071 return ret; 3072 3073 dc_plane_state->src_rect = scaling_info.src_rect; 3074 dc_plane_state->dst_rect = scaling_info.dst_rect; 3075 dc_plane_state->clip_rect = scaling_info.clip_rect; 3076 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 3077 3078 ret = fill_dc_plane_info_and_addr(adev, plane_state, 3079 &plane_info, 3080 &dc_plane_state->address, 3081 afb->tmz_surface); 3082 if (ret) 3083 return ret; 3084 3085 dc_plane_state->format = plane_info.format; 3086 dc_plane_state->color_space = plane_info.color_space; 3087 dc_plane_state->format = plane_info.format; 3088 dc_plane_state->plane_size = plane_info.plane_size; 3089 dc_plane_state->rotation = plane_info.rotation; 3090 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 3091 dc_plane_state->stereo_format = plane_info.stereo_format; 3092 dc_plane_state->tiling_info = plane_info.tiling_info; 3093 dc_plane_state->visible = plane_info.visible; 3094 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 3095 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; 3096 dc_plane_state->global_alpha = plane_info.global_alpha; 3097 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 3098 dc_plane_state->dcc = plane_info.dcc; 3099 dc_plane_state->layer_index = plane_info.layer_index; 3100 dc_plane_state->flip_int_enabled = true; 3101 3102 /* 3103 * Always set input transfer function, since plane state is refreshed 3104 * every time. 3105 */ 3106 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, 3107 plane_state, 3108 dc_plane_state); 3109 if (ret) 3110 return ret; 3111 3112 return 0; 3113 } 3114 3115 static inline void fill_dc_dirty_rect(struct drm_plane *plane, 3116 struct rect *dirty_rect, int32_t x, 3117 s32 y, s32 width, s32 height, 3118 int *i, bool ffu) 3119 { 3120 WARN_ON(*i >= DC_MAX_DIRTY_RECTS); 3121 3122 dirty_rect->x = x; 3123 dirty_rect->y = y; 3124 dirty_rect->width = width; 3125 dirty_rect->height = height; 3126 3127 if (ffu) 3128 drm_dbg(plane->dev, 3129 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", 3130 plane->base.id, width, height); 3131 else 3132 drm_dbg(plane->dev, 3133 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", 3134 plane->base.id, x, y, width, height); 3135 3136 (*i)++; 3137 } 3138 3139 /** 3140 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates 3141 * 3142 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP 3143 * remote fb 3144 * @old_plane_state: Old state of @plane 3145 * @new_plane_state: New state of @plane 3146 * @crtc_state: New state of CRTC connected to the @plane 3147 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects 3148 * @is_psr_su: Flag indicating whether Panel Self Refresh Selective Update (PSR SU) is enabled. 3149 * If PSR SU is enabled and damage clips are available, only the regions of the screen 3150 * that have changed will be updated. If PSR SU is not enabled, 3151 * or if damage clips are not available, the entire screen will be updated. 3152 * @dirty_regions_changed: dirty regions changed 3153 * 3154 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions 3155 * (referred to as "damage clips" in DRM nomenclature) that require updating on 3156 * the eDP remote buffer. The responsibility of specifying the dirty regions is 3157 * amdgpu_dm's. 3158 * 3159 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the 3160 * plane with regions that require flushing to the eDP remote buffer. In 3161 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - 3162 * implicitly provide damage clips without any client support via the plane 3163 * bounds. 3164 */ 3165 static void fill_dc_dirty_rects(struct drm_plane *plane, 3166 struct drm_plane_state *old_plane_state, 3167 struct drm_plane_state *new_plane_state, 3168 struct drm_crtc_state *crtc_state, 3169 struct dc_flip_addrs *flip_addrs, 3170 bool is_psr_su, 3171 bool *dirty_regions_changed) 3172 { 3173 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 3174 struct rect *dirty_rects = flip_addrs->dirty_rects; 3175 u32 num_clips = 0; 3176 struct drm_mode_rect *clips = NULL; 3177 bool bb_changed; 3178 bool fb_changed; 3179 u32 i = 0; 3180 *dirty_regions_changed = false; 3181 3182 /* 3183 * Cursor plane has it's own dirty rect update interface. See 3184 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data 3185 */ 3186 if (plane->type == DRM_PLANE_TYPE_CURSOR) 3187 return; 3188 3189 if (new_plane_state->rotation != DRM_MODE_ROTATE_0) 3190 goto ffu; 3191 3192 if (!new_plane_state->ignore_damage_clips) { 3193 num_clips = drm_plane_get_damage_clips_count(new_plane_state); 3194 clips = drm_plane_get_damage_clips(new_plane_state); 3195 } 3196 3197 if (num_clips && (!amdgpu_damage_clips || (amdgpu_damage_clips < 0 && 3198 is_psr_su))) 3199 goto ffu; 3200 3201 if (!dm_crtc_state->mpo_requested) { 3202 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) 3203 goto ffu; 3204 3205 for (; flip_addrs->dirty_rect_count < num_clips; clips++) 3206 fill_dc_dirty_rect(new_plane_state->plane, 3207 &dirty_rects[flip_addrs->dirty_rect_count], 3208 clips->x1, clips->y1, 3209 clips->x2 - clips->x1, clips->y2 - clips->y1, 3210 &flip_addrs->dirty_rect_count, 3211 false); 3212 return; 3213 } 3214 3215 /* 3216 * MPO is requested. Add entire plane bounding box to dirty rects if 3217 * flipped to or damaged. 3218 * 3219 * If plane is moved or resized, also add old bounding box to dirty 3220 * rects. 3221 */ 3222 fb_changed = old_plane_state->fb->base.id != 3223 new_plane_state->fb->base.id; 3224 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || 3225 old_plane_state->crtc_y != new_plane_state->crtc_y || 3226 old_plane_state->crtc_w != new_plane_state->crtc_w || 3227 old_plane_state->crtc_h != new_plane_state->crtc_h); 3228 3229 drm_dbg(plane->dev, 3230 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", 3231 new_plane_state->plane->base.id, 3232 bb_changed, fb_changed, num_clips); 3233 3234 *dirty_regions_changed = bb_changed; 3235 3236 if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS) 3237 goto ffu; 3238 3239 if (bb_changed) { 3240 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3241 new_plane_state->crtc_x, 3242 new_plane_state->crtc_y, 3243 new_plane_state->crtc_w, 3244 new_plane_state->crtc_h, &i, false); 3245 3246 /* Add old plane bounding-box if plane is moved or resized */ 3247 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3248 old_plane_state->crtc_x, 3249 old_plane_state->crtc_y, 3250 old_plane_state->crtc_w, 3251 old_plane_state->crtc_h, &i, false); 3252 } 3253 3254 if (num_clips) { 3255 for (; i < num_clips; clips++) 3256 fill_dc_dirty_rect(new_plane_state->plane, 3257 &dirty_rects[i], clips->x1, 3258 clips->y1, clips->x2 - clips->x1, 3259 clips->y2 - clips->y1, &i, false); 3260 } else if (fb_changed && !bb_changed) { 3261 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3262 new_plane_state->crtc_x, 3263 new_plane_state->crtc_y, 3264 new_plane_state->crtc_w, 3265 new_plane_state->crtc_h, &i, false); 3266 } 3267 3268 flip_addrs->dirty_rect_count = i; 3269 return; 3270 3271 ffu: 3272 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, 3273 dm_crtc_state->base.mode.crtc_hdisplay, 3274 dm_crtc_state->base.mode.crtc_vdisplay, 3275 &flip_addrs->dirty_rect_count, true); 3276 } 3277 3278 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_commit *state, 3279 struct dc_state *dc_state, 3280 struct dsc_mst_fairness_vars *vars) 3281 { 3282 struct dc_stream_state *stream = NULL; 3283 struct drm_connector *connector; 3284 struct drm_connector_state *new_con_state; 3285 struct amdgpu_dm_connector *aconnector; 3286 struct dm_connector_state *dm_conn_state; 3287 int i, j, ret; 3288 int vcpi, pbn_div, pbn = 0, slot_num = 0; 3289 3290 for_each_new_connector_in_state(state, connector, new_con_state, i) { 3291 3292 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3293 continue; 3294 3295 aconnector = to_amdgpu_dm_connector(connector); 3296 3297 if (!aconnector->mst_output_port) 3298 continue; 3299 3300 if (!new_con_state || !new_con_state->crtc) 3301 continue; 3302 3303 dm_conn_state = to_dm_connector_state(new_con_state); 3304 3305 for (j = 0; j < dc_state->stream_count; j++) { 3306 stream = dc_state->streams[j]; 3307 if (!stream) 3308 continue; 3309 3310 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) 3311 break; 3312 3313 stream = NULL; 3314 } 3315 3316 if (!stream) 3317 continue; 3318 3319 pbn_div = dm_mst_get_pbn_divider(stream->link); 3320 /* pbn is calculated by compute_mst_dsc_configs_for_state*/ 3321 for (j = 0; j < dc_state->stream_count; j++) { 3322 if (vars[j].aconnector == aconnector) { 3323 pbn = vars[j].pbn; 3324 break; 3325 } 3326 } 3327 3328 if (j == dc_state->stream_count || pbn_div == 0) 3329 continue; 3330 3331 slot_num = DIV_ROUND_UP(pbn, pbn_div); 3332 3333 if (stream->timing.flags.DSC != 1) { 3334 dm_conn_state->pbn = pbn; 3335 dm_conn_state->vcpi_slots = slot_num; 3336 3337 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, 3338 dm_conn_state->pbn, false); 3339 if (ret < 0) 3340 return ret; 3341 3342 continue; 3343 } 3344 3345 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); 3346 if (vcpi < 0) 3347 return vcpi; 3348 3349 dm_conn_state->pbn = pbn; 3350 dm_conn_state->vcpi_slots = vcpi; 3351 } 3352 return 0; 3353 } 3354 3355 static void manage_dm_interrupts(struct amdgpu_device *adev, 3356 struct amdgpu_crtc *acrtc, 3357 struct dm_crtc_state *acrtc_state) 3358 { /* 3359 * We cannot be sure that the frontend index maps to the same 3360 * backend index - some even map to more than one. 3361 * So we have to go through the CRTC to find the right IRQ. 3362 */ 3363 int irq_type = amdgpu_display_crtc_idx_to_irq_type( 3364 adev, 3365 acrtc->crtc_id); 3366 struct drm_device *dev = adev_to_drm(adev); 3367 3368 struct drm_vblank_crtc_config config = {0}; 3369 struct dc_crtc_timing *timing; 3370 int offdelay; 3371 3372 if (acrtc_state) { 3373 timing = &acrtc_state->stream->timing; 3374 3375 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < 3376 IP_VERSION(3, 5, 0) || 3377 !(adev->flags & AMD_IS_APU)) { 3378 /* 3379 * Older HW and DGPU have issues with instant off; 3380 * use a 2 frame offdelay. 3381 */ 3382 offdelay = DIV64_U64_ROUND_UP((u64)20 * 3383 timing->v_total * 3384 timing->h_total, 3385 timing->pix_clk_100hz); 3386 3387 config.offdelay_ms = offdelay ?: 30; 3388 } else { 3389 /* offdelay_ms = 0 will never disable vblank */ 3390 config.offdelay_ms = 1; 3391 config.disable_immediate = true; 3392 } 3393 3394 drm_crtc_vblank_on_config(&acrtc->base, 3395 &config); 3396 /* 3397 * Since pflip_high_irq is no longer registered for DCN, grab an 3398 * extra reference to vupdate irq instead to workaround this 3399 * issue: 3400 * https://gitlab.freedesktop.org/drm/amd/-/work_items/3936 3401 * 3402 * The callbacks to drm_vblank_on/off should really take care of 3403 * this though. 3404 */ 3405 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 3406 case IP_VERSION(3, 0, 0): 3407 case IP_VERSION(3, 0, 2): 3408 case IP_VERSION(3, 0, 3): 3409 case IP_VERSION(3, 2, 0): 3410 if (amdgpu_irq_get(adev, &adev->vupdate_irq, irq_type)) 3411 drm_err(dev, "DM_IRQ: Cannot get vupdate irq!\n"); 3412 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3413 if (amdgpu_irq_get(adev, &adev->vline0_irq, irq_type)) 3414 drm_err(dev, "DM_IRQ: Cannot get vline0 irq!\n"); 3415 #endif 3416 } 3417 3418 } else { 3419 /* Allow RX6xxx, RX7700, RX7800 GPUs to call amdgpu_irq_put.*/ 3420 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 3421 case IP_VERSION(3, 0, 0): 3422 case IP_VERSION(3, 0, 2): 3423 case IP_VERSION(3, 0, 3): 3424 case IP_VERSION(3, 2, 0): 3425 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3426 if (amdgpu_irq_put(adev, &adev->vline0_irq, irq_type)) 3427 drm_err(dev, "DM_IRQ: Cannot put vline0 irq!\n"); 3428 #endif 3429 if (amdgpu_irq_put(adev, &adev->vupdate_irq, irq_type)) 3430 drm_err(dev, "DM_IRQ: Cannot put vupdate irq!\n"); 3431 } 3432 3433 drm_crtc_vblank_off(&acrtc->base); 3434 } 3435 } 3436 3437 static void dm_update_pflip_irq_state(struct amdgpu_device *adev, 3438 struct amdgpu_crtc *acrtc) 3439 { 3440 int irq_type = 3441 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 3442 3443 /* GRPH_PFLIP is not used on DCN; nothing to reapply. */ 3444 if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) 3445 return; 3446 3447 /** 3448 * This reads the current state for the IRQ and force reapplies 3449 * the setting to hardware. 3450 */ 3451 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); 3452 } 3453 3454 STATIC_IFN_KUNIT bool 3455 is_scaling_state_different(const struct dm_connector_state *dm_state, 3456 const struct dm_connector_state *old_dm_state) 3457 { 3458 if (dm_state->scaling != old_dm_state->scaling) 3459 return true; 3460 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 3461 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 3462 return true; 3463 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 3464 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 3465 return true; 3466 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 3467 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 3468 return true; 3469 return false; 3470 } 3471 EXPORT_IF_KUNIT(is_scaling_state_different); 3472 3473 STATIC_IFN_KUNIT bool 3474 is_content_protection_different(struct drm_crtc_state *new_crtc_state, 3475 struct drm_crtc_state *old_crtc_state, 3476 struct drm_connector_state *new_conn_state, 3477 struct drm_connector_state *old_conn_state, 3478 const struct drm_connector *connector, 3479 struct hdcp_workqueue *hdcp_w) 3480 { 3481 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3482 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 3483 3484 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 3485 connector->index, connector->status, connector->dpms); 3486 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 3487 old_conn_state->content_protection, new_conn_state->content_protection); 3488 3489 if (old_crtc_state) 3490 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 3491 old_crtc_state->enable, 3492 old_crtc_state->active, 3493 old_crtc_state->mode_changed, 3494 old_crtc_state->active_changed, 3495 old_crtc_state->connectors_changed); 3496 3497 if (new_crtc_state) 3498 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 3499 new_crtc_state->enable, 3500 new_crtc_state->active, 3501 new_crtc_state->mode_changed, 3502 new_crtc_state->active_changed, 3503 new_crtc_state->connectors_changed); 3504 3505 /* hdcp content type change */ 3506 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && 3507 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 3508 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3509 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); 3510 return true; 3511 } 3512 3513 /* CP is being re enabled, ignore this */ 3514 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 3515 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3516 if (new_crtc_state && new_crtc_state->mode_changed) { 3517 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3518 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); 3519 return true; 3520 } 3521 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 3522 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); 3523 return false; 3524 } 3525 3526 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED 3527 * 3528 * Handles: UNDESIRED -> ENABLED 3529 */ 3530 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 3531 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 3532 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3533 3534 /* Stream removed and re-enabled 3535 * 3536 * Can sometimes overlap with the HPD case, 3537 * thus set update_hdcp to false to avoid 3538 * setting HDCP multiple times. 3539 * 3540 * Handles: DESIRED -> DESIRED (Special case) 3541 */ 3542 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && 3543 new_conn_state->crtc && new_conn_state->crtc->enabled && 3544 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3545 dm_con_state->update_hdcp = false; 3546 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", 3547 __func__); 3548 return true; 3549 } 3550 3551 /* Hot-plug, headless s3, dpms 3552 * 3553 * Only start HDCP if the display is connected/enabled. 3554 * update_hdcp flag will be set to false until the next 3555 * HPD comes in. 3556 * 3557 * Handles: DESIRED -> DESIRED (Special case) 3558 */ 3559 if (dm_con_state->update_hdcp && 3560 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && 3561 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { 3562 dm_con_state->update_hdcp = false; 3563 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", 3564 __func__); 3565 return true; 3566 } 3567 3568 if (old_conn_state->content_protection == new_conn_state->content_protection) { 3569 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3570 if (new_crtc_state && new_crtc_state->mode_changed) { 3571 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", 3572 __func__); 3573 return true; 3574 } 3575 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", 3576 __func__); 3577 return false; 3578 } 3579 3580 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); 3581 return false; 3582 } 3583 3584 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 3585 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", 3586 __func__); 3587 return true; 3588 } 3589 3590 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); 3591 return false; 3592 } 3593 EXPORT_IF_KUNIT(is_content_protection_different); 3594 3595 static void remove_stream(struct amdgpu_device *adev, 3596 struct amdgpu_crtc *acrtc, 3597 struct dc_stream_state *stream) 3598 { 3599 /* this is the update mode case */ 3600 3601 acrtc->otg_inst = -1; 3602 acrtc->enabled = false; 3603 } 3604 3605 static void amdgpu_dm_commit_cursors(struct drm_atomic_commit *state) 3606 { 3607 struct drm_plane *plane; 3608 struct drm_plane_state *old_plane_state; 3609 int i; 3610 3611 /* 3612 * TODO: Make this per-stream so we don't issue redundant updates for 3613 * commits with multiple streams. 3614 */ 3615 for_each_old_plane_in_state(state, plane, old_plane_state, i) 3616 if (plane->type == DRM_PLANE_TYPE_CURSOR) 3617 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); 3618 } 3619 3620 static inline uint32_t get_mem_type(struct drm_framebuffer *fb) 3621 { 3622 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); 3623 3624 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; 3625 } 3626 3627 static void amdgpu_dm_update_cursor(struct drm_plane *plane, 3628 struct drm_plane_state *old_plane_state, 3629 struct dc_stream_update *update) 3630 { 3631 struct amdgpu_device *adev = drm_to_adev(plane->dev); 3632 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 3633 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 3634 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 3635 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 3636 uint64_t address = afb ? afb->address : 0; 3637 struct dc_cursor_position position = {0}; 3638 struct dc_cursor_attributes attributes; 3639 int ret; 3640 3641 if (!plane->state->fb && !old_plane_state->fb) 3642 return; 3643 3644 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n", 3645 amdgpu_crtc->crtc_id, plane->state->crtc_w, 3646 plane->state->crtc_h); 3647 3648 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position); 3649 if (ret) 3650 return; 3651 3652 if (!position.enable) { 3653 /* turn off cursor */ 3654 if (crtc_state && crtc_state->stream) { 3655 dc_stream_set_cursor_position(crtc_state->stream, 3656 &position); 3657 update->cursor_position = &crtc_state->stream->cursor_position; 3658 } 3659 return; 3660 } 3661 3662 amdgpu_crtc->cursor_width = plane->state->crtc_w; 3663 amdgpu_crtc->cursor_height = plane->state->crtc_h; 3664 3665 memset(&attributes, 0, sizeof(attributes)); 3666 attributes.address.high_part = upper_32_bits(address); 3667 attributes.address.low_part = lower_32_bits(address); 3668 attributes.width = plane->state->crtc_w; 3669 attributes.height = plane->state->crtc_h; 3670 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 3671 attributes.rotation_angle = 0; 3672 attributes.attribute_flags.value = 0; 3673 3674 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM 3675 * legacy gamma setup. 3676 */ 3677 if (crtc_state->cm_is_degamma_srgb && 3678 adev->dm.dc->caps.color.dpp.gamma_corr) 3679 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; 3680 3681 if (afb) 3682 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 3683 3684 if (crtc_state->stream) { 3685 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 3686 &attributes)) 3687 drm_err(adev_to_drm(adev), "DC failed to set cursor attributes\n"); 3688 3689 update->cursor_attributes = &crtc_state->stream->cursor_attributes; 3690 3691 if (!dc_stream_set_cursor_position(crtc_state->stream, 3692 &position)) 3693 drm_err(adev_to_drm(adev), "DC failed to set cursor position\n"); 3694 3695 update->cursor_position = &crtc_state->stream->cursor_position; 3696 } 3697 } 3698 3699 static void amdgpu_dm_enable_self_refresh(struct amdgpu_display_manager *dm, 3700 struct amdgpu_crtc *acrtc_attach, 3701 const struct dm_crtc_state *acrtc_state, 3702 const u64 current_ts) 3703 { 3704 struct psr_settings *psr = &acrtc_state->stream->link->psr_settings; 3705 struct replay_settings *pr = &acrtc_state->stream->link->replay_settings; 3706 struct amdgpu_dm_connector *aconn = 3707 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 3708 3709 /* Decrement skip count when SR is enabled and we're doing fast updates. */ 3710 if (acrtc_state->update_type == UPDATE_TYPE_FAST && 3711 (psr->psr_feature_enabled || pr->replay_feature_enabled)) { 3712 if (aconn->sr_skip_count > 0) 3713 aconn->sr_skip_count--; 3714 3715 /* Allow SR when skip count is 0. */ 3716 acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count; 3717 3718 /* 3719 * If sink supports PSR SU/Panel Replay, there is no need to rely on 3720 * a vblank event disable request to enable PSR/RP. PSR SU/RP 3721 * can be enabled immediately once OS demonstrates an 3722 * adequate number of fast atomic commits to notify KMD 3723 * of update events. 3724 * See `amdgpu_dm_crtc_vblank_control_worker()`. 3725 */ 3726 if (acrtc_attach->dm_irq_params.allow_sr_entry && 3727 (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) { 3728 amdgpu_dm_psr_set_event(dm, acrtc_state->stream, false, 3729 psr_event_hw_programming, false); 3730 3731 amdgpu_dm_replay_set_event(dm, acrtc_state->stream, false, 3732 replay_event_hw_programming, false); 3733 } 3734 } else { 3735 acrtc_attach->dm_irq_params.allow_sr_entry = false; 3736 } 3737 } 3738 3739 static void dm_arm_vblank_event(struct amdgpu_crtc *acrtc, 3740 struct dm_crtc_state *acrtc_state, 3741 bool pflip_update, 3742 bool cursor_update) 3743 { 3744 assert_spin_locked(&acrtc->base.dev->event_lock); 3745 3746 if (!acrtc->base.state->event || acrtc_state->active_planes == 0) 3747 return; 3748 3749 if (pflip_update) { 3750 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE); 3751 WARN_ON(acrtc->event); 3752 3753 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 3754 acrtc->event = acrtc->base.state->event; 3755 acrtc->base.state->event = NULL; 3756 3757 drm_dbg_state(acrtc->base.dev, 3758 "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 3759 acrtc->crtc_id); 3760 } else if (cursor_update) { 3761 acrtc->event = acrtc->base.state->event; 3762 acrtc->base.state->event = NULL; 3763 } 3764 } 3765 3766 /** 3767 * dm_arm_vblank_event_pre_programming - Prepare for programming 3768 * @acrtc: The amdgpu CRTC to prepare 3769 * @acrtc_state: The new CRTC state 3770 * @pflip_update: Whether a page flip is being programmed 3771 * @cursor_update: Whether a cursor update is being programmed 3772 * 3773 * Grab a reference on the vblank counter if a page flip or cursor update is to 3774 * be programmed. Do this before programming so the HW is not in any 3775 * idle-optimized state (such as PSR). 3776 */ 3777 static void dm_arm_vblank_event_pre_programming(struct amdgpu_crtc *acrtc, 3778 struct dm_crtc_state *acrtc_state, 3779 bool pflip_update, 3780 bool cursor_update) 3781 { 3782 assert_spin_locked(&acrtc->base.dev->event_lock); 3783 3784 if (!acrtc->base.state->event || acrtc_state->active_planes == 0) 3785 return; 3786 3787 if (pflip_update || cursor_update) 3788 drm_crtc_vblank_get(&acrtc->base); 3789 } 3790 3791 static void amdgpu_dm_commit_planes(struct drm_atomic_commit *state, 3792 struct drm_device *dev, 3793 struct amdgpu_display_manager *dm, 3794 struct drm_crtc *pcrtc, 3795 bool wait_for_vblank) 3796 { 3797 u32 i; 3798 u64 timestamp_ns = ktime_get_ns(); 3799 struct drm_plane *plane; 3800 struct drm_plane_state *old_plane_state, *new_plane_state; 3801 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 3802 struct drm_crtc_state *new_pcrtc_state = 3803 drm_atomic_get_new_crtc_state(state, pcrtc); 3804 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 3805 struct dm_crtc_state *dm_old_crtc_state = 3806 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 3807 int planes_count = 0, vpos, hpos; 3808 unsigned long flags; 3809 u32 target_vblank, last_flip_vblank; 3810 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); 3811 bool cursor_update = false; 3812 bool pflip_present = false; 3813 bool immediate_flip = false; 3814 bool flip_latched_during_prog = false; 3815 bool dirty_rects_changed = false; 3816 bool updated_planes_and_streams = false; 3817 struct { 3818 struct dc_surface_update surface_updates[MAX_SURFACES]; 3819 struct dc_plane_info plane_infos[MAX_SURFACES]; 3820 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 3821 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 3822 struct dc_stream_update stream_update; 3823 } *bundle; 3824 3825 bundle = kzalloc_obj(*bundle); 3826 3827 if (!bundle) { 3828 drm_err(dev, "Failed to allocate update bundle\n"); 3829 goto cleanup; 3830 } 3831 3832 /* 3833 * Disable the cursor first if we're disabling all the planes. 3834 * It'll remain on the screen after the planes are re-enabled 3835 * if we don't. 3836 * 3837 * If the cursor is transitioning from native to overlay mode, the 3838 * native cursor needs to be disabled first. 3839 */ 3840 if (acrtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE && 3841 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 3842 struct dc_cursor_position cursor_position = {0}; 3843 3844 if (!dc_stream_set_cursor_position(acrtc_state->stream, 3845 &cursor_position)) 3846 drm_err(dev, "DC failed to disable native cursor\n"); 3847 3848 bundle->stream_update.cursor_position = 3849 &acrtc_state->stream->cursor_position; 3850 } 3851 3852 if (acrtc_state->active_planes == 0 && 3853 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 3854 amdgpu_dm_commit_cursors(state); 3855 3856 /* update planes when needed */ 3857 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 3858 struct drm_crtc *crtc = new_plane_state->crtc; 3859 struct drm_crtc_state *new_crtc_state; 3860 struct drm_framebuffer *fb = new_plane_state->fb; 3861 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; 3862 bool plane_needs_flip; 3863 struct dc_plane_state *dc_plane; 3864 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 3865 3866 /* Cursor plane is handled after stream updates */ 3867 if (plane->type == DRM_PLANE_TYPE_CURSOR && 3868 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 3869 if ((fb && crtc == pcrtc) || 3870 (old_plane_state->fb && old_plane_state->crtc == pcrtc)) { 3871 cursor_update = true; 3872 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0) 3873 amdgpu_dm_update_cursor(plane, old_plane_state, &bundle->stream_update); 3874 } 3875 3876 continue; 3877 } 3878 3879 if (!fb || !crtc || pcrtc != crtc) 3880 continue; 3881 3882 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 3883 if (!new_crtc_state->active) 3884 continue; 3885 3886 dc_plane = dm_new_plane_state->dc_state; 3887 if (!dc_plane) 3888 continue; 3889 3890 bundle->surface_updates[planes_count].surface = dc_plane; 3891 if (new_pcrtc_state->color_mgmt_changed || new_plane_state->color_mgmt_changed) { 3892 bundle->surface_updates[planes_count].gamma = &dc_plane->gamma_correction; 3893 bundle->surface_updates[planes_count].in_transfer_func = &dc_plane->in_transfer_func; 3894 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; 3895 bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult; 3896 bundle->surface_updates[planes_count].cm = &dc_plane->cm; 3897 } 3898 3899 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, 3900 &bundle->scaling_infos[planes_count]); 3901 3902 bundle->surface_updates[planes_count].scaling_info = 3903 &bundle->scaling_infos[planes_count]; 3904 3905 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 3906 3907 pflip_present = pflip_present || plane_needs_flip; 3908 3909 if (!plane_needs_flip) { 3910 planes_count += 1; 3911 continue; 3912 } 3913 3914 fill_dc_plane_info_and_addr( 3915 dm->adev, new_plane_state, 3916 &bundle->plane_infos[planes_count], 3917 &bundle->flip_addrs[planes_count].address, 3918 afb->tmz_surface); 3919 3920 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", 3921 new_plane_state->plane->index, 3922 bundle->plane_infos[planes_count].dcc.enable); 3923 3924 bundle->surface_updates[planes_count].plane_info = 3925 &bundle->plane_infos[planes_count]; 3926 3927 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled || 3928 acrtc_state->stream->link->replay_settings.replay_feature_enabled) { 3929 fill_dc_dirty_rects(plane, old_plane_state, 3930 new_plane_state, new_crtc_state, 3931 &bundle->flip_addrs[planes_count], 3932 acrtc_state->stream->link->psr_settings.psr_version == 3933 DC_PSR_VERSION_SU_1, 3934 &dirty_rects_changed); 3935 3936 /* 3937 * If the dirty regions changed, PSR-SU need to be disabled temporarily 3938 * and enabled it again after dirty regions are stable to avoid video glitch. 3939 * PSR-SU will be enabled in 3940 * amdgpu_dm_crtc_vblank_control_worker() if user 3941 * pause the video during the PSR-SU was disabled. 3942 */ 3943 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 3944 acrtc_attach->dm_irq_params.allow_sr_entry && 3945 dirty_rects_changed) { 3946 mutex_lock(&dm->dc_lock); 3947 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = 3948 timestamp_ns; 3949 dc_exit_ips_for_hw_access(dm->dc); 3950 amdgpu_dm_psr_set_event(dm, acrtc_state->stream, true, 3951 psr_event_hw_programming, true); 3952 mutex_unlock(&dm->dc_lock); 3953 } 3954 } 3955 3956 /* 3957 * Only allow immediate flips for fast updates that don't 3958 * change memory domain, FB pitch, DCC state, rotation or 3959 * mirroring. 3960 * 3961 * dm_crtc_helper_atomic_check() only accepts async flips with 3962 * fast updates. 3963 */ 3964 if (crtc->state->async_flip && 3965 (acrtc_state->update_type != UPDATE_TYPE_FAST || 3966 get_mem_type(old_plane_state->fb) != get_mem_type(fb))) 3967 drm_warn_once(state->dev, 3968 "[PLANE:%d:%s] async flip with non-fast update\n", 3969 plane->base.id, plane->name); 3970 3971 bundle->flip_addrs[planes_count].flip_immediate = 3972 crtc->state->async_flip && 3973 acrtc_state->update_type == UPDATE_TYPE_FAST && 3974 get_mem_type(old_plane_state->fb) == get_mem_type(fb); 3975 3976 immediate_flip |= bundle->flip_addrs[planes_count].flip_immediate; 3977 3978 timestamp_ns = ktime_get_ns(); 3979 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 3980 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 3981 bundle->surface_updates[planes_count].surface = dc_plane; 3982 3983 if (!bundle->surface_updates[planes_count].surface) { 3984 drm_err(dev, "No surface for CRTC: id=%d\n", 3985 acrtc_attach->crtc_id); 3986 continue; 3987 } 3988 3989 if (plane == pcrtc->primary) 3990 amdgpu_dm_update_freesync_state_on_stream( 3991 dm, 3992 acrtc_state, 3993 acrtc_state->stream, 3994 dc_plane, 3995 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 3996 3997 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", 3998 __func__, 3999 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 4000 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 4001 4002 planes_count += 1; 4003 4004 } 4005 4006 if (pflip_present) { 4007 if (!vrr_active) { 4008 /* Use old throttling in non-vrr fixed refresh rate mode 4009 * to keep flip scheduling based on target vblank counts 4010 * working in a backwards compatible way, e.g., for 4011 * clients using the GLX_OML_sync_control extension or 4012 * DRI3/Present extension with defined target_msc. 4013 */ 4014 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 4015 } else { 4016 /* For variable refresh rate mode only: 4017 * Get vblank of last completed flip to avoid > 1 vrr 4018 * flips per video frame by use of throttling, but allow 4019 * flip programming anywhere in the possibly large 4020 * variable vrr vblank interval for fine-grained flip 4021 * timing control and more opportunity to avoid stutter 4022 * on late submission of flips. 4023 */ 4024 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4025 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; 4026 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4027 } 4028 4029 target_vblank = last_flip_vblank + wait_for_vblank; 4030 4031 /* 4032 * Wait until we're out of the vertical blank period before the one 4033 * targeted by the flip 4034 */ 4035 while ((acrtc_attach->enabled && 4036 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 4037 0, &vpos, &hpos, NULL, 4038 NULL, &pcrtc->hwmode) 4039 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 4040 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 4041 (int)(target_vblank - 4042 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { 4043 usleep_range(1000, 1100); 4044 } 4045 4046 if (acrtc_state->stream) { 4047 if (acrtc_state->freesync_vrr_info_changed) 4048 bundle->stream_update.vrr_infopacket = 4049 &acrtc_state->stream->vrr_infopacket; 4050 } 4051 } 4052 4053 scoped_guard(spinlock_irqsave, &pcrtc->dev->event_lock) { 4054 dm_arm_vblank_event_pre_programming(acrtc_attach, acrtc_state, 4055 pflip_present, 4056 cursor_update); 4057 /* 4058 * DCE depends on a combination of GRPH_FLIP, VLINE0, and 4059 * VUPDATE for event delivery. Only GRPH_FLIP handler can send 4060 * pflip events, and it only fires if HW latched to the flip. 4061 * Maintain legacy behavior by arming event before programming. 4062 */ 4063 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) { 4064 dm_arm_vblank_event(acrtc_attach, acrtc_state, 4065 pflip_present, cursor_update); 4066 } 4067 } 4068 4069 /* Update the planes if changed or disable if we don't have any. */ 4070 if ((planes_count || acrtc_state->active_planes == 0) && 4071 acrtc_state->stream) { 4072 /* 4073 * If PSR or idle optimizations are enabled then flush out 4074 * any pending work before hardware programming. 4075 */ 4076 if (dm->vblank_control_workqueue) 4077 flush_workqueue(dm->vblank_control_workqueue); 4078 4079 bundle->stream_update.stream = acrtc_state->stream; 4080 if (new_pcrtc_state->mode_changed) { 4081 bundle->stream_update.src = acrtc_state->stream->src; 4082 bundle->stream_update.dst = acrtc_state->stream->dst; 4083 } 4084 4085 if (new_pcrtc_state->color_mgmt_changed) { 4086 /* 4087 * TODO: This isn't fully correct since we've actually 4088 * already modified the stream in place. 4089 */ 4090 bundle->stream_update.gamut_remap = 4091 &acrtc_state->stream->gamut_remap_matrix; 4092 bundle->stream_update.output_csc_transform = 4093 &acrtc_state->stream->csc_color_matrix; 4094 bundle->stream_update.out_transfer_func = 4095 &acrtc_state->stream->out_transfer_func; 4096 bundle->stream_update.lut3d_func = 4097 (struct dc_3dlut *) acrtc_state->stream->lut3d_func; 4098 bundle->stream_update.func_shaper = 4099 (struct dc_transfer_func *) acrtc_state->stream->func_shaper; 4100 } 4101 4102 acrtc_state->stream->abm_level = acrtc_state->abm_level; 4103 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 4104 bundle->stream_update.abm_level = &acrtc_state->abm_level; 4105 4106 /* 4107 * If FreeSync state on the stream has changed then we need to 4108 * re-adjust the min/max bounds now that DC doesn't handle this 4109 * as part of commit. 4110 */ 4111 if (amdgpu_dm_is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { 4112 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4113 dc_stream_adjust_vmin_vmax( 4114 dm->dc, acrtc_state->stream, 4115 &acrtc_attach->dm_irq_params.vrr_params.adjust); 4116 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4117 } 4118 mutex_lock(&dm->dc_lock); 4119 update_planes_and_stream_adapter(dm->dc, 4120 acrtc_state->update_type, 4121 planes_count, 4122 acrtc_state->stream, 4123 &bundle->stream_update, 4124 bundle->surface_updates); 4125 updated_planes_and_streams = true; 4126 4127 /** 4128 * Enable or disable the interrupts on the backend. 4129 * 4130 * Most pipes are put into power gating when unused. 4131 * 4132 * When power gating is enabled on a pipe we lose the 4133 * interrupt enablement state when power gating is disabled. 4134 * 4135 * So we need to update the IRQ control state in hardware 4136 * whenever the pipe turns on (since it could be previously 4137 * power gated) or off (since some pipes can't be power gated 4138 * on some ASICs). 4139 */ 4140 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) 4141 dm_update_pflip_irq_state(drm_to_adev(dev), 4142 acrtc_attach); 4143 amdgpu_dm_enable_self_refresh(dm, acrtc_attach, acrtc_state, 4144 timestamp_ns); 4145 mutex_unlock(&dm->dc_lock); 4146 } 4147 4148 /* 4149 * Update cursor state *after* programming all the planes. 4150 * This avoids redundant programming in the case where we're going 4151 * to be disabling a single plane - those pipes are being disabled. 4152 */ 4153 if (acrtc_state->active_planes && 4154 (!updated_planes_and_streams || amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) && 4155 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 4156 amdgpu_dm_commit_cursors(state); 4157 4158 /* 4159 * DCN specific vblank handling 4160 * ============================ 4161 * 4162 * With the event_lock held, arm the vblank event, and determine whether 4163 * deliver it immediately, or in VUPDATE_NO_LOCK IRQ (i.e. HW latch 4164 * point) handler. Do this *after* programming so that the IRQ handler 4165 * will not deliver the event before HW laches onto the programmed 4166 * values: 4167 * 4168 * Commit thread IRQ handler HW 4169 * ----------------------------------------------------------------- 4170 * arm_vblank_event() 4171 * vupdate() 4172 * vupdate_handler() 4173 * cook_timestamp() 4174 * # prev flip already latched, 4175 * # so flip_latched == true. 4176 * if event_armed && flip_latched: 4177 * send_vblank_event() 4178 * # sent before latch, **BAD!** 4179 * hw_program() 4180 * vupdate() 4181 * **latch** 4182 * 4183 * There's a consequence of arming after: it's possible for HW to latch 4184 * between start of HW programming and acrtc->event/pflip_status arming. 4185 * When this happens, the IRQ handler will send the event on the next 4186 * immediate latch point, even though HW has already latched. This is 4187 * handled by optimistically checking for HW latch after programming, 4188 * and if latched, send the event immediately: 4189 * 4190 * Commit thread IRQ handler HW 4191 * ----------------------------------------------------------------- 4192 * hw_program() 4193 * vupdate() 4194 * **latch** 4195 * vupdate_handler() 4196 * cook_timestamp() 4197 * # event_armed == false 4198 * # **no event sent!** 4199 * arm_vblank_event() 4200 * if flip_latched: 4201 * **send_vblank_event()** 4202 * disarm_vblank_event() 4203 * 4204 * The IRQ handler is expected to cook the timestamp, but we need to 4205 * cook the timestamp before optimistic sending as well. That's because 4206 * the following sequence is possible: 4207 * 4208 * Commit thread IRQ handler HW 4209 * ----------------------------------------------------------------- 4210 * hw_program() 4211 * arm_vblank_event() 4212 * vupdate() 4213 * **latch** 4214 * if flip_latched: 4215 * # Need cook before send! 4216 * **cook_timestamp()** 4217 * send_vblank_event() 4218 * disarm_vblank_event() 4219 * vupdate_handler() 4220 * cook_timestamp() 4221 * # event_armed == false 4222 * # no event sent! 4223 * 4224 * Cooking twice is OK, since DRM scanout accurate timestamps report A) 4225 * the previous vactive start if currently in vactive, or B) the next 4226 * vactive start if currently in vblank (see &get_vblank_counter). 'A)' 4227 * is what we want for the optimistic send, and for 'B)', we'll cook a 4228 * timestamp no later than the next IRQ handler run. 4229 * 4230 * The more correct fix is to wrap programming and arming with the 4231 * event_lock and thus serializing it with the IRQ handler. However, 4232 * there are various sleep-waits within 4233 * update_planes_and_stream_adapter() that makes spin locking illegal. 4234 * And on full updates, it can take 1-2 frame-times to return (see 4235 * commit_planes_for_stream). 4236 * 4237 * On DCE, GRPH_PFLIP IRQ is used and takes care of this. 4238 */ 4239 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0) { 4240 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4241 4242 if (updated_planes_and_streams) { 4243 flip_latched_during_prog = 4244 !dc_get_flip_pending_on_otg(dm->dc, acrtc_attach->otg_inst); 4245 } 4246 4247 dm_arm_vblank_event(acrtc_attach, acrtc_state, 4248 pflip_present, cursor_update); 4249 4250 /* 4251 * Deliver the event immediately on immediate flip, or on a 4252 * update that has already latched. 4253 */ 4254 if ((immediate_flip || flip_latched_during_prog) && 4255 acrtc_attach->pflip_status == AMDGPU_FLIP_SUBMITTED && 4256 acrtc_attach->event) { 4257 drm_crtc_accurate_vblank_count(&acrtc_attach->base); 4258 drm_crtc_send_vblank_event(&acrtc_attach->base, 4259 acrtc_attach->event); 4260 acrtc_attach->event = NULL; 4261 drm_crtc_vblank_put(&acrtc_attach->base); 4262 acrtc_attach->pflip_status = AMDGPU_FLIP_NONE; 4263 } 4264 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4265 } 4266 4267 cleanup: 4268 kfree(bundle); 4269 } 4270 4271 /* 4272 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 4273 * @crtc_state: the DRM CRTC state 4274 * @stream_state: the DC stream state. 4275 * 4276 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 4277 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 4278 */ 4279 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 4280 struct dc_stream_state *stream_state) 4281 { 4282 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 4283 } 4284 4285 /** 4286 * amdgpu_dm_crtc_complete_writeback - finish a pending writeback job 4287 * @acrtc: the CRTC whose pending writeback should be completed 4288 * 4289 * Clears the pending state, signals the writeback out fence and releases the 4290 * vblank reference taken in dm_set_writeback() while the writeback was armed. 4291 * The pending flag is tested and cleared under the writeback job lock, so this 4292 * is safe to call concurrently from the completion vblank IRQ 4293 * (dm_crtc_high_irq()) and from the writeback teardown path 4294 * (dm_clear_writeback()); only the caller that observes the pending job 4295 * performs the completion. 4296 * 4297 * Return: true if a pending writeback job was completed by this call. 4298 */ 4299 bool amdgpu_dm_crtc_complete_writeback(struct amdgpu_crtc *acrtc) 4300 { 4301 unsigned long flags; 4302 bool pending; 4303 4304 if (!acrtc->wb_conn) 4305 return false; 4306 4307 spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags); 4308 pending = acrtc->wb_pending; 4309 acrtc->wb_pending = false; 4310 acrtc->wb_frame_done = false; 4311 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); 4312 4313 if (!pending) 4314 return false; 4315 4316 drm_writeback_signal_completion(acrtc->wb_conn, 0); 4317 drm_crtc_vblank_put(&acrtc->base); 4318 4319 return true; 4320 } 4321 EXPORT_IF_KUNIT(amdgpu_dm_crtc_complete_writeback); 4322 4323 static void dm_clear_writeback(struct amdgpu_display_manager *dm, 4324 struct amdgpu_crtc *acrtc, 4325 struct dm_crtc_state *crtc_state) 4326 { 4327 dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0); 4328 4329 /* 4330 * If the writeback is still pending when it is torn down (its 4331 * completion vblank IRQ never fired), signal the out fence so a 4332 * waiting client does not stall and release the vblank reference 4333 * taken in dm_set_writeback(). 4334 */ 4335 amdgpu_dm_crtc_complete_writeback(acrtc); 4336 } 4337 4338 /** 4339 * amdgpu_dm_mod_power_update_streams - update mod_power stream state on modeset 4340 * @state: the drm atomic state 4341 * @dm: the display manager to update mod_power on 4342 * 4343 * Notify mod_power of stream changes on modeset events, and disable PSR/Replay 4344 * in preparation for hardware programming. See also 4345 * amdgpu_dm_mod_power_setup_streams() for post-modeset mod_power setup. 4346 */ 4347 static void amdgpu_dm_mod_power_update_streams(struct drm_atomic_commit *state, 4348 struct amdgpu_display_manager *dm) 4349 { 4350 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4351 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4352 struct amdgpu_dm_connector *aconnector; 4353 struct drm_crtc *crtc; 4354 int i = 0; 4355 4356 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4357 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4358 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4359 4360 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 4361 continue; 4362 4363 /* 4364 * Update mod_power on modeset event in preparation for hw 4365 * programming. Always use the old stream, since it would have 4366 * been previously added to mod_power. If old stream is null (on 4367 * crtc enable, for example), mod_power will no-op, which is the 4368 * desried behavior. 4369 */ 4370 if (old_crtc_state->active) { 4371 scoped_guard(mutex, &dm->dc_lock) { 4372 dc_exit_ips_for_hw_access(dm->dc); 4373 amdgpu_dm_psr_set_event(dm, dm_old_crtc_state->stream, true, 4374 psr_event_hw_programming, true); 4375 amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, true, 4376 replay_event_hw_programming, true); 4377 amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, false, 4378 replay_event_general_ui, false); 4379 } 4380 } 4381 4382 if (new_crtc_state->active) { 4383 aconnector = (struct amdgpu_dm_connector *) 4384 dm_new_crtc_state->stream->dm_stream_context; 4385 if (old_crtc_state->active) { 4386 mod_power_replace_stream(dm->power_module, 4387 dm_old_crtc_state->stream, 4388 dm_new_crtc_state->stream, 4389 &aconnector->psr_caps); 4390 } else { 4391 mod_power_add_stream(dm->power_module, 4392 dm_new_crtc_state->stream, 4393 &aconnector->psr_caps); 4394 } 4395 } else if (old_crtc_state->active) { 4396 mod_power_remove_stream(dm->power_module, 4397 dm_old_crtc_state->stream); 4398 } 4399 } 4400 } 4401 4402 /** 4403 * amdgpu_dm_mod_power_setup_streams - setup mod_power stream state post modeset 4404 * @state: the drm atomic state 4405 * @dm: the display manager to update mod_power on 4406 * 4407 * Notify mod_power of mode_change. This needs to be done after dc_stream 4408 * updates have been committed, and VRR parameters have been updated. 4409 */ 4410 static void amdgpu_dm_mod_power_setup_streams(struct drm_atomic_commit *state, 4411 struct amdgpu_display_manager *dm) 4412 { 4413 struct dm_crtc_state *dm_new_crtc_state; 4414 struct drm_crtc_state *new_crtc_state; 4415 struct amdgpu_crtc *acrtc; 4416 struct drm_crtc *crtc; 4417 int i = 0; 4418 4419 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 4420 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4421 acrtc = to_amdgpu_crtc(crtc); 4422 4423 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 4424 continue; 4425 4426 if (new_crtc_state->active) { 4427 amdgpu_dm_link_setup_replay(dm_new_crtc_state->stream, 4428 &acrtc->dm_irq_params.vrr_params); 4429 mod_power_notify_mode_change(dm->power_module, 4430 dm_new_crtc_state->stream, 4431 false); 4432 4433 /* 4434 * Block PSR / Replay on the new stream until display settles post-modeset. 4435 * These events will be cleared by amdgpu_dm_enable_self_refresh() once 4436 * allow_sr_entry becomes true. 4437 */ 4438 amdgpu_dm_psr_set_event(dm, dm_new_crtc_state->stream, true, 4439 psr_event_hw_programming, true); 4440 4441 amdgpu_dm_replay_set_event(dm, dm_new_crtc_state->stream, true, 4442 replay_event_hw_programming | replay_event_general_ui, 4443 true); 4444 } 4445 } 4446 4447 } 4448 4449 static void amdgpu_dm_commit_streams(struct drm_atomic_commit *state, 4450 struct dc_state *dc_state) 4451 { 4452 struct drm_device *dev = state->dev; 4453 struct amdgpu_device *adev = drm_to_adev(dev); 4454 struct amdgpu_display_manager *dm = &adev->dm; 4455 struct drm_crtc *crtc; 4456 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4457 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4458 struct drm_connector_state *old_con_state; 4459 struct drm_connector *connector; 4460 bool mode_set_reset_required = false; 4461 u32 i; 4462 struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count}; 4463 bool set_backlight_level = false; 4464 4465 /* Disable writeback */ 4466 for_each_old_connector_in_state(state, connector, old_con_state, i) { 4467 struct dm_connector_state *dm_old_con_state; 4468 struct amdgpu_crtc *acrtc; 4469 4470 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 4471 continue; 4472 4473 old_crtc_state = NULL; 4474 4475 dm_old_con_state = to_dm_connector_state(old_con_state); 4476 if (!dm_old_con_state->base.crtc) 4477 continue; 4478 4479 acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc); 4480 if (acrtc) 4481 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 4482 4483 if (!acrtc || !acrtc->wb_enabled) 4484 continue; 4485 4486 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4487 4488 dm_clear_writeback(dm, acrtc, dm_old_crtc_state); 4489 acrtc->wb_enabled = false; 4490 } 4491 4492 amdgpu_dm_mod_power_update_streams(state, dm); 4493 4494 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 4495 new_crtc_state, i) { 4496 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4497 4498 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4499 4500 if (old_crtc_state->active && 4501 (!new_crtc_state->active || 4502 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 4503 manage_dm_interrupts(adev, acrtc, NULL); 4504 dc_stream_release(dm_old_crtc_state->stream); 4505 } 4506 } 4507 4508 drm_atomic_helper_calc_timestamping_constants(state); 4509 4510 /* update changed items */ 4511 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4512 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4513 4514 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4515 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4516 4517 drm_dbg_state(state->dev, 4518 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 4519 acrtc->crtc_id, 4520 new_crtc_state->enable, 4521 new_crtc_state->active, 4522 new_crtc_state->planes_changed, 4523 new_crtc_state->mode_changed, 4524 new_crtc_state->active_changed, 4525 new_crtc_state->connectors_changed); 4526 4527 /* Disable cursor if disabling crtc */ 4528 if (old_crtc_state->active && !new_crtc_state->active) { 4529 struct dc_cursor_position position; 4530 4531 memset(&position, 0, sizeof(position)); 4532 mutex_lock(&dm->dc_lock); 4533 dc_exit_ips_for_hw_access(dm->dc); 4534 dc_stream_program_cursor_position(dm_old_crtc_state->stream, &position); 4535 mutex_unlock(&dm->dc_lock); 4536 } 4537 4538 /* Copy all transient state flags into dc state */ 4539 if (dm_new_crtc_state->stream) { 4540 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 4541 dm_new_crtc_state->stream); 4542 } 4543 4544 /* handles headless hotplug case, updating new_state and 4545 * aconnector as needed 4546 */ 4547 4548 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 4549 4550 drm_dbg_atomic(dev, 4551 "Atomic commit: SET crtc id %d: [%p]\n", 4552 acrtc->crtc_id, acrtc); 4553 4554 if (!dm_new_crtc_state->stream) { 4555 /* 4556 * this could happen because of issues with 4557 * userspace notifications delivery. 4558 * In this case userspace tries to set mode on 4559 * display which is disconnected in fact. 4560 * dc_sink is NULL in this case on aconnector. 4561 * We expect reset mode will come soon. 4562 * 4563 * This can also happen when unplug is done 4564 * during resume sequence ended 4565 * 4566 * In this case, we want to pretend we still 4567 * have a sink to keep the pipe running so that 4568 * hw state is consistent with the sw state 4569 */ 4570 drm_dbg_atomic(dev, 4571 "Failed to create new stream for crtc %d\n", 4572 acrtc->base.base.id); 4573 continue; 4574 } 4575 4576 if (dm_old_crtc_state->stream) 4577 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4578 4579 pm_runtime_get_noresume(dev->dev); 4580 4581 acrtc->enabled = true; 4582 acrtc->hw_mode = new_crtc_state->mode; 4583 crtc->hwmode = new_crtc_state->mode; 4584 mode_set_reset_required = true; 4585 set_backlight_level = true; 4586 } else if (modereset_required(new_crtc_state)) { 4587 drm_dbg_atomic(dev, 4588 "Atomic commit: RESET. crtc id %d:[%p]\n", 4589 acrtc->crtc_id, acrtc); 4590 /* i.e. reset mode */ 4591 if (dm_old_crtc_state->stream) 4592 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4593 4594 mode_set_reset_required = true; 4595 } 4596 } /* for_each_crtc_in_state() */ 4597 4598 /* if there mode set or reset, flush vblank work queue */ 4599 if (mode_set_reset_required) { 4600 if (dm->vblank_control_workqueue) 4601 flush_workqueue(dm->vblank_control_workqueue); 4602 } 4603 4604 dm_enable_per_frame_crtc_master_sync(dc_state); 4605 mutex_lock(&dm->dc_lock); 4606 dc_exit_ips_for_hw_access(dm->dc); 4607 WARN_ON(!dc_commit_streams(dm->dc, ¶ms)); 4608 4609 bool frl_stream_found = false; 4610 4611 for (i = 0; i < params.stream_count; i++) { 4612 struct dc_stream_state *stream = params.streams[i]; 4613 4614 if (stream->signal == SIGNAL_TYPE_HDMI_FRL) { 4615 frl_stream_found = true; 4616 break; 4617 } 4618 } 4619 if (frl_stream_found) { 4620 if (queue_delayed_work(dm->hdmi_frl_status_polling_wq, 4621 &dm->hdmi_frl_status_polling_work, 4622 msecs_to_jiffies(dm->hdmi_frl_status_polling_delay_ms))) 4623 drm_dbg_kms(dev, "200ms frl status polling starts ...\n"); 4624 } else { 4625 if (cancel_delayed_work_sync(&dm->hdmi_frl_status_polling_work)) 4626 drm_dbg_kms(dev, "200ms frl status polling stops ...\n"); 4627 } 4628 /* Allow idle optimization when vblank count is 0 for display off */ 4629 if ((dm->active_vblank_irq_count == 0) && amdgpu_dm_is_headless(dm->adev)) 4630 dc_allow_idle_optimizations(dm->dc, true); 4631 mutex_unlock(&dm->dc_lock); 4632 4633 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 4634 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4635 4636 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4637 4638 if (dm_new_crtc_state->stream != NULL) { 4639 const struct dc_stream_status *status = 4640 dc_stream_get_status(dm_new_crtc_state->stream); 4641 4642 if (!status) 4643 status = dc_state_get_stream_status(dc_state, 4644 dm_new_crtc_state->stream); 4645 if (!status) 4646 drm_err(dev, 4647 "got no status for stream %p on acrtc%p\n", 4648 dm_new_crtc_state->stream, acrtc); 4649 else 4650 acrtc->otg_inst = status->primary_otg_inst; 4651 } 4652 } 4653 4654 /* During boot up and resume the DC layer will reset the panel brightness 4655 * to fix a flicker issue. 4656 * It will cause the dm->actual_brightness is not the current panel brightness 4657 * level. (the dm->brightness is the correct panel level) 4658 * So we set the backlight level with dm->brightness value after set mode 4659 */ 4660 if (set_backlight_level) { 4661 for (i = 0; i < dm->num_of_edps; i++) { 4662 if (dm->backlight_dev[i]) 4663 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 4664 } 4665 } 4666 } 4667 4668 static void dm_set_writeback(struct amdgpu_display_manager *dm, 4669 struct dm_crtc_state *crtc_state, 4670 struct drm_connector *connector, 4671 struct drm_connector_state *new_con_state) 4672 { 4673 struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector); 4674 struct amdgpu_device *adev = dm->adev; 4675 struct amdgpu_crtc *acrtc; 4676 struct dc_writeback_info *wb_info; 4677 struct pipe_ctx *pipe = NULL; 4678 struct amdgpu_framebuffer *afb; 4679 int i = 0; 4680 4681 wb_info = kzalloc_obj(*wb_info); 4682 if (!wb_info) { 4683 drm_err(adev_to_drm(adev), "Failed to allocate wb_info\n"); 4684 goto cleanup; 4685 } 4686 4687 acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc); 4688 if (!acrtc) { 4689 drm_err(adev_to_drm(adev), "no amdgpu_crtc found\n"); 4690 goto cleanup; 4691 } 4692 4693 afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb); 4694 if (!afb) { 4695 drm_err(adev_to_drm(adev), "No amdgpu_framebuffer found\n"); 4696 goto cleanup; 4697 } 4698 4699 for (i = 0; i < MAX_PIPES; i++) { 4700 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) { 4701 pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i]; 4702 break; 4703 } 4704 } 4705 4706 if (!pipe) { 4707 drm_err(adev_to_drm(adev), "No pipe found for stream\n"); 4708 goto cleanup; 4709 } 4710 4711 /* fill in wb_info */ 4712 wb_info->wb_enabled = true; 4713 4714 wb_info->dwb_pipe_inst = 0; 4715 wb_info->dwb_params.dwbscl_black_color = 0; 4716 wb_info->dwb_params.hdr_mult = 0x1F000; 4717 wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS; 4718 wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13; 4719 wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC; 4720 wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC; 4721 4722 /* width & height from crtc */ 4723 wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay; 4724 wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay; 4725 wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay; 4726 wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay; 4727 4728 wb_info->dwb_params.cnv_params.crop_en = false; 4729 wb_info->dwb_params.stereo_params.stereo_enabled = false; 4730 4731 wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits 4732 wb_info->dwb_params.cnv_params.out_min_pix_val = 0; 4733 wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB; 4734 wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS; 4735 4736 wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444; 4737 4738 wb_info->dwb_params.capture_rate = dwb_capture_rate_0; 4739 4740 wb_info->dwb_params.scaler_taps.h_taps = 1; 4741 wb_info->dwb_params.scaler_taps.v_taps = 1; 4742 wb_info->dwb_params.scaler_taps.h_taps_c = 1; 4743 wb_info->dwb_params.scaler_taps.v_taps_c = 1; 4744 wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING; 4745 4746 wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0]; 4747 wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1]; 4748 4749 for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) { 4750 wb_info->mcif_buf_params.luma_address[i] = afb->address; 4751 wb_info->mcif_buf_params.chroma_address[i] = 0; 4752 } 4753 4754 wb_info->mcif_buf_params.p_vmid = 1; 4755 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) { 4756 wb_info->mcif_warmup_params.start_address.quad_part = afb->address; 4757 wb_info->mcif_warmup_params.region_size = 4758 wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height; 4759 } 4760 wb_info->mcif_warmup_params.p_vmid = 1; 4761 wb_info->writeback_source_plane = pipe->plane_state; 4762 4763 dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info); 4764 4765 acrtc->wb_conn = wb_conn; 4766 drm_writeback_queue_job(wb_conn, new_con_state); 4767 4768 /* 4769 * Writeback completion is detected in the CRTC vblank IRQ 4770 * (dm_crtc_high_irq()). Take a vblank reference so the vblank interrupt 4771 * stays enabled while the writeback is pending; otherwise a 4772 * writeback-only commit right after drm_crtc_vblank_on() (e.g. 4773 * re-enabling a CRTC that was disabled) has no other vblank reference, 4774 * the IRQ never fires and the out fence times out. The matching put 4775 * happens once completion is signalled in dm_crtc_high_irq(), or when 4776 * the writeback is torn down in dm_clear_writeback(). 4777 * 4778 * Arm wb_pending only after the reference is held so the completion IRQ 4779 * cannot run its matching vblank_put before this get. 4780 */ 4781 WARN_ON(drm_crtc_vblank_get(&acrtc->base)); 4782 acrtc->wb_frame_done = false; 4783 acrtc->wb_pending = true; 4784 4785 cleanup: 4786 kfree(wb_info); 4787 } 4788 4789 static void amdgpu_dm_update_hdcp(struct drm_atomic_commit *state) 4790 { 4791 struct drm_connector_state *old_con_state, *new_con_state; 4792 struct drm_device *dev = state->dev; 4793 struct drm_connector *connector; 4794 struct amdgpu_device *adev = drm_to_adev(dev); 4795 int i; 4796 4797 if (!adev->dm.hdcp_workqueue) 4798 return; 4799 4800 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 4801 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 4802 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 4803 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4804 struct dm_crtc_state *dm_new_crtc_state; 4805 struct amdgpu_dm_connector *aconnector; 4806 4807 if (!connector || connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 4808 continue; 4809 4810 aconnector = to_amdgpu_dm_connector(connector); 4811 4812 drm_dbg(dev, "[HDCP_DM] -------------- i : %x ----------\n", i); 4813 4814 drm_dbg(dev, "[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 4815 connector->index, connector->status, connector->dpms); 4816 drm_dbg(dev, "[HDCP_DM] state protection old: %x new: %x\n", 4817 old_con_state->content_protection, new_con_state->content_protection); 4818 4819 if (aconnector->dc_sink) { 4820 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 4821 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { 4822 drm_dbg(dev, "[HDCP_DM] pipe_ctx dispname=%s\n", 4823 aconnector->dc_sink->edid_caps.display_name); 4824 } 4825 } 4826 4827 new_crtc_state = NULL; 4828 old_crtc_state = NULL; 4829 4830 if (acrtc) { 4831 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 4832 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 4833 } 4834 4835 if (old_crtc_state) 4836 drm_dbg(dev, "old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 4837 old_crtc_state->enable, 4838 old_crtc_state->active, 4839 old_crtc_state->mode_changed, 4840 old_crtc_state->active_changed, 4841 old_crtc_state->connectors_changed); 4842 4843 if (new_crtc_state) 4844 drm_dbg(dev, "NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 4845 new_crtc_state->enable, 4846 new_crtc_state->active, 4847 new_crtc_state->mode_changed, 4848 new_crtc_state->active_changed, 4849 new_crtc_state->connectors_changed); 4850 4851 4852 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4853 4854 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 4855 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 4856 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 4857 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 4858 dm_new_con_state->update_hdcp = true; 4859 continue; 4860 } 4861 4862 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, 4863 old_con_state, connector, adev->dm.hdcp_workqueue)) { 4864 /* when display is unplugged from mst hub, connctor will 4865 * be destroyed within dm_dp_mst_connector_destroy. connector 4866 * hdcp perperties, like type, undesired, desired, enabled, 4867 * will be lost. So, save hdcp properties into hdcp_work within 4868 * amdgpu_dm_atomic_commit_tail. if the same display is 4869 * plugged back with same display index, its hdcp properties 4870 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 4871 */ 4872 4873 bool enable_encryption = false; 4874 4875 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) 4876 enable_encryption = true; 4877 4878 if (aconnector->dc_link && aconnector->dc_sink && 4879 aconnector->dc_link->type == dc_connection_mst_branch) { 4880 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 4881 struct hdcp_workqueue *hdcp_w = 4882 &hdcp_work[aconnector->dc_link->link_index]; 4883 4884 hdcp_w->hdcp_content_type[connector->index] = 4885 new_con_state->hdcp_content_type; 4886 hdcp_w->content_protection[connector->index] = 4887 new_con_state->content_protection; 4888 } 4889 4890 if (new_crtc_state && new_crtc_state->mode_changed && 4891 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) 4892 enable_encryption = true; 4893 4894 drm_info(dev, "[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); 4895 4896 if (aconnector->dc_link) 4897 hdcp_update_display( 4898 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 4899 new_con_state->hdcp_content_type, enable_encryption); 4900 } 4901 } 4902 } 4903 4904 static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_commit *state) 4905 { 4906 struct drm_crtc *crtc; 4907 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4908 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4909 int i, ret; 4910 4911 ret = drm_dp_mst_atomic_setup_commit(state); 4912 if (ret) 4913 return ret; 4914 4915 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4916 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4917 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4918 /* 4919 * Color management settings. We also update color properties 4920 * when a modeset is needed, to ensure it gets reprogrammed. 4921 */ 4922 if (dm_new_crtc_state->base.active && dm_new_crtc_state->stream && 4923 (dm_new_crtc_state->base.color_mgmt_changed || 4924 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 4925 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 4926 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 4927 if (ret) { 4928 drm_dbg_atomic(state->dev, "Failed to update color state\n"); 4929 return ret; 4930 } 4931 } 4932 } 4933 4934 return 0; 4935 } 4936 4937 STATIC_IFN_KUNIT void set_multisync_trigger_params( 4938 struct dc_stream_state *stream) 4939 { 4940 struct dc_stream_state *master = NULL; 4941 4942 if (stream->triggered_crtc_reset.enabled) { 4943 master = stream->triggered_crtc_reset.event_source; 4944 stream->triggered_crtc_reset.event = 4945 master->timing.flags.VSYNC_POSITIVE_POLARITY ? 4946 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; 4947 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; 4948 } 4949 } 4950 EXPORT_IF_KUNIT(set_multisync_trigger_params); 4951 4952 STATIC_IFN_KUNIT void set_master_stream(struct dc_stream_state *stream_set[], 4953 int stream_count) 4954 { 4955 int j, highest_rfr = 0, master_stream = 0; 4956 4957 for (j = 0; j < stream_count; j++) { 4958 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 4959 int refresh_rate = 0; 4960 4961 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 4962 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 4963 if (refresh_rate > highest_rfr) { 4964 highest_rfr = refresh_rate; 4965 master_stream = j; 4966 } 4967 } 4968 } 4969 for (j = 0; j < stream_count; j++) { 4970 if (stream_set[j]) 4971 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 4972 } 4973 } 4974 EXPORT_IF_KUNIT(set_master_stream); 4975 4976 STATIC_IFN_KUNIT void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 4977 { 4978 int i = 0; 4979 struct dc_stream_state *stream; 4980 4981 if (context->stream_count < 2) 4982 return; 4983 for (i = 0; i < context->stream_count ; i++) { 4984 if (!context->streams[i]) 4985 continue; 4986 /* 4987 * TODO: add a function to read AMD VSDB bits and set 4988 * crtc_sync_master.multi_sync_enabled flag 4989 * For now it's set to false 4990 */ 4991 } 4992 4993 set_master_stream(context->streams, context->stream_count); 4994 4995 for (i = 0; i < context->stream_count ; i++) { 4996 stream = context->streams[i]; 4997 4998 if (!stream) 4999 continue; 5000 5001 set_multisync_trigger_params(stream); 5002 } 5003 } 5004 EXPORT_IF_KUNIT(dm_enable_per_frame_crtc_master_sync); 5005 5006 /** 5007 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 5008 * @state: The atomic state to commit 5009 * 5010 * This will tell DC to commit the constructed DC state from atomic_check, 5011 * programming the hardware. Any failures here implies a hardware failure, since 5012 * atomic check should have filtered anything non-kosher. 5013 */ 5014 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_commit *state) 5015 { 5016 struct drm_device *dev = state->dev; 5017 struct amdgpu_device *adev = drm_to_adev(dev); 5018 struct amdgpu_display_manager *dm = &adev->dm; 5019 struct dm_atomic_state *dm_state; 5020 struct dc_state *dc_state = NULL; 5021 u32 i, j; 5022 struct drm_crtc *crtc; 5023 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5024 unsigned long flags; 5025 bool wait_for_vblank = true; 5026 struct drm_connector *connector; 5027 struct drm_connector_state *old_con_state = NULL, *new_con_state = NULL; 5028 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5029 int crtc_disable_count = 0; 5030 5031 trace_amdgpu_dm_atomic_commit_tail_begin(state); 5032 5033 drm_atomic_helper_update_legacy_modeset_state(dev, state); 5034 drm_dp_mst_atomic_wait_for_dependencies(state); 5035 5036 dm_state = dm_atomic_get_new_state(state); 5037 if (dm_state && dm_state->context) { 5038 dc_state = dm_state->context; 5039 amdgpu_dm_commit_streams(state, dc_state); 5040 } 5041 5042 amdgpu_dm_update_hdcp(state); 5043 5044 /* Handle connector state changes */ 5045 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 5046 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5047 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 5048 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5049 struct dc_surface_update *dummy_updates; 5050 struct dc_stream_update stream_update; 5051 struct dc_info_packet hdr_packet; 5052 struct dc_stream_status *status = NULL; 5053 bool abm_changed, hdr_changed, scaling_changed, output_color_space_changed = false; 5054 5055 memset(&stream_update, 0, sizeof(stream_update)); 5056 5057 if (acrtc) { 5058 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5059 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 5060 } 5061 5062 /* Skip any modesets/resets */ 5063 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 5064 continue; 5065 5066 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5067 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5068 5069 scaling_changed = is_scaling_state_different(dm_new_con_state, 5070 dm_old_con_state); 5071 5072 if ((new_con_state->hdmi.broadcast_rgb != old_con_state->hdmi.broadcast_rgb) && 5073 (dm_old_crtc_state->stream->output_color_space != 5074 amdgpu_dm_get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state))) 5075 output_color_space_changed = true; 5076 5077 abm_changed = dm_new_crtc_state->abm_level != 5078 dm_old_crtc_state->abm_level; 5079 5080 hdr_changed = 5081 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); 5082 5083 if (!scaling_changed && !abm_changed && !hdr_changed && !output_color_space_changed) 5084 continue; 5085 5086 stream_update.stream = dm_new_crtc_state->stream; 5087 if (scaling_changed) { 5088 amdgpu_dm_update_stream_scaling_settings(dev, &dm_new_con_state->base.crtc->mode, 5089 dm_new_con_state, dm_new_crtc_state->stream); 5090 5091 stream_update.src = dm_new_crtc_state->stream->src; 5092 stream_update.dst = dm_new_crtc_state->stream->dst; 5093 } 5094 5095 if (output_color_space_changed) { 5096 dm_new_crtc_state->stream->output_color_space 5097 = amdgpu_dm_get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state); 5098 5099 stream_update.output_color_space = &dm_new_crtc_state->stream->output_color_space; 5100 } 5101 5102 if (abm_changed) { 5103 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 5104 5105 stream_update.abm_level = &dm_new_crtc_state->abm_level; 5106 } 5107 5108 if (hdr_changed) { 5109 amdgpu_dm_fill_hdr_info_packet(new_con_state, &hdr_packet); 5110 stream_update.hdr_static_metadata = &hdr_packet; 5111 } 5112 5113 status = dc_stream_get_status(dm_new_crtc_state->stream); 5114 5115 if (WARN_ON(!status)) 5116 continue; 5117 5118 WARN_ON(!status->plane_count); 5119 5120 /* 5121 * TODO: DC refuses to perform stream updates without a dc_surface_update. 5122 * Here we create an empty update on each plane. 5123 * To fix this, DC should permit updating only stream properties. 5124 */ 5125 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_KERNEL); 5126 if (!dummy_updates) { 5127 drm_err(adev_to_drm(adev), "Failed to allocate memory for dummy_updates.\n"); 5128 continue; 5129 } 5130 for (j = 0; j < status->plane_count; j++) 5131 dummy_updates[j].surface = status->plane_states[j]; 5132 5133 sort(dummy_updates, status->plane_count, 5134 sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL); 5135 5136 mutex_lock(&dm->dc_lock); 5137 dc_exit_ips_for_hw_access(dm->dc); 5138 dc_update_planes_and_stream(dm->dc, 5139 dummy_updates, 5140 status->plane_count, 5141 dm_new_crtc_state->stream, 5142 &stream_update); 5143 mutex_unlock(&dm->dc_lock); 5144 kfree(dummy_updates); 5145 5146 drm_connector_update_privacy_screen(new_con_state); 5147 } 5148 5149 /** 5150 * Enable interrupts for CRTCs that are newly enabled or went through 5151 * a modeset. It was intentionally deferred until after the front end 5152 * state was modified to wait until the OTG was on and so the IRQ 5153 * handlers didn't access stale or invalid state. 5154 */ 5155 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5156 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5157 #ifdef CONFIG_DEBUG_FS 5158 enum amdgpu_dm_pipe_crc_source cur_crc_src; 5159 #endif 5160 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 5161 if (old_crtc_state->active && !new_crtc_state->active) 5162 crtc_disable_count++; 5163 5164 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5165 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5166 5167 /* For freesync config update on crtc state and params for irq */ 5168 amdgpu_dm_update_stream_irq_parameters(dm, dm_new_crtc_state); 5169 5170 #ifdef CONFIG_DEBUG_FS 5171 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5172 cur_crc_src = acrtc->dm_irq_params.crc_src; 5173 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5174 #endif 5175 5176 if (new_crtc_state->active && 5177 (!old_crtc_state->active || 5178 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5179 dc_stream_retain(dm_new_crtc_state->stream); 5180 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; 5181 manage_dm_interrupts(adev, acrtc, dm_new_crtc_state); 5182 } 5183 /* Handle vrr on->off / off->on transitions */ 5184 amdgpu_dm_handle_vrr_transition(dm, dm_old_crtc_state, dm_new_crtc_state); 5185 5186 #ifdef CONFIG_DEBUG_FS 5187 if (new_crtc_state->active && 5188 (!old_crtc_state->active || 5189 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5190 /** 5191 * Frontend may have changed so reapply the CRC capture 5192 * settings for the stream. 5193 */ 5194 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { 5195 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 5196 if (amdgpu_dm_crc_window_is_activated(crtc)) { 5197 uint8_t cnt; 5198 5199 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5200 for (cnt = 0; cnt < MAX_CRC_WINDOW_NUM; cnt++) { 5201 if (acrtc->dm_irq_params.window_param[cnt].enable) { 5202 acrtc->dm_irq_params.window_param[cnt].update_win = true; 5203 5204 /** 5205 * It takes 2 frames for HW to stably generate CRC when 5206 * resuming from suspend, so we set skip_frame_cnt 2. 5207 */ 5208 acrtc->dm_irq_params.window_param[cnt].skip_frame_cnt = 2; 5209 } 5210 } 5211 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5212 } 5213 #endif 5214 if (amdgpu_dm_crtc_configure_crc_source( 5215 crtc, dm_new_crtc_state, cur_crc_src)) 5216 drm_dbg_atomic(dev, "Failed to configure crc source"); 5217 } 5218 } 5219 #endif 5220 } 5221 5222 amdgpu_dm_mod_power_setup_streams(state, dm); 5223 5224 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 5225 if (new_crtc_state->async_flip) 5226 wait_for_vblank = false; 5227 5228 /* update planes when needed per crtc*/ 5229 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 5230 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5231 5232 if (dm_new_crtc_state->stream) 5233 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank); 5234 } 5235 5236 /* Enable writeback */ 5237 for_each_new_connector_in_state(state, connector, new_con_state, i) { 5238 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5239 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5240 5241 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 5242 continue; 5243 5244 if (!new_con_state->writeback_job) 5245 continue; 5246 5247 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5248 5249 if (!new_crtc_state) 5250 continue; 5251 5252 if (acrtc->wb_enabled) 5253 continue; 5254 5255 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5256 5257 dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state); 5258 acrtc->wb_enabled = true; 5259 } 5260 5261 /* Update audio instances for each connector. */ 5262 amdgpu_dm_commit_audio(dev, state); 5263 5264 /* restore the backlight level */ 5265 for (i = 0; i < dm->num_of_edps; i++) { 5266 if (dm->backlight_dev[i] && 5267 (dm->actual_brightness[i] != dm->brightness[i])) 5268 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 5269 } 5270 5271 /* 5272 * send vblank event on all events not handled in flip and 5273 * mark consumed event for drm_atomic_helper_commit_hw_done 5274 */ 5275 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5276 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 5277 5278 if (new_crtc_state->event) 5279 drm_send_event_locked(dev, &new_crtc_state->event->base); 5280 5281 new_crtc_state->event = NULL; 5282 } 5283 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5284 5285 /* Signal HW programming completion */ 5286 drm_atomic_helper_commit_hw_done(state); 5287 5288 if (wait_for_vblank) 5289 drm_atomic_helper_wait_for_flip_done(dev, state); 5290 5291 drm_atomic_helper_cleanup_planes(dev, state); 5292 5293 /* Don't free the memory if we are hitting this as part of suspend. 5294 * This way we don't free any memory during suspend; see 5295 * amdgpu_bo_free_kernel(). The memory will be freed in the first 5296 * non-suspend modeset or when the driver is torn down. 5297 */ 5298 if (!adev->in_suspend) { 5299 /* return the stolen vga memory back to VRAM */ 5300 if (!adev->mman.keep_stolen_vga_memory) 5301 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_VGA); 5302 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_EXTENDED); 5303 } 5304 5305 /* 5306 * Finally, drop a runtime PM reference for each newly disabled CRTC, 5307 * so we can put the GPU into runtime suspend if we're not driving any 5308 * displays anymore 5309 */ 5310 for (i = 0; i < crtc_disable_count; i++) 5311 pm_runtime_put_autosuspend(dev->dev); 5312 pm_runtime_mark_last_busy(dev->dev); 5313 5314 trace_amdgpu_dm_atomic_commit_tail_finish(state); 5315 } 5316 5317 /* 5318 * Grabs all modesetting locks to serialize against any blocking commits, 5319 * Waits for completion of all non blocking commits. 5320 */ 5321 static int do_aquire_global_lock(struct drm_device *dev, 5322 struct drm_atomic_commit *state) 5323 { 5324 struct drm_crtc *crtc; 5325 struct drm_crtc_commit *commit; 5326 long ret; 5327 5328 /* 5329 * Adding all modeset locks to aquire_ctx will 5330 * ensure that when the framework release it the 5331 * extra locks we are locking here will get released to 5332 */ 5333 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 5334 if (ret) 5335 return ret; 5336 5337 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 5338 spin_lock(&crtc->commit_lock); 5339 commit = list_first_entry_or_null(&crtc->commit_list, 5340 struct drm_crtc_commit, commit_entry); 5341 if (commit) 5342 drm_crtc_commit_get(commit); 5343 spin_unlock(&crtc->commit_lock); 5344 5345 if (!commit) 5346 continue; 5347 5348 /* 5349 * Make sure all pending HW programming completed and 5350 * page flips done 5351 */ 5352 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 5353 5354 if (ret > 0) 5355 ret = wait_for_completion_interruptible_timeout( 5356 &commit->flip_done, 10*HZ); 5357 5358 if (ret == 0) 5359 drm_err(dev, "[CRTC:%d:%s] hw_done or flip_done timed out\n", 5360 crtc->base.id, crtc->name); 5361 5362 drm_crtc_commit_put(commit); 5363 } 5364 5365 return ret < 0 ? ret : 0; 5366 } 5367 5368 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 5369 struct drm_atomic_commit *state, 5370 struct drm_crtc *crtc, 5371 struct drm_crtc_state *old_crtc_state, 5372 struct drm_crtc_state *new_crtc_state, 5373 bool enable, 5374 bool *lock_and_validation_needed) 5375 { 5376 struct dm_atomic_state *dm_state = NULL; 5377 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5378 struct dc_stream_state *new_stream; 5379 struct amdgpu_device *adev = dm->adev; 5380 int ret = 0; 5381 5382 /* 5383 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 5384 * update changed items 5385 */ 5386 struct amdgpu_crtc *acrtc = NULL; 5387 struct drm_connector *connector = NULL; 5388 struct amdgpu_dm_connector *aconnector = NULL; 5389 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 5390 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 5391 5392 new_stream = NULL; 5393 5394 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5395 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5396 acrtc = to_amdgpu_crtc(crtc); 5397 connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 5398 if (connector) 5399 aconnector = to_amdgpu_dm_connector(connector); 5400 5401 /* TODO This hack should go away */ 5402 if (connector && enable) { 5403 /* Make sure fake sink is created in plug-in scenario */ 5404 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 5405 connector); 5406 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 5407 connector); 5408 5409 if (WARN_ON(!drm_new_conn_state)) { 5410 ret = -EINVAL; 5411 goto fail; 5412 } 5413 5414 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 5415 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 5416 5417 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5418 goto skip_modeset; 5419 5420 new_stream = amdgpu_dm_create_validate_stream_for_sink(connector, 5421 &new_crtc_state->mode, 5422 dm_new_conn_state, 5423 dm_old_crtc_state->stream); 5424 5425 /* 5426 * we can have no stream on ACTION_SET if a display 5427 * was disconnected during S3, in this case it is not an 5428 * error, the OS will be updated after detection, and 5429 * will do the right thing on next atomic commit 5430 */ 5431 5432 if (!new_stream) { 5433 drm_dbg_driver(adev_to_drm(adev), "%s: Failed to create new stream for crtc %d\n", 5434 __func__, acrtc->base.base.id); 5435 ret = -ENOMEM; 5436 goto fail; 5437 } 5438 5439 /* 5440 * TODO: Check VSDB bits to decide whether this should 5441 * be enabled or not. 5442 */ 5443 new_stream->triggered_crtc_reset.enabled = 5444 dm->force_timing_sync; 5445 5446 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 5447 5448 ret = amdgpu_dm_fill_hdr_info_packet(drm_new_conn_state, 5449 &new_stream->hdr_static_metadata); 5450 if (ret) 5451 goto fail; 5452 5453 /* 5454 * If we already removed the old stream from the context 5455 * (and set the new stream to NULL) then we can't reuse 5456 * the old stream even if the stream and scaling are unchanged. 5457 * We'll hit the BUG_ON and black screen. 5458 * 5459 * TODO: Refactor this function to allow this check to work 5460 * in all conditions. 5461 */ 5462 if (amdgpu_freesync_vid_mode && 5463 dm_new_crtc_state->stream && 5464 amdgpu_dm_is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) 5465 goto skip_modeset; 5466 5467 if (dm_new_crtc_state->stream && 5468 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 5469 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 5470 new_crtc_state->mode_changed = false; 5471 drm_dbg_driver(adev_to_drm(adev), "Mode change not required, setting mode_changed to %d", 5472 new_crtc_state->mode_changed); 5473 } 5474 } 5475 5476 /* mode_changed flag may get updated above, need to check again */ 5477 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5478 goto skip_modeset; 5479 5480 drm_dbg_state(state->dev, 5481 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 5482 acrtc->crtc_id, 5483 new_crtc_state->enable, 5484 new_crtc_state->active, 5485 new_crtc_state->planes_changed, 5486 new_crtc_state->mode_changed, 5487 new_crtc_state->active_changed, 5488 new_crtc_state->connectors_changed); 5489 5490 /* Remove stream for any changed/disabled CRTC */ 5491 if (!enable) { 5492 5493 if (!dm_old_crtc_state->stream) 5494 goto skip_modeset; 5495 5496 /* Unset freesync video if it was active before */ 5497 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { 5498 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; 5499 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; 5500 } 5501 5502 /* Now check if we should set freesync video mode */ 5503 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream && 5504 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 5505 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) && 5506 amdgpu_dm_is_timing_unchanged_for_freesync(new_crtc_state, 5507 old_crtc_state)) { 5508 new_crtc_state->mode_changed = false; 5509 drm_dbg_driver(adev_to_drm(adev), 5510 "Mode change not required for front porch change, setting mode_changed to %d", 5511 new_crtc_state->mode_changed); 5512 5513 amdgpu_dm_set_freesync_fixed_config(dm_new_crtc_state); 5514 5515 goto skip_modeset; 5516 } else if (amdgpu_freesync_vid_mode && aconnector && 5517 amdgpu_dm_is_freesync_video_mode(&new_crtc_state->mode, 5518 aconnector)) { 5519 struct drm_display_mode *high_mode; 5520 5521 high_mode = amdgpu_dm_get_highest_refresh_rate_mode(aconnector, false); 5522 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) 5523 amdgpu_dm_set_freesync_fixed_config(dm_new_crtc_state); 5524 } 5525 5526 ret = dm_atomic_get_state(state, &dm_state); 5527 if (ret) 5528 goto fail; 5529 5530 drm_dbg_driver(adev_to_drm(adev), "Disabling DRM crtc: %d\n", 5531 crtc->base.id); 5532 5533 /* i.e. reset mode */ 5534 if (dc_state_remove_stream( 5535 dm->dc, 5536 dm_state->context, 5537 dm_old_crtc_state->stream) != DC_OK) { 5538 ret = -EINVAL; 5539 goto fail; 5540 } 5541 5542 dc_stream_release(dm_old_crtc_state->stream); 5543 dm_new_crtc_state->stream = NULL; 5544 5545 amdgpu_dm_reset_freesync_config_for_crtc(dm_new_crtc_state); 5546 5547 *lock_and_validation_needed = true; 5548 5549 } else {/* Add stream for any updated/enabled CRTC */ 5550 /* 5551 * Quick fix to prevent NULL pointer on new_stream when 5552 * added MST connectors not found in existing crtc_state in the chained mode 5553 * TODO: need to dig out the root cause of that 5554 */ 5555 if (!connector) 5556 goto skip_modeset; 5557 5558 if (modereset_required(new_crtc_state)) 5559 goto skip_modeset; 5560 5561 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, 5562 dm_old_crtc_state->stream)) { 5563 5564 WARN_ON(dm_new_crtc_state->stream); 5565 5566 ret = dm_atomic_get_state(state, &dm_state); 5567 if (ret) 5568 goto fail; 5569 5570 dm_new_crtc_state->stream = new_stream; 5571 5572 dc_stream_retain(new_stream); 5573 5574 drm_dbg_atomic(adev_to_drm(adev), "Enabling DRM crtc: %d\n", 5575 crtc->base.id); 5576 5577 if (dc_state_add_stream( 5578 dm->dc, 5579 dm_state->context, 5580 dm_new_crtc_state->stream) != DC_OK) { 5581 ret = -EINVAL; 5582 goto fail; 5583 } 5584 5585 *lock_and_validation_needed = true; 5586 } 5587 } 5588 5589 skip_modeset: 5590 /* Release extra reference */ 5591 if (new_stream) { 5592 dc_stream_release(new_stream); 5593 new_stream = NULL; 5594 } 5595 new_stream = NULL; 5596 5597 /* 5598 * We want to do dc stream updates that do not require a 5599 * full modeset below. 5600 */ 5601 if (!(enable && connector && new_crtc_state->active)) 5602 return 0; 5603 /* 5604 * Given above conditions, the dc state cannot be NULL because: 5605 * 1. We're in the process of enabling CRTCs (just been added 5606 * to the dc context, or already is on the context) 5607 * 2. Has a valid connector attached, and 5608 * 3. Is currently active and enabled. 5609 * => The dc stream state currently exists. 5610 */ 5611 BUG_ON(dm_new_crtc_state->stream == NULL); 5612 5613 /* Scaling or underscan settings */ 5614 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || 5615 drm_atomic_crtc_needs_modeset(new_crtc_state)) 5616 amdgpu_dm_update_stream_scaling_settings(adev_to_drm(adev), 5617 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 5618 5619 /* ABM settings */ 5620 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 5621 5622 /* 5623 * Color management settings. We also update color properties 5624 * when a modeset is needed, to ensure it gets reprogrammed. 5625 */ 5626 if (dm_new_crtc_state->base.color_mgmt_changed || 5627 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 5628 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 5629 ret = amdgpu_dm_check_crtc_color_mgmt(dm_new_crtc_state, true); 5630 if (ret) 5631 goto fail; 5632 } 5633 5634 /* Update Freesync settings. */ 5635 amdgpu_dm_get_freesync_config_for_crtc(dm_new_crtc_state, 5636 dm_new_conn_state); 5637 5638 return ret; 5639 5640 fail: 5641 if (new_stream) 5642 dc_stream_release(new_stream); 5643 return ret; 5644 } 5645 5646 static bool should_reset_plane(struct drm_atomic_commit *state, 5647 struct drm_plane *plane, 5648 struct drm_plane_state *old_plane_state, 5649 struct drm_plane_state *new_plane_state) 5650 { 5651 struct drm_plane *other; 5652 struct drm_plane_state *old_other_state, *new_other_state; 5653 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5654 struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state; 5655 struct amdgpu_device *adev = drm_to_adev(plane->dev); 5656 struct drm_connector_state *new_con_state; 5657 struct drm_connector *connector; 5658 int i; 5659 5660 /* 5661 * TODO: Remove this hack for all asics once it proves that the 5662 * fast updates works fine on DCN3.2+. 5663 */ 5664 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) && 5665 state->allow_modeset) 5666 return true; 5667 5668 /* Check for writeback commit */ 5669 for_each_new_connector_in_state(state, connector, new_con_state, i) { 5670 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 5671 continue; 5672 5673 if (new_con_state->writeback_job) 5674 return true; 5675 } 5676 5677 if (amdgpu_in_reset(adev) && state->allow_modeset) 5678 return true; 5679 5680 /* Exit early if we know that we're adding or removing the plane. */ 5681 if (old_plane_state->crtc != new_plane_state->crtc) 5682 return true; 5683 5684 /* old crtc == new_crtc == NULL, plane not in context. */ 5685 if (!new_plane_state->crtc) 5686 return false; 5687 5688 new_crtc_state = 5689 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 5690 old_crtc_state = 5691 drm_atomic_get_old_crtc_state(state, old_plane_state->crtc); 5692 5693 if (!new_crtc_state) 5694 return true; 5695 5696 /* 5697 * A change in cursor mode means a new dc pipe needs to be acquired or 5698 * released from the state 5699 */ 5700 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); 5701 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 5702 if (plane->type == DRM_PLANE_TYPE_CURSOR && 5703 old_dm_crtc_state != NULL && 5704 old_dm_crtc_state->cursor_mode != new_dm_crtc_state->cursor_mode) { 5705 return true; 5706 } 5707 5708 /* CRTC Degamma changes currently require us to recreate planes. */ 5709 if (new_crtc_state->color_mgmt_changed) 5710 return true; 5711 5712 /* Plane color pipeline or its colorop changes. */ 5713 if (new_plane_state->color_mgmt_changed) 5714 return true; 5715 5716 /* 5717 * On zpos change, planes need to be reordered by removing and re-adding 5718 * them one by one to the dc state, in order of descending zpos. 5719 * 5720 * TODO: We can likely skip bandwidth validation if the only thing that 5721 * changed about the plane was it'z z-ordering. 5722 */ 5723 if (old_plane_state->normalized_zpos != new_plane_state->normalized_zpos) 5724 return true; 5725 5726 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 5727 return true; 5728 5729 /* 5730 * If there are any new primary or overlay planes being added or 5731 * removed then the z-order can potentially change. To ensure 5732 * correct z-order and pipe acquisition the current DC architecture 5733 * requires us to remove and recreate all existing planes. 5734 * 5735 * TODO: Come up with a more elegant solution for this. 5736 */ 5737 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 5738 struct amdgpu_framebuffer *old_afb, *new_afb; 5739 struct dm_plane_state *dm_new_other_state, *dm_old_other_state; 5740 5741 dm_new_other_state = to_dm_plane_state(new_other_state); 5742 dm_old_other_state = to_dm_plane_state(old_other_state); 5743 5744 if (other->type == DRM_PLANE_TYPE_CURSOR) 5745 continue; 5746 5747 if (old_other_state->crtc != new_plane_state->crtc && 5748 new_other_state->crtc != new_plane_state->crtc) 5749 continue; 5750 5751 if (old_other_state->crtc != new_other_state->crtc) 5752 return true; 5753 5754 /* Src/dst size and scaling updates. */ 5755 if (old_other_state->src_w != new_other_state->src_w || 5756 old_other_state->src_h != new_other_state->src_h || 5757 old_other_state->crtc_w != new_other_state->crtc_w || 5758 old_other_state->crtc_h != new_other_state->crtc_h) 5759 return true; 5760 5761 /* Rotation / mirroring updates. */ 5762 if (old_other_state->rotation != new_other_state->rotation) 5763 return true; 5764 5765 /* Blending updates. */ 5766 if (old_other_state->pixel_blend_mode != 5767 new_other_state->pixel_blend_mode) 5768 return true; 5769 5770 /* Alpha updates. */ 5771 if (old_other_state->alpha != new_other_state->alpha) 5772 return true; 5773 5774 /* Colorspace changes. */ 5775 if (old_other_state->color_range != new_other_state->color_range || 5776 old_other_state->color_encoding != new_other_state->color_encoding) 5777 return true; 5778 5779 /* HDR/Transfer Function changes. */ 5780 if (dm_old_other_state->degamma_tf != dm_new_other_state->degamma_tf || 5781 dm_old_other_state->degamma_lut != dm_new_other_state->degamma_lut || 5782 dm_old_other_state->hdr_mult != dm_new_other_state->hdr_mult || 5783 dm_old_other_state->ctm != dm_new_other_state->ctm || 5784 dm_old_other_state->shaper_lut != dm_new_other_state->shaper_lut || 5785 dm_old_other_state->shaper_tf != dm_new_other_state->shaper_tf || 5786 dm_old_other_state->lut3d != dm_new_other_state->lut3d || 5787 dm_old_other_state->blend_lut != dm_new_other_state->blend_lut || 5788 dm_old_other_state->blend_tf != dm_new_other_state->blend_tf) 5789 return true; 5790 5791 /* Framebuffer checks fall at the end. */ 5792 if (!old_other_state->fb || !new_other_state->fb) 5793 continue; 5794 5795 /* Pixel format changes can require bandwidth updates. */ 5796 if (old_other_state->fb->format != new_other_state->fb->format) 5797 return true; 5798 5799 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; 5800 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; 5801 5802 /* Tiling and DCC changes also require bandwidth updates. */ 5803 if (old_afb->base.modifier != new_afb->base.modifier) 5804 return true; 5805 } 5806 5807 return false; 5808 } 5809 5810 static int dm_update_plane_state(struct dc *dc, 5811 struct drm_atomic_commit *state, 5812 struct drm_plane *plane, 5813 struct drm_plane_state *old_plane_state, 5814 struct drm_plane_state *new_plane_state, 5815 bool enable, 5816 bool *lock_and_validation_needed, 5817 bool *is_top_most_overlay) 5818 { 5819 5820 struct dm_atomic_state *dm_state = NULL; 5821 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 5822 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5823 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 5824 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 5825 bool needs_reset, update_native_cursor; 5826 int ret = 0; 5827 5828 5829 new_plane_crtc = new_plane_state->crtc; 5830 old_plane_crtc = old_plane_state->crtc; 5831 dm_new_plane_state = to_dm_plane_state(new_plane_state); 5832 dm_old_plane_state = to_dm_plane_state(old_plane_state); 5833 5834 update_native_cursor = amdgpu_dm_should_update_native_cursor(state, 5835 old_plane_crtc, 5836 new_plane_crtc, 5837 enable); 5838 5839 if (plane->type == DRM_PLANE_TYPE_CURSOR && update_native_cursor) { 5840 ret = amdgpu_dm_check_native_cursor_state(new_plane_crtc, plane, 5841 new_plane_state, enable); 5842 if (ret) 5843 return ret; 5844 5845 return 0; 5846 } 5847 5848 needs_reset = should_reset_plane(state, plane, old_plane_state, 5849 new_plane_state); 5850 5851 /* Remove any changed/removed planes */ 5852 if (!enable) { 5853 if (!needs_reset) 5854 return 0; 5855 5856 if (!old_plane_crtc) 5857 return 0; 5858 5859 old_crtc_state = drm_atomic_get_old_crtc_state( 5860 state, old_plane_crtc); 5861 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5862 5863 if (!dm_old_crtc_state->stream) 5864 return 0; 5865 5866 drm_dbg_atomic(old_plane_crtc->dev, "Disabling DRM plane: %d on DRM crtc %d\n", 5867 plane->base.id, old_plane_crtc->base.id); 5868 5869 ret = dm_atomic_get_state(state, &dm_state); 5870 if (ret) 5871 return ret; 5872 5873 if (!dc_state_remove_plane( 5874 dc, 5875 dm_old_crtc_state->stream, 5876 dm_old_plane_state->dc_state, 5877 dm_state->context)) { 5878 5879 return -EINVAL; 5880 } 5881 5882 if (dm_old_plane_state->dc_state) 5883 dc_plane_state_release(dm_old_plane_state->dc_state); 5884 5885 dm_new_plane_state->dc_state = NULL; 5886 5887 *lock_and_validation_needed = true; 5888 5889 } else { /* Add new planes */ 5890 struct dc_plane_state *dc_new_plane_state; 5891 5892 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 5893 return 0; 5894 5895 if (!new_plane_crtc) 5896 return 0; 5897 5898 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 5899 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5900 5901 if (!dm_new_crtc_state->stream) 5902 return 0; 5903 5904 if (!needs_reset) 5905 return 0; 5906 5907 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 5908 if (ret) 5909 goto out; 5910 5911 WARN_ON(dm_new_plane_state->dc_state); 5912 5913 dc_new_plane_state = dc_create_plane_state(dc); 5914 if (!dc_new_plane_state) { 5915 ret = -ENOMEM; 5916 goto out; 5917 } 5918 5919 drm_dbg_atomic(new_plane_crtc->dev, "Enabling DRM plane: %d on DRM crtc %d\n", 5920 plane->base.id, new_plane_crtc->base.id); 5921 5922 ret = fill_dc_plane_attributes( 5923 drm_to_adev(new_plane_crtc->dev), 5924 dc_new_plane_state, 5925 new_plane_state, 5926 new_crtc_state); 5927 if (ret) { 5928 dc_plane_state_release(dc_new_plane_state); 5929 goto out; 5930 } 5931 5932 ret = dm_atomic_get_state(state, &dm_state); 5933 if (ret) { 5934 dc_plane_state_release(dc_new_plane_state); 5935 goto out; 5936 } 5937 5938 /* 5939 * Any atomic check errors that occur after this will 5940 * not need a release. The plane state will be attached 5941 * to the stream, and therefore part of the atomic 5942 * state. It'll be released when the atomic state is 5943 * cleaned. 5944 */ 5945 if (!dc_state_add_plane( 5946 dc, 5947 dm_new_crtc_state->stream, 5948 dc_new_plane_state, 5949 dm_state->context)) { 5950 5951 dc_plane_state_release(dc_new_plane_state); 5952 ret = -EINVAL; 5953 goto out; 5954 } 5955 5956 dm_new_plane_state->dc_state = dc_new_plane_state; 5957 5958 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); 5959 5960 /* Tell DC to do a full surface update every time there 5961 * is a plane change. Inefficient, but works for now. 5962 */ 5963 dm_new_plane_state->dc_state->update_bits.full_update = 1; 5964 5965 *lock_and_validation_needed = true; 5966 } 5967 5968 out: 5969 /* If enabling cursor overlay failed, attempt fallback to native mode */ 5970 if (enable && ret == -EINVAL && plane->type == DRM_PLANE_TYPE_CURSOR) { 5971 ret = amdgpu_dm_check_native_cursor_state(new_plane_crtc, plane, 5972 new_plane_state, enable); 5973 if (ret) 5974 return ret; 5975 5976 dm_new_crtc_state->cursor_mode = DM_CURSOR_NATIVE_MODE; 5977 } 5978 5979 return ret; 5980 } 5981 5982 /* 5983 * The normalized_zpos value cannot be used by this iterator directly. It's only 5984 * calculated for enabled planes, potentially causing normalized_zpos collisions 5985 * between enabled/disabled planes in the atomic state. We need a unique value 5986 * so that the iterator will not generate the same object twice, or loop 5987 * indefinitely. 5988 */ 5989 struct __drm_planes_state *amdgpu_dm_get_next_zpos( 5990 struct drm_atomic_commit *state, 5991 struct __drm_planes_state *prev) 5992 { 5993 unsigned int highest_zpos = 0, prev_zpos = 256; 5994 uint32_t highest_id = 0, prev_id = UINT_MAX; 5995 struct drm_plane_state *new_plane_state; 5996 struct drm_plane *plane; 5997 int i, highest_i = -1; 5998 5999 if (prev != NULL) { 6000 prev_zpos = prev->new_state->zpos; 6001 prev_id = prev->ptr->base.id; 6002 } 6003 6004 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 6005 /* Skip planes with higher zpos than the previously returned */ 6006 if (new_plane_state->zpos > prev_zpos || 6007 (new_plane_state->zpos == prev_zpos && 6008 plane->base.id >= prev_id)) 6009 continue; 6010 6011 /* Save the index of the plane with highest zpos */ 6012 if (new_plane_state->zpos > highest_zpos || 6013 (new_plane_state->zpos == highest_zpos && 6014 plane->base.id > highest_id)) { 6015 highest_zpos = new_plane_state->zpos; 6016 highest_id = plane->base.id; 6017 highest_i = i; 6018 } 6019 } 6020 6021 if (highest_i < 0) 6022 return NULL; 6023 6024 return &state->planes[highest_i]; 6025 } 6026 6027 static int add_affected_mst_dsc_crtcs(struct drm_atomic_commit *state, struct drm_crtc *crtc) 6028 { 6029 struct drm_connector *connector; 6030 struct drm_connector_state *conn_state, *old_conn_state; 6031 struct amdgpu_dm_connector *aconnector = NULL; 6032 int i; 6033 6034 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { 6035 if (!conn_state->crtc) 6036 conn_state = old_conn_state; 6037 6038 if (conn_state->crtc != crtc) 6039 continue; 6040 6041 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 6042 continue; 6043 6044 aconnector = to_amdgpu_dm_connector(connector); 6045 if (!aconnector->mst_output_port || !aconnector->mst_root) 6046 aconnector = NULL; 6047 else 6048 break; 6049 } 6050 6051 if (!aconnector) 6052 return 0; 6053 6054 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); 6055 } 6056 6057 static bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev, 6058 struct drm_atomic_commit *state, 6059 struct drm_crtc_state *crtc_state) 6060 { 6061 struct drm_plane *plane; 6062 struct drm_plane_state *new_plane_state, *old_plane_state; 6063 6064 drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) { 6065 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 6066 old_plane_state = drm_atomic_get_old_plane_state(state, plane); 6067 6068 if (!old_plane_state || !new_plane_state) 6069 continue; 6070 6071 if (old_plane_state->fb && new_plane_state->fb && 6072 get_mem_type(old_plane_state->fb) != get_mem_type(new_plane_state->fb)) 6073 return true; 6074 } 6075 6076 return false; 6077 } 6078 6079 /** 6080 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 6081 * 6082 * @dev: The DRM device 6083 * @state: The atomic state to commit 6084 * 6085 * Validate that the given atomic state is programmable by DC into hardware. 6086 * This involves constructing a &struct dc_state reflecting the new hardware 6087 * state we wish to commit, then querying DC to see if it is programmable. It's 6088 * important not to modify the existing DC state. Otherwise, atomic_check 6089 * may unexpectedly commit hardware changes. 6090 * 6091 * When validating the DC state, it's important that the right locks are 6092 * acquired. For full updates case which removes/adds/updates streams on one 6093 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 6094 * that any such full update commit will wait for completion of any outstanding 6095 * flip using DRMs synchronization events. 6096 * 6097 * Note that DM adds the affected connectors for all CRTCs in state, when that 6098 * might not seem necessary. This is because DC stream creation requires the 6099 * DC sink, which is tied to the DRM connector state. Cleaning this up should 6100 * be possible but non-trivial - a possible TODO item. 6101 * 6102 * Return: -Error code if validation failed. 6103 */ 6104 static int amdgpu_dm_atomic_check(struct drm_device *dev, 6105 struct drm_atomic_commit *state) 6106 { 6107 struct amdgpu_device *adev = drm_to_adev(dev); 6108 struct dm_atomic_state *dm_state = NULL; 6109 struct dc *dc = adev->dm.dc; 6110 struct drm_connector *connector; 6111 struct drm_connector_state *old_con_state, *new_con_state; 6112 struct drm_crtc *crtc; 6113 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6114 struct drm_plane *plane; 6115 struct drm_plane_state *old_plane_state, *new_plane_state, *new_cursor_state; 6116 enum dc_status status; 6117 int ret, i; 6118 bool lock_and_validation_needed = false; 6119 bool is_top_most_overlay = true; 6120 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 6121 struct drm_dp_mst_topology_mgr *mgr; 6122 struct drm_dp_mst_topology_state *mst_state; 6123 struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; 6124 6125 trace_amdgpu_dm_atomic_check_begin(state); 6126 6127 ret = drm_atomic_helper_check_modeset(dev, state); 6128 if (ret) { 6129 drm_dbg_atomic(dev, "drm_atomic_helper_check_modeset() failed: %pe\n", ERR_PTR(ret)); 6130 goto fail; 6131 } 6132 6133 /* Check connector changes */ 6134 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6135 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 6136 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 6137 6138 /* Skip connectors that are disabled or part of modeset already. */ 6139 if (!new_con_state->crtc) 6140 continue; 6141 6142 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); 6143 if (IS_ERR(new_crtc_state)) { 6144 drm_dbg_atomic(dev, "drm_atomic_get_crtc_state() failed: %pe\n", new_crtc_state); 6145 ret = PTR_ERR(new_crtc_state); 6146 goto fail; 6147 } 6148 6149 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || 6150 dm_old_con_state->scaling != dm_new_con_state->scaling) 6151 new_crtc_state->connectors_changed = true; 6152 } 6153 6154 if (dc_resource_is_dsc_encoding_supported(dc)) { 6155 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6156 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6157 dm_new_crtc_state->mode_changed_independent_from_dsc = new_crtc_state->mode_changed; 6158 } 6159 6160 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6161 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 6162 ret = add_affected_mst_dsc_crtcs(state, crtc); 6163 if (ret) { 6164 drm_dbg_atomic(dev, "add_affected_mst_dsc_crtcs() failed: %pe\n", ERR_PTR(ret)); 6165 goto fail; 6166 } 6167 } 6168 } 6169 } 6170 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6171 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6172 6173 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 6174 !new_crtc_state->color_mgmt_changed && 6175 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && 6176 dm_old_crtc_state->dsc_force_changed == false) 6177 continue; 6178 6179 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); 6180 if (ret) { 6181 drm_dbg_atomic(dev, "amdgpu_dm_verify_lut_sizes() failed: %pe\n", ERR_PTR(ret)); 6182 goto fail; 6183 } 6184 6185 if (!new_crtc_state->enable) 6186 continue; 6187 6188 ret = drm_atomic_add_affected_connectors(state, crtc); 6189 if (ret) { 6190 drm_dbg_atomic(dev, "drm_atomic_add_affected_connectors() failed: %pe\n", ERR_PTR(ret)); 6191 goto fail; 6192 } 6193 6194 ret = drm_atomic_add_affected_planes(state, crtc); 6195 if (ret) { 6196 drm_dbg_atomic(dev, "drm_atomic_add_affected_planes() failed: %pe\n", ERR_PTR(ret)); 6197 goto fail; 6198 } 6199 6200 if (dm_old_crtc_state->dsc_force_changed) 6201 new_crtc_state->mode_changed = true; 6202 } 6203 6204 /* 6205 * Add all primary and overlay planes on the CRTC to the state 6206 * whenever a plane is enabled to maintain correct z-ordering 6207 * and to enable fast surface updates. 6208 */ 6209 drm_for_each_crtc(crtc, dev) { 6210 bool modified = false; 6211 6212 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 6213 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6214 continue; 6215 6216 if (new_plane_state->crtc == crtc || 6217 old_plane_state->crtc == crtc) { 6218 modified = true; 6219 break; 6220 } 6221 } 6222 6223 if (!modified) 6224 continue; 6225 6226 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 6227 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6228 continue; 6229 6230 new_plane_state = 6231 drm_atomic_get_plane_state(state, plane); 6232 6233 if (IS_ERR(new_plane_state)) { 6234 ret = PTR_ERR(new_plane_state); 6235 drm_dbg_atomic(dev, "new_plane_state is BAD: %pe\n", new_plane_state); 6236 goto fail; 6237 } 6238 } 6239 } 6240 6241 /* 6242 * DC consults the zpos (layer_index in DC terminology) to determine the 6243 * hw plane on which to enable the hw cursor (see 6244 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in 6245 * atomic state, so call drm helper to normalize zpos. 6246 */ 6247 ret = drm_atomic_normalize_zpos(dev, state); 6248 if (ret) { 6249 drm_dbg(dev, "drm_atomic_normalize_zpos() failed: %pe\n", ERR_PTR(ret)); 6250 goto fail; 6251 } 6252 6253 /* 6254 * Determine whether cursors on each CRTC should be enabled in native or 6255 * overlay mode. 6256 */ 6257 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6258 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6259 6260 ret = amdgpu_dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 6261 &dm_new_crtc_state->cursor_mode); 6262 if (ret) { 6263 drm_dbg(dev, "Failed to determine cursor mode: %pe\n", ERR_PTR(ret)); 6264 goto fail; 6265 } 6266 6267 /* 6268 * If overlay cursor is needed, DC cannot go through the 6269 * native cursor update path. All enabled planes on the CRTC 6270 * need to be added for DC to not disable a plane by mistake 6271 */ 6272 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) { 6273 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { 6274 drm_dbg(dev, "Overlay cursor not supported on DCE\n"); 6275 ret = -EINVAL; 6276 goto fail; 6277 } 6278 6279 ret = drm_atomic_add_affected_planes(state, crtc); 6280 if (ret) 6281 goto fail; 6282 } 6283 } 6284 6285 /* Remove exiting planes if they are modified */ 6286 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 6287 6288 ret = dm_update_plane_state(dc, state, plane, 6289 old_plane_state, 6290 new_plane_state, 6291 false, 6292 &lock_and_validation_needed, 6293 &is_top_most_overlay); 6294 if (ret) { 6295 drm_dbg_atomic(dev, "dm_update_plane_state() failed: %pe\n", ERR_PTR(ret)); 6296 goto fail; 6297 } 6298 } 6299 6300 /* Disable all crtcs which require disable */ 6301 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6302 ret = dm_update_crtc_state(&adev->dm, state, crtc, 6303 old_crtc_state, 6304 new_crtc_state, 6305 false, 6306 &lock_and_validation_needed); 6307 if (ret) { 6308 drm_dbg_atomic(dev, "DISABLE: dm_update_crtc_state() failed: %pe\n", ERR_PTR(ret)); 6309 goto fail; 6310 } 6311 } 6312 6313 /* Enable all crtcs which require enable */ 6314 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6315 ret = dm_update_crtc_state(&adev->dm, state, crtc, 6316 old_crtc_state, 6317 new_crtc_state, 6318 true, 6319 &lock_and_validation_needed); 6320 if (ret) { 6321 drm_dbg_atomic(dev, "ENABLE: dm_update_crtc_state() failed: %pe\n", ERR_PTR(ret)); 6322 goto fail; 6323 } 6324 } 6325 6326 /* Add new/modified planes */ 6327 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 6328 ret = dm_update_plane_state(dc, state, plane, 6329 old_plane_state, 6330 new_plane_state, 6331 true, 6332 &lock_and_validation_needed, 6333 &is_top_most_overlay); 6334 if (ret) { 6335 drm_dbg_atomic(dev, "dm_update_plane_state() failed: %pe\n", ERR_PTR(ret)); 6336 goto fail; 6337 } 6338 } 6339 6340 #if defined(CONFIG_DRM_AMD_DC_FP) 6341 if (dc_resource_is_dsc_encoding_supported(dc)) { 6342 ret = pre_validate_dsc(state, &dm_state, vars); 6343 if (ret != 0) 6344 goto fail; 6345 } 6346 #endif 6347 6348 /* Run this here since we want to validate the streams we created */ 6349 ret = drm_atomic_helper_check_planes(dev, state); 6350 if (ret) { 6351 drm_dbg_atomic(dev, "drm_atomic_helper_check_planes() failed: %pe\n", ERR_PTR(ret)); 6352 goto fail; 6353 } 6354 6355 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6356 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6357 if (dm_new_crtc_state->mpo_requested) 6358 drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc); 6359 } 6360 6361 /* Check cursor restrictions */ 6362 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6363 enum amdgpu_dm_cursor_mode required_cursor_mode; 6364 int is_rotated, is_scaled; 6365 6366 /* Overlay cusor not subject to native cursor restrictions */ 6367 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6368 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) 6369 continue; 6370 6371 /* Check if rotation or scaling is enabled on DCN 4x and above */ 6372 if ((drm_plane_mask(crtc->cursor) & new_crtc_state->plane_mask) && 6373 (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 0, 1))) { 6374 new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor); 6375 6376 is_rotated = new_cursor_state && 6377 ((new_cursor_state->rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0); 6378 is_scaled = new_cursor_state && ((new_cursor_state->src_w >> 16 != new_cursor_state->crtc_w) || 6379 (new_cursor_state->src_h >> 16 != new_cursor_state->crtc_h)); 6380 6381 if (is_rotated || is_scaled) { 6382 drm_dbg_driver( 6383 crtc->dev, 6384 "[CRTC:%d:%s] cannot enable hardware cursor due to rotation/scaling\n", 6385 crtc->base.id, crtc->name); 6386 ret = -EINVAL; 6387 goto fail; 6388 } 6389 } 6390 6391 /* If HW can only do native cursor, check restrictions again */ 6392 ret = amdgpu_dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 6393 &required_cursor_mode); 6394 if (ret) { 6395 drm_dbg_driver(crtc->dev, 6396 "[CRTC:%d:%s] Checking cursor mode failed\n", 6397 crtc->base.id, crtc->name); 6398 goto fail; 6399 } else if (required_cursor_mode == DM_CURSOR_OVERLAY_MODE) { 6400 drm_dbg_driver(crtc->dev, 6401 "[CRTC:%d:%s] Cannot enable native cursor due to scaling, YUV, or color pipeline restrictions\n", 6402 crtc->base.id, crtc->name); 6403 ret = -EINVAL; 6404 goto fail; 6405 } 6406 } 6407 6408 if (state->legacy_cursor_update) { 6409 /* 6410 * This is a fast cursor update coming from the plane update 6411 * helper, check if it can be done asynchronously for better 6412 * performance. 6413 */ 6414 state->async_update = 6415 !drm_atomic_helper_async_check(dev, state); 6416 6417 /* 6418 * Skip the remaining global validation if this is an async 6419 * update. Cursor updates can be done without affecting 6420 * state or bandwidth calcs and this avoids the performance 6421 * penalty of locking the private state object and 6422 * allocating a new dc_state. 6423 */ 6424 if (state->async_update) 6425 return 0; 6426 } 6427 6428 /* Check scaling and underscan changes*/ 6429 /* TODO Removed scaling changes validation due to inability to commit 6430 * new stream into context w\o causing full reset. Need to 6431 * decide how to handle. 6432 */ 6433 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6434 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 6435 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 6436 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 6437 6438 /* Skip any modesets/resets */ 6439 if (!acrtc || drm_atomic_crtc_needs_modeset( 6440 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 6441 continue; 6442 6443 /* Skip any thing not scale or underscan changes */ 6444 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 6445 continue; 6446 6447 lock_and_validation_needed = true; 6448 } 6449 6450 /* set the slot info for each mst_state based on the link encoding format */ 6451 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 6452 struct amdgpu_dm_connector *aconnector; 6453 struct drm_connector *connector; 6454 struct drm_connector_list_iter iter; 6455 u8 link_coding_cap; 6456 6457 drm_connector_list_iter_begin(dev, &iter); 6458 drm_for_each_connector_iter(connector, &iter) { 6459 if (connector->index == mst_state->mgr->conn_base_id) { 6460 aconnector = to_amdgpu_dm_connector(connector); 6461 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); 6462 drm_dp_mst_update_slots(mst_state, link_coding_cap); 6463 6464 break; 6465 } 6466 } 6467 drm_connector_list_iter_end(&iter); 6468 } 6469 6470 /** 6471 * Streams and planes are reset when there are changes that affect 6472 * bandwidth. Anything that affects bandwidth needs to go through 6473 * DC global validation to ensure that the configuration can be applied 6474 * to hardware. 6475 * 6476 * We have to currently stall out here in atomic_check for outstanding 6477 * commits to finish in this case because our IRQ handlers reference 6478 * DRM state directly - we can end up disabling interrupts too early 6479 * if we don't. 6480 * 6481 * TODO: Remove this stall and drop DM state private objects. 6482 */ 6483 if (lock_and_validation_needed) { 6484 ret = dm_atomic_get_state(state, &dm_state); 6485 if (ret) { 6486 drm_dbg_atomic(dev, "dm_atomic_get_state() failed: %pe\n", ERR_PTR(ret)); 6487 goto fail; 6488 } 6489 6490 ret = do_aquire_global_lock(dev, state); 6491 if (ret) { 6492 drm_dbg_atomic(dev, "do_aquire_global_lock() failed: %pe\n", ERR_PTR(ret)); 6493 goto fail; 6494 } 6495 6496 #if defined(CONFIG_DRM_AMD_DC_FP) 6497 if (dc_resource_is_dsc_encoding_supported(dc)) { 6498 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); 6499 if (ret) { 6500 drm_dbg_atomic(dev, "MST_DSC compute_mst_dsc_configs_for_state() failed: %pe\n", ERR_PTR(ret)); 6501 ret = -EINVAL; 6502 goto fail; 6503 } 6504 } 6505 #endif 6506 6507 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); 6508 if (ret) { 6509 drm_dbg_atomic(dev, "dm_update_mst_vcpi_slots_for_dsc() failed: %pe\n", ERR_PTR(ret)); 6510 goto fail; 6511 } 6512 6513 /* 6514 * Perform validation of MST topology in the state: 6515 * We need to perform MST atomic check before calling 6516 * dc_validate_global_state(), or there is a chance 6517 * to get stuck in an infinite loop and hang eventually. 6518 */ 6519 ret = drm_dp_mst_atomic_check(state); 6520 if (ret) { 6521 drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed: %pe\n", ERR_PTR(ret)); 6522 goto fail; 6523 } 6524 status = dc_validate_global_state(dc, dm_state->context, DC_VALIDATE_MODE_ONLY); 6525 if (status != DC_OK) { 6526 drm_dbg_atomic(dev, "DC global validation failure: %s (%d)", 6527 dc_status_to_str(status), status); 6528 ret = -EINVAL; 6529 goto fail; 6530 } 6531 } else { 6532 /* 6533 * The commit is a fast update. Fast updates shouldn't change 6534 * the DC context, affect global validation, and can have their 6535 * commit work done in parallel with other commits not touching 6536 * the same resource. If we have a new DC context as part of 6537 * the DM atomic state from validation we need to free it and 6538 * retain the existing one instead. 6539 * 6540 * Furthermore, since the DM atomic state only contains the DC 6541 * context and can safely be annulled, we can free the state 6542 * and clear the associated private object now to free 6543 * some memory and avoid a possible use-after-free later. 6544 */ 6545 6546 for (i = 0; i < state->num_private_objs; i++) { 6547 struct drm_private_obj *obj = state->private_objs[i].ptr; 6548 6549 if (obj->funcs == adev->dm.atomic_obj.funcs) { 6550 int j = state->num_private_objs-1; 6551 6552 dm_atomic_destroy_state(obj, 6553 state->private_objs[i].state_to_destroy); 6554 6555 /* If i is not at the end of the array then the 6556 * last element needs to be moved to where i was 6557 * before the array can safely be truncated. 6558 */ 6559 if (i != j) 6560 state->private_objs[i] = 6561 state->private_objs[j]; 6562 6563 state->private_objs[j].ptr = NULL; 6564 state->private_objs[j].state_to_destroy = NULL; 6565 state->private_objs[j].old_state = NULL; 6566 state->private_objs[j].new_state = NULL; 6567 6568 state->num_private_objs = j; 6569 break; 6570 } 6571 } 6572 } 6573 6574 /* Store the overall update type for use later in atomic check. */ 6575 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6576 struct dm_crtc_state *dm_new_crtc_state = 6577 to_dm_crtc_state(new_crtc_state); 6578 6579 /* 6580 * Only allow async flips for fast updates that don't change 6581 * the FB pitch, the DCC state, rotation, mem_type, etc. 6582 */ 6583 if (new_crtc_state->async_flip && 6584 (lock_and_validation_needed || 6585 amdgpu_dm_crtc_mem_type_changed(dev, state, new_crtc_state))) { 6586 drm_dbg_atomic(crtc->dev, 6587 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 6588 crtc->base.id, crtc->name); 6589 ret = -EINVAL; 6590 goto fail; 6591 } 6592 6593 dm_new_crtc_state->update_type = lock_and_validation_needed ? 6594 UPDATE_TYPE_FULL : UPDATE_TYPE_FAST; 6595 } 6596 6597 /* Must be success */ 6598 WARN_ON(ret); 6599 6600 trace_amdgpu_dm_atomic_check_finish(state, ret); 6601 6602 return ret; 6603 6604 fail: 6605 if (ret == -EDEADLK) 6606 drm_dbg_atomic(dev, "Atomic check stopped to avoid deadlock.\n"); 6607 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 6608 drm_dbg_atomic(dev, "Atomic check stopped due to signal.\n"); 6609 else 6610 drm_dbg_atomic(dev, "Atomic check failed: %pe\n", ERR_PTR(ret)); 6611 6612 trace_amdgpu_dm_atomic_check_finish(state, ret); 6613 6614 return ret; 6615 } 6616 6617 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 6618 { 6619 struct amdgpu_device *adev = drm_to_adev(dev); 6620 struct dc *dc = adev->dm.dc; 6621 int i; 6622 6623 mutex_lock(&adev->dm.dc_lock); 6624 if (dc->current_state) { 6625 for (i = 0; i < dc->current_state->stream_count; ++i) 6626 dc->current_state->streams[i] 6627 ->triggered_crtc_reset.enabled = 6628 adev->dm.force_timing_sync; 6629 6630 dm_enable_per_frame_crtc_master_sync(dc->current_state); 6631 dc_trigger_sync(dc, dc->current_state); 6632 } 6633 mutex_unlock(&adev->dm.dc_lock); 6634 } 6635 6636 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 6637 u32 value, const char *func_name) 6638 { 6639 #ifdef DM_CHECK_ADDR_0 6640 if (address == 0) { 6641 drm_err(adev_to_drm(ctx->driver_context), 6642 "invalid register write. address = 0"); 6643 return; 6644 } 6645 #endif 6646 6647 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 6648 cgs_write_register(ctx->cgs_device, address, value); 6649 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); 6650 } 6651 6652 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, 6653 const char *func_name) 6654 { 6655 u32 value; 6656 #ifdef DM_CHECK_ADDR_0 6657 if (address == 0) { 6658 drm_err(adev_to_drm(ctx->driver_context), 6659 "invalid register read; address = 0\n"); 6660 return 0; 6661 } 6662 #endif 6663 6664 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 6665 6666 value = cgs_read_register(ctx->cgs_device, address); 6667 6668 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 6669 6670 return value; 6671 } 6672 6673 void dm_acpi_process_phy_transition_interlock( 6674 const struct dc_context *ctx, 6675 struct dm_process_phy_transition_init_params process_phy_transition_init_params) 6676 { 6677 // Not yet implemented 6678 } 6679