| df822f2e | 14-Aug-2026 |
Stephen Boyd <sboyd@kernel.org> |
Merge tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile
Pull clk patches from Brian Masney:
- New clock controller drivers for the Cix Sky1 audio subsystem (AUDSS),
Merge tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile
Pull clk patches from Brian Masney:
- New clock controller drivers for the Cix Sky1 audio subsystem (AUDSS), UltraRISC DP1000, and MediaTek MT8173 MFG_TOP, along with their devicetree bindings. Si549 support was added to the existing si544 driver. - New clock and reset support for the Aspeed AST2700 PECI controller and Airoha EN7523 PCIe PERSTOUT reset lines. - The clk core gains devm_clk_bulk_get_enable() as the mandatory counterpart to the existing optional variant, and exports devm_clk_hw_register_composite_pdata() for modular drivers. - Tegra gets a proper EMC clock implementation for Tegra114, 48MHz pll_p_out1 support needed for UEFI on Surface2, and the Xilinx clocking-wizard gains PLL charge pump/lock parameter programming during dynamic reconfiguration. - Bug fixes for a NULL pointer dereference from uninitialized clk_init_data in the eswin driver, an IO remap leak in the MediaTek pllfh error path, inverted gate control for MT8135 devapc_ck, a missing OF node put in tegra124-emc on registration failure, a prepare reference leak in the palmas driver, unregistered PLLs on MT6735 probe failure, a missing kasprintf NULL check in pmc_atom, PCIe warm boot instability in the Airoha EN7523 driver, and a clocking-wizard clock difference detection bug. - Various cleanups across tegra, st, and mvebu providers to stop misusing the consumer clock API, along with other minor fixes and improvements.
Signed-off-by: Brian Masney <bmasney@redhat.com>
* tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux: (45 commits) clk: tegra: set up proper EMC clock implementation for Tegra114 clk: clocking-wizard: remove 20kHz restriction clk: clocking-wizard: optimize clock search clk: clocking-wizard: fix clock difference detection clk: mediatek: mt8135: Fix inverted gate control for devapc_ck clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig clk: tegra: support 48MHz clock for pll_p_out1 clk: aspeed: add AST2700 PECI clock dt-bindings: clock: ast2700: add PECI clock clk: mediatek: Add mt8173-mfgtop driver dt-bindings: clock: mediatek: Add mt8173 mfgtop clk: tegra: clean-up simple provider misuse of the consumer API clk: st: clean-up simple provider misuse of the consumer API clk: mvebu: clean-up simple provider misuse of the consumer API clk: remove conditional return with no effect clk: Add devm_clk_bulk_get_enable() clk: en7523: add support for dedicated PCIe PERSTOUT reset dt-bindings: clock: airoha: Add additional reset for PCIe PERSTOUT arm64: dts: cix: sky1: add audss cru reset: cix: add sky1 audss auxiliary reset driver ...
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| 54ed94b7 | 29-Jun-2026 |
Colin Foster <colin.foster@in-advantage.com> |
clk: clocking-wizard: remove 20kHz restriction
Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Colin Foster <colin.foster@i
clk: clocking-wizard: remove 20kHz restriction
Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Colin Foster <colin.foster@in-advantage.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
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| 93297144 | 29-Jun-2026 |
Colin Foster <colin.foster@in-advantage.com> |
clk: clocking-wizard: optimize clock search
When an exact clock match is found, there is no need to continue searching. This process was optimized for versal as part of 'commit e0a94c6bb5b4 ("clk: x
clk: clocking-wizard: optimize clock search
When an exact clock match is found, there is no need to continue searching. This process was optimized for versal as part of 'commit e0a94c6bb5b4 ("clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver()")' but that logic wasn't applied to the non-versal driver.
Apply this fast-exit logic to the non-versal driver.
Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Colin Foster <colin.foster@in-advantage.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
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| 006ba909 | 29-Jun-2026 |
Colin Foster <colin.foster@in-advantage.com> |
clk: clocking-wizard: fix clock difference detection
Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Colin Foster <colin.fo
clk: clocking-wizard: fix clock difference detection
Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Colin Foster <colin.foster@in-advantage.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
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| 7c2e86f7 | 05-Sep-2025 |
Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> |
clk: clocking-wizard: Fix output clock register offset for Versal platforms
The output clock register offset used in clk_wzrd_register_output_clocks was incorrectly referencing 0x3C instead of 0x38,
clk: clocking-wizard: Fix output clock register offset for Versal platforms
The output clock register offset used in clk_wzrd_register_output_clocks was incorrectly referencing 0x3C instead of 0x38, which caused misconfiguration of output dividers on Versal platforms.
Correcting the off-by-one error ensures proper configuration of output clocks.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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| 5352b650 | 11-Aug-2025 |
Brian Masney <bmasney@redhat.com> |
clk: xilinx: xlnx_vcu: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semanti
clk: xilinx: xlnx_vcu: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series.
Signed-off-by: Brian Masney <bmasney@redhat.com>
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| af9019b5 | 10-Feb-2025 |
Rohit Visavalia <rohit.visavalia@amd.com> |
clk: xilinx: vcu: Update vcu init/reset sequence
Updated vcu init/reset sequence as per design changes. If VCU reset GPIO is available then do assert and de-assert it before enabling/disabling gaske
clk: xilinx: vcu: Update vcu init/reset sequence
Updated vcu init/reset sequence as per design changes. If VCU reset GPIO is available then do assert and de-assert it before enabling/disabling gasket isolation. This GPIO is added because gasket isolation will be removed during startup that requires access to SLCR register space. Post startup, the ownership of the register interface lies with logiCORE IP.
Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com> Link: https://lore.kernel.org/r/20250210113614.4149050-3-rohit.visavalia@amd.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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| 8e742c6e | 13-Sep-2024 |
Harry Austen <hpausten@protonmail.com> |
clk: clocking-wizard: move dynamic reconfig setup behind flag
Xilinx clocking wizard IP core's dynamic reconfiguration support is optionally enabled at build time. Use the new boolean devicetree pro
clk: clocking-wizard: move dynamic reconfig setup behind flag
Xilinx clocking wizard IP core's dynamic reconfiguration support is optionally enabled at build time. Use the new boolean devicetree property to indicate whether the hardware supports this feature or not.
Signed-off-by: Harry Austen <hpausten@protonmail.com> Link: https://lore.kernel.org/r/20240913191037.2690-7-hpausten@protonmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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| 32c9262a | 13-Sep-2024 |
Harry Austen <hpausten@protonmail.com> |
clk: clocking-wizard: move clock registration to separate function
Provide clear separation of dynamic reconfiguration logic, by moving its setup procedure to its own dedicated function.
Signed-off
clk: clocking-wizard: move clock registration to separate function
Provide clear separation of dynamic reconfiguration logic, by moving its setup procedure to its own dedicated function.
Signed-off-by: Harry Austen <hpausten@protonmail.com> Link: https://lore.kernel.org/r/20240913191037.2690-5-hpausten@protonmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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| fc51bad7 | 13-Sep-2024 |
Harry Austen <hpausten@protonmail.com> |
clk: clocking-wizard: use devres versions of clk_hw API
Use device managed versions of the clk_hw API, entirely removing the need for the driver's remove() callback and greatly simplifying the probe
clk: clocking-wizard: use devres versions of clk_hw API
Use device managed versions of the clk_hw API, entirely removing the need for the driver's remove() callback and greatly simplifying the probe() function's error paths.
Signed-off-by: Harry Austen <hpausten@protonmail.com> Link: https://lore.kernel.org/r/20240913191037.2690-4-hpausten@protonmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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| bb487924 | 13-Sep-2024 |
Harry Austen <hpausten@protonmail.com> |
clk: clocking-wizard: use newer clk_hw API
Utilise clock provider API with struct clk_hw instances instead of the consumer-side struct clk.
Signed-off-by: Harry Austen <hpausten@protonmail.com> Lin
clk: clocking-wizard: use newer clk_hw API
Utilise clock provider API with struct clk_hw instances instead of the consumer-side struct clk.
Signed-off-by: Harry Austen <hpausten@protonmail.com> Link: https://lore.kernel.org/r/20240913191037.2690-3-hpausten@protonmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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