1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/device.h> 7 #include <linux/interconnect.h> 8 #include <linux/interconnect-provider.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 12 #include <dt-bindings/interconnect/qcom,sdm845.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 17 static struct qcom_icc_node qhm_a1noc_cfg; 18 static struct qcom_icc_node qhm_qup1; 19 static struct qcom_icc_node qhm_tsif; 20 static struct qcom_icc_node xm_sdc2; 21 static struct qcom_icc_node xm_sdc4; 22 static struct qcom_icc_node xm_ufs_card; 23 static struct qcom_icc_node xm_ufs_mem; 24 static struct qcom_icc_node xm_pcie_0; 25 static struct qcom_icc_node qhm_a2noc_cfg; 26 static struct qcom_icc_node qhm_qdss_bam; 27 static struct qcom_icc_node qhm_qup2; 28 static struct qcom_icc_node qnm_cnoc; 29 static struct qcom_icc_node qxm_crypto; 30 static struct qcom_icc_node qxm_ipa; 31 static struct qcom_icc_node xm_pcie3_1; 32 static struct qcom_icc_node xm_qdss_etr; 33 static struct qcom_icc_node xm_usb3_0; 34 static struct qcom_icc_node xm_usb3_1; 35 static struct qcom_icc_node qxm_camnoc_hf0_uncomp; 36 static struct qcom_icc_node qxm_camnoc_hf1_uncomp; 37 static struct qcom_icc_node qxm_camnoc_sf_uncomp; 38 static struct qcom_icc_node qhm_spdm; 39 static struct qcom_icc_node qhm_tic; 40 static struct qcom_icc_node qnm_snoc; 41 static struct qcom_icc_node xm_qdss_dap; 42 static struct qcom_icc_node qhm_cnoc; 43 static struct qcom_icc_node acm_l3; 44 static struct qcom_icc_node pm_gnoc_cfg; 45 static struct qcom_icc_node llcc_mc; 46 static struct qcom_icc_node acm_tcu; 47 static struct qcom_icc_node qhm_memnoc_cfg; 48 static struct qcom_icc_node qnm_apps; 49 static struct qcom_icc_node qnm_mnoc_hf; 50 static struct qcom_icc_node qnm_mnoc_sf; 51 static struct qcom_icc_node qnm_snoc_gc; 52 static struct qcom_icc_node qnm_snoc_sf; 53 static struct qcom_icc_node qxm_gpu; 54 static struct qcom_icc_node qhm_mnoc_cfg; 55 static struct qcom_icc_node qxm_camnoc_hf0; 56 static struct qcom_icc_node qxm_camnoc_hf1; 57 static struct qcom_icc_node qxm_camnoc_sf; 58 static struct qcom_icc_node qxm_mdp0; 59 static struct qcom_icc_node qxm_mdp1; 60 static struct qcom_icc_node qxm_rot; 61 static struct qcom_icc_node qxm_venus0; 62 static struct qcom_icc_node qxm_venus1; 63 static struct qcom_icc_node qxm_venus_arm9; 64 static struct qcom_icc_node qhm_snoc_cfg; 65 static struct qcom_icc_node qnm_aggre1_noc; 66 static struct qcom_icc_node qnm_aggre2_noc; 67 static struct qcom_icc_node qnm_gladiator_sodv; 68 static struct qcom_icc_node qnm_memnoc; 69 static struct qcom_icc_node qnm_pcie_anoc; 70 static struct qcom_icc_node qxm_pimem; 71 static struct qcom_icc_node xm_gic; 72 static struct qcom_icc_node qns_a1noc_snoc; 73 static struct qcom_icc_node srvc_aggre1_noc; 74 static struct qcom_icc_node qns_pcie_a1noc_snoc; 75 static struct qcom_icc_node qns_a2noc_snoc; 76 static struct qcom_icc_node qns_pcie_snoc; 77 static struct qcom_icc_node srvc_aggre2_noc; 78 static struct qcom_icc_node qns_camnoc_uncomp; 79 static struct qcom_icc_node qhs_a1_noc_cfg; 80 static struct qcom_icc_node qhs_a2_noc_cfg; 81 static struct qcom_icc_node qhs_aop; 82 static struct qcom_icc_node qhs_aoss; 83 static struct qcom_icc_node qhs_camera_cfg; 84 static struct qcom_icc_node qhs_clk_ctl; 85 static struct qcom_icc_node qhs_compute_dsp_cfg; 86 static struct qcom_icc_node qhs_cpr_cx; 87 static struct qcom_icc_node qhs_crypto0_cfg; 88 static struct qcom_icc_node qhs_dcc_cfg; 89 static struct qcom_icc_node qhs_ddrss_cfg; 90 static struct qcom_icc_node qhs_display_cfg; 91 static struct qcom_icc_node qhs_glm; 92 static struct qcom_icc_node qhs_gpuss_cfg; 93 static struct qcom_icc_node qhs_imem_cfg; 94 static struct qcom_icc_node qhs_ipa; 95 static struct qcom_icc_node qhs_mnoc_cfg; 96 static struct qcom_icc_node qhs_pcie0_cfg; 97 static struct qcom_icc_node qhs_pcie_gen3_cfg; 98 static struct qcom_icc_node qhs_pdm; 99 static struct qcom_icc_node qhs_phy_refgen_south; 100 static struct qcom_icc_node qhs_pimem_cfg; 101 static struct qcom_icc_node qhs_prng; 102 static struct qcom_icc_node qhs_qdss_cfg; 103 static struct qcom_icc_node qhs_qupv3_north; 104 static struct qcom_icc_node qhs_qupv3_south; 105 static struct qcom_icc_node qhs_sdc2; 106 static struct qcom_icc_node qhs_sdc4; 107 static struct qcom_icc_node qhs_snoc_cfg; 108 static struct qcom_icc_node qhs_spdm; 109 static struct qcom_icc_node qhs_spss_cfg; 110 static struct qcom_icc_node qhs_tcsr; 111 static struct qcom_icc_node qhs_tlmm_north; 112 static struct qcom_icc_node qhs_tlmm_south; 113 static struct qcom_icc_node qhs_tsif; 114 static struct qcom_icc_node qhs_ufs_card_cfg; 115 static struct qcom_icc_node qhs_ufs_mem_cfg; 116 static struct qcom_icc_node qhs_usb3_0; 117 static struct qcom_icc_node qhs_usb3_1; 118 static struct qcom_icc_node qhs_venus_cfg; 119 static struct qcom_icc_node qhs_vsense_ctrl_cfg; 120 static struct qcom_icc_node qns_cnoc_a2noc; 121 static struct qcom_icc_node srvc_cnoc; 122 static struct qcom_icc_node qhs_llcc; 123 static struct qcom_icc_node qhs_memnoc; 124 static struct qcom_icc_node qns_gladiator_sodv; 125 static struct qcom_icc_node qns_gnoc_memnoc; 126 static struct qcom_icc_node srvc_gnoc; 127 static struct qcom_icc_node ebi; 128 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; 129 static struct qcom_icc_node qns_apps_io; 130 static struct qcom_icc_node qns_llcc; 131 static struct qcom_icc_node qns_memnoc_snoc; 132 static struct qcom_icc_node srvc_memnoc; 133 static struct qcom_icc_node qns2_mem_noc; 134 static struct qcom_icc_node qns_mem_noc_hf; 135 static struct qcom_icc_node srvc_mnoc; 136 static struct qcom_icc_node qhs_apss; 137 static struct qcom_icc_node qns_cnoc; 138 static struct qcom_icc_node qns_memnoc_gc; 139 static struct qcom_icc_node qns_memnoc_sf; 140 static struct qcom_icc_node qxs_imem; 141 static struct qcom_icc_node qxs_pcie; 142 static struct qcom_icc_node qxs_pcie_gen3; 143 static struct qcom_icc_node qxs_pimem; 144 static struct qcom_icc_node srvc_snoc; 145 static struct qcom_icc_node xs_qdss_stm; 146 static struct qcom_icc_node xs_sys_tcu_cfg; 147 148 static struct qcom_icc_node qhm_a1noc_cfg = { 149 .name = "qhm_a1noc_cfg", 150 .channels = 1, 151 .buswidth = 4, 152 .num_links = 1, 153 .link_nodes = { &srvc_aggre1_noc }, 154 }; 155 156 static struct qcom_icc_node qhm_qup1 = { 157 .name = "qhm_qup1", 158 .channels = 1, 159 .buswidth = 4, 160 .num_links = 1, 161 .link_nodes = { &qns_a1noc_snoc }, 162 }; 163 164 static struct qcom_icc_node qhm_tsif = { 165 .name = "qhm_tsif", 166 .channels = 1, 167 .buswidth = 4, 168 .num_links = 1, 169 .link_nodes = { &qns_a1noc_snoc }, 170 }; 171 172 static struct qcom_icc_node xm_sdc2 = { 173 .name = "xm_sdc2", 174 .channels = 1, 175 .buswidth = 8, 176 .num_links = 1, 177 .link_nodes = { &qns_a1noc_snoc }, 178 }; 179 180 static struct qcom_icc_node xm_sdc4 = { 181 .name = "xm_sdc4", 182 .channels = 1, 183 .buswidth = 8, 184 .num_links = 1, 185 .link_nodes = { &qns_a1noc_snoc }, 186 }; 187 188 static struct qcom_icc_node xm_ufs_card = { 189 .name = "xm_ufs_card", 190 .channels = 1, 191 .buswidth = 8, 192 .num_links = 1, 193 .link_nodes = { &qns_a1noc_snoc }, 194 }; 195 196 static struct qcom_icc_node xm_ufs_mem = { 197 .name = "xm_ufs_mem", 198 .channels = 1, 199 .buswidth = 8, 200 .num_links = 1, 201 .link_nodes = { &qns_a1noc_snoc }, 202 }; 203 204 static struct qcom_icc_node xm_pcie_0 = { 205 .name = "xm_pcie_0", 206 .channels = 1, 207 .buswidth = 8, 208 .num_links = 1, 209 .link_nodes = { &qns_pcie_a1noc_snoc }, 210 }; 211 212 static struct qcom_icc_node qhm_a2noc_cfg = { 213 .name = "qhm_a2noc_cfg", 214 .channels = 1, 215 .buswidth = 4, 216 .num_links = 1, 217 .link_nodes = { &srvc_aggre2_noc }, 218 }; 219 220 static struct qcom_icc_node qhm_qdss_bam = { 221 .name = "qhm_qdss_bam", 222 .channels = 1, 223 .buswidth = 4, 224 .num_links = 1, 225 .link_nodes = { &qns_a2noc_snoc }, 226 }; 227 228 static struct qcom_icc_node qhm_qup2 = { 229 .name = "qhm_qup2", 230 .channels = 1, 231 .buswidth = 4, 232 .num_links = 1, 233 .link_nodes = { &qns_a2noc_snoc }, 234 }; 235 236 static struct qcom_icc_node qnm_cnoc = { 237 .name = "qnm_cnoc", 238 .channels = 1, 239 .buswidth = 8, 240 .num_links = 1, 241 .link_nodes = { &qns_a2noc_snoc }, 242 }; 243 244 static struct qcom_icc_node qxm_crypto = { 245 .name = "qxm_crypto", 246 .channels = 1, 247 .buswidth = 8, 248 .num_links = 1, 249 .link_nodes = { &qns_a2noc_snoc }, 250 }; 251 252 static struct qcom_icc_node qxm_ipa = { 253 .name = "qxm_ipa", 254 .channels = 1, 255 .buswidth = 8, 256 .num_links = 1, 257 .link_nodes = { &qns_a2noc_snoc }, 258 }; 259 260 static struct qcom_icc_node xm_pcie3_1 = { 261 .name = "xm_pcie3_1", 262 .channels = 1, 263 .buswidth = 8, 264 .num_links = 1, 265 .link_nodes = { &qns_pcie_snoc }, 266 }; 267 268 static struct qcom_icc_node xm_qdss_etr = { 269 .name = "xm_qdss_etr", 270 .channels = 1, 271 .buswidth = 8, 272 .num_links = 1, 273 .link_nodes = { &qns_a2noc_snoc }, 274 }; 275 276 static struct qcom_icc_node xm_usb3_0 = { 277 .name = "xm_usb3_0", 278 .channels = 1, 279 .buswidth = 8, 280 .num_links = 1, 281 .link_nodes = { &qns_a2noc_snoc }, 282 }; 283 284 static struct qcom_icc_node xm_usb3_1 = { 285 .name = "xm_usb3_1", 286 .channels = 1, 287 .buswidth = 8, 288 .num_links = 1, 289 .link_nodes = { &qns_a2noc_snoc }, 290 }; 291 292 static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { 293 .name = "qxm_camnoc_hf0_uncomp", 294 .channels = 1, 295 .buswidth = 32, 296 .num_links = 1, 297 .link_nodes = { &qns_camnoc_uncomp }, 298 }; 299 300 static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { 301 .name = "qxm_camnoc_hf1_uncomp", 302 .channels = 1, 303 .buswidth = 32, 304 .num_links = 1, 305 .link_nodes = { &qns_camnoc_uncomp }, 306 }; 307 308 static struct qcom_icc_node qxm_camnoc_sf_uncomp = { 309 .name = "qxm_camnoc_sf_uncomp", 310 .channels = 1, 311 .buswidth = 32, 312 .num_links = 1, 313 .link_nodes = { &qns_camnoc_uncomp }, 314 }; 315 316 static struct qcom_icc_node qhm_spdm = { 317 .name = "qhm_spdm", 318 .channels = 1, 319 .buswidth = 4, 320 .num_links = 1, 321 .link_nodes = { &qns_cnoc_a2noc }, 322 }; 323 324 static struct qcom_icc_node qhm_tic = { 325 .name = "qhm_tic", 326 .channels = 1, 327 .buswidth = 4, 328 .num_links = 43, 329 .link_nodes = { &qhs_a1_noc_cfg, 330 &qhs_a2_noc_cfg, 331 &qhs_aop, 332 &qhs_aoss, 333 &qhs_camera_cfg, 334 &qhs_clk_ctl, 335 &qhs_compute_dsp_cfg, 336 &qhs_cpr_cx, 337 &qhs_crypto0_cfg, 338 &qhs_dcc_cfg, 339 &qhs_ddrss_cfg, 340 &qhs_display_cfg, 341 &qhs_glm, 342 &qhs_gpuss_cfg, 343 &qhs_imem_cfg, 344 &qhs_ipa, 345 &qhs_mnoc_cfg, 346 &qhs_pcie0_cfg, 347 &qhs_pcie_gen3_cfg, 348 &qhs_pdm, 349 &qhs_phy_refgen_south, 350 &qhs_pimem_cfg, 351 &qhs_prng, 352 &qhs_qdss_cfg, 353 &qhs_qupv3_north, 354 &qhs_qupv3_south, 355 &qhs_sdc2, 356 &qhs_sdc4, 357 &qhs_snoc_cfg, 358 &qhs_spdm, 359 &qhs_spss_cfg, 360 &qhs_tcsr, 361 &qhs_tlmm_north, 362 &qhs_tlmm_south, 363 &qhs_tsif, 364 &qhs_ufs_card_cfg, 365 &qhs_ufs_mem_cfg, 366 &qhs_usb3_0, 367 &qhs_usb3_1, 368 &qhs_venus_cfg, 369 &qhs_vsense_ctrl_cfg, 370 &qns_cnoc_a2noc, 371 &srvc_cnoc }, 372 }; 373 374 static struct qcom_icc_node qnm_snoc = { 375 .name = "qnm_snoc", 376 .channels = 1, 377 .buswidth = 8, 378 .num_links = 42, 379 .link_nodes = { &qhs_a1_noc_cfg, 380 &qhs_a2_noc_cfg, 381 &qhs_aop, 382 &qhs_aoss, 383 &qhs_camera_cfg, 384 &qhs_clk_ctl, 385 &qhs_compute_dsp_cfg, 386 &qhs_cpr_cx, 387 &qhs_crypto0_cfg, 388 &qhs_dcc_cfg, 389 &qhs_ddrss_cfg, 390 &qhs_display_cfg, 391 &qhs_glm, 392 &qhs_gpuss_cfg, 393 &qhs_imem_cfg, 394 &qhs_ipa, 395 &qhs_mnoc_cfg, 396 &qhs_pcie0_cfg, 397 &qhs_pcie_gen3_cfg, 398 &qhs_pdm, 399 &qhs_phy_refgen_south, 400 &qhs_pimem_cfg, 401 &qhs_prng, 402 &qhs_qdss_cfg, 403 &qhs_qupv3_north, 404 &qhs_qupv3_south, 405 &qhs_sdc2, 406 &qhs_sdc4, 407 &qhs_snoc_cfg, 408 &qhs_spdm, 409 &qhs_spss_cfg, 410 &qhs_tcsr, 411 &qhs_tlmm_north, 412 &qhs_tlmm_south, 413 &qhs_tsif, 414 &qhs_ufs_card_cfg, 415 &qhs_ufs_mem_cfg, 416 &qhs_usb3_0, 417 &qhs_usb3_1, 418 &qhs_venus_cfg, 419 &qhs_vsense_ctrl_cfg, 420 &srvc_cnoc }, 421 }; 422 423 static struct qcom_icc_node xm_qdss_dap = { 424 .name = "xm_qdss_dap", 425 .channels = 1, 426 .buswidth = 8, 427 .num_links = 43, 428 .link_nodes = { &qhs_a1_noc_cfg, 429 &qhs_a2_noc_cfg, 430 &qhs_aop, 431 &qhs_aoss, 432 &qhs_camera_cfg, 433 &qhs_clk_ctl, 434 &qhs_compute_dsp_cfg, 435 &qhs_cpr_cx, 436 &qhs_crypto0_cfg, 437 &qhs_dcc_cfg, 438 &qhs_ddrss_cfg, 439 &qhs_display_cfg, 440 &qhs_glm, 441 &qhs_gpuss_cfg, 442 &qhs_imem_cfg, 443 &qhs_ipa, 444 &qhs_mnoc_cfg, 445 &qhs_pcie0_cfg, 446 &qhs_pcie_gen3_cfg, 447 &qhs_pdm, 448 &qhs_phy_refgen_south, 449 &qhs_pimem_cfg, 450 &qhs_prng, 451 &qhs_qdss_cfg, 452 &qhs_qupv3_north, 453 &qhs_qupv3_south, 454 &qhs_sdc2, 455 &qhs_sdc4, 456 &qhs_snoc_cfg, 457 &qhs_spdm, 458 &qhs_spss_cfg, 459 &qhs_tcsr, 460 &qhs_tlmm_north, 461 &qhs_tlmm_south, 462 &qhs_tsif, 463 &qhs_ufs_card_cfg, 464 &qhs_ufs_mem_cfg, 465 &qhs_usb3_0, 466 &qhs_usb3_1, 467 &qhs_venus_cfg, 468 &qhs_vsense_ctrl_cfg, 469 &qns_cnoc_a2noc, 470 &srvc_cnoc }, 471 }; 472 473 static struct qcom_icc_node qhm_cnoc = { 474 .name = "qhm_cnoc", 475 .channels = 1, 476 .buswidth = 4, 477 .num_links = 2, 478 .link_nodes = { &qhs_llcc, 479 &qhs_memnoc }, 480 }; 481 482 static struct qcom_icc_node acm_l3 = { 483 .name = "acm_l3", 484 .channels = 1, 485 .buswidth = 16, 486 .num_links = 3, 487 .link_nodes = { &qns_gladiator_sodv, 488 &qns_gnoc_memnoc, 489 &srvc_gnoc }, 490 }; 491 492 static struct qcom_icc_node pm_gnoc_cfg = { 493 .name = "pm_gnoc_cfg", 494 .channels = 1, 495 .buswidth = 4, 496 .num_links = 1, 497 .link_nodes = { &srvc_gnoc }, 498 }; 499 500 static struct qcom_icc_node llcc_mc = { 501 .name = "llcc_mc", 502 .channels = 4, 503 .buswidth = 4, 504 .num_links = 1, 505 .link_nodes = { &ebi }, 506 }; 507 508 static struct qcom_icc_node acm_tcu = { 509 .name = "acm_tcu", 510 .channels = 1, 511 .buswidth = 8, 512 .num_links = 3, 513 .link_nodes = { &qns_apps_io, 514 &qns_llcc, 515 &qns_memnoc_snoc }, 516 }; 517 518 static struct qcom_icc_node qhm_memnoc_cfg = { 519 .name = "qhm_memnoc_cfg", 520 .channels = 1, 521 .buswidth = 4, 522 .num_links = 2, 523 .link_nodes = { &qhs_mdsp_ms_mpu_cfg, 524 &srvc_memnoc }, 525 }; 526 527 static struct qcom_icc_node qnm_apps = { 528 .name = "qnm_apps", 529 .channels = 2, 530 .buswidth = 32, 531 .num_links = 1, 532 .link_nodes = { &qns_llcc }, 533 }; 534 535 static struct qcom_icc_node qnm_mnoc_hf = { 536 .name = "qnm_mnoc_hf", 537 .channels = 2, 538 .buswidth = 32, 539 .num_links = 2, 540 .link_nodes = { &qns_apps_io, 541 &qns_llcc }, 542 }; 543 544 static struct qcom_icc_node qnm_mnoc_sf = { 545 .name = "qnm_mnoc_sf", 546 .channels = 1, 547 .buswidth = 32, 548 .num_links = 3, 549 .link_nodes = { &qns_apps_io, 550 &qns_llcc, 551 &qns_memnoc_snoc }, 552 }; 553 554 static struct qcom_icc_node qnm_snoc_gc = { 555 .name = "qnm_snoc_gc", 556 .channels = 1, 557 .buswidth = 8, 558 .num_links = 1, 559 .link_nodes = { &qns_llcc }, 560 }; 561 562 static struct qcom_icc_node qnm_snoc_sf = { 563 .name = "qnm_snoc_sf", 564 .channels = 1, 565 .buswidth = 16, 566 .num_links = 2, 567 .link_nodes = { &qns_apps_io, 568 &qns_llcc }, 569 }; 570 571 static struct qcom_icc_node qxm_gpu = { 572 .name = "qxm_gpu", 573 .channels = 2, 574 .buswidth = 32, 575 .num_links = 3, 576 .link_nodes = { &qns_apps_io, 577 &qns_llcc, 578 &qns_memnoc_snoc }, 579 }; 580 581 static struct qcom_icc_node qhm_mnoc_cfg = { 582 .name = "qhm_mnoc_cfg", 583 .channels = 1, 584 .buswidth = 4, 585 .num_links = 1, 586 .link_nodes = { &srvc_mnoc }, 587 }; 588 589 static struct qcom_icc_node qxm_camnoc_hf0 = { 590 .name = "qxm_camnoc_hf0", 591 .channels = 1, 592 .buswidth = 32, 593 .num_links = 1, 594 .link_nodes = { &qns_mem_noc_hf }, 595 }; 596 597 static struct qcom_icc_node qxm_camnoc_hf1 = { 598 .name = "qxm_camnoc_hf1", 599 .channels = 1, 600 .buswidth = 32, 601 .num_links = 1, 602 .link_nodes = { &qns_mem_noc_hf }, 603 }; 604 605 static struct qcom_icc_node qxm_camnoc_sf = { 606 .name = "qxm_camnoc_sf", 607 .channels = 1, 608 .buswidth = 32, 609 .num_links = 1, 610 .link_nodes = { &qns2_mem_noc }, 611 }; 612 613 static struct qcom_icc_node qxm_mdp0 = { 614 .name = "qxm_mdp0", 615 .channels = 1, 616 .buswidth = 32, 617 .num_links = 1, 618 .link_nodes = { &qns_mem_noc_hf }, 619 }; 620 621 static struct qcom_icc_node qxm_mdp1 = { 622 .name = "qxm_mdp1", 623 .channels = 1, 624 .buswidth = 32, 625 .num_links = 1, 626 .link_nodes = { &qns_mem_noc_hf }, 627 }; 628 629 static struct qcom_icc_node qxm_rot = { 630 .name = "qxm_rot", 631 .channels = 1, 632 .buswidth = 32, 633 .num_links = 1, 634 .link_nodes = { &qns2_mem_noc }, 635 }; 636 637 static struct qcom_icc_node qxm_venus0 = { 638 .name = "qxm_venus0", 639 .channels = 1, 640 .buswidth = 32, 641 .num_links = 1, 642 .link_nodes = { &qns2_mem_noc }, 643 }; 644 645 static struct qcom_icc_node qxm_venus1 = { 646 .name = "qxm_venus1", 647 .channels = 1, 648 .buswidth = 32, 649 .num_links = 1, 650 .link_nodes = { &qns2_mem_noc }, 651 }; 652 653 static struct qcom_icc_node qxm_venus_arm9 = { 654 .name = "qxm_venus_arm9", 655 .channels = 1, 656 .buswidth = 8, 657 .num_links = 1, 658 .link_nodes = { &qns2_mem_noc }, 659 }; 660 661 static struct qcom_icc_node qhm_snoc_cfg = { 662 .name = "qhm_snoc_cfg", 663 .channels = 1, 664 .buswidth = 4, 665 .num_links = 1, 666 .link_nodes = { &srvc_snoc }, 667 }; 668 669 static struct qcom_icc_node qnm_aggre1_noc = { 670 .name = "qnm_aggre1_noc", 671 .channels = 1, 672 .buswidth = 16, 673 .num_links = 6, 674 .link_nodes = { &qhs_apss, 675 &qns_cnoc, 676 &qns_memnoc_sf, 677 &qxs_imem, 678 &qxs_pimem, 679 &xs_qdss_stm }, 680 }; 681 682 static struct qcom_icc_node qnm_aggre2_noc = { 683 .name = "qnm_aggre2_noc", 684 .channels = 1, 685 .buswidth = 16, 686 .num_links = 9, 687 .link_nodes = { &qhs_apss, 688 &qns_cnoc, 689 &qns_memnoc_sf, 690 &qxs_imem, 691 &qxs_pcie, 692 &qxs_pcie_gen3, 693 &qxs_pimem, 694 &xs_qdss_stm, 695 &xs_sys_tcu_cfg }, 696 }; 697 698 static struct qcom_icc_node qnm_gladiator_sodv = { 699 .name = "qnm_gladiator_sodv", 700 .channels = 1, 701 .buswidth = 8, 702 .num_links = 8, 703 .link_nodes = { &qhs_apss, 704 &qns_cnoc, 705 &qxs_imem, 706 &qxs_pcie, 707 &qxs_pcie_gen3, 708 &qxs_pimem, 709 &xs_qdss_stm, 710 &xs_sys_tcu_cfg }, 711 }; 712 713 static struct qcom_icc_node qnm_memnoc = { 714 .name = "qnm_memnoc", 715 .channels = 1, 716 .buswidth = 8, 717 .num_links = 5, 718 .link_nodes = { &qhs_apss, 719 &qns_cnoc, 720 &qxs_imem, 721 &qxs_pimem, 722 &xs_qdss_stm }, 723 }; 724 725 static struct qcom_icc_node qnm_pcie_anoc = { 726 .name = "qnm_pcie_anoc", 727 .channels = 1, 728 .buswidth = 16, 729 .num_links = 5, 730 .link_nodes = { &qhs_apss, 731 &qns_cnoc, 732 &qns_memnoc_sf, 733 &qxs_imem, 734 &xs_qdss_stm }, 735 }; 736 737 static struct qcom_icc_node qxm_pimem = { 738 .name = "qxm_pimem", 739 .channels = 1, 740 .buswidth = 8, 741 .num_links = 2, 742 .link_nodes = { &qns_memnoc_gc, 743 &qxs_imem }, 744 }; 745 746 static struct qcom_icc_node xm_gic = { 747 .name = "xm_gic", 748 .channels = 1, 749 .buswidth = 8, 750 .num_links = 2, 751 .link_nodes = { &qns_memnoc_gc, 752 &qxs_imem }, 753 }; 754 755 static struct qcom_icc_node qns_a1noc_snoc = { 756 .name = "qns_a1noc_snoc", 757 .channels = 1, 758 .buswidth = 16, 759 .num_links = 1, 760 .link_nodes = { &qnm_aggre1_noc }, 761 }; 762 763 static struct qcom_icc_node srvc_aggre1_noc = { 764 .name = "srvc_aggre1_noc", 765 .channels = 1, 766 .buswidth = 4, 767 }; 768 769 static struct qcom_icc_node qns_pcie_a1noc_snoc = { 770 .name = "qns_pcie_a1noc_snoc", 771 .channels = 1, 772 .buswidth = 16, 773 .num_links = 1, 774 .link_nodes = { &qnm_pcie_anoc }, 775 }; 776 777 static struct qcom_icc_node qns_a2noc_snoc = { 778 .name = "qns_a2noc_snoc", 779 .channels = 1, 780 .buswidth = 16, 781 .num_links = 1, 782 .link_nodes = { &qnm_aggre2_noc }, 783 }; 784 785 static struct qcom_icc_node qns_pcie_snoc = { 786 .name = "qns_pcie_snoc", 787 .channels = 1, 788 .buswidth = 16, 789 .num_links = 1, 790 .link_nodes = { &qnm_pcie_anoc }, 791 }; 792 793 static struct qcom_icc_node srvc_aggre2_noc = { 794 .name = "srvc_aggre2_noc", 795 .channels = 1, 796 .buswidth = 4, 797 }; 798 799 static struct qcom_icc_node qns_camnoc_uncomp = { 800 .name = "qns_camnoc_uncomp", 801 .channels = 1, 802 .buswidth = 32, 803 }; 804 805 static struct qcom_icc_node qhs_a1_noc_cfg = { 806 .name = "qhs_a1_noc_cfg", 807 .channels = 1, 808 .buswidth = 4, 809 .num_links = 1, 810 .link_nodes = { &qhm_a1noc_cfg }, 811 }; 812 813 static struct qcom_icc_node qhs_a2_noc_cfg = { 814 .name = "qhs_a2_noc_cfg", 815 .channels = 1, 816 .buswidth = 4, 817 .num_links = 1, 818 .link_nodes = { &qhm_a2noc_cfg }, 819 }; 820 821 static struct qcom_icc_node qhs_aop = { 822 .name = "qhs_aop", 823 .channels = 1, 824 .buswidth = 4, 825 }; 826 827 static struct qcom_icc_node qhs_aoss = { 828 .name = "qhs_aoss", 829 .channels = 1, 830 .buswidth = 4, 831 }; 832 833 static struct qcom_icc_node qhs_camera_cfg = { 834 .name = "qhs_camera_cfg", 835 .channels = 1, 836 .buswidth = 4, 837 }; 838 839 static struct qcom_icc_node qhs_clk_ctl = { 840 .name = "qhs_clk_ctl", 841 .channels = 1, 842 .buswidth = 4, 843 }; 844 845 static struct qcom_icc_node qhs_compute_dsp_cfg = { 846 .name = "qhs_compute_dsp_cfg", 847 .channels = 1, 848 .buswidth = 4, 849 }; 850 851 static struct qcom_icc_node qhs_cpr_cx = { 852 .name = "qhs_cpr_cx", 853 .channels = 1, 854 .buswidth = 4, 855 }; 856 857 static struct qcom_icc_node qhs_crypto0_cfg = { 858 .name = "qhs_crypto0_cfg", 859 .channels = 1, 860 .buswidth = 4, 861 }; 862 863 static struct qcom_icc_node qhs_dcc_cfg = { 864 .name = "qhs_dcc_cfg", 865 .channels = 1, 866 .buswidth = 4, 867 .num_links = 1, 868 .link_nodes = { &qhm_cnoc }, 869 }; 870 871 static struct qcom_icc_node qhs_ddrss_cfg = { 872 .name = "qhs_ddrss_cfg", 873 .channels = 1, 874 .buswidth = 4, 875 }; 876 877 static struct qcom_icc_node qhs_display_cfg = { 878 .name = "qhs_display_cfg", 879 .channels = 1, 880 .buswidth = 4, 881 }; 882 883 static struct qcom_icc_node qhs_glm = { 884 .name = "qhs_glm", 885 .channels = 1, 886 .buswidth = 4, 887 }; 888 889 static struct qcom_icc_node qhs_gpuss_cfg = { 890 .name = "qhs_gpuss_cfg", 891 .channels = 1, 892 .buswidth = 8, 893 }; 894 895 static struct qcom_icc_node qhs_imem_cfg = { 896 .name = "qhs_imem_cfg", 897 .channels = 1, 898 .buswidth = 4, 899 }; 900 901 static struct qcom_icc_node qhs_ipa = { 902 .name = "qhs_ipa", 903 .channels = 1, 904 .buswidth = 4, 905 }; 906 907 static struct qcom_icc_node qhs_mnoc_cfg = { 908 .name = "qhs_mnoc_cfg", 909 .channels = 1, 910 .buswidth = 4, 911 .num_links = 1, 912 .link_nodes = { &qhm_mnoc_cfg }, 913 }; 914 915 static struct qcom_icc_node qhs_pcie0_cfg = { 916 .name = "qhs_pcie0_cfg", 917 .channels = 1, 918 .buswidth = 4, 919 }; 920 921 static struct qcom_icc_node qhs_pcie_gen3_cfg = { 922 .name = "qhs_pcie_gen3_cfg", 923 .channels = 1, 924 .buswidth = 4, 925 }; 926 927 static struct qcom_icc_node qhs_pdm = { 928 .name = "qhs_pdm", 929 .channels = 1, 930 .buswidth = 4, 931 }; 932 933 static struct qcom_icc_node qhs_phy_refgen_south = { 934 .name = "qhs_phy_refgen_south", 935 .channels = 1, 936 .buswidth = 4, 937 }; 938 939 static struct qcom_icc_node qhs_pimem_cfg = { 940 .name = "qhs_pimem_cfg", 941 .channels = 1, 942 .buswidth = 4, 943 }; 944 945 static struct qcom_icc_node qhs_prng = { 946 .name = "qhs_prng", 947 .channels = 1, 948 .buswidth = 4, 949 }; 950 951 static struct qcom_icc_node qhs_qdss_cfg = { 952 .name = "qhs_qdss_cfg", 953 .channels = 1, 954 .buswidth = 4, 955 }; 956 957 static struct qcom_icc_node qhs_qupv3_north = { 958 .name = "qhs_qupv3_north", 959 .channels = 1, 960 .buswidth = 4, 961 }; 962 963 static struct qcom_icc_node qhs_qupv3_south = { 964 .name = "qhs_qupv3_south", 965 .channels = 1, 966 .buswidth = 4, 967 }; 968 969 static struct qcom_icc_node qhs_sdc2 = { 970 .name = "qhs_sdc2", 971 .channels = 1, 972 .buswidth = 4, 973 }; 974 975 static struct qcom_icc_node qhs_sdc4 = { 976 .name = "qhs_sdc4", 977 .channels = 1, 978 .buswidth = 4, 979 }; 980 981 static struct qcom_icc_node qhs_snoc_cfg = { 982 .name = "qhs_snoc_cfg", 983 .channels = 1, 984 .buswidth = 4, 985 .num_links = 1, 986 .link_nodes = { &qhm_snoc_cfg }, 987 }; 988 989 static struct qcom_icc_node qhs_spdm = { 990 .name = "qhs_spdm", 991 .channels = 1, 992 .buswidth = 4, 993 }; 994 995 static struct qcom_icc_node qhs_spss_cfg = { 996 .name = "qhs_spss_cfg", 997 .channels = 1, 998 .buswidth = 4, 999 }; 1000 1001 static struct qcom_icc_node qhs_tcsr = { 1002 .name = "qhs_tcsr", 1003 .channels = 1, 1004 .buswidth = 4, 1005 }; 1006 1007 static struct qcom_icc_node qhs_tlmm_north = { 1008 .name = "qhs_tlmm_north", 1009 .channels = 1, 1010 .buswidth = 4, 1011 }; 1012 1013 static struct qcom_icc_node qhs_tlmm_south = { 1014 .name = "qhs_tlmm_south", 1015 .channels = 1, 1016 .buswidth = 4, 1017 }; 1018 1019 static struct qcom_icc_node qhs_tsif = { 1020 .name = "qhs_tsif", 1021 .channels = 1, 1022 .buswidth = 4, 1023 }; 1024 1025 static struct qcom_icc_node qhs_ufs_card_cfg = { 1026 .name = "qhs_ufs_card_cfg", 1027 .channels = 1, 1028 .buswidth = 4, 1029 }; 1030 1031 static struct qcom_icc_node qhs_ufs_mem_cfg = { 1032 .name = "qhs_ufs_mem_cfg", 1033 .channels = 1, 1034 .buswidth = 4, 1035 }; 1036 1037 static struct qcom_icc_node qhs_usb3_0 = { 1038 .name = "qhs_usb3_0", 1039 .channels = 1, 1040 .buswidth = 4, 1041 }; 1042 1043 static struct qcom_icc_node qhs_usb3_1 = { 1044 .name = "qhs_usb3_1", 1045 .channels = 1, 1046 .buswidth = 4, 1047 }; 1048 1049 static struct qcom_icc_node qhs_venus_cfg = { 1050 .name = "qhs_venus_cfg", 1051 .channels = 1, 1052 .buswidth = 4, 1053 }; 1054 1055 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1056 .name = "qhs_vsense_ctrl_cfg", 1057 .channels = 1, 1058 .buswidth = 4, 1059 }; 1060 1061 static struct qcom_icc_node qns_cnoc_a2noc = { 1062 .name = "qns_cnoc_a2noc", 1063 .channels = 1, 1064 .buswidth = 8, 1065 .num_links = 1, 1066 .link_nodes = { &qnm_cnoc }, 1067 }; 1068 1069 static struct qcom_icc_node srvc_cnoc = { 1070 .name = "srvc_cnoc", 1071 .channels = 1, 1072 .buswidth = 4, 1073 }; 1074 1075 static struct qcom_icc_node qhs_llcc = { 1076 .name = "qhs_llcc", 1077 .channels = 1, 1078 .buswidth = 4, 1079 }; 1080 1081 static struct qcom_icc_node qhs_memnoc = { 1082 .name = "qhs_memnoc", 1083 .channels = 1, 1084 .buswidth = 4, 1085 .num_links = 1, 1086 .link_nodes = { &qhm_memnoc_cfg }, 1087 }; 1088 1089 static struct qcom_icc_node qns_gladiator_sodv = { 1090 .name = "qns_gladiator_sodv", 1091 .channels = 1, 1092 .buswidth = 8, 1093 .num_links = 1, 1094 .link_nodes = { &qnm_gladiator_sodv }, 1095 }; 1096 1097 static struct qcom_icc_node qns_gnoc_memnoc = { 1098 .name = "qns_gnoc_memnoc", 1099 .channels = 2, 1100 .buswidth = 32, 1101 .num_links = 1, 1102 .link_nodes = { &qnm_apps }, 1103 }; 1104 1105 static struct qcom_icc_node srvc_gnoc = { 1106 .name = "srvc_gnoc", 1107 .channels = 1, 1108 .buswidth = 4, 1109 }; 1110 1111 static struct qcom_icc_node ebi = { 1112 .name = "ebi", 1113 .channels = 4, 1114 .buswidth = 4, 1115 }; 1116 1117 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 1118 .name = "qhs_mdsp_ms_mpu_cfg", 1119 .channels = 1, 1120 .buswidth = 4, 1121 }; 1122 1123 static struct qcom_icc_node qns_apps_io = { 1124 .name = "qns_apps_io", 1125 .channels = 1, 1126 .buswidth = 32, 1127 }; 1128 1129 static struct qcom_icc_node qns_llcc = { 1130 .name = "qns_llcc", 1131 .channels = 4, 1132 .buswidth = 16, 1133 .num_links = 1, 1134 .link_nodes = { &llcc_mc }, 1135 }; 1136 1137 static struct qcom_icc_node qns_memnoc_snoc = { 1138 .name = "qns_memnoc_snoc", 1139 .channels = 1, 1140 .buswidth = 8, 1141 .num_links = 1, 1142 .link_nodes = { &qnm_memnoc }, 1143 }; 1144 1145 static struct qcom_icc_node srvc_memnoc = { 1146 .name = "srvc_memnoc", 1147 .channels = 1, 1148 .buswidth = 4, 1149 }; 1150 1151 static struct qcom_icc_node qns2_mem_noc = { 1152 .name = "qns2_mem_noc", 1153 .channels = 1, 1154 .buswidth = 32, 1155 .num_links = 1, 1156 .link_nodes = { &qnm_mnoc_sf }, 1157 }; 1158 1159 static struct qcom_icc_node qns_mem_noc_hf = { 1160 .name = "qns_mem_noc_hf", 1161 .channels = 2, 1162 .buswidth = 32, 1163 .num_links = 1, 1164 .link_nodes = { &qnm_mnoc_hf }, 1165 }; 1166 1167 static struct qcom_icc_node srvc_mnoc = { 1168 .name = "srvc_mnoc", 1169 .channels = 1, 1170 .buswidth = 4, 1171 }; 1172 1173 static struct qcom_icc_node qhs_apss = { 1174 .name = "qhs_apss", 1175 .channels = 1, 1176 .buswidth = 8, 1177 }; 1178 1179 static struct qcom_icc_node qns_cnoc = { 1180 .name = "qns_cnoc", 1181 .channels = 1, 1182 .buswidth = 8, 1183 .num_links = 1, 1184 .link_nodes = { &qnm_snoc }, 1185 }; 1186 1187 static struct qcom_icc_node qns_memnoc_gc = { 1188 .name = "qns_memnoc_gc", 1189 .channels = 1, 1190 .buswidth = 8, 1191 .num_links = 1, 1192 .link_nodes = { &qnm_snoc_gc }, 1193 }; 1194 1195 static struct qcom_icc_node qns_memnoc_sf = { 1196 .name = "qns_memnoc_sf", 1197 .channels = 1, 1198 .buswidth = 16, 1199 .num_links = 1, 1200 .link_nodes = { &qnm_snoc_sf }, 1201 }; 1202 1203 static struct qcom_icc_node qxs_imem = { 1204 .name = "qxs_imem", 1205 .channels = 1, 1206 .buswidth = 8, 1207 }; 1208 1209 static struct qcom_icc_node qxs_pcie = { 1210 .name = "qxs_pcie", 1211 .channels = 1, 1212 .buswidth = 8, 1213 }; 1214 1215 static struct qcom_icc_node qxs_pcie_gen3 = { 1216 .name = "qxs_pcie_gen3", 1217 .channels = 1, 1218 .buswidth = 8, 1219 }; 1220 1221 static struct qcom_icc_node qxs_pimem = { 1222 .name = "qxs_pimem", 1223 .channels = 1, 1224 .buswidth = 8, 1225 }; 1226 1227 static struct qcom_icc_node srvc_snoc = { 1228 .name = "srvc_snoc", 1229 .channels = 1, 1230 .buswidth = 4, 1231 }; 1232 1233 static struct qcom_icc_node xs_qdss_stm = { 1234 .name = "xs_qdss_stm", 1235 .channels = 1, 1236 .buswidth = 4, 1237 }; 1238 1239 static struct qcom_icc_node xs_sys_tcu_cfg = { 1240 .name = "xs_sys_tcu_cfg", 1241 .channels = 1, 1242 .buswidth = 8, 1243 }; 1244 1245 static struct qcom_icc_bcm bcm_acv = { 1246 .name = "ACV", 1247 .enable_mask = BIT(3), 1248 .keepalive = false, 1249 .num_nodes = 1, 1250 .nodes = { &ebi }, 1251 }; 1252 1253 static struct qcom_icc_bcm bcm_mc0 = { 1254 .name = "MC0", 1255 .keepalive = true, 1256 .num_nodes = 1, 1257 .nodes = { &ebi }, 1258 }; 1259 1260 static struct qcom_icc_bcm bcm_sh0 = { 1261 .name = "SH0", 1262 .keepalive = true, 1263 .num_nodes = 1, 1264 .nodes = { &qns_llcc }, 1265 }; 1266 1267 static struct qcom_icc_bcm bcm_mm0 = { 1268 .name = "MM0", 1269 .keepalive = false, 1270 .num_nodes = 1, 1271 .nodes = { &qns_mem_noc_hf }, 1272 }; 1273 1274 static struct qcom_icc_bcm bcm_sh1 = { 1275 .name = "SH1", 1276 .keepalive = false, 1277 .num_nodes = 1, 1278 .nodes = { &qns_apps_io }, 1279 }; 1280 1281 static struct qcom_icc_bcm bcm_mm1 = { 1282 .name = "MM1", 1283 .keepalive = true, 1284 .num_nodes = 7, 1285 .nodes = { &qxm_camnoc_hf0_uncomp, 1286 &qxm_camnoc_hf1_uncomp, 1287 &qxm_camnoc_sf_uncomp, 1288 &qxm_camnoc_hf0, 1289 &qxm_camnoc_hf1, 1290 &qxm_mdp0, 1291 &qxm_mdp1 1292 }, 1293 }; 1294 1295 static struct qcom_icc_bcm bcm_sh2 = { 1296 .name = "SH2", 1297 .keepalive = false, 1298 .num_nodes = 1, 1299 .nodes = { &qns_memnoc_snoc }, 1300 }; 1301 1302 static struct qcom_icc_bcm bcm_mm2 = { 1303 .name = "MM2", 1304 .keepalive = false, 1305 .num_nodes = 1, 1306 .nodes = { &qns2_mem_noc }, 1307 }; 1308 1309 static struct qcom_icc_bcm bcm_sh3 = { 1310 .name = "SH3", 1311 .keepalive = false, 1312 .num_nodes = 1, 1313 .nodes = { &acm_tcu }, 1314 }; 1315 1316 static struct qcom_icc_bcm bcm_mm3 = { 1317 .name = "MM3", 1318 .keepalive = false, 1319 .num_nodes = 5, 1320 .nodes = { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 }, 1321 }; 1322 1323 static struct qcom_icc_bcm bcm_sh5 = { 1324 .name = "SH5", 1325 .keepalive = false, 1326 .num_nodes = 1, 1327 .nodes = { &qnm_apps }, 1328 }; 1329 1330 static struct qcom_icc_bcm bcm_sn0 = { 1331 .name = "SN0", 1332 .keepalive = true, 1333 .num_nodes = 1, 1334 .nodes = { &qns_memnoc_sf }, 1335 }; 1336 1337 static struct qcom_icc_bcm bcm_ce0 = { 1338 .name = "CE0", 1339 .keepalive = false, 1340 .num_nodes = 1, 1341 .nodes = { &qxm_crypto }, 1342 }; 1343 1344 static struct qcom_icc_bcm bcm_cn0 = { 1345 .name = "CN0", 1346 .keepalive = false, 1347 .num_nodes = 47, 1348 .nodes = { &qhm_spdm, 1349 &qhm_tic, 1350 &qnm_snoc, 1351 &xm_qdss_dap, 1352 &qhs_a1_noc_cfg, 1353 &qhs_a2_noc_cfg, 1354 &qhs_aop, 1355 &qhs_aoss, 1356 &qhs_camera_cfg, 1357 &qhs_clk_ctl, 1358 &qhs_compute_dsp_cfg, 1359 &qhs_cpr_cx, 1360 &qhs_crypto0_cfg, 1361 &qhs_dcc_cfg, 1362 &qhs_ddrss_cfg, 1363 &qhs_display_cfg, 1364 &qhs_glm, 1365 &qhs_gpuss_cfg, 1366 &qhs_imem_cfg, 1367 &qhs_ipa, 1368 &qhs_mnoc_cfg, 1369 &qhs_pcie0_cfg, 1370 &qhs_pcie_gen3_cfg, 1371 &qhs_pdm, 1372 &qhs_phy_refgen_south, 1373 &qhs_pimem_cfg, 1374 &qhs_prng, 1375 &qhs_qdss_cfg, 1376 &qhs_qupv3_north, 1377 &qhs_qupv3_south, 1378 &qhs_sdc2, 1379 &qhs_sdc4, 1380 &qhs_snoc_cfg, 1381 &qhs_spdm, 1382 &qhs_spss_cfg, 1383 &qhs_tcsr, 1384 &qhs_tlmm_north, 1385 &qhs_tlmm_south, 1386 &qhs_tsif, 1387 &qhs_ufs_card_cfg, 1388 &qhs_ufs_mem_cfg, 1389 &qhs_usb3_0, 1390 &qhs_usb3_1, 1391 &qhs_venus_cfg, 1392 &qhs_vsense_ctrl_cfg, 1393 &qns_cnoc_a2noc, 1394 &srvc_cnoc 1395 }, 1396 }; 1397 1398 static struct qcom_icc_bcm bcm_qup0 = { 1399 .name = "QUP0", 1400 .keepalive = false, 1401 .num_nodes = 2, 1402 .nodes = { &qhm_qup1, &qhm_qup2 }, 1403 }; 1404 1405 static struct qcom_icc_bcm bcm_sn1 = { 1406 .name = "SN1", 1407 .keepalive = false, 1408 .num_nodes = 1, 1409 .nodes = { &qxs_imem }, 1410 }; 1411 1412 static struct qcom_icc_bcm bcm_sn2 = { 1413 .name = "SN2", 1414 .keepalive = false, 1415 .num_nodes = 1, 1416 .nodes = { &qns_memnoc_gc }, 1417 }; 1418 1419 static struct qcom_icc_bcm bcm_sn3 = { 1420 .name = "SN3", 1421 .keepalive = false, 1422 .num_nodes = 1, 1423 .nodes = { &qns_cnoc }, 1424 }; 1425 1426 static struct qcom_icc_bcm bcm_sn4 = { 1427 .name = "SN4", 1428 .keepalive = false, 1429 .num_nodes = 1, 1430 .nodes = { &qxm_pimem }, 1431 }; 1432 1433 static struct qcom_icc_bcm bcm_sn5 = { 1434 .name = "SN5", 1435 .keepalive = false, 1436 .num_nodes = 1, 1437 .nodes = { &xs_qdss_stm }, 1438 }; 1439 1440 static struct qcom_icc_bcm bcm_sn6 = { 1441 .name = "SN6", 1442 .keepalive = false, 1443 .num_nodes = 3, 1444 .nodes = { &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg }, 1445 }; 1446 1447 static struct qcom_icc_bcm bcm_sn7 = { 1448 .name = "SN7", 1449 .keepalive = false, 1450 .num_nodes = 1, 1451 .nodes = { &qxs_pcie }, 1452 }; 1453 1454 static struct qcom_icc_bcm bcm_sn8 = { 1455 .name = "SN8", 1456 .keepalive = false, 1457 .num_nodes = 1, 1458 .nodes = { &qxs_pcie_gen3 }, 1459 }; 1460 1461 static struct qcom_icc_bcm bcm_sn9 = { 1462 .name = "SN9", 1463 .keepalive = false, 1464 .num_nodes = 2, 1465 .nodes = { &srvc_aggre1_noc, &qnm_aggre1_noc }, 1466 }; 1467 1468 static struct qcom_icc_bcm bcm_sn11 = { 1469 .name = "SN11", 1470 .keepalive = false, 1471 .num_nodes = 2, 1472 .nodes = { &srvc_aggre2_noc, &qnm_aggre2_noc }, 1473 }; 1474 1475 static struct qcom_icc_bcm bcm_sn12 = { 1476 .name = "SN12", 1477 .keepalive = false, 1478 .num_nodes = 2, 1479 .nodes = { &qnm_gladiator_sodv, &xm_gic }, 1480 }; 1481 1482 static struct qcom_icc_bcm bcm_sn14 = { 1483 .name = "SN14", 1484 .keepalive = false, 1485 .num_nodes = 1, 1486 .nodes = { &qnm_pcie_anoc }, 1487 }; 1488 1489 static struct qcom_icc_bcm bcm_sn15 = { 1490 .name = "SN15", 1491 .keepalive = false, 1492 .num_nodes = 1, 1493 .nodes = { &qnm_memnoc }, 1494 }; 1495 1496 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1497 &bcm_sn9, 1498 &bcm_qup0, 1499 }; 1500 1501 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1502 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, 1503 [MASTER_TSIF] = &qhm_tsif, 1504 [MASTER_SDCC_2] = &xm_sdc2, 1505 [MASTER_SDCC_4] = &xm_sdc4, 1506 [MASTER_UFS_CARD] = &xm_ufs_card, 1507 [MASTER_UFS_MEM] = &xm_ufs_mem, 1508 [MASTER_PCIE_0] = &xm_pcie_0, 1509 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1510 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1511 [SLAVE_ANOC_PCIE_A1NOC_SNOC] = &qns_pcie_a1noc_snoc, 1512 [MASTER_QUP_1] = &qhm_qup1, 1513 }; 1514 1515 static const struct qcom_icc_desc sdm845_aggre1_noc = { 1516 .nodes = aggre1_noc_nodes, 1517 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1518 .bcms = aggre1_noc_bcms, 1519 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1520 }; 1521 1522 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1523 &bcm_ce0, 1524 &bcm_sn11, 1525 &bcm_qup0, 1526 }; 1527 1528 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1529 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, 1530 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1531 [MASTER_CNOC_A2NOC] = &qnm_cnoc, 1532 [MASTER_CRYPTO] = &qxm_crypto, 1533 [MASTER_IPA] = &qxm_ipa, 1534 [MASTER_PCIE_1] = &xm_pcie3_1, 1535 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1536 [MASTER_USB3_0] = &xm_usb3_0, 1537 [MASTER_USB3_1] = &xm_usb3_1, 1538 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1539 [SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc, 1540 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1541 [MASTER_QUP_2] = &qhm_qup2, 1542 }; 1543 1544 static const struct qcom_icc_desc sdm845_aggre2_noc = { 1545 .nodes = aggre2_noc_nodes, 1546 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1547 .bcms = aggre2_noc_bcms, 1548 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1549 }; 1550 1551 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1552 &bcm_cn0, 1553 }; 1554 1555 static struct qcom_icc_node * const config_noc_nodes[] = { 1556 [MASTER_SPDM] = &qhm_spdm, 1557 [MASTER_TIC] = &qhm_tic, 1558 [MASTER_SNOC_CNOC] = &qnm_snoc, 1559 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1560 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, 1561 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, 1562 [SLAVE_AOP] = &qhs_aop, 1563 [SLAVE_AOSS] = &qhs_aoss, 1564 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1565 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1566 [SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg, 1567 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1568 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1569 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 1570 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 1571 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1572 [SLAVE_GLM] = &qhs_glm, 1573 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1574 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1575 [SLAVE_IPA_CFG] = &qhs_ipa, 1576 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, 1577 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1578 [SLAVE_PCIE_1_CFG] = &qhs_pcie_gen3_cfg, 1579 [SLAVE_PDM] = &qhs_pdm, 1580 [SLAVE_SOUTH_PHY_CFG] = &qhs_phy_refgen_south, 1581 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1582 [SLAVE_PRNG] = &qhs_prng, 1583 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1584 [SLAVE_BLSP_2] = &qhs_qupv3_north, 1585 [SLAVE_BLSP_1] = &qhs_qupv3_south, 1586 [SLAVE_SDCC_2] = &qhs_sdc2, 1587 [SLAVE_SDCC_4] = &qhs_sdc4, 1588 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1589 [SLAVE_SPDM_WRAPPER] = &qhs_spdm, 1590 [SLAVE_SPSS_CFG] = &qhs_spss_cfg, 1591 [SLAVE_TCSR] = &qhs_tcsr, 1592 [SLAVE_TLMM_NORTH] = &qhs_tlmm_north, 1593 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south, 1594 [SLAVE_TSIF] = &qhs_tsif, 1595 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, 1596 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1597 [SLAVE_USB3_0] = &qhs_usb3_0, 1598 [SLAVE_USB3_1] = &qhs_usb3_1, 1599 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1600 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1601 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, 1602 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1603 }; 1604 1605 static const struct qcom_icc_desc sdm845_config_noc = { 1606 .nodes = config_noc_nodes, 1607 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1608 .bcms = config_noc_bcms, 1609 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1610 }; 1611 1612 static struct qcom_icc_bcm * const dc_noc_bcms[] = { 1613 }; 1614 1615 static struct qcom_icc_node * const dc_noc_nodes[] = { 1616 [MASTER_CNOC_DC_NOC] = &qhm_cnoc, 1617 [SLAVE_LLCC_CFG] = &qhs_llcc, 1618 [SLAVE_MEM_NOC_CFG] = &qhs_memnoc, 1619 }; 1620 1621 static const struct qcom_icc_desc sdm845_dc_noc = { 1622 .nodes = dc_noc_nodes, 1623 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1624 .bcms = dc_noc_bcms, 1625 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 1626 }; 1627 1628 static struct qcom_icc_bcm * const gladiator_noc_bcms[] = { 1629 }; 1630 1631 static struct qcom_icc_node * const gladiator_noc_nodes[] = { 1632 [MASTER_APPSS_PROC] = &acm_l3, 1633 [MASTER_GNOC_CFG] = &pm_gnoc_cfg, 1634 [SLAVE_GNOC_SNOC] = &qns_gladiator_sodv, 1635 [SLAVE_GNOC_MEM_NOC] = &qns_gnoc_memnoc, 1636 [SLAVE_SERVICE_GNOC] = &srvc_gnoc, 1637 }; 1638 1639 static const struct qcom_icc_desc sdm845_gladiator_noc = { 1640 .nodes = gladiator_noc_nodes, 1641 .num_nodes = ARRAY_SIZE(gladiator_noc_nodes), 1642 .bcms = gladiator_noc_bcms, 1643 .num_bcms = ARRAY_SIZE(gladiator_noc_bcms), 1644 }; 1645 1646 static struct qcom_icc_bcm * const mem_noc_bcms[] = { 1647 &bcm_mc0, 1648 &bcm_acv, 1649 &bcm_sh0, 1650 &bcm_sh1, 1651 &bcm_sh2, 1652 &bcm_sh3, 1653 &bcm_sh5, 1654 }; 1655 1656 static struct qcom_icc_node * const mem_noc_nodes[] = { 1657 [MASTER_TCU_0] = &acm_tcu, 1658 [MASTER_MEM_NOC_CFG] = &qhm_memnoc_cfg, 1659 [MASTER_GNOC_MEM_NOC] = &qnm_apps, 1660 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1661 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1662 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1663 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1664 [MASTER_GFX3D] = &qxm_gpu, 1665 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1666 [SLAVE_MEM_NOC_GNOC] = &qns_apps_io, 1667 [SLAVE_LLCC] = &qns_llcc, 1668 [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc, 1669 [SLAVE_SERVICE_MEM_NOC] = &srvc_memnoc, 1670 [MASTER_LLCC] = &llcc_mc, 1671 [SLAVE_EBI1] = &ebi, 1672 }; 1673 1674 static const struct qcom_icc_desc sdm845_mem_noc = { 1675 .nodes = mem_noc_nodes, 1676 .num_nodes = ARRAY_SIZE(mem_noc_nodes), 1677 .bcms = mem_noc_bcms, 1678 .num_bcms = ARRAY_SIZE(mem_noc_bcms), 1679 }; 1680 1681 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1682 &bcm_mm0, 1683 &bcm_mm1, 1684 &bcm_mm2, 1685 &bcm_mm3, 1686 }; 1687 1688 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1689 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, 1690 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, 1691 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, 1692 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 1693 [MASTER_MDP0] = &qxm_mdp0, 1694 [MASTER_MDP1] = &qxm_mdp1, 1695 [MASTER_ROTATOR] = &qxm_rot, 1696 [MASTER_VIDEO_P0] = &qxm_venus0, 1697 [MASTER_VIDEO_P1] = &qxm_venus1, 1698 [MASTER_VIDEO_PROC] = &qxm_venus_arm9, 1699 [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc, 1700 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1701 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1702 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, 1703 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp, 1704 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, 1705 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, 1706 }; 1707 1708 static const struct qcom_icc_desc sdm845_mmss_noc = { 1709 .nodes = mmss_noc_nodes, 1710 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1711 .bcms = mmss_noc_bcms, 1712 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1713 }; 1714 1715 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1716 &bcm_sn0, 1717 &bcm_sn1, 1718 &bcm_sn2, 1719 &bcm_sn3, 1720 &bcm_sn4, 1721 &bcm_sn5, 1722 &bcm_sn6, 1723 &bcm_sn7, 1724 &bcm_sn8, 1725 &bcm_sn9, 1726 &bcm_sn11, 1727 &bcm_sn12, 1728 &bcm_sn14, 1729 &bcm_sn15, 1730 }; 1731 1732 static struct qcom_icc_node * const system_noc_nodes[] = { 1733 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1734 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1735 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1736 [MASTER_GNOC_SNOC] = &qnm_gladiator_sodv, 1737 [MASTER_MEM_NOC_SNOC] = &qnm_memnoc, 1738 [MASTER_ANOC_PCIE_SNOC] = &qnm_pcie_anoc, 1739 [MASTER_PIMEM] = &qxm_pimem, 1740 [MASTER_GIC] = &xm_gic, 1741 [SLAVE_APPSS] = &qhs_apss, 1742 [SLAVE_SNOC_CNOC] = &qns_cnoc, 1743 [SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc, 1744 [SLAVE_SNOC_MEM_NOC_SF] = &qns_memnoc_sf, 1745 [SLAVE_IMEM] = &qxs_imem, 1746 [SLAVE_PCIE_0] = &qxs_pcie, 1747 [SLAVE_PCIE_1] = &qxs_pcie_gen3, 1748 [SLAVE_PIMEM] = &qxs_pimem, 1749 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1750 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1751 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1752 }; 1753 1754 static const struct qcom_icc_desc sdm845_system_noc = { 1755 .nodes = system_noc_nodes, 1756 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1757 .bcms = system_noc_bcms, 1758 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1759 }; 1760 1761 static const struct of_device_id qnoc_of_match[] = { 1762 { .compatible = "qcom,sdm845-aggre1-noc", 1763 .data = &sdm845_aggre1_noc}, 1764 { .compatible = "qcom,sdm845-aggre2-noc", 1765 .data = &sdm845_aggre2_noc}, 1766 { .compatible = "qcom,sdm845-config-noc", 1767 .data = &sdm845_config_noc}, 1768 { .compatible = "qcom,sdm845-dc-noc", 1769 .data = &sdm845_dc_noc}, 1770 { .compatible = "qcom,sdm845-gladiator-noc", 1771 .data = &sdm845_gladiator_noc}, 1772 { .compatible = "qcom,sdm845-mem-noc", 1773 .data = &sdm845_mem_noc}, 1774 { .compatible = "qcom,sdm845-mmss-noc", 1775 .data = &sdm845_mmss_noc}, 1776 { .compatible = "qcom,sdm845-system-noc", 1777 .data = &sdm845_system_noc}, 1778 { } 1779 }; 1780 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1781 1782 static struct platform_driver qnoc_driver = { 1783 .probe = qcom_icc_rpmh_probe, 1784 .remove = qcom_icc_rpmh_remove, 1785 .driver = { 1786 .name = "qnoc-sdm845", 1787 .of_match_table = qnoc_of_match, 1788 .sync_state = icc_sync_state, 1789 }, 1790 }; 1791 module_platform_driver(qnoc_driver); 1792 1793 MODULE_AUTHOR("David Dai <daidavid1@codeaurora.org>"); 1794 MODULE_DESCRIPTION("Qualcomm sdm845 NoC driver"); 1795 MODULE_LICENSE("GPL v2"); 1796