1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Renesas RZ/N1 Real Time Clock interface for Linux 4 * 5 * Copyright: 6 * - 2014 Renesas Electronics Europe Limited 7 * - 2022 Schneider Electric 8 * 9 * Authors: 10 * - Michel Pollet <buserror@gmail.com> 11 * - Miquel Raynal <miquel.raynal@bootlin.com> 12 */ 13 14 #include <linux/bcd.h> 15 #include <linux/clk.h> 16 #include <linux/init.h> 17 #include <linux/iopoll.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/rtc.h> 22 #include <linux/spinlock.h> 23 24 #define RZN1_RTC_CTL0 0x00 25 #define RZN1_RTC_CTL0_SLSB_SCMP BIT(4) 26 #define RZN1_RTC_CTL0_AMPM BIT(5) 27 #define RZN1_RTC_CTL0_CEST BIT(6) 28 #define RZN1_RTC_CTL0_CE BIT(7) 29 30 #define RZN1_RTC_CTL1 0x04 31 #define RZN1_RTC_CTL1_1SE BIT(3) 32 #define RZN1_RTC_CTL1_ALME BIT(4) 33 34 #define RZN1_RTC_CTL2 0x08 35 #define RZN1_RTC_CTL2_WAIT BIT(0) 36 #define RZN1_RTC_CTL2_WST BIT(1) 37 #define RZN1_RTC_CTL2_WUST BIT(5) 38 #define RZN1_RTC_CTL2_STOPPED (RZN1_RTC_CTL2_WAIT | RZN1_RTC_CTL2_WST) 39 40 #define RZN1_RTC_TIME 0x30 41 #define RZN1_RTC_TIME_MIN_SHIFT 8 42 #define RZN1_RTC_TIME_HOUR_SHIFT 16 43 #define RZN1_RTC_CAL 0x34 44 #define RZN1_RTC_CAL_DAY_SHIFT 8 45 #define RZN1_RTC_CAL_MON_SHIFT 16 46 #define RZN1_RTC_CAL_YEAR_SHIFT 24 47 48 #define RZN1_RTC_SUBU 0x38 49 #define RZN1_RTC_SUBU_DEV BIT(7) 50 #define RZN1_RTC_SUBU_DECR BIT(6) 51 52 #define RZN1_RTC_SCMP 0x3c 53 54 #define RZN1_RTC_ALM 0x40 55 #define RZN1_RTC_ALH 0x44 56 #define RZN1_RTC_ALW 0x48 57 58 #define RZN1_RTC_SECC 0x4c 59 #define RZN1_RTC_TIMEC 0x68 60 #define RZN1_RTC_CALC 0x6c 61 62 struct rzn1_rtc { 63 struct rtc_device *rtcdev; 64 void __iomem *base; 65 /* 66 * Protects access to RZN1_RTC_CTL1 reg. rtc_lock with threaded_irqs 67 * would introduce race conditions when switching interrupts because 68 * of potential sleeps 69 */ 70 spinlock_t ctl1_access_lock; 71 struct rtc_time tm_alarm; 72 }; 73 74 static void rzn1_rtc_get_time_snapshot(struct rzn1_rtc *rtc, struct rtc_time *tm) 75 { 76 u32 val; 77 78 val = readl(rtc->base + RZN1_RTC_TIMEC); 79 tm->tm_sec = bcd2bin(val); 80 tm->tm_min = bcd2bin(val >> RZN1_RTC_TIME_MIN_SHIFT); 81 tm->tm_hour = bcd2bin(val >> RZN1_RTC_TIME_HOUR_SHIFT); 82 83 val = readl(rtc->base + RZN1_RTC_CALC); 84 tm->tm_wday = val & 0x0f; 85 tm->tm_mday = bcd2bin(val >> RZN1_RTC_CAL_DAY_SHIFT); 86 tm->tm_mon = bcd2bin(val >> RZN1_RTC_CAL_MON_SHIFT) - 1; 87 tm->tm_year = bcd2bin(val >> RZN1_RTC_CAL_YEAR_SHIFT) + 100; 88 } 89 90 static int rzn1_rtc_read_time(struct device *dev, struct rtc_time *tm) 91 { 92 struct rzn1_rtc *rtc = dev_get_drvdata(dev); 93 u32 val, secs; 94 95 /* 96 * The RTC was not started or is stopped and thus does not carry the 97 * proper time/date. 98 */ 99 val = readl(rtc->base + RZN1_RTC_CTL2); 100 if (val & RZN1_RTC_CTL2_STOPPED) 101 return -EINVAL; 102 103 rzn1_rtc_get_time_snapshot(rtc, tm); 104 secs = readl(rtc->base + RZN1_RTC_SECC); 105 if (tm->tm_sec != bcd2bin(secs)) 106 rzn1_rtc_get_time_snapshot(rtc, tm); 107 108 return 0; 109 } 110 111 static int rzn1_rtc_set_time(struct device *dev, struct rtc_time *tm) 112 { 113 struct rzn1_rtc *rtc = dev_get_drvdata(dev); 114 u32 val; 115 int ret; 116 117 val = readl(rtc->base + RZN1_RTC_CTL2); 118 if (!(val & RZN1_RTC_CTL2_STOPPED)) { 119 /* Hold the counter if it was counting up */ 120 writel(RZN1_RTC_CTL2_WAIT, rtc->base + RZN1_RTC_CTL2); 121 122 /* Wait for the counter to stop: two 32k clock cycles */ 123 usleep_range(61, 100); 124 ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, val, 125 val & RZN1_RTC_CTL2_WST, 0, 100); 126 if (ret) 127 return ret; 128 } 129 130 val = bin2bcd(tm->tm_sec); 131 val |= bin2bcd(tm->tm_min) << RZN1_RTC_TIME_MIN_SHIFT; 132 val |= bin2bcd(tm->tm_hour) << RZN1_RTC_TIME_HOUR_SHIFT; 133 writel(val, rtc->base + RZN1_RTC_TIME); 134 135 val = tm->tm_wday; 136 val |= bin2bcd(tm->tm_mday) << RZN1_RTC_CAL_DAY_SHIFT; 137 val |= bin2bcd(tm->tm_mon + 1) << RZN1_RTC_CAL_MON_SHIFT; 138 val |= bin2bcd(tm->tm_year - 100) << RZN1_RTC_CAL_YEAR_SHIFT; 139 writel(val, rtc->base + RZN1_RTC_CAL); 140 141 writel(0, rtc->base + RZN1_RTC_CTL2); 142 143 return 0; 144 } 145 146 static irqreturn_t rzn1_rtc_alarm_irq(int irq, void *dev_id) 147 { 148 struct rzn1_rtc *rtc = dev_id; 149 u32 ctl1, set_irq_bits = 0; 150 151 if (rtc->tm_alarm.tm_sec == 0) 152 rtc_update_irq(rtc->rtcdev, 1, RTC_AF | RTC_IRQF); 153 else 154 /* Switch to 1s interrupts */ 155 set_irq_bits = RZN1_RTC_CTL1_1SE; 156 157 guard(spinlock)(&rtc->ctl1_access_lock); 158 159 ctl1 = readl(rtc->base + RZN1_RTC_CTL1); 160 ctl1 &= ~RZN1_RTC_CTL1_ALME; 161 ctl1 |= set_irq_bits; 162 writel(ctl1, rtc->base + RZN1_RTC_CTL1); 163 164 return IRQ_HANDLED; 165 } 166 167 static irqreturn_t rzn1_rtc_1s_irq(int irq, void *dev_id) 168 { 169 struct rzn1_rtc *rtc = dev_id; 170 u32 ctl1; 171 172 if (readl(rtc->base + RZN1_RTC_SECC) == bin2bcd(rtc->tm_alarm.tm_sec)) { 173 guard(spinlock)(&rtc->ctl1_access_lock); 174 175 ctl1 = readl(rtc->base + RZN1_RTC_CTL1); 176 ctl1 &= ~RZN1_RTC_CTL1_1SE; 177 writel(ctl1, rtc->base + RZN1_RTC_CTL1); 178 179 rtc_update_irq(rtc->rtcdev, 1, RTC_AF | RTC_IRQF); 180 } 181 182 return IRQ_HANDLED; 183 } 184 185 static int rzn1_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) 186 { 187 struct rzn1_rtc *rtc = dev_get_drvdata(dev); 188 struct rtc_time *tm = &rtc->tm_alarm, tm_now; 189 u32 ctl1; 190 int ret; 191 192 guard(spinlock_irqsave)(&rtc->ctl1_access_lock); 193 194 ctl1 = readl(rtc->base + RZN1_RTC_CTL1); 195 196 if (enable) { 197 /* 198 * Use alarm interrupt if alarm time is at least a minute away 199 * or less than a minute but in the next minute. Otherwise use 200 * 1 second interrupt to wait for the proper second 201 */ 202 do { 203 ctl1 &= ~(RZN1_RTC_CTL1_ALME | RZN1_RTC_CTL1_1SE); 204 205 ret = rzn1_rtc_read_time(dev, &tm_now); 206 if (ret) 207 return ret; 208 209 if (rtc_tm_sub(tm, &tm_now) > 59 || tm->tm_min != tm_now.tm_min) 210 ctl1 |= RZN1_RTC_CTL1_ALME; 211 else 212 ctl1 |= RZN1_RTC_CTL1_1SE; 213 214 writel(ctl1, rtc->base + RZN1_RTC_CTL1); 215 } while (readl(rtc->base + RZN1_RTC_SECC) != bin2bcd(tm_now.tm_sec)); 216 } else { 217 ctl1 &= ~(RZN1_RTC_CTL1_ALME | RZN1_RTC_CTL1_1SE); 218 writel(ctl1, rtc->base + RZN1_RTC_CTL1); 219 } 220 221 return 0; 222 } 223 224 static int rzn1_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 225 { 226 struct rzn1_rtc *rtc = dev_get_drvdata(dev); 227 struct rtc_time *tm = &alrm->time; 228 unsigned int min, hour, wday, delta_days; 229 time64_t alarm; 230 u32 ctl1; 231 int ret; 232 233 ret = rzn1_rtc_read_time(dev, tm); 234 if (ret) 235 return ret; 236 237 min = readl(rtc->base + RZN1_RTC_ALM); 238 hour = readl(rtc->base + RZN1_RTC_ALH); 239 wday = readl(rtc->base + RZN1_RTC_ALW); 240 241 tm->tm_sec = 0; 242 tm->tm_min = bcd2bin(min); 243 tm->tm_hour = bcd2bin(hour); 244 delta_days = ((fls(wday) - 1) - tm->tm_wday + 7) % 7; 245 tm->tm_wday = fls(wday) - 1; 246 247 if (delta_days) { 248 alarm = rtc_tm_to_time64(tm) + (delta_days * 86400); 249 rtc_time64_to_tm(alarm, tm); 250 } 251 252 ctl1 = readl(rtc->base + RZN1_RTC_CTL1); 253 alrm->enabled = !!(ctl1 & (RZN1_RTC_CTL1_ALME | RZN1_RTC_CTL1_1SE)); 254 255 return 0; 256 } 257 258 static int rzn1_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 259 { 260 struct rzn1_rtc *rtc = dev_get_drvdata(dev); 261 struct rtc_time *tm = &alrm->time, tm_now; 262 unsigned long alarm, farest; 263 unsigned int days_ahead, wday; 264 int ret; 265 266 ret = rzn1_rtc_read_time(dev, &tm_now); 267 if (ret) 268 return ret; 269 270 /* We cannot set alarms more than one week ahead */ 271 farest = rtc_tm_to_time64(&tm_now) + rtc->rtcdev->alarm_offset_max; 272 alarm = rtc_tm_to_time64(tm); 273 if (time_after(alarm, farest)) 274 return -ERANGE; 275 276 /* Convert alarm day into week day */ 277 days_ahead = tm->tm_mday - tm_now.tm_mday; 278 wday = (tm_now.tm_wday + days_ahead) % 7; 279 280 writel(bin2bcd(tm->tm_min), rtc->base + RZN1_RTC_ALM); 281 writel(bin2bcd(tm->tm_hour), rtc->base + RZN1_RTC_ALH); 282 writel(BIT(wday), rtc->base + RZN1_RTC_ALW); 283 284 rtc->tm_alarm = alrm->time; 285 286 rzn1_rtc_alarm_irq_enable(dev, alrm->enabled); 287 288 return 0; 289 } 290 291 static int rzn1_rtc_read_offset(struct device *dev, long *offset) 292 { 293 struct rzn1_rtc *rtc = dev_get_drvdata(dev); 294 unsigned int ppb_per_step; 295 bool subtract; 296 u32 val; 297 298 val = readl(rtc->base + RZN1_RTC_SUBU); 299 ppb_per_step = val & RZN1_RTC_SUBU_DEV ? 1017 : 3051; 300 subtract = val & RZN1_RTC_SUBU_DECR; 301 val &= 0x3F; 302 303 if (!val) 304 *offset = 0; 305 else if (subtract) 306 *offset = -(((~val) & 0x3F) + 1) * ppb_per_step; 307 else 308 *offset = (val - 1) * ppb_per_step; 309 310 return 0; 311 } 312 313 static int rzn1_rtc_set_offset(struct device *dev, long offset) 314 { 315 struct rzn1_rtc *rtc = dev_get_drvdata(dev); 316 int stepsh, stepsl, steps; 317 u32 subu = 0, ctl2; 318 int ret; 319 320 /* 321 * Check which resolution mode (every 20 or 60s) can be used. 322 * Between 2 and 124 clock pulses can be added or substracted. 323 * 324 * In 20s mode, the minimum resolution is 2 / (32768 * 20) which is 325 * close to 3051 ppb. In 60s mode, the resolution is closer to 1017. 326 */ 327 stepsh = DIV_ROUND_CLOSEST(offset, 1017); 328 stepsl = DIV_ROUND_CLOSEST(offset, 3051); 329 330 if (stepsh >= -0x3E && stepsh <= 0x3E) { 331 /* 1017 ppb per step */ 332 steps = stepsh; 333 subu |= RZN1_RTC_SUBU_DEV; 334 } else if (stepsl >= -0x3E && stepsl <= 0x3E) { 335 /* 3051 ppb per step */ 336 steps = stepsl; 337 } else { 338 return -ERANGE; 339 } 340 341 if (!steps) 342 return 0; 343 344 if (steps > 0) { 345 subu |= steps + 1; 346 } else { 347 subu |= RZN1_RTC_SUBU_DECR; 348 subu |= (~(-steps - 1)) & 0x3F; 349 } 350 351 ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, ctl2, 352 !(ctl2 & RZN1_RTC_CTL2_WUST), 100, 2000000); 353 if (ret) 354 return ret; 355 356 writel(subu, rtc->base + RZN1_RTC_SUBU); 357 358 return 0; 359 } 360 361 static const struct rtc_class_ops rzn1_rtc_ops_subu = { 362 .read_time = rzn1_rtc_read_time, 363 .set_time = rzn1_rtc_set_time, 364 .read_alarm = rzn1_rtc_read_alarm, 365 .set_alarm = rzn1_rtc_set_alarm, 366 .alarm_irq_enable = rzn1_rtc_alarm_irq_enable, 367 .read_offset = rzn1_rtc_read_offset, 368 .set_offset = rzn1_rtc_set_offset, 369 }; 370 371 static const struct rtc_class_ops rzn1_rtc_ops_scmp = { 372 .read_time = rzn1_rtc_read_time, 373 .set_time = rzn1_rtc_set_time, 374 .read_alarm = rzn1_rtc_read_alarm, 375 .set_alarm = rzn1_rtc_set_alarm, 376 .alarm_irq_enable = rzn1_rtc_alarm_irq_enable, 377 }; 378 379 static int rzn1_rtc_probe(struct platform_device *pdev) 380 { 381 struct rzn1_rtc *rtc; 382 u32 val, scmp_val = 0; 383 struct clk *xtal; 384 unsigned long rate; 385 int irq, ret; 386 387 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); 388 if (!rtc) 389 return -ENOMEM; 390 391 platform_set_drvdata(pdev, rtc); 392 393 rtc->base = devm_platform_ioremap_resource(pdev, 0); 394 if (IS_ERR(rtc->base)) 395 return dev_err_probe(&pdev->dev, PTR_ERR(rtc->base), "Missing reg\n"); 396 397 irq = platform_get_irq_byname(pdev, "alarm"); 398 if (irq < 0) 399 return irq; 400 401 rtc->rtcdev = devm_rtc_allocate_device(&pdev->dev); 402 if (IS_ERR(rtc->rtcdev)) 403 return PTR_ERR(rtc->rtcdev); 404 405 rtc->rtcdev->range_min = RTC_TIMESTAMP_BEGIN_2000; 406 rtc->rtcdev->range_max = RTC_TIMESTAMP_END_2099; 407 rtc->rtcdev->alarm_offset_max = 7 * 86400; 408 409 ret = devm_pm_runtime_enable(&pdev->dev); 410 if (ret < 0) 411 return ret; 412 ret = pm_runtime_resume_and_get(&pdev->dev); 413 if (ret < 0) 414 return ret; 415 416 /* Only switch to scmp if we have an xtal clock with a valid rate and != 32768 */ 417 xtal = devm_clk_get_optional(&pdev->dev, "xtal"); 418 if (IS_ERR(xtal)) { 419 ret = PTR_ERR(xtal); 420 goto dis_runtime_pm; 421 } else if (xtal) { 422 rate = clk_get_rate(xtal); 423 424 if (rate < 32000 || rate > BIT(22)) { 425 ret = -EOPNOTSUPP; 426 goto dis_runtime_pm; 427 } 428 429 if (rate != 32768) 430 scmp_val = RZN1_RTC_CTL0_SLSB_SCMP; 431 } 432 433 /* Disable controller during SUBU/SCMP setup */ 434 val = readl(rtc->base + RZN1_RTC_CTL0) & ~RZN1_RTC_CTL0_CE; 435 writel(val, rtc->base + RZN1_RTC_CTL0); 436 /* Wait 2-4 32k clock cycles for the disabled controller */ 437 ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL0, val, 438 !(val & RZN1_RTC_CTL0_CEST), 62, 123); 439 if (ret) 440 goto dis_runtime_pm; 441 442 /* Set desired modes leaving the controller disabled */ 443 writel(RZN1_RTC_CTL0_AMPM | scmp_val, rtc->base + RZN1_RTC_CTL0); 444 445 if (scmp_val) { 446 writel(rate - 1, rtc->base + RZN1_RTC_SCMP); 447 rtc->rtcdev->ops = &rzn1_rtc_ops_scmp; 448 } else { 449 rtc->rtcdev->ops = &rzn1_rtc_ops_subu; 450 } 451 452 /* Enable controller finally */ 453 writel(RZN1_RTC_CTL0_CE | RZN1_RTC_CTL0_AMPM | scmp_val, rtc->base + RZN1_RTC_CTL0); 454 455 /* Disable all interrupts */ 456 writel(0, rtc->base + RZN1_RTC_CTL1); 457 458 spin_lock_init(&rtc->ctl1_access_lock); 459 460 ret = devm_request_irq(&pdev->dev, irq, rzn1_rtc_alarm_irq, 0, "RZN1 RTC Alarm", rtc); 461 if (ret) { 462 dev_err(&pdev->dev, "RTC alarm interrupt not available\n"); 463 goto dis_runtime_pm; 464 } 465 466 irq = platform_get_irq_byname_optional(pdev, "pps"); 467 if (irq >= 0) 468 ret = devm_request_irq(&pdev->dev, irq, rzn1_rtc_1s_irq, 0, "RZN1 RTC 1s", rtc); 469 470 if (irq < 0 || ret) { 471 set_bit(RTC_FEATURE_ALARM_RES_MINUTE, rtc->rtcdev->features); 472 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, rtc->rtcdev->features); 473 dev_warn(&pdev->dev, "RTC pps interrupt not available. Alarm has only minute accuracy\n"); 474 } 475 476 ret = devm_rtc_register_device(rtc->rtcdev); 477 if (ret) 478 goto dis_runtime_pm; 479 480 return 0; 481 482 dis_runtime_pm: 483 pm_runtime_put(&pdev->dev); 484 485 return ret; 486 } 487 488 static void rzn1_rtc_remove(struct platform_device *pdev) 489 { 490 struct rzn1_rtc *rtc = platform_get_drvdata(pdev); 491 492 /* Disable all interrupts */ 493 writel(0, rtc->base + RZN1_RTC_CTL1); 494 495 pm_runtime_put(&pdev->dev); 496 } 497 498 static const struct of_device_id rzn1_rtc_of_match[] = { 499 { .compatible = "renesas,rzn1-rtc" }, 500 {}, 501 }; 502 MODULE_DEVICE_TABLE(of, rzn1_rtc_of_match); 503 504 static struct platform_driver rzn1_rtc_driver = { 505 .probe = rzn1_rtc_probe, 506 .remove = rzn1_rtc_remove, 507 .driver = { 508 .name = "rzn1-rtc", 509 .of_match_table = rzn1_rtc_of_match, 510 }, 511 }; 512 module_platform_driver(rzn1_rtc_driver); 513 514 MODULE_AUTHOR("Michel Pollet <buserror@gmail.com>"); 515 MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com"); 516 MODULE_DESCRIPTION("RZ/N1 RTC driver"); 517 MODULE_LICENSE("GPL"); 518