1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * On-Chip RTC Support available on RZ/G3S SoC 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 #include <linux/bcd.h> 8 #include <linux/bitfield.h> 9 #include <linux/cleanup.h> 10 #include <linux/clk.h> 11 #include <linux/completion.h> 12 #include <linux/delay.h> 13 #include <linux/iopoll.h> 14 #include <linux/interrupt.h> 15 #include <linux/jiffies.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/reset.h> 20 #include <linux/rtc.h> 21 22 /* Counter registers. */ 23 #define RTCA3_RSECCNT 0x2 24 #define RTCA3_RSECCNT_SEC GENMASK(6, 0) 25 #define RTCA3_RMINCNT 0x4 26 #define RTCA3_RMINCNT_MIN GENMASK(6, 0) 27 #define RTCA3_RHRCNT 0x6 28 #define RTCA3_RHRCNT_HR GENMASK(5, 0) 29 #define RTCA3_RHRCNT_PM BIT(6) 30 #define RTCA3_RWKCNT 0x8 31 #define RTCA3_RWKCNT_WK GENMASK(2, 0) 32 #define RTCA3_RDAYCNT 0xa 33 #define RTCA3_RDAYCNT_DAY GENMASK(5, 0) 34 #define RTCA3_RMONCNT 0xc 35 #define RTCA3_RMONCNT_MONTH GENMASK(4, 0) 36 #define RTCA3_RYRCNT 0xe 37 #define RTCA3_RYRCNT_YEAR GENMASK(7, 0) 38 39 /* Alarm registers. */ 40 #define RTCA3_RSECAR 0x10 41 #define RTCA3_RSECAR_SEC GENMASK(6, 0) 42 #define RTCA3_RMINAR 0x12 43 #define RTCA3_RMINAR_MIN GENMASK(6, 0) 44 #define RTCA3_RHRAR 0x14 45 #define RTCA3_RHRAR_HR GENMASK(5, 0) 46 #define RTCA3_RHRAR_PM BIT(6) 47 #define RTCA3_RWKAR 0x16 48 #define RTCA3_RWKAR_DAYW GENMASK(2, 0) 49 #define RTCA3_RDAYAR 0x18 50 #define RTCA3_RDAYAR_DATE GENMASK(5, 0) 51 #define RTCA3_RMONAR 0x1a 52 #define RTCA3_RMONAR_MON GENMASK(4, 0) 53 #define RTCA3_RYRAR 0x1c 54 #define RTCA3_RYRAR_YR GENMASK(7, 0) 55 #define RTCA3_RYRAREN 0x1e 56 57 /* Alarm enable bit (for all alarm registers). */ 58 #define RTCA3_AR_ENB BIT(7) 59 60 /* Control registers. */ 61 #define RTCA3_RCR1 0x22 62 #define RTCA3_RCR1_AIE BIT(0) 63 #define RTCA3_RCR1_CIE BIT(1) 64 #define RTCA3_RCR1_PIE BIT(2) 65 #define RTCA3_RCR1_PES GENMASK(7, 4) 66 #define RTCA3_RCR1_PES_1_64_SEC 0x8 67 #define RTCA3_RCR2 0x24 68 #define RTCA3_RCR2_START BIT(0) 69 #define RTCA3_RCR2_RESET BIT(1) 70 #define RTCA3_RCR2_AADJE BIT(4) 71 #define RTCA3_RCR2_ADJP BIT(5) 72 #define RTCA3_RCR2_HR24 BIT(6) 73 #define RTCA3_RCR2_CNTMD BIT(7) 74 #define RTCA3_RSR 0x20 75 #define RTCA3_RSR_AF BIT(0) 76 #define RTCA3_RSR_CF BIT(1) 77 #define RTCA3_RSR_PF BIT(2) 78 #define RTCA3_RADJ 0x2e 79 #define RTCA3_RADJ_ADJ GENMASK(5, 0) 80 #define RTCA3_RADJ_ADJ_MAX 0x3f 81 #define RTCA3_RADJ_PMADJ GENMASK(7, 6) 82 #define RTCA3_RADJ_PMADJ_NONE 0 83 #define RTCA3_RADJ_PMADJ_ADD 1 84 #define RTCA3_RADJ_PMADJ_SUB 2 85 86 /* Polling operation timeouts. */ 87 #define RTCA3_DEFAULT_TIMEOUT_US 150 88 #define RTCA3_IRQSET_TIMEOUT_US 5000 89 #define RTCA3_START_TIMEOUT_US 150000 90 #define RTCA3_RESET_TIMEOUT_US 200000 91 92 /** 93 * enum rtca3_alrm_set_step - RTCA3 alarm set steps 94 * @RTCA3_ALRM_SSTEP_DONE: alarm setup done step 95 * @RTCA3_ALRM_SSTEP_IRQ: two 1/64 periodic IRQs were generated step 96 * @RTCA3_ALRM_SSTEP_INIT: alarm setup initialization step 97 */ 98 enum rtca3_alrm_set_step { 99 RTCA3_ALRM_SSTEP_DONE = 0, 100 RTCA3_ALRM_SSTEP_IRQ = 1, 101 RTCA3_ALRM_SSTEP_INIT = 3, 102 }; 103 104 /** 105 * struct rtca3_ppb_per_cycle - PPB per cycle 106 * @ten_sec: PPB per cycle in 10 seconds adjustment mode 107 * @sixty_sec: PPB per cycle in 60 seconds adjustment mode 108 */ 109 struct rtca3_ppb_per_cycle { 110 int ten_sec; 111 int sixty_sec; 112 }; 113 114 /** 115 * struct rtca3_priv - RTCA3 private data structure 116 * @base: base address 117 * @rtc_dev: RTC device 118 * @rstc: reset control 119 * @set_alarm_completion: alarm setup completion 120 * @alrm_sstep: alarm setup step (see enum rtca3_alrm_set_step) 121 * @lock: device lock 122 * @ppb: ppb per cycle for each the available adjustment modes 123 * @wakeup_irq: wakeup IRQ 124 */ 125 struct rtca3_priv { 126 void __iomem *base; 127 struct rtc_device *rtc_dev; 128 struct reset_control *rstc; 129 struct completion set_alarm_completion; 130 atomic_t alrm_sstep; 131 spinlock_t lock; 132 struct rtca3_ppb_per_cycle ppb; 133 int wakeup_irq; 134 }; 135 136 static void rtca3_byte_update_bits(struct rtca3_priv *priv, u8 off, u8 mask, u8 val) 137 { 138 u8 tmp; 139 140 tmp = readb(priv->base + off); 141 tmp &= ~mask; 142 tmp |= (val & mask); 143 writeb(tmp, priv->base + off); 144 } 145 146 static u8 rtca3_alarm_handler_helper(struct rtca3_priv *priv) 147 { 148 u8 val, pending; 149 150 val = readb(priv->base + RTCA3_RSR); 151 pending = val & RTCA3_RSR_AF; 152 writeb(val & ~pending, priv->base + RTCA3_RSR); 153 154 if (pending) 155 rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF); 156 157 return pending; 158 } 159 160 static irqreturn_t rtca3_alarm_handler(int irq, void *dev_id) 161 { 162 struct rtca3_priv *priv = dev_id; 163 u8 pending; 164 165 guard(spinlock)(&priv->lock); 166 167 pending = rtca3_alarm_handler_helper(priv); 168 169 return IRQ_RETVAL(pending); 170 } 171 172 static irqreturn_t rtca3_periodic_handler(int irq, void *dev_id) 173 { 174 struct rtca3_priv *priv = dev_id; 175 u8 val, pending; 176 177 guard(spinlock)(&priv->lock); 178 179 val = readb(priv->base + RTCA3_RSR); 180 pending = val & RTCA3_RSR_PF; 181 182 if (pending) { 183 writeb(val & ~pending, priv->base + RTCA3_RSR); 184 185 if (atomic_read(&priv->alrm_sstep) > RTCA3_ALRM_SSTEP_IRQ) { 186 /* Alarm setup in progress. */ 187 atomic_dec(&priv->alrm_sstep); 188 189 if (atomic_read(&priv->alrm_sstep) == RTCA3_ALRM_SSTEP_IRQ) { 190 /* 191 * We got 2 * 1/64 periodic interrupts. Disable 192 * interrupt and let alarm setup continue. 193 */ 194 rtca3_byte_update_bits(priv, RTCA3_RCR1, 195 RTCA3_RCR1_PIE, 0); 196 readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, val, 197 !(val & RTCA3_RCR1_PIE), 198 10, RTCA3_DEFAULT_TIMEOUT_US); 199 complete(&priv->set_alarm_completion); 200 } 201 } 202 } 203 204 return IRQ_RETVAL(pending); 205 } 206 207 static void rtca3_prepare_cntalrm_regs_for_read(struct rtca3_priv *priv, bool cnt) 208 { 209 /* Offset b/w time and alarm registers. */ 210 u8 offset = cnt ? 0 : 0xe; 211 212 /* 213 * According to HW manual (section 22.6.4. Notes on writing to and 214 * reading from registers) after writing to count registers, alarm 215 * registers, year alarm enable register, bits RCR2.AADJE, AADJP, 216 * and HR24 register, we need to do 3 empty reads before being 217 * able to fetch the registers content. 218 */ 219 for (u8 i = 0; i < 3; i++) { 220 readb(priv->base + RTCA3_RSECCNT + offset); 221 readb(priv->base + RTCA3_RMINCNT + offset); 222 readb(priv->base + RTCA3_RHRCNT + offset); 223 readb(priv->base + RTCA3_RWKCNT + offset); 224 readb(priv->base + RTCA3_RDAYCNT + offset); 225 readw(priv->base + RTCA3_RYRCNT + offset); 226 if (!cnt) 227 readb(priv->base + RTCA3_RYRAREN); 228 } 229 } 230 231 static u32 rtca3_decode_year(u8 mask, u16 year) 232 { 233 u8 y = FIELD_GET(mask, year); 234 u32 century = bcd2bin((y == 0x99) ? 0x19 : 0x20); 235 236 return (century * 100 + bcd2bin(y)) - 1900; 237 } 238 239 static int rtca3_read_time(struct device *dev, struct rtc_time *tm) 240 { 241 struct rtca3_priv *priv = dev_get_drvdata(dev); 242 u8 sec, min, hour, wday, mday, month, tmp; 243 u8 trials = 0; 244 u16 year; 245 246 guard(spinlock_irqsave)(&priv->lock); 247 248 tmp = readb(priv->base + RTCA3_RCR2); 249 if (!(tmp & RTCA3_RCR2_START)) 250 return -EINVAL; 251 252 do { 253 /* Clear carry interrupt. */ 254 rtca3_byte_update_bits(priv, RTCA3_RSR, RTCA3_RSR_CF, 0); 255 256 /* Read counters. */ 257 sec = readb(priv->base + RTCA3_RSECCNT); 258 min = readb(priv->base + RTCA3_RMINCNT); 259 hour = readb(priv->base + RTCA3_RHRCNT); 260 wday = readb(priv->base + RTCA3_RWKCNT); 261 mday = readb(priv->base + RTCA3_RDAYCNT); 262 month = readb(priv->base + RTCA3_RMONCNT); 263 year = readw(priv->base + RTCA3_RYRCNT); 264 265 tmp = readb(priv->base + RTCA3_RSR); 266 267 /* 268 * We cannot generate carries due to reading 64Hz counter as 269 * the driver doesn't implement carry, thus, carries will be 270 * generated once per seconds. Add a timeout of 5 trials here 271 * to avoid infinite loop, if any. 272 */ 273 } while ((tmp & RTCA3_RSR_CF) && ++trials < 5); 274 275 if (trials >= 5) 276 return -ETIMEDOUT; 277 278 tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECCNT_SEC, sec)); 279 tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINCNT_MIN, min)); 280 tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRCNT_HR, hour)); 281 tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKCNT_WK, wday)); 282 tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYCNT_DAY, mday)); 283 tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONCNT_MONTH, month)) - 1; 284 tm->tm_year = rtca3_decode_year(RTCA3_RYRCNT_YEAR, year); 285 286 return 0; 287 } 288 289 static int rtca3_set_time(struct device *dev, struct rtc_time *tm) 290 { 291 struct rtca3_priv *priv = dev_get_drvdata(dev); 292 u8 rcr2, tmp; 293 int ret; 294 295 guard(spinlock_irqsave)(&priv->lock); 296 297 /* Stop the RTC. */ 298 rcr2 = readb(priv->base + RTCA3_RCR2); 299 writeb(rcr2 & ~RTCA3_RCR2_START, priv->base + RTCA3_RCR2); 300 ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, 301 !(tmp & RTCA3_RCR2_START), 302 10, RTCA3_DEFAULT_TIMEOUT_US); 303 if (ret) 304 return ret; 305 306 /* Update time. */ 307 writeb(bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECCNT); 308 writeb(bin2bcd(tm->tm_min), priv->base + RTCA3_RMINCNT); 309 writeb(bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRCNT); 310 writeb(bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKCNT); 311 writeb(bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYCNT); 312 writeb(bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONCNT); 313 writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRCNT); 314 315 /* Make sure we can read back the counters. */ 316 rtca3_prepare_cntalrm_regs_for_read(priv, true); 317 318 /* Start RTC. */ 319 writeb(rcr2 | RTCA3_RCR2_START, priv->base + RTCA3_RCR2); 320 return readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, 321 (tmp & RTCA3_RCR2_START), 322 10, RTCA3_DEFAULT_TIMEOUT_US); 323 } 324 325 static int rtca3_alarm_irq_set_helper(struct rtca3_priv *priv, 326 u8 interrupts, 327 unsigned int enabled) 328 { 329 u8 tmp, val; 330 331 if (enabled) { 332 /* 333 * AIE, CIE, PIE bit indexes in RSR corresponds with 334 * those on RCR1. Same interrupts mask can be used. 335 */ 336 rtca3_byte_update_bits(priv, RTCA3_RSR, interrupts, 0); 337 val = interrupts; 338 } else { 339 val = 0; 340 } 341 342 rtca3_byte_update_bits(priv, RTCA3_RCR1, interrupts, val); 343 return readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, 344 ((tmp & interrupts) == val), 345 10, RTCA3_IRQSET_TIMEOUT_US); 346 } 347 348 static int rtca3_alarm_irq_enable(struct device *dev, unsigned int enabled) 349 { 350 struct rtca3_priv *priv = dev_get_drvdata(dev); 351 352 guard(spinlock_irqsave)(&priv->lock); 353 354 return rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE, enabled); 355 } 356 357 static int rtca3_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) 358 { 359 struct rtca3_priv *priv = dev_get_drvdata(dev); 360 u8 sec, min, hour, wday, mday, month; 361 struct rtc_time *tm = &wkalrm->time; 362 u16 year; 363 364 guard(spinlock_irqsave)(&priv->lock); 365 366 sec = readb(priv->base + RTCA3_RSECAR); 367 min = readb(priv->base + RTCA3_RMINAR); 368 hour = readb(priv->base + RTCA3_RHRAR); 369 wday = readb(priv->base + RTCA3_RWKAR); 370 mday = readb(priv->base + RTCA3_RDAYAR); 371 month = readb(priv->base + RTCA3_RMONAR); 372 year = readw(priv->base + RTCA3_RYRAR); 373 374 tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECAR_SEC, sec)); 375 tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINAR_MIN, min)); 376 tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRAR_HR, hour)); 377 tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKAR_DAYW, wday)); 378 tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYAR_DATE, mday)); 379 tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONAR_MON, month)) - 1; 380 tm->tm_year = rtca3_decode_year(RTCA3_RYRAR_YR, year); 381 382 wkalrm->enabled = !!(readb(priv->base + RTCA3_RCR1) & RTCA3_RCR1_AIE); 383 384 return 0; 385 } 386 387 static int rtca3_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) 388 { 389 struct rtca3_priv *priv = dev_get_drvdata(dev); 390 struct rtc_time *tm = &wkalrm->time; 391 u8 rcr1, tmp; 392 int ret; 393 394 scoped_guard(spinlock_irqsave, &priv->lock) { 395 tmp = readb(priv->base + RTCA3_RCR2); 396 if (!(tmp & RTCA3_RCR2_START)) 397 return -EPERM; 398 399 /* Disable AIE to prevent false interrupts. */ 400 rcr1 = readb(priv->base + RTCA3_RCR1); 401 rcr1 &= ~RTCA3_RCR1_AIE; 402 writeb(rcr1, priv->base + RTCA3_RCR1); 403 ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, 404 !(tmp & RTCA3_RCR1_AIE), 405 10, RTCA3_DEFAULT_TIMEOUT_US); 406 if (ret) 407 return ret; 408 409 /* Set the time and enable the alarm. */ 410 writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECAR); 411 writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_min), priv->base + RTCA3_RMINAR); 412 writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRAR); 413 writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKAR); 414 writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYAR); 415 writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONAR); 416 417 writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRAR); 418 writeb(RTCA3_AR_ENB, priv->base + RTCA3_RYRAREN); 419 420 /* Make sure we can read back the counters. */ 421 rtca3_prepare_cntalrm_regs_for_read(priv, false); 422 423 /* Need to wait for 2 * 1/64 periodic interrupts to be generated. */ 424 atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_INIT); 425 reinit_completion(&priv->set_alarm_completion); 426 427 /* Enable periodic interrupt. */ 428 rcr1 |= RTCA3_RCR1_PIE; 429 writeb(rcr1, priv->base + RTCA3_RCR1); 430 ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, 431 (tmp & RTCA3_RCR1_PIE), 432 10, RTCA3_IRQSET_TIMEOUT_US); 433 } 434 435 if (ret) 436 goto setup_failed; 437 438 /* Wait for the 2 * 1/64 periodic interrupts. */ 439 ret = wait_for_completion_interruptible_timeout(&priv->set_alarm_completion, 440 msecs_to_jiffies(500)); 441 if (ret <= 0) { 442 ret = -ETIMEDOUT; 443 goto setup_failed; 444 } 445 446 scoped_guard(spinlock_irqsave, &priv->lock) { 447 ret = rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE, wkalrm->enabled); 448 atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); 449 } 450 451 return ret; 452 453 setup_failed: 454 scoped_guard(spinlock_irqsave, &priv->lock) { 455 /* 456 * Disable PIE to avoid interrupt storm in case HW needed more than 457 * specified timeout for setup. 458 */ 459 writeb(rcr1 & ~RTCA3_RCR1_PIE, priv->base + RTCA3_RCR1); 460 readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, !(tmp & RTCA3_RCR1_PIE), 461 10, RTCA3_DEFAULT_TIMEOUT_US); 462 atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); 463 } 464 465 return ret; 466 } 467 468 static int rtca3_read_offset(struct device *dev, long *offset) 469 { 470 struct rtca3_priv *priv = dev_get_drvdata(dev); 471 u8 val, radj, cycles; 472 u32 ppb_per_cycle; 473 474 scoped_guard(spinlock_irqsave, &priv->lock) { 475 radj = readb(priv->base + RTCA3_RADJ); 476 val = readb(priv->base + RTCA3_RCR2); 477 } 478 479 cycles = FIELD_GET(RTCA3_RADJ_ADJ, radj); 480 481 if (!cycles) { 482 *offset = 0; 483 return 0; 484 } 485 486 if (val & RTCA3_RCR2_ADJP) 487 ppb_per_cycle = priv->ppb.ten_sec; 488 else 489 ppb_per_cycle = priv->ppb.sixty_sec; 490 491 *offset = cycles * ppb_per_cycle; 492 val = FIELD_GET(RTCA3_RADJ_PMADJ, radj); 493 if (val == RTCA3_RADJ_PMADJ_SUB) 494 *offset = -(*offset); 495 496 return 0; 497 } 498 499 static int rtca3_set_offset(struct device *dev, long offset) 500 { 501 struct rtca3_priv *priv = dev_get_drvdata(dev); 502 int cycles, cycles10, cycles60; 503 u8 radj, adjp, tmp; 504 int ret; 505 506 /* 507 * Automatic time error adjustment could be set at intervals of 10 508 * or 60 seconds. 509 */ 510 cycles10 = DIV_ROUND_CLOSEST(offset, priv->ppb.ten_sec); 511 cycles60 = DIV_ROUND_CLOSEST(offset, priv->ppb.sixty_sec); 512 513 /* We can set b/w 1 and 63 clock cycles. */ 514 if (cycles60 >= -RTCA3_RADJ_ADJ_MAX && 515 cycles60 <= RTCA3_RADJ_ADJ_MAX) { 516 cycles = cycles60; 517 adjp = 0; 518 } else if (cycles10 >= -RTCA3_RADJ_ADJ_MAX && 519 cycles10 <= RTCA3_RADJ_ADJ_MAX) { 520 cycles = cycles10; 521 adjp = RTCA3_RCR2_ADJP; 522 } else { 523 return -ERANGE; 524 } 525 526 radj = FIELD_PREP(RTCA3_RADJ_ADJ, abs(cycles)); 527 if (!cycles) 528 radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_NONE); 529 else if (cycles > 0) 530 radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_ADD); 531 else 532 radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_SUB); 533 534 guard(spinlock_irqsave)(&priv->lock); 535 536 tmp = readb(priv->base + RTCA3_RCR2); 537 538 if ((tmp & RTCA3_RCR2_ADJP) != adjp) { 539 /* RADJ.PMADJ need to be set to zero before setting RCR2.ADJP. */ 540 writeb(0, priv->base + RTCA3_RADJ); 541 ret = readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, !tmp, 542 10, RTCA3_DEFAULT_TIMEOUT_US); 543 if (ret) 544 return ret; 545 546 rtca3_byte_update_bits(priv, RTCA3_RCR2, RTCA3_RCR2_ADJP, adjp); 547 ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp, 548 ((tmp & RTCA3_RCR2_ADJP) == adjp), 549 10, RTCA3_DEFAULT_TIMEOUT_US); 550 if (ret) 551 return ret; 552 } 553 554 writeb(radj, priv->base + RTCA3_RADJ); 555 return readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, (tmp == radj), 556 10, RTCA3_DEFAULT_TIMEOUT_US); 557 } 558 559 static const struct rtc_class_ops rtca3_ops = { 560 .read_time = rtca3_read_time, 561 .set_time = rtca3_set_time, 562 .read_alarm = rtca3_read_alarm, 563 .set_alarm = rtca3_set_alarm, 564 .alarm_irq_enable = rtca3_alarm_irq_enable, 565 .set_offset = rtca3_set_offset, 566 .read_offset = rtca3_read_offset, 567 }; 568 569 static int rtca3_initial_setup(struct clk *clk, struct rtca3_priv *priv) 570 { 571 unsigned long osc32k_rate; 572 u8 val, tmp, mask; 573 u32 sleep_us; 574 int ret; 575 576 osc32k_rate = clk_get_rate(clk); 577 if (!osc32k_rate) 578 return -EINVAL; 579 580 sleep_us = DIV_ROUND_UP_ULL(1000000ULL, osc32k_rate) * 6; 581 582 priv->ppb.ten_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 10)); 583 priv->ppb.sixty_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 60)); 584 585 /* 586 * According to HW manual (section 22.4.2. Clock and count mode setting procedure) 587 * we need to wait at least 6 cycles of the 32KHz clock after clock was enabled. 588 */ 589 usleep_range(sleep_us, sleep_us + 10); 590 591 mask = RTCA3_RCR2_START | RTCA3_RCR2_HR24; 592 val = readb(priv->base + RTCA3_RCR2); 593 /* Only disable the interrupts if already started in 24 hours and calendar count mode. */ 594 if ((val & mask) == mask) { 595 /* Disable all interrupts. */ 596 mask = RTCA3_RCR1_AIE | RTCA3_RCR1_CIE | RTCA3_RCR1_PIE; 597 return rtca3_alarm_irq_set_helper(priv, mask, 0); 598 } 599 600 /* Reconfigure the RTC in 24 hours and calendar count mode. */ 601 mask = RTCA3_RCR2_START | RTCA3_RCR2_CNTMD; 602 writeb(0, priv->base + RTCA3_RCR2); 603 ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask), 604 10, RTCA3_DEFAULT_TIMEOUT_US); 605 if (ret) 606 return ret; 607 608 /* 609 * Set 24 hours mode. According to HW manual (section 22.3.19. RTC Control 610 * Register 2) this needs to be done separate from stop operation. 611 */ 612 mask = RTCA3_RCR2_HR24; 613 val = RTCA3_RCR2_HR24; 614 writeb(val, priv->base + RTCA3_RCR2); 615 ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, (tmp & mask), 616 10, RTCA3_DEFAULT_TIMEOUT_US); 617 if (ret) 618 return ret; 619 620 /* Execute reset. */ 621 mask = RTCA3_RCR2_RESET; 622 writeb(val | RTCA3_RCR2_RESET, priv->base + RTCA3_RCR2); 623 ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask), 624 10, RTCA3_RESET_TIMEOUT_US); 625 if (ret) 626 return ret; 627 628 /* 629 * According to HW manual (section 22.6.3. Notes on writing to and reading 630 * from registers) after reset we need to wait 6 clock cycles before 631 * writing to RTC registers. 632 */ 633 usleep_range(sleep_us, sleep_us + 10); 634 635 /* Set no adjustment. */ 636 writeb(0, priv->base + RTCA3_RADJ); 637 ret = readb_poll_timeout(priv->base + RTCA3_RADJ, tmp, !tmp, 10, 638 RTCA3_DEFAULT_TIMEOUT_US); 639 if (ret) 640 return ret; 641 642 /* Start the RTC and enable automatic time error adjustment. */ 643 mask = RTCA3_RCR2_START | RTCA3_RCR2_AADJE; 644 val |= RTCA3_RCR2_START | RTCA3_RCR2_AADJE; 645 writeb(val, priv->base + RTCA3_RCR2); 646 ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, ((tmp & mask) == mask), 647 10, RTCA3_START_TIMEOUT_US); 648 if (ret) 649 return ret; 650 651 /* 652 * According to HW manual (section 22.6.4. Notes on writing to and reading 653 * from registers) we need to wait 1/128 seconds while the clock is operating 654 * (RCR2.START bit = 1) to be able to read the counters after a return from 655 * reset. 656 */ 657 usleep_range(8000, 9000); 658 659 /* Set period interrupt to 1/64 seconds. It is necessary for alarm setup. */ 660 val = FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC); 661 rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_PES, val); 662 return readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, ((tmp & RTCA3_RCR1_PES) == val), 663 10, RTCA3_DEFAULT_TIMEOUT_US); 664 } 665 666 static int rtca3_request_irqs(struct platform_device *pdev, struct rtca3_priv *priv) 667 { 668 struct device *dev = &pdev->dev; 669 int ret, irq; 670 671 irq = platform_get_irq_byname(pdev, "alarm"); 672 if (irq < 0) 673 return dev_err_probe(dev, irq, "Failed to get alarm IRQ!\n"); 674 675 ret = devm_request_irq(dev, irq, rtca3_alarm_handler, 0, "rtca3-alarm", priv); 676 if (ret) 677 return dev_err_probe(dev, ret, "Failed to request alarm IRQ!\n"); 678 priv->wakeup_irq = irq; 679 680 irq = platform_get_irq_byname(pdev, "period"); 681 if (irq < 0) 682 return dev_err_probe(dev, irq, "Failed to get period IRQ!\n"); 683 684 ret = devm_request_irq(dev, irq, rtca3_periodic_handler, 0, "rtca3-period", priv); 685 if (ret) 686 return dev_err_probe(dev, ret, "Failed to request period IRQ!\n"); 687 688 /* 689 * Driver doesn't implement carry handler. Just get the IRQ here 690 * for backward compatibility, in case carry support will be added later. 691 */ 692 irq = platform_get_irq_byname(pdev, "carry"); 693 if (irq < 0) 694 return dev_err_probe(dev, irq, "Failed to get carry IRQ!\n"); 695 696 return 0; 697 } 698 699 static void rtca3_action(void *data) 700 { 701 struct device *dev = data; 702 struct rtca3_priv *priv = dev_get_drvdata(dev); 703 int ret; 704 705 ret = reset_control_assert(priv->rstc); 706 if (ret) 707 dev_err(dev, "Failed to assert reset!"); 708 709 ret = pm_runtime_put_sync(dev); 710 if (ret < 0) 711 dev_err(dev, "Failed to runtime suspend!"); 712 } 713 714 static int rtca3_probe(struct platform_device *pdev) 715 { 716 struct device *dev = &pdev->dev; 717 struct rtca3_priv *priv; 718 struct clk *clk; 719 int ret; 720 721 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 722 if (!priv) 723 return -ENOMEM; 724 725 priv->base = devm_platform_ioremap_resource(pdev, 0); 726 if (IS_ERR(priv->base)) 727 return PTR_ERR(priv->base); 728 729 ret = devm_pm_runtime_enable(dev); 730 if (ret) 731 return ret; 732 733 priv->rstc = devm_reset_control_array_get_shared(dev); 734 if (IS_ERR(priv->rstc)) 735 return PTR_ERR(priv->rstc); 736 737 ret = pm_runtime_resume_and_get(dev); 738 if (ret) 739 return ret; 740 741 ret = reset_control_deassert(priv->rstc); 742 if (ret) { 743 pm_runtime_put_sync(dev); 744 return ret; 745 } 746 747 dev_set_drvdata(dev, priv); 748 ret = devm_add_action_or_reset(dev, rtca3_action, dev); 749 if (ret) 750 return ret; 751 752 /* 753 * This must be an always-on clock to keep the RTC running even after 754 * driver is unbinded. 755 */ 756 clk = devm_clk_get_enabled(dev, "counter"); 757 if (IS_ERR(clk)) 758 return PTR_ERR(clk); 759 760 spin_lock_init(&priv->lock); 761 atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE); 762 init_completion(&priv->set_alarm_completion); 763 764 ret = rtca3_initial_setup(clk, priv); 765 if (ret) 766 return dev_err_probe(dev, ret, "Failed to setup the RTC!\n"); 767 768 ret = rtca3_request_irqs(pdev, priv); 769 if (ret) 770 return ret; 771 772 device_init_wakeup(&pdev->dev, true); 773 774 priv->rtc_dev = devm_rtc_allocate_device(&pdev->dev); 775 if (IS_ERR(priv->rtc_dev)) 776 return PTR_ERR(priv->rtc_dev); 777 778 priv->rtc_dev->ops = &rtca3_ops; 779 priv->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000; 780 priv->rtc_dev->range_max = RTC_TIMESTAMP_END_2099; 781 782 return devm_rtc_register_device(priv->rtc_dev); 783 } 784 785 static void rtca3_remove(struct platform_device *pdev) 786 { 787 struct rtca3_priv *priv = platform_get_drvdata(pdev); 788 789 guard(spinlock_irqsave)(&priv->lock); 790 791 /* 792 * Disable alarm, periodic interrupts. The RTC device cannot 793 * power up the system. 794 */ 795 rtca3_alarm_irq_set_helper(priv, RTCA3_RCR1_AIE | RTCA3_RCR1_PIE, 0); 796 } 797 798 static int rtca3_suspend(struct device *dev) 799 { 800 struct rtca3_priv *priv = dev_get_drvdata(dev); 801 802 if (!device_may_wakeup(dev)) 803 return 0; 804 805 /* Alarm setup in progress. */ 806 if (atomic_read(&priv->alrm_sstep) != RTCA3_ALRM_SSTEP_DONE) 807 return -EBUSY; 808 809 enable_irq_wake(priv->wakeup_irq); 810 811 return 0; 812 } 813 814 static int rtca3_clean_alarm(struct rtca3_priv *priv) 815 { 816 struct rtc_device *rtc_dev = priv->rtc_dev; 817 time64_t alarm_time, now; 818 struct rtc_wkalrm alarm; 819 struct rtc_time tm; 820 u8 pending; 821 int ret; 822 823 ret = rtc_read_alarm(rtc_dev, &alarm); 824 if (ret) 825 return ret; 826 827 if (!alarm.enabled) 828 return 0; 829 830 ret = rtc_read_time(rtc_dev, &tm); 831 if (ret) 832 return ret; 833 834 alarm_time = rtc_tm_to_time64(&alarm.time); 835 now = rtc_tm_to_time64(&tm); 836 if (alarm_time >= now) 837 return 0; 838 839 /* 840 * Heuristically, it has been determined that when returning from deep 841 * sleep state the RTCA3_RSR.AF is zero even though the alarm expired. 842 * Call again the rtc_update_irq() if alarm helper detects this. 843 */ 844 845 guard(spinlock_irqsave)(&priv->lock); 846 847 pending = rtca3_alarm_handler_helper(priv); 848 if (!pending) 849 rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF); 850 851 return 0; 852 } 853 854 static int rtca3_resume(struct device *dev) 855 { 856 struct rtca3_priv *priv = dev_get_drvdata(dev); 857 858 if (!device_may_wakeup(dev)) 859 return 0; 860 861 disable_irq_wake(priv->wakeup_irq); 862 863 /* 864 * According to the HW manual (section 22.6.4 Notes on writing to 865 * and reading from registers) we need to wait 1/128 seconds while 866 * RCR2.START = 1 to be able to read the counters after a return from low 867 * power consumption state. 868 */ 869 mdelay(8); 870 871 /* 872 * The alarm cannot wake the system from deep sleep states. In case 873 * we return from deep sleep states and the alarm expired we need 874 * to disable it to avoid failures when setting another alarm. 875 */ 876 return rtca3_clean_alarm(priv); 877 } 878 879 static DEFINE_SIMPLE_DEV_PM_OPS(rtca3_pm_ops, rtca3_suspend, rtca3_resume); 880 881 static const struct of_device_id rtca3_of_match[] = { 882 { .compatible = "renesas,rz-rtca3", }, 883 { /* sentinel */ } 884 }; 885 MODULE_DEVICE_TABLE(of, rtca3_of_match); 886 887 static struct platform_driver rtca3_platform_driver = { 888 .driver = { 889 .name = "rtc-rtca3", 890 .pm = pm_ptr(&rtca3_pm_ops), 891 .of_match_table = rtca3_of_match, 892 }, 893 .probe = rtca3_probe, 894 .remove = rtca3_remove, 895 }; 896 module_platform_driver(rtca3_platform_driver); 897 898 MODULE_DESCRIPTION("Renesas RTCA-3 RTC driver"); 899 MODULE_AUTHOR("Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>"); 900 MODULE_LICENSE("GPL"); 901