1# SPDX-License-Identifier: GPL-2.0 2# Audio subsystem clock support for Cixtech SoC family 3menu "Cixtech Audio Subsystem Clock Driver" 4 5config CLK_SKY1_AUDSS 6 tristate "Cixtech Sky1 Audio Subsystem Clock Driver" 7 depends on ARCH_CIX || COMPILE_TEST 8 select AUXILIARY_BUS 9 select REGMAP_MMIO 10 select RESET_CONTROLLER 11 help 12 Support for the Audio Subsystem clock controller present on 13 Cixtech Sky1 SoC. This driver provides mux, divider and gate 14 clocks for DSP, I2S, HDA and related blocks in the audio 15 subsystem. Say M or Y here if you want to build this driver. 16endmenu 17