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Searched refs:CLK_PLL1 (Results 1 – 25 of 26) sorted by relevance

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/linux/drivers/clk/renesas/
H A Dr8a7792-cpg-mssr.c32 CLK_PLL1, enumerator
47 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
50 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
56 DEF_FIXED("zg", R8A7792_CLK_ZG, CLK_PLL1, 5, 1),
57 DEF_FIXED("zx", R8A7792_CLK_ZX, CLK_PLL1, 3, 1),
58 DEF_FIXED("zs", R8A7792_CLK_ZS, CLK_PLL1, 6, 1),
59 DEF_FIXED("hp", R8A7792_CLK_HP, CLK_PLL1, 12, 1),
60 DEF_FIXED("i", R8A7792_CLK_I, CLK_PLL1, 3, 1),
61 DEF_FIXED("b", R8A7792_CLK_B, CLK_PLL1, 12, 1),
62 DEF_FIXED("lb", R8A7792_CLK_LB, CLK_PLL1, 24, 1),
[all …]
H A Dr8a77470-cpg-mssr.c29 CLK_PLL1, enumerator
45 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
48 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
51 DEF_BASE("sdh", R8A77470_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
52 DEF_BASE("sd0", R8A77470_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
53 DEF_BASE("sd1", R8A77470_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1),
58 DEF_FIXED("zx", R8A77470_CLK_ZX, CLK_PLL1, 3, 1),
59 DEF_FIXED("zs", R8A77470_CLK_ZS, CLK_PLL1, 6, 1),
60 DEF_FIXED("hp", R8A77470_CLK_HP, CLK_PLL1, 12, 1),
61 DEF_FIXED("b", R8A77470_CLK_B, CLK_PLL1, 12, 1),
[all …]
H A Dr8a7794-cpg-mssr.c33 CLK_PLL1, enumerator
49 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
52 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
55 DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
56 DEF_BASE("sdh", R8A7794_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
57 DEF_BASE("sd0", R8A7794_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
62 DEF_FIXED("zg", R8A7794_CLK_ZG, CLK_PLL1, 6, 1),
63 DEF_FIXED("zx", R8A7794_CLK_ZX, CLK_PLL1, 3, 1),
64 DEF_FIXED("zs", R8A7794_CLK_ZS, CLK_PLL1, 6, 1),
65 DEF_FIXED("hp", R8A7794_CLK_HP, CLK_PLL1, 12, 1),
[all …]
H A Dr8a7790-cpg-mssr.c33 CLK_PLL1, enumerator
49 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
52 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
56 DEF_BASE("lb", R8A7790_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
57 DEF_BASE("adsp", R8A7790_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
58 DEF_BASE("sdh", R8A7790_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
59 DEF_BASE("sd0", R8A7790_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
60 DEF_BASE("sd1", R8A7790_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1),
64 DEF_FIXED("z2", R8A7790_CLK_Z2, CLK_PLL1, 2, 1),
65 DEF_FIXED("zg", R8A7790_CLK_ZG, CLK_PLL1, 3, 1),
[all …]
H A Dr8a7745-cpg-mssr.c29 CLK_PLL1, enumerator
45 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
48 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
51 DEF_BASE("sdh", R8A7745_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
52 DEF_BASE("sd0", R8A7745_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
57 DEF_FIXED("zg", R8A7745_CLK_ZG, CLK_PLL1, 6, 1),
58 DEF_FIXED("zx", R8A7745_CLK_ZX, CLK_PLL1, 3, 1),
59 DEF_FIXED("zs", R8A7745_CLK_ZS, CLK_PLL1, 6, 1),
60 DEF_FIXED("hp", R8A7745_CLK_HP, CLK_PLL1, 12, 1),
61 DEF_FIXED("b", R8A7745_CLK_B, CLK_PLL1, 12, 1),
[all …]
H A Dr8a7742-cpg-mssr.c29 CLK_PLL1, enumerator
45 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
48 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
52 DEF_BASE("lb", R8A7742_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
53 DEF_BASE("sdh", R8A7742_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
54 DEF_BASE("sd0", R8A7742_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
55 DEF_BASE("sd1", R8A7742_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1),
59 DEF_FIXED("z2", R8A7742_CLK_Z2, CLK_PLL1, 2, 1),
60 DEF_FIXED("zg", R8A7742_CLK_ZG, CLK_PLL1, 3, 1),
61 DEF_FIXED("zx", R8A7742_CLK_ZX, CLK_PLL1, 3, 1),
[all …]
H A Dr8a7791-cpg-mssr.c34 CLK_PLL1, enumerator
50 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
53 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
57 DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
58 DEF_BASE("sdh", R8A7791_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
59 DEF_BASE("sd0", R8A7791_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
63 DEF_FIXED("zg", R8A7791_CLK_ZG, CLK_PLL1, 3, 1),
64 DEF_FIXED("zx", R8A7791_CLK_ZX, CLK_PLL1, 3, 1),
65 DEF_FIXED("zs", R8A7791_CLK_ZS, CLK_PLL1, 6, 1),
66 DEF_FIXED("hp", R8A7791_CLK_HP, CLK_PLL1, 12, 1),
[all …]
H A Dr8a7743-cpg-mssr.c30 CLK_PLL1, enumerator
46 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
49 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
53 DEF_BASE("sdh", R8A7743_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
54 DEF_BASE("sd0", R8A7743_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
58 DEF_FIXED("zg", R8A7743_CLK_ZG, CLK_PLL1, 3, 1),
59 DEF_FIXED("zx", R8A7743_CLK_ZX, CLK_PLL1, 3, 1),
60 DEF_FIXED("zs", R8A7743_CLK_ZS, CLK_PLL1, 6, 1),
61 DEF_FIXED("hp", R8A7743_CLK_HP, CLK_PLL1, 12, 1),
62 DEF_FIXED("b", R8A7743_CLK_B, CLK_PLL1, 12, 1),
[all …]
H A Dr8a77995-cpg-mssr.c33 CLK_PLL1, enumerator
59 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
66 DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
68 DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
69 DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
70 DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
71 DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
72 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
74 DEF_FIXED_RPCSRC_D3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
83 DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
[all …]
H A Dr8a774c0-cpg-mssr.c33 CLK_PLL1, enumerator
61 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
70 DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
72 DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
73 DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
74 DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
75 DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
76 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
78 DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
88 DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1),
[all …]
H A Dr8a77990-cpg-mssr.c33 CLK_PLL1, enumerator
61 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
70 DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
72 DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
73 DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
74 DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
75 DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
76 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
78 DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
88 DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1),
[all …]
H A Dr8a77980-cpg-mssr.c34 CLK_PLL1, enumerator
58 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
62 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
70 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
H A Dr8a774a1-cpg-mssr.c33 CLK_PLL1, enumerator
59 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
64 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
72 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
H A Dr8a774b1-cpg-mssr.c33 CLK_PLL1, enumerator
58 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
62 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
70 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
H A Dr8a779f0-cpg-mssr.c33 CLK_PLL1, enumerator
61 DEF_GEN4_PLL_F9_24(".pll1", 1, CLK_PLL1, CLK_MAIN),
67 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
H A Dr8a774e1-cpg-mssr.c33 CLK_PLL1, enumerator
59 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
64 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
72 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
H A Dr8a77965-cpg-mssr.c35 CLK_PLL1, enumerator
61 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
65 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
73 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
H A Dr8a7796-cpg-mssr.c37 CLK_PLL1, enumerator
64 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
69 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
77 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
H A Dr8a7795-cpg-mssr.c35 CLK_PLL1, enumerator
62 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
67 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
75 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
H A Dr8a779a0-cpg-mssr.c37 CLK_PLL1, enumerator
78 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
86 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
H A Dr9a08g045-cpg.c72 CLK_PLL1, enumerator
137 DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8, 0x100),
161 DEF_G3S_DIV("I", R9A08G045_CLK_I, CLK_PLL1, DIVPL1A, G3S_DIVPL1A_STS, dtable_1_8,
H A Dr9a07g043-cpg.c37 CLK_PLL1, enumerator
106 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
133 DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8),
H A Dr9a09g077-cpg.c86 CLK_PLL1, enumerator
137 DEF_FIXED(".pll1", CLK_PLL1, CLK_EXTAL, 1, 40),
H A Dr9a07g044-cpg.c38 CLK_PLL1, enumerator
162 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
202 DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8),
/linux/include/dt-bindings/clock/
H A Dspacemit,k1-syscon.h10 #define CLK_PLL1 0 macro

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