xref: /linux/drivers/clk/renesas/r8a77470-cpg-mssr.c (revision cbecf716ca618fd44feda6bd9a64a8179d031fc5)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * r8a77470 Clock Pulse Generator / Module Standby and Software Reset
4  *
5  * Copyright (C) 2018 Renesas Electronics Corp.
6  */
7 
8 #include <linux/device.h>
9 #include <linux/init.h>
10 #include <linux/kernel.h>
11 #include <linux/soc/renesas/rcar-rst.h>
12 
13 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
14 
15 #include "renesas-cpg-mssr.h"
16 #include "rcar-gen2-cpg.h"
17 
18 enum clk_ids {
19 	/* Core Clock Outputs exported to DT */
20 	LAST_DT_CORE_CLK = R8A77470_CLK_OSC,
21 
22 	/* External Input Clocks */
23 	CLK_EXTAL,
24 	CLK_USB_EXTAL,
25 
26 	/* Internal Core Clocks */
27 	CLK_MAIN,
28 	CLK_PLL0,
29 	CLK_PLL1,
30 	CLK_PLL3,
31 	CLK_PLL1_DIV2,
32 
33 	/* Module Clocks */
34 	MOD_CLK_BASE
35 };
36 
37 static const struct cpg_core_clk r8a77470_core_clks[] __initconst = {
38 	/* External Clock Inputs */
39 	DEF_INPUT("extal",	CLK_EXTAL),
40 	DEF_INPUT("usb_extal",	CLK_USB_EXTAL),
41 
42 	/* Internal Core Clocks */
43 	DEF_BASE(".main",	CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
44 	DEF_BASE(".pll0",	CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
45 	DEF_BASE(".pll1",	CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
46 	DEF_BASE(".pll3",	CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
47 
48 	DEF_FIXED(".pll1_div2",	CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
49 
50 	/* Core Clock Outputs */
51 	DEF_BASE("sdh",  R8A77470_CLK_SDH,  CLK_TYPE_GEN2_SDH,	CLK_PLL1),
52 	DEF_BASE("sd0",  R8A77470_CLK_SD0,  CLK_TYPE_GEN2_SD0,	CLK_PLL1),
53 	DEF_BASE("sd1",  R8A77470_CLK_SD1,  CLK_TYPE_GEN2_SD1,	CLK_PLL1),
54 	DEF_BASE("qspi", R8A77470_CLK_QSPI, CLK_TYPE_GEN2_QSPI,	CLK_PLL1_DIV2),
55 	DEF_BASE("rcan", R8A77470_CLK_RCAN, CLK_TYPE_GEN2_RCAN,	CLK_USB_EXTAL),
56 
57 	DEF_FIXED("z2",    R8A77470_CLK_Z2,	CLK_PLL0,	    1, 1),
58 	DEF_FIXED("zx",    R8A77470_CLK_ZX,	CLK_PLL1,	    3, 1),
59 	DEF_FIXED("zs",    R8A77470_CLK_ZS,	CLK_PLL1,	    6, 1),
60 	DEF_FIXED("hp",    R8A77470_CLK_HP,	CLK_PLL1,	   12, 1),
61 	DEF_FIXED("b",     R8A77470_CLK_B,	CLK_PLL1,	   12, 1),
62 	DEF_FIXED("lb",	   R8A77470_CLK_LB,     CLK_PLL1,	   24, 1),
63 	DEF_FIXED("p",     R8A77470_CLK_P,	CLK_PLL1,	   24, 1),
64 	DEF_FIXED("cl",    R8A77470_CLK_CL,	CLK_PLL1,	   48, 1),
65 	DEF_FIXED("cp",    R8A77470_CLK_CP,	CLK_PLL1,	   48, 1),
66 	DEF_FIXED("m2",    R8A77470_CLK_M2,	CLK_PLL1,	    8, 1),
67 	DEF_FIXED("zb3",   R8A77470_CLK_ZB3,	CLK_PLL3,	    4, 1),
68 	DEF_FIXED("mp",    R8A77470_CLK_MP,	CLK_PLL1_DIV2,	   15, 1),
69 	DEF_FIXED("cpex",  R8A77470_CLK_CPEX,	CLK_EXTAL,	    2, 1),
70 	DEF_FIXED("r",     R8A77470_CLK_R,	CLK_PLL1,	49152, 1),
71 	DEF_FIXED("osc",   R8A77470_CLK_OSC,	CLK_PLL1,	12288, 1),
72 
73 	DEF_DIV6P1("sd2",  R8A77470_CLK_SD2,	CLK_PLL1_DIV2,	0x078),
74 };
75 
76 static const struct mssr_mod_clk r8a77470_mod_clks[] __initconst = {
77 	DEF_MOD("msiof0",		   0,	R8A77470_CLK_MP),
78 	DEF_MOD("vcp0",			 101,	R8A77470_CLK_ZS),
79 	DEF_MOD("vpc0",			 103,	R8A77470_CLK_ZS),
80 	DEF_MOD("tmu1",			 111,	R8A77470_CLK_P),
81 	DEF_MOD("3dg",			 112,	R8A77470_CLK_ZS),
82 	DEF_MOD("2d-dmac",		 115,	R8A77470_CLK_ZS),
83 	DEF_MOD("fdp1-0",		 119,	R8A77470_CLK_ZS),
84 	DEF_MOD("tmu3",			 121,	R8A77470_CLK_P),
85 	DEF_MOD("tmu2",			 122,	R8A77470_CLK_P),
86 	DEF_MOD("cmt0",			 124,	R8A77470_CLK_R),
87 	DEF_MOD("vsp1du0",		 128,	R8A77470_CLK_ZS),
88 	DEF_MOD("vsps",			 131,	R8A77470_CLK_ZS),
89 	DEF_MOD("msiof2",		 205,	R8A77470_CLK_MP),
90 	DEF_MOD("msiof1",		 208,	R8A77470_CLK_MP),
91 	DEF_MOD("sys-dmac1",		 218,	R8A77470_CLK_ZS),
92 	DEF_MOD("sys-dmac0",		 219,	R8A77470_CLK_ZS),
93 	DEF_MOD("sdhi2",		 312,	R8A77470_CLK_SD2),
94 	DEF_MOD("sdhi1",		 313,	R8A77470_CLK_SD1),
95 	DEF_MOD("sdhi0",		 314,	R8A77470_CLK_SD0),
96 	DEF_MOD("usbhs-dmac0-ch1",	 326,	R8A77470_CLK_HP),
97 	DEF_MOD("usbhs-dmac1-ch1",	 327,	R8A77470_CLK_HP),
98 	DEF_MOD("cmt1",			 329,	R8A77470_CLK_R),
99 	DEF_MOD("usbhs-dmac0-ch0",	 330,	R8A77470_CLK_HP),
100 	DEF_MOD("usbhs-dmac1-ch0",	 331,	R8A77470_CLK_HP),
101 	DEF_MOD("rwdt",			 402,	R8A77470_CLK_R),
102 	DEF_MOD("irqc",			 407,	R8A77470_CLK_CP),
103 	DEF_MOD("intc-sys",		 408,	R8A77470_CLK_ZS),
104 	DEF_MOD("audio-dmac0",		 502,	R8A77470_CLK_HP),
105 	DEF_MOD("pwm",			 523,	R8A77470_CLK_P),
106 	DEF_MOD("usb-ehci-0",		 703,	R8A77470_CLK_MP),
107 	DEF_MOD("usbhs-0",		 704,	R8A77470_CLK_HP),
108 	DEF_MOD("usb-ehci-1",		 705,	R8A77470_CLK_MP),
109 	DEF_MOD("usbhs-1",		 706,	R8A77470_CLK_HP),
110 	DEF_MOD("hscif2",		 713,	R8A77470_CLK_ZS),
111 	DEF_MOD("scif5",		 714,	R8A77470_CLK_P),
112 	DEF_MOD("scif4",		 715,	R8A77470_CLK_P),
113 	DEF_MOD("hscif1",		 716,	R8A77470_CLK_ZS),
114 	DEF_MOD("hscif0",		 717,	R8A77470_CLK_ZS),
115 	DEF_MOD("scif3",		 718,	R8A77470_CLK_P),
116 	DEF_MOD("scif2",		 719,	R8A77470_CLK_P),
117 	DEF_MOD("scif1",		 720,	R8A77470_CLK_P),
118 	DEF_MOD("scif0",		 721,	R8A77470_CLK_P),
119 	DEF_MOD("du1",			 723,	R8A77470_CLK_ZX),
120 	DEF_MOD("du0",			 724,	R8A77470_CLK_ZX),
121 	DEF_MOD("ipmmu-sgx",		 800,	R8A77470_CLK_ZX),
122 	DEF_MOD("etheravb",		 812,	R8A77470_CLK_HP),
123 	DEF_MOD("ether",		 813,	R8A77470_CLK_P),
124 	DEF_MOD("gpio5",		 907,	R8A77470_CLK_CP),
125 	DEF_MOD("gpio4",		 908,	R8A77470_CLK_CP),
126 	DEF_MOD("gpio3",		 909,	R8A77470_CLK_CP),
127 	DEF_MOD("gpio2",		 910,	R8A77470_CLK_CP),
128 	DEF_MOD("gpio1",		 911,	R8A77470_CLK_CP),
129 	DEF_MOD("gpio0",		 912,	R8A77470_CLK_CP),
130 	DEF_MOD("can1",			 915,	R8A77470_CLK_P),
131 	DEF_MOD("can0",			 916,	R8A77470_CLK_P),
132 	DEF_MOD("qspi_mod-1",		 917,	R8A77470_CLK_QSPI),
133 	DEF_MOD("qspi_mod-0",		 918,	R8A77470_CLK_QSPI),
134 	DEF_MOD("i2c4",			 927,	R8A77470_CLK_HP),
135 	DEF_MOD("i2c3",			 928,	R8A77470_CLK_HP),
136 	DEF_MOD("i2c2",			 929,	R8A77470_CLK_HP),
137 	DEF_MOD("i2c1",			 930,	R8A77470_CLK_HP),
138 	DEF_MOD("i2c0",			 931,	R8A77470_CLK_HP),
139 	DEF_MOD("ssi-all",		1005,	R8A77470_CLK_P),
140 	DEF_MOD("ssi9",			1006,	MOD_CLK_ID(1005)),
141 	DEF_MOD("ssi8",			1007,	MOD_CLK_ID(1005)),
142 	DEF_MOD("ssi7",			1008,	MOD_CLK_ID(1005)),
143 	DEF_MOD("ssi6",			1009,	MOD_CLK_ID(1005)),
144 	DEF_MOD("ssi5",			1010,	MOD_CLK_ID(1005)),
145 	DEF_MOD("ssi4",			1011,	MOD_CLK_ID(1005)),
146 	DEF_MOD("ssi3",			1012,	MOD_CLK_ID(1005)),
147 	DEF_MOD("ssi2",			1013,	MOD_CLK_ID(1005)),
148 	DEF_MOD("ssi1",			1014,	MOD_CLK_ID(1005)),
149 	DEF_MOD("ssi0",			1015,	MOD_CLK_ID(1005)),
150 	DEF_MOD("scu-all",		1017,	R8A77470_CLK_P),
151 	DEF_MOD("scu-dvc1",		1018,	MOD_CLK_ID(1017)),
152 	DEF_MOD("scu-dvc0",		1019,	MOD_CLK_ID(1017)),
153 	DEF_MOD("scu-ctu1-mix1",	1020,	MOD_CLK_ID(1017)),
154 	DEF_MOD("scu-ctu0-mix0",	1021,	MOD_CLK_ID(1017)),
155 	DEF_MOD("scu-src6",		1025,	MOD_CLK_ID(1017)),
156 	DEF_MOD("scu-src5",		1026,	MOD_CLK_ID(1017)),
157 	DEF_MOD("scu-src4",		1027,	MOD_CLK_ID(1017)),
158 	DEF_MOD("scu-src3",		1028,	MOD_CLK_ID(1017)),
159 	DEF_MOD("scu-src2",		1029,	MOD_CLK_ID(1017)),
160 	DEF_MOD("scu-src1",		1030,	MOD_CLK_ID(1017)),
161 };
162 
163 static const unsigned int r8a77470_crit_mod_clks[] __initconst = {
164 	MOD_CLK_ID(402),	/* RWDT */
165 	MOD_CLK_ID(408),	/* INTC-SYS (GIC) */
166 };
167 
168 /*
169  * CPG Clock Data
170  */
171 
172 /*
173  *    MD	EXTAL		PLL0	PLL1	PLL3
174  * 14 13	(MHz)		*1	*2
175  *---------------------------------------------------
176  * 0  0		20		x80	x78	x50
177  * 0  1		26		x60	x60	x56
178  * 1  0		Prohibited setting
179  * 1  1		30		x52	x52	x50
180  *
181  * *1 :	Table 7.4 indicates VCO output (PLL0 = VCO)
182  * *2 :	Table 7.4 indicates VCO output (PLL1 = VCO)
183  */
184 #define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 13) | \
185 					 (((md) & BIT(13)) >> 13))
186 
187 static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = {
188 	/* EXTAL div	PLL1 mult x2	PLL3 mult */
189 	{ 1,		156,		50,	},
190 	{ 1,		120,		56,	},
191 	{ /* Invalid*/				},
192 	{ 1,		104,		50,	},
193 };
194 
r8a77470_cpg_mssr_init(struct device * dev)195 static int __init r8a77470_cpg_mssr_init(struct device *dev)
196 {
197 	const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
198 	u32 cpg_mode;
199 	int error;
200 
201 	error = rcar_rst_read_mode_pins(&cpg_mode);
202 	if (error)
203 		return error;
204 
205 	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
206 
207 	return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
208 }
209 
210 const struct cpg_mssr_info r8a77470_cpg_mssr_info __initconst = {
211 	/* Core Clocks */
212 	.core_clks = r8a77470_core_clks,
213 	.num_core_clks = ARRAY_SIZE(r8a77470_core_clks),
214 	.last_dt_core_clk = LAST_DT_CORE_CLK,
215 	.num_total_core_clks = MOD_CLK_BASE,
216 
217 	/* Module Clocks */
218 	.mod_clks = r8a77470_mod_clks,
219 	.num_mod_clks = ARRAY_SIZE(r8a77470_mod_clks),
220 	.num_hw_mod_clks = 12 * 32,
221 
222 	/* Critical Module Clocks */
223 	.crit_mod_clks = r8a77470_crit_mod_clks,
224 	.num_crit_mod_clks = ARRAY_SIZE(r8a77470_crit_mod_clks),
225 
226 	/* Callbacks */
227 	.init = r8a77470_cpg_mssr_init,
228 	.cpg_clk_register = rcar_gen2_cpg_clk_register,
229 };
230