1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (C) 2024-2025 Haylen Chu <heylenay@outlook.com> 4 */ 5 6 #ifndef _DT_BINDINGS_SPACEMIT_CCU_H_ 7 #define _DT_BINDINGS_SPACEMIT_CCU_H_ 8 9 /* APBS (PLL) clocks */ 10 #define CLK_PLL1 0 11 #define CLK_PLL2 1 12 #define CLK_PLL3 2 13 #define CLK_PLL1_D2 3 14 #define CLK_PLL1_D3 4 15 #define CLK_PLL1_D4 5 16 #define CLK_PLL1_D5 6 17 #define CLK_PLL1_D6 7 18 #define CLK_PLL1_D7 8 19 #define CLK_PLL1_D8 9 20 #define CLK_PLL1_D11 10 21 #define CLK_PLL1_D13 11 22 #define CLK_PLL1_D23 12 23 #define CLK_PLL1_D64 13 24 #define CLK_PLL1_D10_AUD 14 25 #define CLK_PLL1_D100_AUD 15 26 #define CLK_PLL2_D1 16 27 #define CLK_PLL2_D2 17 28 #define CLK_PLL2_D3 18 29 #define CLK_PLL2_D4 19 30 #define CLK_PLL2_D5 20 31 #define CLK_PLL2_D6 21 32 #define CLK_PLL2_D7 22 33 #define CLK_PLL2_D8 23 34 #define CLK_PLL3_D1 24 35 #define CLK_PLL3_D2 25 36 #define CLK_PLL3_D3 26 37 #define CLK_PLL3_D4 27 38 #define CLK_PLL3_D5 28 39 #define CLK_PLL3_D6 29 40 #define CLK_PLL3_D7 30 41 #define CLK_PLL3_D8 31 42 #define CLK_PLL3_80 32 43 #define CLK_PLL3_40 33 44 #define CLK_PLL3_20 34 45 46 /* MPMU clocks */ 47 #define CLK_PLL1_307P2 0 48 #define CLK_PLL1_76P8 1 49 #define CLK_PLL1_61P44 2 50 #define CLK_PLL1_153P6 3 51 #define CLK_PLL1_102P4 4 52 #define CLK_PLL1_51P2 5 53 #define CLK_PLL1_51P2_AP 6 54 #define CLK_PLL1_57P6 7 55 #define CLK_PLL1_25P6 8 56 #define CLK_PLL1_12P8 9 57 #define CLK_PLL1_12P8_WDT 10 58 #define CLK_PLL1_6P4 11 59 #define CLK_PLL1_3P2 12 60 #define CLK_PLL1_1P6 13 61 #define CLK_PLL1_0P8 14 62 #define CLK_PLL1_409P6 15 63 #define CLK_PLL1_204P8 16 64 #define CLK_PLL1_491 17 65 #define CLK_PLL1_245P76 18 66 #define CLK_PLL1_614 19 67 #define CLK_PLL1_47P26 20 68 #define CLK_PLL1_31P5 21 69 #define CLK_PLL1_819 22 70 #define CLK_PLL1_1228 23 71 #define CLK_SLOW_UART 24 72 #define CLK_SLOW_UART1 25 73 #define CLK_SLOW_UART2 26 74 #define CLK_WDT 27 75 #define CLK_RIPC 28 76 #define CLK_I2S_SYSCLK 29 77 #define CLK_I2S_BCLK 30 78 #define CLK_APB 31 79 #define CLK_WDT_BUS 32 80 81 /* APBC clocks */ 82 #define CLK_UART0 0 83 #define CLK_UART2 1 84 #define CLK_UART3 2 85 #define CLK_UART4 3 86 #define CLK_UART5 4 87 #define CLK_UART6 5 88 #define CLK_UART7 6 89 #define CLK_UART8 7 90 #define CLK_UART9 8 91 #define CLK_GPIO 9 92 #define CLK_PWM0 10 93 #define CLK_PWM1 11 94 #define CLK_PWM2 12 95 #define CLK_PWM3 13 96 #define CLK_PWM4 14 97 #define CLK_PWM5 15 98 #define CLK_PWM6 16 99 #define CLK_PWM7 17 100 #define CLK_PWM8 18 101 #define CLK_PWM9 19 102 #define CLK_PWM10 20 103 #define CLK_PWM11 21 104 #define CLK_PWM12 22 105 #define CLK_PWM13 23 106 #define CLK_PWM14 24 107 #define CLK_PWM15 25 108 #define CLK_PWM16 26 109 #define CLK_PWM17 27 110 #define CLK_PWM18 28 111 #define CLK_PWM19 29 112 #define CLK_SSP3 30 113 #define CLK_RTC 31 114 #define CLK_TWSI0 32 115 #define CLK_TWSI1 33 116 #define CLK_TWSI2 34 117 #define CLK_TWSI4 35 118 #define CLK_TWSI5 36 119 #define CLK_TWSI6 37 120 #define CLK_TWSI7 38 121 #define CLK_TWSI8 39 122 #define CLK_TIMERS1 40 123 #define CLK_TIMERS2 41 124 #define CLK_AIB 42 125 #define CLK_ONEWIRE 43 126 #define CLK_SSPA0 44 127 #define CLK_SSPA1 45 128 #define CLK_DRO 46 129 #define CLK_IR 47 130 #define CLK_TSEN 48 131 #define CLK_IPC_AP2AUD 49 132 #define CLK_CAN0 50 133 #define CLK_CAN0_BUS 51 134 #define CLK_UART0_BUS 52 135 #define CLK_UART2_BUS 53 136 #define CLK_UART3_BUS 54 137 #define CLK_UART4_BUS 55 138 #define CLK_UART5_BUS 56 139 #define CLK_UART6_BUS 57 140 #define CLK_UART7_BUS 58 141 #define CLK_UART8_BUS 59 142 #define CLK_UART9_BUS 60 143 #define CLK_GPIO_BUS 61 144 #define CLK_PWM0_BUS 62 145 #define CLK_PWM1_BUS 63 146 #define CLK_PWM2_BUS 64 147 #define CLK_PWM3_BUS 65 148 #define CLK_PWM4_BUS 66 149 #define CLK_PWM5_BUS 67 150 #define CLK_PWM6_BUS 68 151 #define CLK_PWM7_BUS 69 152 #define CLK_PWM8_BUS 70 153 #define CLK_PWM9_BUS 71 154 #define CLK_PWM10_BUS 72 155 #define CLK_PWM11_BUS 73 156 #define CLK_PWM12_BUS 74 157 #define CLK_PWM13_BUS 75 158 #define CLK_PWM14_BUS 76 159 #define CLK_PWM15_BUS 77 160 #define CLK_PWM16_BUS 78 161 #define CLK_PWM17_BUS 79 162 #define CLK_PWM18_BUS 80 163 #define CLK_PWM19_BUS 81 164 #define CLK_SSP3_BUS 82 165 #define CLK_RTC_BUS 83 166 #define CLK_TWSI0_BUS 84 167 #define CLK_TWSI1_BUS 85 168 #define CLK_TWSI2_BUS 86 169 #define CLK_TWSI4_BUS 87 170 #define CLK_TWSI5_BUS 88 171 #define CLK_TWSI6_BUS 89 172 #define CLK_TWSI7_BUS 90 173 #define CLK_TWSI8_BUS 91 174 #define CLK_TIMERS1_BUS 92 175 #define CLK_TIMERS2_BUS 93 176 #define CLK_AIB_BUS 94 177 #define CLK_ONEWIRE_BUS 95 178 #define CLK_SSPA0_BUS 96 179 #define CLK_SSPA1_BUS 97 180 #define CLK_TSEN_BUS 98 181 #define CLK_IPC_AP2AUD_BUS 99 182 183 /* APMU clocks */ 184 #define CLK_CCI550 0 185 #define CLK_CPU_C0_HI 1 186 #define CLK_CPU_C0_CORE 2 187 #define CLK_CPU_C0_ACE 3 188 #define CLK_CPU_C0_TCM 4 189 #define CLK_CPU_C1_HI 5 190 #define CLK_CPU_C1_CORE 6 191 #define CLK_CPU_C1_ACE 7 192 #define CLK_CCIC_4X 8 193 #define CLK_CCIC1PHY 9 194 #define CLK_SDH_AXI 10 195 #define CLK_SDH0 11 196 #define CLK_SDH1 12 197 #define CLK_SDH2 13 198 #define CLK_USB_P1 14 199 #define CLK_USB_AXI 15 200 #define CLK_USB30 16 201 #define CLK_QSPI 17 202 #define CLK_QSPI_BUS 18 203 #define CLK_DMA 19 204 #define CLK_AES 20 205 #define CLK_VPU 21 206 #define CLK_GPU 22 207 #define CLK_EMMC 23 208 #define CLK_EMMC_X 24 209 #define CLK_AUDIO 25 210 #define CLK_HDMI 26 211 #define CLK_PMUA_ACLK 27 212 #define CLK_PCIE0_MASTER 28 213 #define CLK_PCIE0_SLAVE 29 214 #define CLK_PCIE0_DBI 30 215 #define CLK_PCIE1_MASTER 31 216 #define CLK_PCIE1_SLAVE 32 217 #define CLK_PCIE1_DBI 33 218 #define CLK_PCIE2_MASTER 34 219 #define CLK_PCIE2_SLAVE 35 220 #define CLK_PCIE2_DBI 36 221 #define CLK_EMAC0_BUS 37 222 #define CLK_EMAC0_PTP 38 223 #define CLK_EMAC1_BUS 39 224 #define CLK_EMAC1_PTP 40 225 #define CLK_JPG 41 226 #define CLK_CCIC2PHY 42 227 #define CLK_CCIC3PHY 43 228 #define CLK_CSI 44 229 #define CLK_CAMM0 45 230 #define CLK_CAMM1 46 231 #define CLK_CAMM2 47 232 #define CLK_ISP_CPP 48 233 #define CLK_ISP_BUS 49 234 #define CLK_ISP 50 235 #define CLK_DPU_MCLK 51 236 #define CLK_DPU_ESC 52 237 #define CLK_DPU_BIT 53 238 #define CLK_DPU_PXCLK 54 239 #define CLK_DPU_HCLK 55 240 #define CLK_DPU_SPI 56 241 #define CLK_DPU_SPI_HBUS 57 242 #define CLK_DPU_SPIBUS 58 243 #define CLK_DPU_SPI_ACLK 59 244 #define CLK_V2D 60 245 #define CLK_EMMC_BUS 61 246 247 #endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */ 248