19e288cefSKuninori Morimoto // SPDX-License-Identifier: GPL-2.0
22d75588aSGeert Uytterhoeven /*
32d75588aSGeert Uytterhoeven * r8a7794 Clock Pulse Generator / Module Standby and Software Reset
42d75588aSGeert Uytterhoeven *
52d75588aSGeert Uytterhoeven * Copyright (C) 2017 Glider bvba
62d75588aSGeert Uytterhoeven *
72d75588aSGeert Uytterhoeven * Based on clk-rcar-gen2.c
82d75588aSGeert Uytterhoeven *
92d75588aSGeert Uytterhoeven * Copyright (C) 2013 Ideas On Board SPRL
102d75588aSGeert Uytterhoeven */
112d75588aSGeert Uytterhoeven
122d75588aSGeert Uytterhoeven #include <linux/device.h>
132d75588aSGeert Uytterhoeven #include <linux/init.h>
142d75588aSGeert Uytterhoeven #include <linux/kernel.h>
152d75588aSGeert Uytterhoeven #include <linux/soc/renesas/rcar-rst.h>
162d75588aSGeert Uytterhoeven
172d75588aSGeert Uytterhoeven #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
182d75588aSGeert Uytterhoeven
192d75588aSGeert Uytterhoeven #include "renesas-cpg-mssr.h"
202d75588aSGeert Uytterhoeven #include "rcar-gen2-cpg.h"
212d75588aSGeert Uytterhoeven
222d75588aSGeert Uytterhoeven enum clk_ids {
232d75588aSGeert Uytterhoeven /* Core Clock Outputs exported to DT */
242d75588aSGeert Uytterhoeven LAST_DT_CORE_CLK = R8A7794_CLK_OSC,
252d75588aSGeert Uytterhoeven
262d75588aSGeert Uytterhoeven /* External Input Clocks */
272d75588aSGeert Uytterhoeven CLK_EXTAL,
282d75588aSGeert Uytterhoeven CLK_USB_EXTAL,
292d75588aSGeert Uytterhoeven
302d75588aSGeert Uytterhoeven /* Internal Core Clocks */
312d75588aSGeert Uytterhoeven CLK_MAIN,
322d75588aSGeert Uytterhoeven CLK_PLL0,
332d75588aSGeert Uytterhoeven CLK_PLL1,
342d75588aSGeert Uytterhoeven CLK_PLL3,
352d75588aSGeert Uytterhoeven CLK_PLL1_DIV2,
362d75588aSGeert Uytterhoeven
372d75588aSGeert Uytterhoeven /* Module Clocks */
382d75588aSGeert Uytterhoeven MOD_CLK_BASE
392d75588aSGeert Uytterhoeven };
402d75588aSGeert Uytterhoeven
412d75588aSGeert Uytterhoeven static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
422d75588aSGeert Uytterhoeven /* External Clock Inputs */
432d75588aSGeert Uytterhoeven DEF_INPUT("extal", CLK_EXTAL),
442d75588aSGeert Uytterhoeven DEF_INPUT("usb_extal", CLK_USB_EXTAL),
452d75588aSGeert Uytterhoeven
462d75588aSGeert Uytterhoeven /* Internal Core Clocks */
472d75588aSGeert Uytterhoeven DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
482d75588aSGeert Uytterhoeven DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
492d75588aSGeert Uytterhoeven DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
502d75588aSGeert Uytterhoeven DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
512d75588aSGeert Uytterhoeven
522d75588aSGeert Uytterhoeven DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
532d75588aSGeert Uytterhoeven
542d75588aSGeert Uytterhoeven /* Core Clock Outputs */
552d75588aSGeert Uytterhoeven DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
562d75588aSGeert Uytterhoeven DEF_BASE("sdh", R8A7794_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
572d75588aSGeert Uytterhoeven DEF_BASE("sd0", R8A7794_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
582d75588aSGeert Uytterhoeven DEF_BASE("qspi", R8A7794_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
592d75588aSGeert Uytterhoeven DEF_BASE("rcan", R8A7794_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
602d75588aSGeert Uytterhoeven
612d75588aSGeert Uytterhoeven DEF_FIXED("z2", R8A7794_CLK_Z2, CLK_PLL0, 1, 1),
622d75588aSGeert Uytterhoeven DEF_FIXED("zg", R8A7794_CLK_ZG, CLK_PLL1, 6, 1),
632d75588aSGeert Uytterhoeven DEF_FIXED("zx", R8A7794_CLK_ZX, CLK_PLL1, 3, 1),
642d75588aSGeert Uytterhoeven DEF_FIXED("zs", R8A7794_CLK_ZS, CLK_PLL1, 6, 1),
652d75588aSGeert Uytterhoeven DEF_FIXED("hp", R8A7794_CLK_HP, CLK_PLL1, 12, 1),
662d75588aSGeert Uytterhoeven DEF_FIXED("i", R8A7794_CLK_I, CLK_PLL1, 2, 1),
672d75588aSGeert Uytterhoeven DEF_FIXED("b", R8A7794_CLK_B, CLK_PLL1, 12, 1),
68279ebbcaSGeert Uytterhoeven DEF_FIXED("lb", R8A7794_CLK_LB, CLK_PLL1, 24, 1),
692d75588aSGeert Uytterhoeven DEF_FIXED("p", R8A7794_CLK_P, CLK_PLL1, 24, 1),
702d75588aSGeert Uytterhoeven DEF_FIXED("cl", R8A7794_CLK_CL, CLK_PLL1, 48, 1),
712d75588aSGeert Uytterhoeven DEF_FIXED("cp", R8A7794_CLK_CP, CLK_PLL1, 48, 1),
722d75588aSGeert Uytterhoeven DEF_FIXED("m2", R8A7794_CLK_M2, CLK_PLL1, 8, 1),
732d75588aSGeert Uytterhoeven DEF_FIXED("zb3", R8A7794_CLK_ZB3, CLK_PLL3, 4, 1),
742d75588aSGeert Uytterhoeven DEF_FIXED("zb3d2", R8A7794_CLK_ZB3D2, CLK_PLL3, 8, 1),
752d75588aSGeert Uytterhoeven DEF_FIXED("ddr", R8A7794_CLK_DDR, CLK_PLL3, 8, 1),
762d75588aSGeert Uytterhoeven DEF_FIXED("mp", R8A7794_CLK_MP, CLK_PLL1_DIV2, 15, 1),
772d75588aSGeert Uytterhoeven DEF_FIXED("cpex", R8A7794_CLK_CPEX, CLK_EXTAL, 2, 1),
782d75588aSGeert Uytterhoeven DEF_FIXED("r", R8A7794_CLK_R, CLK_PLL1, 49152, 1),
792d75588aSGeert Uytterhoeven DEF_FIXED("osc", R8A7794_CLK_OSC, CLK_PLL1, 12288, 1),
802d75588aSGeert Uytterhoeven
812d75588aSGeert Uytterhoeven DEF_DIV6P1("sd2", R8A7794_CLK_SD2, CLK_PLL1_DIV2, 0x078),
822d75588aSGeert Uytterhoeven DEF_DIV6P1("sd3", R8A7794_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
832d75588aSGeert Uytterhoeven DEF_DIV6P1("mmc0", R8A7794_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
842d75588aSGeert Uytterhoeven };
852d75588aSGeert Uytterhoeven
862d75588aSGeert Uytterhoeven static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
872d75588aSGeert Uytterhoeven DEF_MOD("msiof0", 0, R8A7794_CLK_MP),
882d75588aSGeert Uytterhoeven DEF_MOD("vcp0", 101, R8A7794_CLK_ZS),
892d75588aSGeert Uytterhoeven DEF_MOD("vpc0", 103, R8A7794_CLK_ZS),
902d75588aSGeert Uytterhoeven DEF_MOD("jpu", 106, R8A7794_CLK_M2),
912d75588aSGeert Uytterhoeven DEF_MOD("tmu1", 111, R8A7794_CLK_P),
922d75588aSGeert Uytterhoeven DEF_MOD("3dg", 112, R8A7794_CLK_ZG),
932d75588aSGeert Uytterhoeven DEF_MOD("2d-dmac", 115, R8A7794_CLK_ZS),
942d75588aSGeert Uytterhoeven DEF_MOD("fdp1-0", 119, R8A7794_CLK_ZS),
952d75588aSGeert Uytterhoeven DEF_MOD("tmu3", 121, R8A7794_CLK_P),
962d75588aSGeert Uytterhoeven DEF_MOD("tmu2", 122, R8A7794_CLK_P),
972d75588aSGeert Uytterhoeven DEF_MOD("cmt0", 124, R8A7794_CLK_R),
982d75588aSGeert Uytterhoeven DEF_MOD("tmu0", 125, R8A7794_CLK_CP),
992d75588aSGeert Uytterhoeven DEF_MOD("vsp1du0", 128, R8A7794_CLK_ZS),
100*e41cb217SLad Prabhakar DEF_MOD("vsps", 131, R8A7794_CLK_ZS),
1012d75588aSGeert Uytterhoeven DEF_MOD("scifa2", 202, R8A7794_CLK_MP),
1022d75588aSGeert Uytterhoeven DEF_MOD("scifa1", 203, R8A7794_CLK_MP),
1032d75588aSGeert Uytterhoeven DEF_MOD("scifa0", 204, R8A7794_CLK_MP),
1042d75588aSGeert Uytterhoeven DEF_MOD("msiof2", 205, R8A7794_CLK_MP),
1052d75588aSGeert Uytterhoeven DEF_MOD("scifb0", 206, R8A7794_CLK_MP),
1062d75588aSGeert Uytterhoeven DEF_MOD("scifb1", 207, R8A7794_CLK_MP),
1072d75588aSGeert Uytterhoeven DEF_MOD("msiof1", 208, R8A7794_CLK_MP),
1082d75588aSGeert Uytterhoeven DEF_MOD("scifb2", 216, R8A7794_CLK_MP),
1092d75588aSGeert Uytterhoeven DEF_MOD("sys-dmac1", 218, R8A7794_CLK_ZS),
1102d75588aSGeert Uytterhoeven DEF_MOD("sys-dmac0", 219, R8A7794_CLK_ZS),
1112d75588aSGeert Uytterhoeven DEF_MOD("tpu0", 304, R8A7794_CLK_CP),
1122d75588aSGeert Uytterhoeven DEF_MOD("sdhi3", 311, R8A7794_CLK_SD3),
1132d75588aSGeert Uytterhoeven DEF_MOD("sdhi2", 312, R8A7794_CLK_SD2),
1142d75588aSGeert Uytterhoeven DEF_MOD("sdhi0", 314, R8A7794_CLK_SD0),
1152d75588aSGeert Uytterhoeven DEF_MOD("mmcif0", 315, R8A7794_CLK_MMC0),
1162d75588aSGeert Uytterhoeven DEF_MOD("iic0", 318, R8A7794_CLK_HP),
1172d75588aSGeert Uytterhoeven DEF_MOD("iic1", 323, R8A7794_CLK_HP),
1182d75588aSGeert Uytterhoeven DEF_MOD("cmt1", 329, R8A7794_CLK_R),
1192d75588aSGeert Uytterhoeven DEF_MOD("usbhs-dmac0", 330, R8A7794_CLK_HP),
1202d75588aSGeert Uytterhoeven DEF_MOD("usbhs-dmac1", 331, R8A7794_CLK_HP),
121c43d8630SFabrizio Castro DEF_MOD("rwdt", 402, R8A7794_CLK_R),
1222d75588aSGeert Uytterhoeven DEF_MOD("irqc", 407, R8A7794_CLK_CP),
1232d75588aSGeert Uytterhoeven DEF_MOD("intc-sys", 408, R8A7794_CLK_ZS),
1242d75588aSGeert Uytterhoeven DEF_MOD("audio-dmac0", 502, R8A7794_CLK_HP),
1252d75588aSGeert Uytterhoeven DEF_MOD("adsp_mod", 506, R8A7794_CLK_ADSP),
1262d75588aSGeert Uytterhoeven DEF_MOD("pwm", 523, R8A7794_CLK_P),
1272d75588aSGeert Uytterhoeven DEF_MOD("usb-ehci", 703, R8A7794_CLK_MP),
1282d75588aSGeert Uytterhoeven DEF_MOD("usbhs", 704, R8A7794_CLK_HP),
1292d75588aSGeert Uytterhoeven DEF_MOD("hscif2", 713, R8A7794_CLK_ZS),
1302d75588aSGeert Uytterhoeven DEF_MOD("scif5", 714, R8A7794_CLK_P),
1312d75588aSGeert Uytterhoeven DEF_MOD("scif4", 715, R8A7794_CLK_P),
1322d75588aSGeert Uytterhoeven DEF_MOD("hscif1", 716, R8A7794_CLK_ZS),
1332d75588aSGeert Uytterhoeven DEF_MOD("hscif0", 717, R8A7794_CLK_ZS),
1342d75588aSGeert Uytterhoeven DEF_MOD("scif3", 718, R8A7794_CLK_P),
1352d75588aSGeert Uytterhoeven DEF_MOD("scif2", 719, R8A7794_CLK_P),
1362d75588aSGeert Uytterhoeven DEF_MOD("scif1", 720, R8A7794_CLK_P),
1372d75588aSGeert Uytterhoeven DEF_MOD("scif0", 721, R8A7794_CLK_P),
1382d75588aSGeert Uytterhoeven DEF_MOD("du1", 723, R8A7794_CLK_ZX),
1392d75588aSGeert Uytterhoeven DEF_MOD("du0", 724, R8A7794_CLK_ZX),
1402d75588aSGeert Uytterhoeven DEF_MOD("ipmmu-sgx", 800, R8A7794_CLK_ZX),
1412d75588aSGeert Uytterhoeven DEF_MOD("mlb", 802, R8A7794_CLK_HP),
1422d75588aSGeert Uytterhoeven DEF_MOD("vin1", 810, R8A7794_CLK_ZG),
1432d75588aSGeert Uytterhoeven DEF_MOD("vin0", 811, R8A7794_CLK_ZG),
1442d75588aSGeert Uytterhoeven DEF_MOD("etheravb", 812, R8A7794_CLK_HP),
1452d75588aSGeert Uytterhoeven DEF_MOD("ether", 813, R8A7794_CLK_P),
1462d75588aSGeert Uytterhoeven DEF_MOD("gyro-adc", 901, R8A7794_CLK_P),
1472d75588aSGeert Uytterhoeven DEF_MOD("gpio6", 905, R8A7794_CLK_CP),
1482d75588aSGeert Uytterhoeven DEF_MOD("gpio5", 907, R8A7794_CLK_CP),
1492d75588aSGeert Uytterhoeven DEF_MOD("gpio4", 908, R8A7794_CLK_CP),
1502d75588aSGeert Uytterhoeven DEF_MOD("gpio3", 909, R8A7794_CLK_CP),
1512d75588aSGeert Uytterhoeven DEF_MOD("gpio2", 910, R8A7794_CLK_CP),
1522d75588aSGeert Uytterhoeven DEF_MOD("gpio1", 911, R8A7794_CLK_CP),
1532d75588aSGeert Uytterhoeven DEF_MOD("gpio0", 912, R8A7794_CLK_CP),
1542d75588aSGeert Uytterhoeven DEF_MOD("can1", 915, R8A7794_CLK_P),
1552d75588aSGeert Uytterhoeven DEF_MOD("can0", 916, R8A7794_CLK_P),
1562d75588aSGeert Uytterhoeven DEF_MOD("qspi_mod", 917, R8A7794_CLK_QSPI),
1572d75588aSGeert Uytterhoeven DEF_MOD("i2c5", 925, R8A7794_CLK_HP),
1582d75588aSGeert Uytterhoeven DEF_MOD("i2c4", 927, R8A7794_CLK_HP),
1592d75588aSGeert Uytterhoeven DEF_MOD("i2c3", 928, R8A7794_CLK_HP),
1602d75588aSGeert Uytterhoeven DEF_MOD("i2c2", 929, R8A7794_CLK_HP),
1612d75588aSGeert Uytterhoeven DEF_MOD("i2c1", 930, R8A7794_CLK_HP),
1622d75588aSGeert Uytterhoeven DEF_MOD("i2c0", 931, R8A7794_CLK_HP),
1632d75588aSGeert Uytterhoeven DEF_MOD("ssi-all", 1005, R8A7794_CLK_P),
1642d75588aSGeert Uytterhoeven DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
1652d75588aSGeert Uytterhoeven DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
1662d75588aSGeert Uytterhoeven DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
1672d75588aSGeert Uytterhoeven DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
1682d75588aSGeert Uytterhoeven DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
1692d75588aSGeert Uytterhoeven DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
1702d75588aSGeert Uytterhoeven DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
1712d75588aSGeert Uytterhoeven DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
1722d75588aSGeert Uytterhoeven DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
1732d75588aSGeert Uytterhoeven DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
1742d75588aSGeert Uytterhoeven DEF_MOD("scu-all", 1017, R8A7794_CLK_P),
1752d75588aSGeert Uytterhoeven DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
1762d75588aSGeert Uytterhoeven DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
1772d75588aSGeert Uytterhoeven DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
1782d75588aSGeert Uytterhoeven DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
1792d75588aSGeert Uytterhoeven DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
1802d75588aSGeert Uytterhoeven DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
1812d75588aSGeert Uytterhoeven DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
1822d75588aSGeert Uytterhoeven DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
1832d75588aSGeert Uytterhoeven DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
1842d75588aSGeert Uytterhoeven DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
1852d75588aSGeert Uytterhoeven DEF_MOD("scifa3", 1106, R8A7794_CLK_MP),
1862d75588aSGeert Uytterhoeven DEF_MOD("scifa4", 1107, R8A7794_CLK_MP),
1872d75588aSGeert Uytterhoeven DEF_MOD("scifa5", 1108, R8A7794_CLK_MP),
1882d75588aSGeert Uytterhoeven };
1892d75588aSGeert Uytterhoeven
1902d75588aSGeert Uytterhoeven static const unsigned int r8a7794_crit_mod_clks[] __initconst = {
191c43d8630SFabrizio Castro MOD_CLK_ID(402), /* RWDT */
1922d75588aSGeert Uytterhoeven MOD_CLK_ID(408), /* INTC-SYS (GIC) */
1932d75588aSGeert Uytterhoeven };
1942d75588aSGeert Uytterhoeven
1952d75588aSGeert Uytterhoeven /*
1962d75588aSGeert Uytterhoeven * CPG Clock Data
1972d75588aSGeert Uytterhoeven */
1982d75588aSGeert Uytterhoeven
1992d75588aSGeert Uytterhoeven /*
2002d75588aSGeert Uytterhoeven * MD EXTAL PLL0 PLL1 PLL3
2012d75588aSGeert Uytterhoeven * 14 13 19 (MHz) *1 *2
2022d75588aSGeert Uytterhoeven *---------------------------------------------------
2032d75588aSGeert Uytterhoeven * 0 0 1 15 x200/3 x208/2 x88
2042d75588aSGeert Uytterhoeven * 0 1 1 20 x150/3 x156/2 x66
2052d75588aSGeert Uytterhoeven * 1 0 1 26 / 2 x230/3 x240/2 x102
2062d75588aSGeert Uytterhoeven * 1 1 1 30 / 2 x200/3 x208/2 x88
2072d75588aSGeert Uytterhoeven *
2082d75588aSGeert Uytterhoeven * *1 : Table 7.5c indicates VCO output (PLL0 = VCO/3)
2092d75588aSGeert Uytterhoeven * *2 : Table 7.5c indicates VCO output (PLL1 = VCO/2)
2102d75588aSGeert Uytterhoeven */
2112d75588aSGeert Uytterhoeven #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
2122d75588aSGeert Uytterhoeven (((md) & BIT(13)) >> 13))
2132d75588aSGeert Uytterhoeven static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = {
2142d75588aSGeert Uytterhoeven { 1, 208, 88, 200 },
2152d75588aSGeert Uytterhoeven { 1, 156, 66, 150 },
2162d75588aSGeert Uytterhoeven { 2, 240, 102, 230 },
2172d75588aSGeert Uytterhoeven { 2, 208, 88, 200 },
2182d75588aSGeert Uytterhoeven };
2192d75588aSGeert Uytterhoeven
r8a7794_cpg_mssr_init(struct device * dev)2202d75588aSGeert Uytterhoeven static int __init r8a7794_cpg_mssr_init(struct device *dev)
2212d75588aSGeert Uytterhoeven {
2222d75588aSGeert Uytterhoeven const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
2232d75588aSGeert Uytterhoeven u32 cpg_mode;
2242d75588aSGeert Uytterhoeven int error;
2252d75588aSGeert Uytterhoeven
2262d75588aSGeert Uytterhoeven error = rcar_rst_read_mode_pins(&cpg_mode);
2272d75588aSGeert Uytterhoeven if (error)
2282d75588aSGeert Uytterhoeven return error;
2292d75588aSGeert Uytterhoeven
2302d75588aSGeert Uytterhoeven cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
2312d75588aSGeert Uytterhoeven
2322d75588aSGeert Uytterhoeven return rcar_gen2_cpg_init(cpg_pll_config, 3, cpg_mode);
2332d75588aSGeert Uytterhoeven }
2342d75588aSGeert Uytterhoeven
2352d75588aSGeert Uytterhoeven const struct cpg_mssr_info r8a7794_cpg_mssr_info __initconst = {
2362d75588aSGeert Uytterhoeven /* Core Clocks */
2372d75588aSGeert Uytterhoeven .core_clks = r8a7794_core_clks,
2382d75588aSGeert Uytterhoeven .num_core_clks = ARRAY_SIZE(r8a7794_core_clks),
2392d75588aSGeert Uytterhoeven .last_dt_core_clk = LAST_DT_CORE_CLK,
2402d75588aSGeert Uytterhoeven .num_total_core_clks = MOD_CLK_BASE,
2412d75588aSGeert Uytterhoeven
2422d75588aSGeert Uytterhoeven /* Module Clocks */
2432d75588aSGeert Uytterhoeven .mod_clks = r8a7794_mod_clks,
2442d75588aSGeert Uytterhoeven .num_mod_clks = ARRAY_SIZE(r8a7794_mod_clks),
2452d75588aSGeert Uytterhoeven .num_hw_mod_clks = 12 * 32,
2462d75588aSGeert Uytterhoeven
2472d75588aSGeert Uytterhoeven /* Critical Module Clocks */
2482d75588aSGeert Uytterhoeven .crit_mod_clks = r8a7794_crit_mod_clks,
2492d75588aSGeert Uytterhoeven .num_crit_mod_clks = ARRAY_SIZE(r8a7794_crit_mod_clks),
2502d75588aSGeert Uytterhoeven
2512d75588aSGeert Uytterhoeven /* Callbacks */
2522d75588aSGeert Uytterhoeven .init = r8a7794_cpg_mssr_init,
2532d75588aSGeert Uytterhoeven .cpg_clk_register = rcar_gen2_cpg_clk_register,
2542d75588aSGeert Uytterhoeven };
255