zynq\-can\-1 (full) in projects: freebsd

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Searched +full:zynq +full:- +full:can +full:- +full:1 (Results 1 – 25 of 28) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/net/can/
H A D	xilinx_can.txt	1 Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings 2 --------------------------------------------------------- 5 - compatible : Should be: 6 - "xlnx,zynq-can-1.0" for Zynq CAN controllers 7 - "xlnx,axi-can-1.00.a" for Axi CAN controllers 8 - "xlnx,canfd-1.0" for CAN FD controllers 9 - "xlnx,canfd-2.0" for CAN FD 2.0 controllers 10 - reg : Physical base address and size of the controller 12 - interrupts : Property with a value describing the interrupt 14 - clock-names : List of input clock names [all …]
H A D	xilinx,can.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/net/can/xilinx,can.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 Xilinx CAN and CANFD controller 11 - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> 16 - xlnx,zynq-can-1.0 17 - xlnx,axi-can-1.00.a 18 - xlnx,canfd-1.0 19 - xlnx,canfd-2.0 [all …]`
H A D	ctu,ctucanfd.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/net/can/ctu,ctucanfd.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: CTU CAN FD Open-source IP Core 10 Open-source CAN FD IP core developed at the Czech Technical University in Prague 13 [1] sources : https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core 16 Integration in Xilinx Zynq SoC based system together with 18 [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top 21 …https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-… [all …]
/freebsd/sys/contrib/device-tree/src/arm/xilinx/
H A D	zynq-7000.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2011 - 2014 Xilinx 7 #address-cells = <1>; 8 #size-cells = <1>; 9 compatible = "xlnx,zynq-7000"; 12 #address-cells = <1>; 13 #size-cells = <0>; 16 compatible = "arm,cortex-a9"; 20 clock-latency = <1000>; 21 cpu0-supply = <&regulator_vccpint>; [all …]`
/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A D	xilinx-xadc.txt	6 The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx. 8 frontends for the DRP interface exist. One that is only available on the ZYNQ 9 family as a hardmacro in the SoC portion of the ZYNQ. The other one is available 16 communication. Xilinx provides a standard IP core that can be used to access the 22 - compatible: Should be one of 23 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device 25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to 27 * "xlnx,system-management-wiz-1.3": When using the 30 - reg: Address and length of the register set for the device 31 - interrupts: Interrupt for the XADC control interface. [all …]
H A D	xlnx,zynqmp-ams.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/iio/adc/xlnx,zynqmp-am [all...]`
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A D	xlnx,pinctrl-zynq.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/xlnx,pinctrl-zynq.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Xilinx Zynq Pinctrl 10 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> 13 Please refer to pinctrl-bindings.txt in this directory for details of the 17 Zynq's pin configuration nodes act as a container for an arbitrary number of 19 pin, a group, or a list of pins or groups. This configuration can include the 21 parameters, such as pull-up, slew rate, etc. [all …]
H A D	xlnx,zynq-pinctrl.yaml	`1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/xlnx,zynq [all...]`
H A D	xlnx,zynq-pinctrl.txt	1 Binding for Xilinx Zynq Pinctrl 4 - compatible: "xlnx,zynq-pinctrl" 5 - syscon: phandle to SLCR 6 - reg: Offset and length of pinctrl space in SLCR 8 Please refer to pinctrl-bindings.txt in this directory for details of the 12 Zynq's pin configuration nodes act as a container for an arbitrary number of 14 pin, a group, or a list of pins or groups. This configuration can include the 16 parameters, such as pull-up, slew rate, etc. 18 Each configuration node can consist of multiple nodes describing the pinmux and 19 pinconf options. Those nodes can be pinmux nodes or pinconf nodes. [all …]
/freebsd/share/man/man4/
H A D	cgem.4	`8 .\" 1. Redistributions of source code must retain the above copyright 35 .Bd -ragged -offset indent 45 the Xilinx Zynq-7000, the Xilinx Zynq UltraScale+, and the SiFive 51 .Bl -tag -width ".Cm 10baseT/UTP" 54 The user can manually override 64 option can also be used to select either 65 .Cm full-duplex 67 .Cm half-duplex 74 option can also be used to select either 75 .Cm full-duplex [all …]`
/freebsd/sys/contrib/device-tree/Bindings/net/
H A D	cdns,macb.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Nicolas Ferre <nicolas.ferre@microchip.com> 11 - Claudiu Beznea <claudiu.beznea@microchip.com> 16 - items: 17 - enum: 18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC 19 - const: cdns,emac # Generic 21 - items: [all …]`
/freebsd/share/man/man4/man4.arm/
H A D	devcfg.4	8 .\" 1. Redistributions of source code must retain the above copyright 30 .Nd Zynq PL device config interface 36 can be used to configure the PL (FPGA) section of the Xilinx Zynq-7000. 41 asserts the top-level PL reset signals, disables the PS-PL level shifters, 45 shifters and release the top-level PL reset signals. 47 The PL (FPGA) can be configured by writing the bitstream to the character 49 .Bd -literal -offset indent 58 tool can do the conversion: 59 .Bd -literal -offset indent 60 promgen -b -w -p bin -data_width 32 -u 0 design.bit -o design.bit.bin [all …]
/freebsd/sys/arm/xilinx/
H A D	zy7_gpio.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 10 * 1. Redistributions of source code must retain the above copyright 30 * A GPIO driver for Xilinx Zynq-7000. 32 * The GPIO peripheral on Zynq allows controlling 114 general purpose I/Os. 34 * Pins 53-0 are sent to the MIO. Any MIO pins not used by a PS peripheral are 35 * available as a GPIO pin. Pins 64-127 are sent to the PL (FPGA) section of 36 * Zynq as EMIO signals. 41 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 71 /* Zynq 7000 */ [all …]
H A D	zy7_slcr.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 10 * 1. Redistributions of source code must retain the above copyright 30 * Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff. 33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 66 #define ZSLCR_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 67 #define ZSLCR_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 69 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \ 71 #define ZSLCR_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 73 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) [all …]
H A D	zy7_ehci.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (c) 2012-2013 Thomas Skibo 10 * 1. Redistributions of source code must retain the above copyright 30 * A host-controller driver for Zynq-7000's USB OTG controller. 32 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 100 #define ZY7_USB_ULPI_VIEWPORT_WU (1<<31) 101 #define ZY7_USB_ULPI_VIEWPORT_RUN (1<<30) 102 #define ZY7_USB_ULPI_VIEWPORT_RW (1<<29) 103 #define ZY7_USB_ULPI_VIEWPORT_SS (1<<27) [all …]`
H A D	zy7_qspi.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 10 * 1. Redistributions of source code must retain the above copyright 31 * This is a driver for the Quad-SPI Flash Controller in the Xilinx 32 * Zynq-7000 SoC. 63 {"xlnx,zy7_qspi", 1}, 64 {"xlnx,zynq-qspi-1.0", 1}, 98 #define QSPI_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 99 #define QSPI_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 101 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), NULL, MTX_DEF) [all …]`
H A D	zy7_spi.c	`1 /- 8 1. Redistributions of source code must retain the above copyright 53 {"xlnx,zy7_spi", 1}, 54 {"xlnx,zynq-spi-1.0", 1}, 55 {"cdns,spi-r1p6", 1}, 85 #define SPI_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 86 #define SPI_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 88 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), NULL, MTX_DEF) 89 #define SPI_SC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx) 90 #define SPI_SC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) [all …]`
/freebsd/sys/contrib/device-tree/Bindings/fpga/
H A D	fpga-region.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Michal Simek <michal.simek@amd.com> 14 - Introduction 15 - Terminology 16 - Sequence 17 - FPGA Region 18 - Supported Use Models [all …]`
H A D	fpga-region.txt	`6 - Introduction 7 - Terminology 8 - Sequence 9 - FPGA Region 10 - Supported Use Models 11 - Device Tree Examples 12 - Constraints 82 --- [all...]`
/freebsd/sys/contrib/device-tree/Bindings/firmware/xilinx/
H A D	xlnx,zynqmp-firmware.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Nava kishore Manne <nava.kishore.manne@amd.com> 12 description: The zynqmp-firmware node describes the interface to platform 15 can be used by any driver to communicate to PMUFW(Platform Management Unit). 23 - description: For implementations complying for Zynq Ultrascale+ MPSoC. 24 const: xlnx,zynqmp-firmware 26 - description: For implementations complying for Versal. [all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A D	ci-hdrc-usb2.txt	`4 - compatible: should be one of: 5 "fsl,imx23-usb" 6 "fsl,imx27-usb" 7 "fsl,imx28-usb" 8 "fsl,imx6q-usb" 9 "fsl,imx6sl-usb" 10 "fsl,imx6sx-usb" 11 "fsl,imx6ul-usb" 12 "fsl,imx7d-usb" 13 "fsl,imx7ulp-usb" [all …]`
/freebsd/sys/contrib/device-tree/Bindings/display/
H A D	xylon,logicvc-display.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com> 16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs. 20 synthesis time. As a result, many of the device-tree bindings are meant to 24 Layers are declared in the "layers" sub-node and have dedicated configuration. 32 - xylon,logicvc-3.02.a-display 33 - xylon,logicvc-4.01.a-display [all …]
/freebsd/sys/dev/cadence/
H A D	if_cgem.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (c) 2012-2014 Thomas Skibo <thomasskibo@yahoo.com> 10 * 1. Redistributions of source code must retain the above copyright 31 * interface such as the one used in Xilinx Zynq-7000 SoC. 33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 102 #define HWQUIRK_NEEDNULLQS 1 106 { "cdns,zynq-gem", HWQUIRK_RXHANGWAR }, /* Deprecated / 107 { "cdns,zynqmp-gem", HWQUIRK_NEEDNULLQS }, / Deprecated */ 108 { "xlnx,zynq-gem", HWQUIRK_RXHANGWAR }, [all …]
/freebsd/sys/dev/iicbus/controller/cadence/
H A D	cdnc_i2c.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (c) 2019-2020 Thomas Skibo <thomasskibo@yahoo.com> 9 * 1. Redistributions of source code must retain the above copyright 28 /* Cadence / Zynq i2c driver. 30 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 31 * (v1.12.2) July 1, 2018. Xilinx doc UG585. I2C Controller is documented 69 #define HWTYPE_CDNS_R1P10 1 75 {"cdns,i2c-r1p10", HWTYPE_CDNS_R1P10}, 77 {"cdns,i2c-r1p14", HWTYPE_CDNS_R1P14}, [all …]`
/freebsd/sys/dev/sdhci/
H A D	sdhci_fdt.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 11 * 1. Redistributions of source code must retain the above copyright 70 #define SDHCI_FDT_ARMADA38X 1 75 { "marvell,armada-380-sdhci", SDHCI_FDT_ARMADA38X }, 76 { "qcom,sdhci-msm-v4", SDHCI_FDT_QUALCOMM }, 106 int id = 1; /* Our clock id starts at 1 */ in sdhci_clock_ofw_map() 109 id = cells[1]; in sdhci_clock_ofw_map() 130 node = ofw_bus_get_node(sc->dev); in sdhci_export_clocks() 133 device_printf(sc->dev, "cannot parse 'reg' property\n"); in sdhci_export_clocks() [all …]