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8 .\" 1. Redistributions of source code must retain the above copyright
30 .Nd Zynq PL device config interface
36 can be used to configure the PL (FPGA) section of the Xilinx Zynq-7000.
41 asserts the top-level PL reset signals, disables the PS-PL level shifters,
45 shifters and release the top-level PL reset signals.
47 The PL (FPGA) can be configured by writing the bitstream to the character
49 .Bd -literal -offset indent
58 tool can do the conversion:
59 .Bd -literal -offset indent
60 promgen -b -w -p bin -data_width 32 -u 0 design.bit -o design.bit.bin
68 .Bl -tag -width 4n
72 A 1 means the PL section has been properly programmed.
75 This variable controls if the PS-PL level shifters are enabled after the
77 This variable is 1 by default but setting it to 0 allows the PL section to be
84 .Bl -tag -width 12n
91 Zynq-7000 SoC Technical Reference Manual (Xilinx doc UG585)