xref: /freebsd/sys/contrib/device-tree/Bindings/net/can/ctu,ctucanfd.yaml (revision 8bab661a3316d8bd9b9fbd11a3b4371b91507bd2)
1d5b0e70fSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2d5b0e70fSEmmanuel Vadot%YAML 1.2
3d5b0e70fSEmmanuel Vadot---
4d5b0e70fSEmmanuel Vadot$id: http://devicetree.org/schemas/net/can/ctu,ctucanfd.yaml#
5d5b0e70fSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml#
6d5b0e70fSEmmanuel Vadot
7*8bab661aSEmmanuel Vadottitle: CTU CAN FD Open-source IP Core
8d5b0e70fSEmmanuel Vadot
9d5b0e70fSEmmanuel Vadotdescription: |
10d5b0e70fSEmmanuel Vadot  Open-source CAN FD IP core developed at the Czech Technical University in Prague
11d5b0e70fSEmmanuel Vadot
12d5b0e70fSEmmanuel Vadot  The core sources and documentation on project page
13d5b0e70fSEmmanuel Vadot    [1] sources : https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core
14d5b0e70fSEmmanuel Vadot    [2] datasheet : https://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/Datasheet.pdf
15d5b0e70fSEmmanuel Vadot
16d5b0e70fSEmmanuel Vadot  Integration in Xilinx Zynq SoC based system together with
17d5b0e70fSEmmanuel Vadot  OpenCores SJA1000 compatible controllers
18d5b0e70fSEmmanuel Vadot    [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top
19d5b0e70fSEmmanuel Vadot  Martin Jerabek dimploma thesis with integration and testing
20d5b0e70fSEmmanuel Vadot  framework description
21d5b0e70fSEmmanuel Vadot    [4] PDF : https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-canfd.pdf
22d5b0e70fSEmmanuel Vadot
23d5b0e70fSEmmanuel Vadotmaintainers:
24d5b0e70fSEmmanuel Vadot  - Pavel Pisa <pisa@cmp.felk.cvut.cz>
25d5b0e70fSEmmanuel Vadot  - Ondrej Ille <ondrej.ille@gmail.com>
26d5b0e70fSEmmanuel Vadot  - Martin Jerabek <martin.jerabek01@gmail.com>
27d5b0e70fSEmmanuel Vadot
28d5b0e70fSEmmanuel VadotallOf:
29d5b0e70fSEmmanuel Vadot  - $ref: can-controller.yaml#
30d5b0e70fSEmmanuel Vadot
31d5b0e70fSEmmanuel Vadotproperties:
32d5b0e70fSEmmanuel Vadot  compatible:
33d5b0e70fSEmmanuel Vadot    oneOf:
34d5b0e70fSEmmanuel Vadot      - items:
35d5b0e70fSEmmanuel Vadot          - const: ctu,ctucanfd-2
36d5b0e70fSEmmanuel Vadot          - const: ctu,ctucanfd
37d5b0e70fSEmmanuel Vadot      - const: ctu,ctucanfd
38d5b0e70fSEmmanuel Vadot
39d5b0e70fSEmmanuel Vadot  reg:
40d5b0e70fSEmmanuel Vadot    maxItems: 1
41d5b0e70fSEmmanuel Vadot
42d5b0e70fSEmmanuel Vadot  interrupts:
43d5b0e70fSEmmanuel Vadot    maxItems: 1
44d5b0e70fSEmmanuel Vadot
45d5b0e70fSEmmanuel Vadot  clocks:
46d5b0e70fSEmmanuel Vadot    description: |
47d5b0e70fSEmmanuel Vadot      phandle of reference clock (100 MHz is appropriate
48d5b0e70fSEmmanuel Vadot      for FPGA implementation on Zynq-7000 system).
49d5b0e70fSEmmanuel Vadot    maxItems: 1
50d5b0e70fSEmmanuel Vadot
51d5b0e70fSEmmanuel Vadotrequired:
52d5b0e70fSEmmanuel Vadot  - compatible
53d5b0e70fSEmmanuel Vadot  - reg
54d5b0e70fSEmmanuel Vadot  - interrupts
55d5b0e70fSEmmanuel Vadot  - clocks
56d5b0e70fSEmmanuel Vadot
57d5b0e70fSEmmanuel VadotadditionalProperties: false
58d5b0e70fSEmmanuel Vadot
59d5b0e70fSEmmanuel Vadotexamples:
60d5b0e70fSEmmanuel Vadot  - |
61d5b0e70fSEmmanuel Vadot    ctu_can_fd_0: can@43c30000 {
62d5b0e70fSEmmanuel Vadot      compatible = "ctu,ctucanfd";
63d5b0e70fSEmmanuel Vadot      interrupts = <0 30 4>;
64d5b0e70fSEmmanuel Vadot      clocks = <&clkc 15>;
65d5b0e70fSEmmanuel Vadot      reg = <0x43c30000 0x10000>;
66d5b0e70fSEmmanuel Vadot    };
67