1 Binding for Xilinx Zynq Pinctrl 2 3Required properties: 4- compatible: "xlnx,zynq-pinctrl" 5- syscon: phandle to SLCR 6- reg: Offset and length of pinctrl space in SLCR 7 8Please refer to pinctrl-bindings.txt in this directory for details of the 9common pinctrl bindings used by client devices, including the meaning of the 10phrase "pin configuration node". 11 12Zynq's pin configuration nodes act as a container for an arbitrary number of 13subnodes. Each of these subnodes represents some desired configuration for a 14pin, a group, or a list of pins or groups. This configuration can include the 15mux function to select on those pin(s)/group(s), and various pin configuration 16parameters, such as pull-up, slew rate, etc. 17 18Each configuration node can consist of multiple nodes describing the pinmux and 19pinconf options. Those nodes can be pinmux nodes or pinconf nodes. 20 21The name of each subnode is not important; all subnodes should be enumerated 22and processed purely based on their content. 23 24Required properties for pinmux nodes are: 25 - groups: A list of pinmux groups. 26 - function: The name of a pinmux function to activate for the specified set 27 of groups. 28 29Required properties for configuration nodes: 30One of: 31 - pins: a list of pin names 32 - groups: A list of pinmux groups. 33 34The following generic properties as defined in pinctrl-bindings.txt are valid 35to specify in a pinmux subnode: 36 groups, function 37 38The following generic properties as defined in pinctrl-bindings.txt are valid 39to specify in a pinconf subnode: 40 groups, pins, bias-disable, bias-high-impedance, bias-pull-up, slew-rate, 41 low-power-disable, low-power-enable 42 43 Valid arguments for 'slew-rate' are '0' and '1' to select between slow and fast 44 respectively. 45 46 Valid values for groups are: 47 ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, mdio1_0_grp, 48 qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp - spi0_2_grp, 49 spi0_X_ssY (X=0..2, Y=0..2), spi1_0_grp - spi1_3_grp, 50 spi1_X_ssY (X=0..3, Y=0..2), sdio0_0_grp - sdio0_2_grp, 51 sdio1_0_grp - sdio1_3_grp, sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp, 52 sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, smc0_nor_addr25_grp, smc0_nand, 53 can0_0_grp - can0_10_grp, can1_0_grp - can1_11_grp, uart0_0_grp - uart0_10_grp, 54 uart1_0_grp - uart1_11_grp, i2c0_0_grp - i2c0_10_grp, i2c1_0_grp - i2c1_10_grp, 55 ttc0_0_grp - ttc0_2_grp, ttc1_0_grp - ttc1_2_grp, swdt0_0_grp - swdt0_4_grp, 56 gpio0_0_grp - gpio0_53_grp, usb0_0_grp, usb1_0_grp 57 58 Valid values for pins are: 59 MIO0 - MIO53 60 61 Valid values for function are: 62 ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, qspi_cs1, 63 spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc, sdio0_cd, sdio0_wp, 64 sdio1, sdio1_pc, sdio1_cd, sdio1_wp, 65 smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, can1, uart0, uart1, 66 i2c0, i2c1, ttc0, ttc1, swdt0, gpio0, usb0, usb1 67 68The following driver-specific properties as defined here are valid to specify in 69a pin configuration subnode: 70 - io-standard: Configure the pin to use the selected IO standard according to 71 this mapping: 72 1: LVCMOS18 73 2: LVCMOS25 74 3: LVCMOS33 75 4: HSTL 76 77Example: 78 pinctrl0: pinctrl@700 { 79 compatible = "xlnx,pinctrl-zynq"; 80 reg = <0x700 0x200>; 81 syscon = <&slcr>; 82 83 pinctrl_uart1_default: uart1-default { 84 mux { 85 groups = "uart1_10_grp"; 86 function = "uart1"; 87 }; 88 89 conf { 90 groups = "uart1_10_grp"; 91 slew-rate = <0>; 92 io-standard = <1>; 93 }; 94 95 conf-rx { 96 pins = "MIO49"; 97 bias-high-impedance; 98 }; 99 100 conf-tx { 101 pins = "MIO48"; 102 bias-disable; 103 }; 104 }; 105 }; 106