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/linux/arch/arm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
65 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
66 select GENERIC_IRQ_IPI if SMP
132 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
162 The ARM series is a line of low-power-consumption RISC chip designs
164 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
165 manufactured, but legacy ARM-based PC hardware remains popular in
173 relocations. The combined range is -/+ 256 MiB, which is usually
266 Patch phys-to-virt and virt-to-phys translation functions at
270 This can only be used with non-XIP MMU kernels where the base
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/linux/arch/arm/mach-omap2/
H A Domap-smp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP4 SMP source file. It contains platform specific functions
4 * needed for the linux smp kernel.
11 * Platform file needed for the OMAP4 SMP. This file is based on arm
12 * realview smp platform.
17 #include <linux/smp.h>
19 #include <linux/irqchip/arm-gic.h>
25 #include "omap-secure.h"
26 #include "omap-wakeupgen.h"
87 * BIT(27) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
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H A Domap-headsmp.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2014 Texas Instruments, Inc.
10 * Interface functions needed for the SMP. This file is based on arm
11 * realview smp platform.
58 .arch armv7-a
113 * bit 1 == Non-Secure Enable
114 * The Non-Secure banked register has not changed
116 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
120 * 2) CPU1 must re-enable the GIC distributor on
/linux/Documentation/arch/x86/i386/
H A DIO-APIC.rst1 .. SPDX-License-Identifier: GPL-2.0
4 IO-APIC
9 Most (all) Intel-MP compliant SMP boards have the so-called 'IO-APIC',
12 IO-APIC, interrupts from hardware will be delivered only to the
15 Linux supports all variants of compliant SMP boards, including ones with
16 multiple IO-APICs. Multiple IO-APICs are used in high-end servers to
20 usually worked around by the kernel. If your MP-compliant SMP board does
21 not boot Linux, then consult the linux-smp mailing list archives first.
23 If your box boots fine with enabled IO-APIC IRQs, then your
28 0: 1360293 IO-APIC-edge timer
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/linux/include/linux/
H A Dvirtio_ring.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Barriers in virtio are tricky. Non-SMP virtio guests can't assume
12 * they're not on an SMP host system, so they need to assume real
13 * barriers. Non-SMP virti
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/linux/arch/x86/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 bool "64-bit kernel" if "$(ARCH)" = "x86"
7 Say yes to build a 64-bit kernel - formerly known as x86_64
8 Say no to build a 32-bit kernel - formerly known as i386
13 # Options that are inherently 32-bit kernel only:
26 # Options that are inherently 64-bit kernel only:
48 in order to test the non static function tracing in the
56 # ported to 32-bit as well. )
158 # Word-size accesses may read uninitialized data past the trailing \0
174 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
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/linux/arch/riscv/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
65 # clang >= 17: https://github.com/llvm/llvm-project/commit/62fa708ceb027713b386c7e0efda994f8bdc27e2
77 select ARCH_SUPPORTS_SCHED_MC if SMP
108 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
116 select GENERIC_IRQ_IPI if SMP
117 select GENERIC_IRQ_IPI_MUX if SMP
122 select GENERIC_PENDING_IRQ if SMP
206 select MMU_GATHER_RCU_TABLE_FREE if SMP && MMU
234 # -Zsanitizer=shadow-call-stack flag.
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/linux/kernel/
H A Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic helpers for smp ipi calls
19 #include <linux/smp.h>
36 #include "sched/smp.h"
38 #define CSD_TYPE(_csd) ((_csd)->node.u_flags & CSD_FLAG_TYPE_MASK)
58 if (!zalloc_cpumask_var_node(&cfd->cpumask, GFP_KERNEL, in smpcfd_prepare_cpu()
60 return -ENOMEM; in smpcfd_prepare_cpu()
61 if (!zalloc_cpumask_var_node(&cfd->cpumask_ipi, GFP_KERNEL, in smpcfd_prepare_cpu()
63 free_cpumask_var(cfd->cpumask); in smpcfd_prepare_cpu()
64 return -ENOMEM; in smpcfd_prepare_cpu()
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/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_pipe.c1 // SPDX-License-Identifier: GPL-2.0-only
14 struct msm_drm_private *priv = s->dev->dev_private; in mdp5_pipe_assign()
15 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); in mdp5_pipe_assign()
27 old_state = &old_global_state->hwpipe; in mdp5_pipe_assign()
28 new_state = &new_global_state->hwpipe; in mdp5_pipe_assign()
30 for (i = 0; i < mdp5_kms->num_hwpipes; i++) { in mdp5_pipe_assign()
31 struct mdp5_hw_pipe *cur = mdp5_kms->hwpipes[i]; in mdp5_pipe_assign()
33 /* skip if already in-use.. check both new and old state, in mdp5_pipe_assign()
34 * since we cannot immediately re-use a pipe that is in mdp5_pipe_assign()
36 * (1) mdp5 can have SMP (non-double-buffered) in mdp5_pipe_assign()
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/linux/arch/arm/mm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
190 # ARM946E-S
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
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/linux/arch/arm/include/asm/
H A Dsmp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/include/asm/smp.h
5 * Copyright (C) 2004-2005 ARM Ltd.
15 # error "<asm/smp.h> included in non-SMP build"
18 #define raw_smp_processor_id() (current_thread_info()->cpu)
38 * Register IPI interrupts with the arch SMP code
114 * set platform specific SMP operations
/linux/kernel/irq/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
23 depends on SMP
51 # Generic irq_domain hw <--> linux irq number translation
66 # Support for obsolete non-mapping irq domains
78 depends on SMP
84 depends on SMP
121 out the interrupt descriptors in a more NUMA-friendly way. )
149 imply SMP
H A Dipi.c1 // SPDX-License-Identifier: GPL-2.0
15 * irq_reserve_ipi() - Setup an IPI to destination cpumask
31 pr_warn("Reservation on a non IPI domain\n"); in irq_reserve_ipi()
32 return -EINVAL; in irq_reserve_ipi()
37 return -EINVAL; in irq_reserve_ipi()
43 return -EINVAL; in irq_reserve_ipi()
74 return -EINVAL; in irq_reserve_ipi()
78 virq = irq_domain_alloc_descs(-1, nr_irqs, 0, NUMA_NO_NODE, NULL); in irq_reserve_ipi()
81 return -ENOMEM; in irq_reserve_ipi()
94 cpumask_copy(data->common->affinity, dest); in irq_reserve_ipi()
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/linux/arch/powerpc/platforms/
H A DKconfig.cputype1 # SPDX-License-Identifier: GPL-2.0
7 bool "64-bit kernel"
10 This option selects whether a 32-bit or a 64-bit kernel
267 default "-mtune=power10" if $(cc-option,-mtune=power10)
268 default "-mtune=power9" if $(cc-option,-mtune=power9)
269 default "-mtune=power8" if $(cc-option,-mtune=power8)
346 This option enables kernel support for larger than 32-bit physical
351 is platform-dependent.
367 any affect on a non-altivec cpu (it does, however add code to the
383 VSX (P7 and above), but does not have any affect on a non-VSX
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/linux/arch/mips/include/asm/mach-cavium-octeon/
H A Dkernel-entry-init.h6 * Copyright (C) 2005-2008 Cavium Networks, Inc
48 xor t1, t1, 0x9000 # 63-P1
51 xor t1, t1, 0x9008 # 63-P2
54 xor t1, t1, 0x9100 # 68-P1
57 xor t1, t1, 0x9200 # 66-PX
60 slti t1, t1, 2 # 66-P1.2 and later good.
63 4: # core-16057 work around
66 5: # No core-16057 work around
77 sd $0, -32768(v0)
98 # All cores other than the master need to wait here for SMP bootstrap
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/linux/arch/arm/mach-mmp/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <asm/smp.h>
8 #include "addr-map.h"
16 * register becoming non-zero and then jumps to the address written in mmp3_boot_secondary()
32 CPU_METHOD_OF_DECLARE(mmp3_smp, "marvell,mmp3-smp", &mmp3_smp_ops);
/linux/drivers/sh/intc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 This enables support for hardware-assisted userspace hardirq
17 SH-4A and newer interrupt blocks all support a special shadowed
18 page with all non-masking registers obscured when mapped in to
26 depends on SMP && SUPERH && CPU_SHX3
28 This enables support for IRQ auto-distribution mode on SH-X3
29 SMP parts. All of the balancing and CPU wakeup decisions are
36 bool "Expose IRQ to per-controller id mapping via debugfs"
40 between system IRQs and the per-controller id tables.
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dcsky,mpintc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/csky,mpintc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: C-SKY Multi-processors Interrupt Controller
10 - Guo Ren <guoren@kernel.org>
13 C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860
14 SMP soc, and it also could be used in non-SMP system.
17 0-15 : software irq, and we use 15 as our IPI_IRQ.
18 16-31 : private irq, and we use 16 as the co-processor timer.
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/linux/arch/powerpc/kernel/
H A Ddbell.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/smp.h>
45 printk(KERN_WARNING "Received doorbell on non-smp system\n"); in DEFINE_INTERRUPT_HANDLER_ASYNC()
/linux/arch/mips/bmips/
H A Dsetup.c20 #include <linux/smp.h>
24 #include <asm/cpu-type.h>
27 #include <asm/smp-ops.h>
40 * with "brcm,bmips-cbr-reg" in the "cpus" node.
65 * load address to a non-conflicting region (e.g. via in bcm3384_viper_quirks()
71 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our in bcm3384_viper_quirks()
72 * logical CPU#1). For the Viper TP1 case, SMP is off limits. in bcm3384_viper_quirks()
112 * disable SMP for now in bcm6358_quirks()
131 { "brcm,bcm3384-viper", &bcm3384_viper_quirks },
132 { "brcm,bcm33843-viper", &bcm3384_viper_quirks },
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/linux/arch/x86/kernel/
H A Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Intel SMP support routines.
6 * (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
40 * Some notes on x86 processor bugs affecting SMP operation:
43 * The Linux implications for SMP are handled as follows:
46 * None of the E1AP-E3AP errata are visible to the user.
53 * None of the A1AP-A3AP errata are visible to the user.
60 * None of 1AP-9AP errata are visible to the normal user,
62 * This is very rare and a non-problem.
64 * 1AP. Linux maps APIC as non-cacheable
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H A Dalternative.c1 // SPDX-License-Identifier: GPL-2.0-only
2 #define pr_fmt(fmt) "SMP alternatives: " fmt
10 #include <asm/text-patching.h>
20 #define MAX_PATCH_LEN (255-1)
41 __setup("debug-alternative", debug_alt);
50 __setup("noreplace-smp", setup_noreplace_smp);
67 for (j = 0; j < (len) - 1; j++) \
127 void *tmp = krealloc(pages->pages, (pages->num+1) * sizeof(void *), in __its_alloc()
132 pages->pages = tmp; in __its_alloc()
133 pages->pages[pages->num++] = page; in __its_alloc()
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/linux/arch/loongarch/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
75 select ARCH_SUPPORTS_SCHED_SMT if SMP
76 select ARCH_SUPPORTS_SCHED_MC if SMP
250 # MIPS Loongson code, to preserve Loongson-specific code paths in drivers that
281 def_bool $(as-instr,x:pcalau12i \$t0$(comma)%pc_hi20(x))
284 def_bool $(as-instr,movfcsr2gr \$t0$(comma)\$fcsr0)
287 def_bool $(cc-option,-Wa$(comma)-mthin-add-sub) || AS_IS_LLVM
290 def_bool $(as-instr,vld \$vr0$(comma)\$a0$(comma)0)
293 def_bool $(as-instr,xvld \$xr0$(comma)\$a0$(comma)0)
296 def_bool $(as-instr,movscr2gr \$a0$(comma)\$scr0)
[all …]
/linux/arch/powerpc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
5 def_bool PPC64 && $(cc-option, -mabi=elfv2)
8 def_bool PPC64 && $(cc-option, -mcpu=power10 -mprefixed)
11 # Clang has a bug (https://github.com/llvm/llvm-project/issues/62372)
12 # where pcrel code is not generated if -msoft-float, -mno-altivec, or
13 # -mno-vsx options are also given. Without these options, fp/vec
16 def_bool PPC64 && CC_IS_GCC && $(cc-option, -mcpu=power10 -mpcrel)
35 # On Book3S 64, the default virtual address space for 64-bit processes
38 # between bottom-up and top-down allocations for applications that
41 default 29 if PPC_BOOK3S_64 && PPC_64K_PAGES # 29 = 45 (32T) - 16 (64K)
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/linux/arch/riscv/kernel/
H A Dsmpboot.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SMP initialisation and IPI support
4 * Based on arch/arm64/kernel/smp.c
36 #include <asm/smp.h>
56 /* This covers non-smp usecase mandated by "nosmp" option */ in smp_prepare_cpus()
82 if (!(processor->flags & ACPI_MADT_ENABLED)) in acpi_parse_rintc()
86 return -EINVAL; in acpi_parse_rintc()
88 acpi_table_print_madt_entry(&header->common); in acpi_parse_rintc()
90 hart = processor->hart_id; in acpi_parse_rintc()
176 if (cpu_ops->cpu_start) in start_secondary_cpu()
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