1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2d9817ebeSThomas Gleixnermenu "IRQ subsystem" 3d9817ebeSThomas Gleixner# Options selectable by the architecture code 4c68fd4f3SThomas Gleixner 5c68fd4f3SThomas Gleixner# Make sparse irq Kconfig switch below available 62ed86b16SRob Herringconfig MAY_HAVE_SPARSE_IRQ 7fd4afaf3SJan Beulich bool 8d9817ebeSThomas Gleixner 9c940e01cSThomas Gleixner# Legacy support, required for itanic 10c940e01cSThomas Gleixnerconfig GENERIC_IRQ_LEGACY 11c940e01cSThomas Gleixner bool 12c940e01cSThomas Gleixner 13c68fd4f3SThomas Gleixner# Enable the generic irq autoprobe mechanism 14d9817ebeSThomas Gleixnerconfig GENERIC_IRQ_PROBE 15fd4afaf3SJan Beulich bool 16d9817ebeSThomas Gleixner 17c68fd4f3SThomas Gleixner# Use the generic /proc/interrupts implementation 18c78b9b65SThomas Gleixnerconfig GENERIC_IRQ_SHOW 19fd4afaf3SJan Beulich bool 20c78b9b65SThomas Gleixner 21ab7798ffSThomas Gleixner# Print level/edge extra information 22ab7798ffSThomas Gleixnerconfig GENERIC_IRQ_SHOW_LEVEL 23ab7798ffSThomas Gleixner bool 24ab7798ffSThomas Gleixner 250d3f5425SThomas Gleixner# Supports effective affinity mask 260d3f5425SThomas Gleixnerconfig GENERIC_IRQ_EFFECTIVE_AFF_MASK 270e6c027cSSamuel Holland depends on SMP 280d3f5425SThomas Gleixner bool 290d3f5425SThomas Gleixner 30c68fd4f3SThomas Gleixner# Support for delayed migration from interrupt context 31d9817ebeSThomas Gleixnerconfig GENERIC_PENDING_IRQ 32fd4afaf3SJan Beulich bool 33d9817ebeSThomas Gleixner 34f1e0bb0aSYang Yingliang# Support for generic irq migrating off cpu before the cpu is offline. 35f1e0bb0aSYang Yingliangconfig GENERIC_IRQ_MIGRATION 36f1e0bb0aSYang Yingliang bool 37f1e0bb0aSYang Yingliang 38c68fd4f3SThomas Gleixner# Alpha specific irq affinity mechanism 39d9817ebeSThomas Gleixnerconfig AUTO_IRQ_AFFINITY 40fd4afaf3SJan Beulich bool 41d9817ebeSThomas Gleixner 42acd26bcfSThomas Gleixner# Interrupt injection mechanism 43acd26bcfSThomas Gleixnerconfig GENERIC_IRQ_INJECTION 44acd26bcfSThomas Gleixner bool 45acd26bcfSThomas Gleixner 46c68fd4f3SThomas Gleixner# Tasklet based software resend for pending interrupts on enable_irq() 47d9817ebeSThomas Gleixnerconfig HARDIRQS_SW_RESEND 48fd4afaf3SJan Beulich bool 49d9817ebeSThomas Gleixner 500521c8fbSThomas Gleixner# Generic configurable interrupt chip implementation 510521c8fbSThomas Gleixnerconfig GENERIC_IRQ_CHIP 520521c8fbSThomas Gleixner bool 530521c8fbSThomas Gleixner select IRQ_DOMAIN 54c42321c7SThomas Gleixner 55c42321c7SThomas Gleixner# Generic irq_domain hw <--> linux irq number translation 56c42321c7SThomas Gleixnerconfig IRQ_DOMAIN 57923fa4eaSNitin A Kamble bool 58c42321c7SThomas Gleixner 5908a543adSGrant Likely# Support for simulated interrupts 6008a543adSGrant Likelyconfig IRQ_SIM 6108a543adSGrant Likely bool 6208a543adSGrant Likely select IRQ_WORK 63b19af510SBartosz Golaszewski select IRQ_DOMAIN 64b19af510SBartosz Golaszewski 65b19af510SBartosz Golaszewski# Support for hierarchical irq domains 66b19af510SBartosz Golaszewskiconfig IRQ_DOMAIN_HIERARCHY 67337cbeb2SBartosz Golaszewski bool 68b19af510SBartosz Golaszewski select IRQ_DOMAIN 69f8264e34SJiang Liu 70f8264e34SJiang Liu# Support for obsolete non-mapping irq domains 71f8264e34SJiang Liuconfig IRQ_DOMAIN_NOMAP 72f8264e34SJiang Liu bool 73f8264e34SJiang Liu select IRQ_DOMAIN 74e37af801SMarc Zyngier 75e37af801SMarc Zyngier# Support for hierarchical fasteoi+edge and fasteoi+level handlers 76e37af801SMarc Zyngierconfig IRQ_FASTEOI_HIERARCHY_HANDLERS 77e37af801SMarc Zyngier bool 78e37af801SMarc Zyngier 797703b08cSDavid Daney# Generic IRQ IPI support 807703b08cSDavid Daneyconfig GENERIC_IRQ_IPI 817703b08cSDavid Daney bool 827703b08cSDavid Daney depends on SMP 83379b6564SQais Yousef select IRQ_DOMAIN_HIERARCHY 84379b6564SQais Yousef 85379b6564SQais Yousef# Generic IRQ IPI Mux support 860f5209feSSamuel Hollandconfig GENERIC_IRQ_IPI_MUX 87151a5351SMarc Zyngier bool 88379b6564SQais Yousef depends on SMP 89835a486cSAnup Patel 90835a486cSAnup Patel# Generic MSI hierarchical interrupt domain support 91835a486cSAnup Patelconfig GENERIC_MSI_IRQ 92835a486cSAnup Patel bool 93835a486cSAnup Patel select IRQ_DOMAIN_HIERARCHY 9413e7accbSThomas Gleixner 95f3cf8bb0SJiang Liu# irqchip drivers should select this if they call iommu_dma_prepare_msi() 96f3cf8bb0SJiang Liuconfig IRQ_MSI_IOMMU 97f3cf8bb0SJiang Liu bool 98f3cf8bb0SJiang Liu 99aaebdf8dSJulien Grallconfig IRQ_TIMINGS 100aaebdf8dSJulien Grall bool 101aaebdf8dSJulien Grall 102b2d3d61aSDaniel Lezcanoconfig GENERIC_IRQ_MATRIX_ALLOCATOR 103b2d3d61aSDaniel Lezcano bool 104b2d3d61aSDaniel Lezcano 1052f75d9e1SThomas Gleixnerconfig GENERIC_IRQ_RESERVATION_MODE 1062f75d9e1SThomas Gleixner bool 1072f75d9e1SThomas Gleixner 1082b5175c4SThomas Gleixner# Snapshot for interrupt statistics 1092b5175c4SThomas Gleixnerconfig GENERIC_IRQ_STAT_SNAPSHOT 1102b5175c4SThomas Gleixner bool 11199cf63c5SBitao Hu 11299cf63c5SBitao Hu# Support forced irq threading 11399cf63c5SBitao Huconfig IRQ_FORCED_THREADING 11499cf63c5SBitao Hu bool 115c68fd4f3SThomas Gleixner 1168d32a307SThomas Gleixnerconfig SPARSE_IRQ 1178d32a307SThomas Gleixner bool "Support sparse irq numbering" if MAY_HAVE_SPARSE_IRQ 1188d32a307SThomas Gleixner help 119d9817ebeSThomas Gleixner 1202ed86b16SRob Herring Sparse irq numbering is useful for distro kernels that want 121a7f7f624SMasahiro Yamada to define a high CONFIG_NR_CPUS value but still want to have 122d9817ebeSThomas Gleixner low kernel memory footprint on smaller machines. 123d9817ebeSThomas Gleixner 124d9817ebeSThomas Gleixner ( Sparse irqs can also be beneficial on NUMA boxes, as they spread 125d9817ebeSThomas Gleixner out the interrupt descriptors in a more NUMA-friendly way. ) 126d9817ebeSThomas Gleixner 127d9817ebeSThomas Gleixner If you don't know what to do here, say N. 128d9817ebeSThomas Gleixner 129d9817ebeSThomas Gleixnerconfig GENERIC_IRQ_DEBUGFS 130d9817ebeSThomas Gleixner bool "Expose irq internals in debugfs" 131d9817ebeSThomas Gleixner depends on DEBUG_FS 132087cdfb6SThomas Gleixner select GENERIC_IRQ_INJECTION 133087cdfb6SThomas Gleixner default n 134087cdfb6SThomas Gleixner help 135acd26bcfSThomas Gleixner 136087cdfb6SThomas Gleixner Exposes internal state information through debugfs. Mostly for 137a7f7f624SMasahiro Yamada developers and debugging of hard to diagnose interrupt problems. 138087cdfb6SThomas Gleixner 139087cdfb6SThomas Gleixner If you don't know what to do here, say N. 140087cdfb6SThomas Gleixner 141087cdfb6SThomas Gleixner# Clear forwarded VM interrupts during kexec. 142087cdfb6SThomas Gleixner# This option ensures the kernel clears active states for interrupts 143087cdfb6SThomas Gleixner# forwarded to virtual machines (VMs) during a machine kexec. 144*bad6722eSEliav Farberconfig GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD 145*bad6722eSEliav Farber bool 146*bad6722eSEliav Farber 147*bad6722eSEliav Farberendmenu 148*bad6722eSEliav Farber 149*bad6722eSEliav Farberconfig GENERIC_IRQ_MULTI_HANDLER 150d9817ebeSThomas Gleixner bool 151caacdbf4SPalmer Dabbelt help 152caacdbf4SPalmer Dabbelt Allow to specify the low level IRQ handler at run time. 153caacdbf4SPalmer Dabbelt 154caacdbf4SPalmer Dabbelt# Cavium Octeon is the last system to use this deprecated option 155caacdbf4SPalmer Dabbelt# Do not even think of enabling this on any new platform 1568d15a729SMarc Zyngierconfig DEPRECATED_IRQ_CPU_ONOFFLINE 1578d15a729SMarc Zyngier bool 1588d15a729SMarc Zyngier depends on CAVIUM_OCTEON_SOC 1598d15a729SMarc Zyngier default CAVIUM_OCTEON_SOC 1608d15a729SMarc Zyngier