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12

/freebsd/sys/contrib/device-tree/src/mips/img/
H A Dpistachio.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/pistachio-clk.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #include <dt-bindings/reset/pistachio-resets.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
22 #address-cells = <1>;
[all …]
/freebsd/sys/dev/gpio/
H A Dgpiomdio.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
61 #define MDO sc->miibb_ops.mbo_bits[MII_BIT_MDO]
62 #define MDI sc->miibb_ops.mbo_bits[MII_BIT_MDI]
63 #define MDC sc->miibb_ops.mbo_bits[MII_BIT_MDC] macro
64 #define MDIRPHY sc->miibb_ops.mbo_bits[MII_BIT_DIR_HOST_PHY]
65 #define MDIRHOST sc->miibb_ops.mbo_bits[MII_BIT_DIR_PHY_HOST]
90 if (devi->npins < GPIOMDIO_MIN_PINS) { in gpiomdio_probe()
93 GPIOMDIO_MIN_PINS, devi->npins); in gpiomdio_probe()
96 device_set_desc(dev, "GPIO MDIO bit-banging Bus driver"); in gpiomdio_probe()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dfsl,cpm-mdio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,cpm-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,pq1-fec-mdio
17 - fsl,cpm2-mdio-bitbang
18 - items:
19 - const: fsl,mpc8272ads-mdio-bitbang
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/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/
H A Dnetwork.txt4 - fsl,cpm1-scc-enet
5 - fsl,cpm2-scc-enet
6 - fsl,cpm1-fec-enet
7 - fsl,cpm2-fcc-enet (third resource is GFEMR)
8 - fsl,qe-enet
13 compatible = "fsl,mpc8272-fcc-enet",
14 "fsl,cpm2-fcc-enet";
16 local-mac-address = [ 00 00 00 00 00 00 ];
18 interrupt-parent = <&PIC>;
19 phy-handle = <&PHY0>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dkmeter1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * 2008-2011 DENX Software Engineering GmbH
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
36 d-cache-size = <32768>; // L1, 32K
[all …]
H A Dmgcoge.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
28 d-cache-line-size = <32>;
29 i-cache-line-size = <32>;
30 d-cache-size = <16384>;
31 i-cache-size = <16384>;
[all …]
H A Dpq2fads.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Device Tree for the PQ2FADS-ZU board with an MPC8280 chip.
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <32>;
32 i-cache-line-size = <32>;
33 d-cache-size = <16384>;
[all …]
H A Dmpc8272ads.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <16384>;
33 i-cache-size = <16384>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dpinctrl-mt7622.txt4 - compatible: Should be one of the following
5 "mediatek,mt7622-pinctrl" for MT7622 SoC
6 "mediatek,mt7629-pinctrl" for MT7629 SoC
7 - reg: offset and length of the pinctrl space
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells: Should be two. The first cell is the pin number and the
14 - interrupt-controller : Marks the device node as an interrupt controller
16 If the property interrupt-controller is defined, following property is required
17 - reg-names: A string describing the "reg" entries. Must contain "eint".
18 - interrupts : The interrupt output from the controller.
[all …]
H A Dqcom,ipq4019-pinctrl.txt7 - compatible: "qcom,ipq4019-pinctrl"
8 - reg: Should be the base address and length of the TLMM block.
9 - interrupts: Should be the parent IRQ of the TLMM block.
10 - interrupt-controller: Marks the device node as an interrupt controller.
11 - #interrupt-cells: Should be two.
12 - gpio-controller: Marks the device node as a GPIO controller.
13 - #gpio-cells : Should be two.
14 The first cell is the gpio pin number and the
16 - gpio-ranges: see ../gpio/gpio.txt
20 - gpio-reserved-ranges: see ../gpio/gpio.txt
[all …]
H A Dqcom,ipq8074-pinctrl.txt6 - compatible:
9 Definition: must be "qcom,ipq8074-pinctrl"
11 - reg:
13 Value type: <prop-encoded-array>
16 - interrupts:
18 Value type: <prop-encoded-array>
21 - interrupt-controller:
26 - #interrupt-cells:
29 Definition: must be 2. Specifying the pin number and flags, as defined
30 in <dt-bindings/interrupt-controller/irq.h>
[all …]
H A Dmediatek,mt7622-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7622 Pin Controller
10 - Sean Wang <sean.wang@kernel.org>
13 The MediaTek's MT7622 Pin controller is used to control SoC pins.
18 - mediatek,mt7622-pinctrl
19 - mediatek,mt7629-pinctrl
24 reg-names:
[all …]
H A Dqcom,ipq5018-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq5018-tlm
[all...]
H A Dqcom,ipq4019-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq4019-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 Top Level Mode Multiplexer pin controller in Qualcomm IPQ4019 SoC.
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,ipq4019-pinctrl
28 gpio-reserved-ranges: true
31 "-state$":
[all …]
H A Dqcom,ipq8074-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq8074-pinctr
[all...]
H A Dqcom,ipq9574-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq9574-tlm
[all...]
/freebsd/sys/contrib/device-tree/Bindings/arm/marvell/
H A Dcp110-system-controller.txt6 giving access to numerous features: clocks, pin-muxing and many other
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the CP110 system controller
18 -----
[all...]
/freebsd/sys/contrib/device-tree/src/arm/gemini/
H A Dgemini-sq201.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
24 stdout-path = &uart0;
28 compatible = "gpio-keys";
30 button-setup {
31 debounce-interval = <100>;
32 wakeup-source;
[all …]
H A Dgemini-sl93512r.dts1 // SPDX-License-Identifier: GPL-2.0
5 * "Gemini324 EV-Board" before Storm acquired Storlink Semiconductor.
9 /dts-v1/;
12 #include <dt-bindings/input/input.h>
15 model = "Storlink Semiconductor Gemini324 EV-Board / Storm Semiconductor SL93512R_BRD";
17 #address-cells = <1>;
18 #size-cells = <1>;
28 stdout-path = &uart0;
32 compatible = "gpio-keys";
34 button-wps {
[all …]
H A Dgemini-dlink-dir-685.dts2 * Device Tree file for D-Link DIR-685 Xtreme N Storage Router
5 /dts-v1/;
8 #include <dt-bindings/input/input.h>
11 model = "D-Link DIR-685 Xtreme N Storage Router";
12 compatible = "dlink,dir-685", "cortina,gemini";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */
24 stdout-path = "uart0:19200n8";
28 compatible = "gpio-keys";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstih407-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "st-pincfg.h"
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 /* 0-5: PIO_SBC */
18 /* 10-19: PIO_FRONT0 */
31 /* 30-35: PIO_REAR */
38 /* 40-42: PIO_FLASH */
45 pin-controller-sbc@961f080 {
46 #address-cells = <1>;
47 #size-cells = <1>;
[all …]
/freebsd/sys/dev/e1000/
H A De1000_82543.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
81 * e1000_init_phy_params_82543 - Init PHY func ptrs.
86 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82543()
91 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_82543()
92 phy->type = e1000_phy_none; in e1000_init_phy_params_82543()
95 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_82543()
96 phy->ops.power_down = e1000_power_down_phy_copper; in e1000_init_phy_params_82543()
99 phy->addr = 1; in e1000_init_phy_params_82543()
100 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_82543()
[all …]
/freebsd/sys/dev/qcom_tlmm/
H A Dqcom_tlmm_ipq4018.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
79 GDEF(7, "mdc", NULL, "wcss0_dbg19", "wcss1_dbg19", NULL,
173 GDEF(52, "qpic_pad", "mdc", "pcie_clk", "i2s_tx_mclk", NULL, NULL,
245 GDEF(-1),
255 if (ofw_bus_is_compatible(dev, "qcom,ipq4019-pinctrl") == 0) in qcom_tlmm_ipq4018_probe()
268 KASSERT(mtx_initialized(&sc->gpio_mtx), ("gpio mutex not initialized")); in qcom_tlmm_ipq4018_detach()
271 if (sc->gpio_ih) in qcom_tlmm_ipq4018_detach()
272 bus_teardown_intr(dev, sc->gpio_irq_res, sc->gpio_ih); in qcom_tlmm_ipq4018_detach()
273 if (sc->gpio_irq_res) in qcom_tlmm_ipq4018_detach()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynosautov9-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as
11 #include "exynos-pinctrl.h"
14 gpa0: gpa0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
17 interrupt-controller;
18 #interrupt-cells = <2>;
19 interrupt-parent = <&gic>;
[all …]
/freebsd/sys/arm/ti/am335x/
H A Dam335x_dmtpps.c1 /*-
32 * signal on an IO pin. Each of timers 4-7 have an associated pin, and this
40 * holding a mutex) is scheduled to be done later in a non-interrupt context.
93 {"ti,am335x-timer", 1},
94 {"ti,am335x-timer-1ms", 1},
112 {"MDC", 5},
127 * This is either brilliantly user-friendly, or utterly lame...
130 * pins for all four capture-capable timers available on the P8 header. Allow
131 * users to configure the input pin by giving the name of the header pin.
138 {"P8-7", "GPMC_ADVn_ALE"},
[all …]

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