Lines Matching +full:mdc +full:- +full:pin
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq8074-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm IPQ8074 TLMM pin controller
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
14 Top Level Mode Multiplexer pin controller in Qualcomm IPQ8074 SoC.
18 const: qcom,ipq8074-pinctrl
26 gpio-reserved-ranges:
30 gpio-line-names:
34 "-state$":
36 - $ref: "#/$defs/qcom-ipq8074-tlmm-state"
37 - patternProperties:
38 "-pins$":
39 $ref: "#/$defs/qcom-ipq8074-tlmm-state"
43 qcom-ipq8074-tlmm-state:
46 Pinctrl node's client devices use subnodes for desired pin configuration.
48 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
57 pattern: "^gpio([0-9]|[1-6][0-9]|70)$"
77 mac1_sa3, mac2_sa0, mac2_sa1, mdc, mdio, pcie0_clk, pcie0_rst,
90 - pins
93 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
96 - compatible
97 - reg
102 - |
103 #include <dt-bindings/interrupt-controller/arm-gic.h>
106 compatible = "qcom,ipq8074-pinctrl";
108 gpio-controller;
109 #gpio-cells = <0x2>;
110 gpio-ranges = <&tlmm 0 0 70>;
112 interrupt-controller;
113 #interrupt-cells = <0x2>;
115 serial4-state {
118 drive-strength = <8>;
119 bias-disable;