Lines Matching +full:mdc +full:- +full:pin
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq9574-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
14 Top Level Mode Multiplexer pin controller in Qualcomm IPQ9574 SoC.
18 const: qcom,ipq9574-tlmm
26 gpio-reserved-ranges:
30 gpio-line-names:
34 "-state$":
36 - $ref: "#/$defs/qcom-ipq9574-tlmm-state"
37 - patternProperties:
38 "-pins$":
39 $ref: "#/$defs/qcom-ipq9574-tlmm-state"
43 qcom-ipq9574-tlmm-state:
46 Pinctrl node's client devices use subnodes for desired pin configuration.
48 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
57 pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$"
72 gcc_plltest, gcc_tlmm, gpio, mac, mdc, mdio, pcie0_clk, pcie0_wake,
84 - pins
87 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
90 - compatible
91 - reg
96 - |
97 #include <dt-bindings/interrupt-controller/arm-gic.h>
99 compatible = "qcom,ipq9574-tlmm";
102 gpio-controller;
103 #gpio-cells = <2>;
104 interrupt-controller;
105 #interrupt-cells = <2>;
106 gpio-ranges = <&tlmm 0 0 65>;
108 uart2-state {
111 drive-strength = <8>;
112 bias-pull-down;