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/linux/drivers/mailbox/
H A Dstm32-ipcc.c54 spinlock_t lock; /* protect access to IPCC registers */
84 struct stm32_ipcc *ipcc = data; in stm32_ipcc_rx_irq() local
85 struct device *dev = ipcc->controller.dev; in stm32_ipcc_rx_irq()
91 proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST; in stm32_ipcc_rx_irq()
92 tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); in stm32_ipcc_rx_irq()
93 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); in stm32_ipcc_rx_irq()
98 for (chan = 0; chan < ipcc->n_chans; chan++) { in stm32_ipcc_rx_irq()
104 mbox_chan_received_data(&ipcc->controller.chans[chan], NULL); in stm32_ipcc_rx_irq()
106 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR, in stm32_ipcc_rx_irq()
117 struct stm32_ipcc *ipcc = data; in stm32_ipcc_tx_irq() local
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H A Dqcom-ipcc.c14 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 /* IPCC Register offsets */
44 * @base: Base address of the IPCC frame associated to APSS
76 struct qcom_ipcc *ipcc = data; in qcom_ipcc_irq_fn() local
81 hwirq = readl(ipcc->base + IPCC_REG_RECV_ID); in qcom_ipcc_irq_fn()
85 virq = irq_find_mapping(ipcc->irq_domain, hwirq); in qcom_ipcc_irq_fn()
86 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR); in qcom_ipcc_irq_fn()
95 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd); in qcom_ipcc_mask_irq() local
98 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE); in qcom_ipcc_mask_irq()
103 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd); in qcom_ipcc_unmask_irq() local
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/linux/Documentation/devicetree/bindings/mailbox/
H A Dst,stm32-ipcc.yaml4 $id: http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#
10 The IPCC block provides a non blocking signaling mechanism to post and
21 const: st,stm32mp1-ipcc
64 ipcc: mailbox@4c001000 {
65 compatible = "st,stm32mp1-ipcc";
72 clocks = <&rcc_clk IPCC>;
/linux/sound/soc/intel/catpt/
H A Dipc.c65 catpt_writel_shim(cdev, IPCC, header); in catpt_dsp_send_tx()
276 u32 isc, ipcc; in catpt_dsp_irq_handler()
286 ipcc = catpt_readl_shim(cdev, IPCC); in catpt_dsp_irq_handler()
287 trace_catpt_ipc_reply(ipcc); in catpt_dsp_irq_handler()
288 catpt_dsp_copy_rx(cdev, ipcc); in catpt_dsp_irq_handler()
292 catpt_updatel_shim(cdev, IPCC, CATPT_IPCC_DONE, 0); in catpt_dsp_irq_handler()
268 u32 isc, ipcc; catpt_dsp_irq_handler() local
H A Ddsp.c326 catpt_writel_shim(cdev, IPCC, CATPT_IPCC_DEFAULT); in catpt_dsp_set_regs_defaults()
/linux/arch/arm/boot/dts/st/
H A Dstm32mp157a-microgea-stm32mp1.dtsi116 &ipcc {
128 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
H A Dstm32mp15xx-osd32.dtsi200 &ipcc {
207 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
H A Dstm32mp15xx-dhcor-som.dtsi218 &ipcc {
230 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
H A Dstm32mp157c-odyssey-som.dtsi221 &ipcc {
233 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
H A Dstm32mp157a-icore-stm32mp1.dtsi164 &ipcc {
176 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
H A Dstm32mp157c-emstamp-argon.dtsi358 &ipcc {
370 mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,glink-edge.yaml81 #include <dt-bindings/mailbox/qcom-ipcc.h>
88 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
91 mboxes = <&ipcc IPCC_CLIENT_WPSS
H A Dqcom,sm6375-pas.yaml106 #include <dt-bindings/mailbox/qcom-ipcc.h>
134 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
137 mboxes = <&ipcc IPCC_CLIENT_LPASS
H A Dqcom,sm6350-pas.yaml128 #include <dt-bindings/mailbox/qcom-ipcc.h>
157 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
160 mboxes = <&ipcc IPCC_CLIENT_LPASS
/linux/include/dt-bindings/clock/
H A Dstm32mp1-clks.h96 #define IPCC 83 macro
/linux/drivers/clk/stm32/
H A Dclk-stm32mp1.c1969 PCLK(IPCC, "ipcc", "ck_mcu", 0, G_IPCC),
/linux/
H A DMAINTAINERS22265 QUALCOMM IPCC MAILBOX DRIVER
22269 F: Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
22270 F: drivers/mailbox/qcom-ipcc.c
22271 F: include/dt-bindings/mailbox/qcom-ipcc.h