1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6#include <dt-bindings/clock/qcom,glymur-dispcc.h> 7#include <dt-bindings/clock/qcom,glymur-gcc.h> 8#include <dt-bindings/clock/qcom,glymur-tcsr.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interconnect/qcom,icc.h> 13#include <dt-bindings/interconnect/qcom,glymur-rpmh.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/phy/phy-qcom-qmp.h> 17#include <dt-bindings/power/qcom,rpmhpd.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/spmi/spmi.h> 22 23#include "glymur-ipcc.h" 24 25/ { 26 interrupt-parent = <&intc>; 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 cpus { 31 #address-cells = <2>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "qcom,oryon-2-2"; 37 reg = <0x0 0x0>; 38 enable-method = "psci"; 39 power-domains = <&cpu_pd0>, <&scmi_perf 0>; 40 power-domain-names = "psci", "perf"; 41 next-level-cache = <&l2_0>; 42 43 l2_0: l2-cache { 44 compatible = "cache"; 45 cache-level = <2>; 46 cache-unified; 47 }; 48 }; 49 50 cpu1: cpu@100 { 51 device_type = "cpu"; 52 compatible = "qcom,oryon-2-2"; 53 reg = <0x0 0x100>; 54 enable-method = "psci"; 55 power-domains = <&cpu_pd1>, <&scmi_perf 0>; 56 power-domain-names = "psci", "perf"; 57 next-level-cache = <&l2_0>; 58 }; 59 60 cpu2: cpu@200 { 61 device_type = "cpu"; 62 compatible = "qcom,oryon-2-2"; 63 reg = <0x0 0x200>; 64 enable-method = "psci"; 65 power-domains = <&cpu_pd2>, <&scmi_perf 0>; 66 power-domain-names = "psci", "perf"; 67 next-level-cache = <&l2_0>; 68 }; 69 70 cpu3: cpu@300 { 71 device_type = "cpu"; 72 compatible = "qcom,oryon-2-2"; 73 reg = <0x0 0x300>; 74 enable-method = "psci"; 75 power-domains = <&cpu_pd3>, <&scmi_perf 0>; 76 power-domain-names = "psci", "perf"; 77 next-level-cache = <&l2_0>; 78 }; 79 80 cpu4: cpu@400 { 81 device_type = "cpu"; 82 compatible = "qcom,oryon-2-2"; 83 reg = <0x0 0x400>; 84 enable-method = "psci"; 85 power-domains = <&cpu_pd4>, <&scmi_perf 0>; 86 power-domain-names = "psci", "perf"; 87 next-level-cache = <&l2_0>; 88 }; 89 90 cpu5: cpu@500 { 91 device_type = "cpu"; 92 compatible = "qcom,oryon-2-2"; 93 reg = <0x0 0x500>; 94 enable-method = "psci"; 95 power-domains = <&cpu_pd5>, <&scmi_perf 0>; 96 power-domain-names = "psci", "perf"; 97 next-level-cache = <&l2_0>; 98 }; 99 100 cpu6: cpu@10000 { 101 device_type = "cpu"; 102 compatible = "qcom,oryon-2-1"; 103 reg = <0x0 0x10000>; 104 enable-method = "psci"; 105 power-domains = <&cpu_pd6>, <&scmi_perf 1>; 106 power-domain-names = "psci", "perf"; 107 next-level-cache = <&l2_1>; 108 109 l2_1: l2-cache { 110 compatible = "cache"; 111 cache-level = <2>; 112 cache-unified; 113 }; 114 }; 115 116 cpu7: cpu@10100 { 117 device_type = "cpu"; 118 compatible = "qcom,oryon-2-1"; 119 reg = <0x0 0x10100>; 120 enable-method = "psci"; 121 power-domains = <&cpu_pd7>, <&scmi_perf 1>; 122 power-domain-names = "psci", "perf"; 123 next-level-cache = <&l2_1>; 124 }; 125 126 cpu8: cpu@10200 { 127 device_type = "cpu"; 128 compatible = "qcom,oryon-2-1"; 129 reg = <0x0 0x10200>; 130 enable-method = "psci"; 131 power-domains = <&cpu_pd8>, <&scmi_perf 1>; 132 power-domain-names = "psci", "perf"; 133 next-level-cache = <&l2_1>; 134 }; 135 136 cpu9: cpu@10300 { 137 device_type = "cpu"; 138 compatible = "qcom,oryon-2-1"; 139 reg = <0x0 0x10300>; 140 enable-method = "psci"; 141 power-domains = <&cpu_pd9>, <&scmi_perf 1>; 142 power-domain-names = "psci", "perf"; 143 next-level-cache = <&l2_1>; 144 }; 145 146 cpu10: cpu@10400 { 147 device_type = "cpu"; 148 compatible = "qcom,oryon-2-1"; 149 reg = <0x0 0x10400>; 150 enable-method = "psci"; 151 power-domains = <&cpu_pd10>, <&scmi_perf 1>; 152 power-domain-names = "psci", "perf"; 153 next-level-cache = <&l2_1>; 154 }; 155 156 cpu11: cpu@10500 { 157 device_type = "cpu"; 158 compatible = "qcom,oryon-2-1"; 159 reg = <0x0 0x10500>; 160 enable-method = "psci"; 161 power-domains = <&cpu_pd11>, <&scmi_perf 1>; 162 power-domain-names = "psci", "perf"; 163 next-level-cache = <&l2_1>; 164 }; 165 166 cpu12: cpu@20000 { 167 device_type = "cpu"; 168 compatible = "qcom,oryon-2-1"; 169 reg = <0x0 0x20000>; 170 enable-method = "psci"; 171 power-domains = <&cpu_pd12>, <&scmi_perf 2>; 172 power-domain-names = "psci", "perf"; 173 next-level-cache = <&l2_2>; 174 175 l2_2: l2-cache { 176 compatible = "cache"; 177 cache-level = <2>; 178 cache-unified; 179 }; 180 }; 181 182 cpu13: cpu@20100 { 183 device_type = "cpu"; 184 compatible = "qcom,oryon-2-1"; 185 reg = <0x0 0x20100>; 186 enable-method = "psci"; 187 power-domains = <&cpu_pd13>, <&scmi_perf 2>; 188 power-domain-names = "psci", "perf"; 189 next-level-cache = <&l2_2>; 190 }; 191 192 cpu14: cpu@20200 { 193 device_type = "cpu"; 194 compatible = "qcom,oryon-2-1"; 195 reg = <0x0 0x20200>; 196 enable-method = "psci"; 197 power-domains = <&cpu_pd14>, <&scmi_perf 2>; 198 power-domain-names = "psci", "perf"; 199 next-level-cache = <&l2_2>; 200 }; 201 202 cpu15: cpu@20300 { 203 device_type = "cpu"; 204 compatible = "qcom,oryon-2-1"; 205 reg = <0x0 0x20300>; 206 enable-method = "psci"; 207 power-domains = <&cpu_pd15>, <&scmi_perf 2>; 208 power-domain-names = "psci", "perf"; 209 next-level-cache = <&l2_2>; 210 }; 211 212 cpu16: cpu@20400 { 213 device_type = "cpu"; 214 compatible = "qcom,oryon-2-1"; 215 reg = <0x0 0x20400>; 216 enable-method = "psci"; 217 power-domains = <&cpu_pd16>, <&scmi_perf 2>; 218 power-domain-names = "psci", "perf"; 219 next-level-cache = <&l2_2>; 220 }; 221 222 cpu17: cpu@20500 { 223 device_type = "cpu"; 224 compatible = "qcom,oryon-2-1"; 225 reg = <0x0 0x20500>; 226 enable-method = "psci"; 227 power-domains = <&cpu_pd17>, <&scmi_perf 2>; 228 power-domain-names = "psci", "perf"; 229 next-level-cache = <&l2_2>; 230 }; 231 232 cpu-map { 233 cluster0 { 234 core0 { 235 cpu = <&cpu0>; 236 }; 237 238 core1 { 239 cpu = <&cpu1>; 240 }; 241 242 core2 { 243 cpu = <&cpu2>; 244 }; 245 246 core3 { 247 cpu = <&cpu3>; 248 }; 249 250 core4 { 251 cpu = <&cpu4>; 252 }; 253 254 core5 { 255 cpu = <&cpu5>; 256 }; 257 }; 258 259 cluster1 { 260 core0 { 261 cpu = <&cpu6>; 262 }; 263 264 core1 { 265 cpu = <&cpu7>; 266 }; 267 268 core2 { 269 cpu = <&cpu8>; 270 }; 271 272 core3 { 273 cpu = <&cpu9>; 274 }; 275 276 core4 { 277 cpu = <&cpu10>; 278 }; 279 280 core5 { 281 cpu = <&cpu11>; 282 }; 283 }; 284 285 cpu_map_cluster2: cluster2 { 286 core0 { 287 cpu = <&cpu12>; 288 }; 289 290 core1 { 291 cpu = <&cpu13>; 292 }; 293 294 core2 { 295 cpu = <&cpu14>; 296 }; 297 298 core3 { 299 cpu = <&cpu15>; 300 }; 301 302 core4 { 303 cpu = <&cpu16>; 304 }; 305 306 core5 { 307 cpu = <&cpu17>; 308 }; 309 }; 310 }; 311 312 idle-states { 313 entry-method = "psci"; 314 315 cpu_c4: cpu-sleep-0 { 316 compatible = "arm,idle-state"; 317 idle-state-name = "ret"; 318 arm,psci-suspend-param = <0x00000004>; 319 entry-latency-us = <180>; 320 exit-latency-us = <320>; 321 min-residency-us = <1000>; 322 }; 323 }; 324 325 domain-idle-states { 326 cluster_cl5: cluster-sleep-0 { 327 compatible = "domain-idle-state"; 328 arm,psci-suspend-param = <0x01000054>; 329 entry-latency-us = <2000>; 330 exit-latency-us = <2000>; 331 min-residency-us = <9000>; 332 }; 333 334 domain_ss3: domain-sleep-0 { 335 compatible = "domain-idle-state"; 336 arm,psci-suspend-param = <0x0200c354>; 337 entry-latency-us = <2800>; 338 exit-latency-us = <4400>; 339 min-residency-us = <10150>; 340 }; 341 }; 342 }; 343 344 firmware { 345 scm: scm { 346 compatible = "qcom,scm-glymur", "qcom,scm"; 347 qcom,dload-mode = <&tcsr 0x4000>; 348 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 349 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 350 }; 351 352 scmi { 353 compatible = "arm,scmi"; 354 mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>; 355 mbox-names = "tx", "rx"; 356 shmem = <&cpu_scp_lpri1>, <&cpu_scp_lpri0>; 357 358 #address-cells = <1>; 359 #size-cells = <0>; 360 361 scmi_perf: protocol@13 { 362 reg = <0x13>; 363 #power-domain-cells = <1>; 364 }; 365 }; 366 }; 367 368 clk_virt: interconnect-0 { 369 compatible = "qcom,glymur-clk-virt"; 370 #interconnect-cells = <2>; 371 qcom,bcm-voters = <&apps_bcm_voter>; 372 }; 373 374 mc_virt: interconnect-1 { 375 compatible = "qcom,glymur-mc-virt"; 376 #interconnect-cells = <2>; 377 qcom,bcm-voters = <&apps_bcm_voter>; 378 }; 379 380 pmu { 381 compatible = "arm,armv8-pmuv3"; 382 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 383 }; 384 385 psci { 386 compatible = "arm,psci-1.0"; 387 method = "smc"; 388 389 cpu_pd0: power-domain-cpu0 { 390 #power-domain-cells = <0>; 391 power-domains = <&cluster0_pd>; 392 domain-idle-states = <&cpu_c4>; 393 }; 394 395 cpu_pd1: power-domain-cpu1 { 396 #power-domain-cells = <0>; 397 power-domains = <&cluster0_pd>; 398 domain-idle-states = <&cpu_c4>; 399 }; 400 401 cpu_pd2: power-domain-cpu2 { 402 #power-domain-cells = <0>; 403 power-domains = <&cluster0_pd>; 404 domain-idle-states = <&cpu_c4>; 405 }; 406 407 cpu_pd3: power-domain-cpu3 { 408 #power-domain-cells = <0>; 409 power-domains = <&cluster0_pd>; 410 domain-idle-states = <&cpu_c4>; 411 }; 412 413 cpu_pd4: power-domain-cpu4 { 414 #power-domain-cells = <0>; 415 power-domains = <&cluster0_pd>; 416 domain-idle-states = <&cpu_c4>; 417 }; 418 419 cpu_pd5: power-domain-cpu5 { 420 #power-domain-cells = <0>; 421 power-domains = <&cluster0_pd>; 422 domain-idle-states = <&cpu_c4>; 423 }; 424 425 cpu_pd6: power-domain-cpu6 { 426 #power-domain-cells = <0>; 427 power-domains = <&cluster1_pd>; 428 domain-idle-states = <&cpu_c4>; 429 }; 430 431 cpu_pd7: power-domain-cpu7 { 432 #power-domain-cells = <0>; 433 power-domains = <&cluster1_pd>; 434 domain-idle-states = <&cpu_c4>; 435 }; 436 437 cpu_pd8: power-domain-cpu8 { 438 #power-domain-cells = <0>; 439 power-domains = <&cluster1_pd>; 440 domain-idle-states = <&cpu_c4>; 441 }; 442 443 cpu_pd9: power-domain-cpu9 { 444 #power-domain-cells = <0>; 445 power-domains = <&cluster1_pd>; 446 domain-idle-states = <&cpu_c4>; 447 }; 448 449 cpu_pd10: power-domain-cpu10 { 450 #power-domain-cells = <0>; 451 power-domains = <&cluster1_pd>; 452 domain-idle-states = <&cpu_c4>; 453 }; 454 455 cpu_pd11: power-domain-cpu11 { 456 #power-domain-cells = <0>; 457 power-domains = <&cluster1_pd>; 458 domain-idle-states = <&cpu_c4>; 459 }; 460 461 cpu_pd12: power-domain-cpu12 { 462 #power-domain-cells = <0>; 463 power-domains = <&cluster2_pd>; 464 domain-idle-states = <&cpu_c4>; 465 }; 466 467 cpu_pd13: power-domain-cpu13 { 468 #power-domain-cells = <0>; 469 power-domains = <&cluster2_pd>; 470 domain-idle-states = <&cpu_c4>; 471 }; 472 473 cpu_pd14: power-domain-cpu14 { 474 #power-domain-cells = <0>; 475 power-domains = <&cluster2_pd>; 476 domain-idle-states = <&cpu_c4>; 477 }; 478 479 cpu_pd15: power-domain-cpu15 { 480 #power-domain-cells = <0>; 481 power-domains = <&cluster2_pd>; 482 domain-idle-states = <&cpu_c4>; 483 }; 484 485 cpu_pd16: power-domain-cpu16 { 486 #power-domain-cells = <0>; 487 power-domains = <&cluster2_pd>; 488 domain-idle-states = <&cpu_c4>; 489 }; 490 491 cpu_pd17: power-domain-cpu17 { 492 #power-domain-cells = <0>; 493 power-domains = <&cluster2_pd>; 494 domain-idle-states = <&cpu_c4>; 495 }; 496 497 cluster0_pd: power-domain-cpu-cluster0 { 498 #power-domain-cells = <0>; 499 power-domains = <&system_pd>; 500 domain-idle-states = <&cluster_cl5>; 501 }; 502 503 cluster1_pd: power-domain-cpu-cluster1 { 504 #power-domain-cells = <0>; 505 power-domains = <&system_pd>; 506 domain-idle-states = <&cluster_cl5>; 507 }; 508 509 cluster2_pd: power-domain-cpu-cluster2 { 510 #power-domain-cells = <0>; 511 power-domains = <&system_pd>; 512 domain-idle-states = <&cluster_cl5>; 513 }; 514 515 system_pd: power-domain-system { 516 #power-domain-cells = <0>; 517 domain-idle-states = <&domain_ss3>; 518 }; 519 }; 520 521 reserved-memory { 522 #address-cells = <2>; 523 #size-cells = <2>; 524 ranges; 525 526 pdp_mem: pdp@81400000 { 527 reg = <0x0 0x81400000 0x0 0x100000>; 528 no-map; 529 }; 530 531 aop_cmd_db_mem: aop-cmd-db@81c60000 { 532 compatible = "qcom,cmd-db"; 533 reg = <0x0 0x81c60000 0x0 0x20000>; 534 no-map; 535 }; 536 537 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 538 reg = <0x0 0x81e00000 0x0 0x200000>; 539 no-map; 540 }; 541 542 oobdaretag_mem: oobdaretag@86e10000 { 543 reg = <0x0 0x86e10000 0x0 0x360000>; 544 no-map; 545 }; 546 547 oob_secure_mem: oob-secure@87170000 { 548 reg = <0x0 0x87170000 0x0 0xbc0000>; 549 no-map; 550 }; 551 552 oobdtbqc_mem: oobdtbqc@87d30000 { 553 reg = <0x0 0x87d30000 0x0 0x20000>; 554 no-map; 555 }; 556 557 oobdtboem_mem: oobdtboem@87d50000 { 558 reg = <0x0 0x87d50000 0x0 0x20000>; 559 no-map; 560 }; 561 562 oob_nonsecure_mem: oob-nonsecure@87e00000 { 563 reg = <0x0 0x87e00000 0x0 0xc00000>; 564 no-map; 565 }; 566 567 spss_region_mem: spss@88a00000 { 568 reg = <0x0 0x88a00000 0x0 0x400000>; 569 no-map; 570 }; 571 572 soccpdtb_mem: soccpdtb@892e0000 { 573 reg = <0x0 0x892e0000 0x0 0x20000>; 574 no-map; 575 }; 576 577 soccp_mem: soccp@89300000 { 578 reg = <0x0 0x89300000 0x0 0x400000>; 579 no-map; 580 }; 581 582 cvp_mem: cvp@89700000 { 583 reg = <0x0 0x89700000 0x0 0x700000>; 584 no-map; 585 }; 586 587 adspslpi_mem: adspslpi@89e00000 { 588 reg = <0x0 0x89e00000 0x0 0x3a00000>; 589 no-map; 590 }; 591 592 q6_adsp_dtb_mem: q6-adsp-dtb@8d800000 { 593 reg = <0x0 0x8d800000 0x0 0x80000>; 594 no-map; 595 }; 596 597 cdsp_mem: cdsp@8d900000 { 598 reg = <0x0 0x8d900000 0x0 0x4000000>; 599 no-map; 600 }; 601 602 q6_cdsp_dtb_mem: q6-cdsp-dtb@91900000 { 603 reg = <0x0 0x91900000 0x0 0x80000>; 604 no-map; 605 }; 606 607 gpu_microcode_mem: gpu-microcode@919fe000 { 608 reg = <0x0 0x919fe000 0x0 0x2000>; 609 no-map; 610 }; 611 612 camera_mem: camera@91a00000 { 613 reg = <0x0 0x91a00000 0x0 0x800000>; 614 no-map; 615 }; 616 617 av1_encoder_mem: av1-encoder@92200000 { 618 reg = <0x0 0x92200000 0x0 0x700000>; 619 no-map; 620 }; 621 622 video_mem: video@92900000 { 623 reg = <0x0 0x92900000 0x0 0xc00000>; 624 no-map; 625 }; 626 627 smem_mem: smem@ffe00000 { 628 compatible = "qcom,smem"; 629 reg = <0x0 0xffe00000 0x0 0x200000>; 630 hwlocks = <&tcsr_mutex 3>; 631 no-map; 632 }; 633 }; 634 635 smp2p-adsp { 636 compatible = "qcom,smp2p"; 637 638 interrupts-extended = <&ipcc IPCC_MPROC_LPASS 639 IPCC_MPROC_SIGNAL_SMP2P 640 IRQ_TYPE_EDGE_RISING>; 641 642 mboxes = <&ipcc IPCC_MPROC_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 643 644 qcom,smem = <443>, <429>; 645 qcom,local-pid = <0>; 646 qcom,remote-pid = <2>; 647 648 smp2p_adsp_out: master-kernel { 649 qcom,entry-name = "master-kernel"; 650 #qcom,smem-state-cells = <1>; 651 }; 652 653 smp2p_adsp_in: slave-kernel { 654 qcom,entry-name = "slave-kernel"; 655 interrupt-controller; 656 #interrupt-cells = <2>; 657 }; 658 }; 659 660 smp2p-cdsp { 661 compatible = "qcom,smp2p"; 662 663 interrupts-extended = <&ipcc IPCC_MPROC_CDSP 664 IPCC_MPROC_SIGNAL_SMP2P 665 IRQ_TYPE_EDGE_RISING>; 666 667 mboxes = <&ipcc IPCC_MPROC_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 668 669 qcom,smem = <94>, <432>; 670 qcom,local-pid = <0>; 671 qcom,remote-pid = <5>; 672 673 smp2p_cdsp_out: master-kernel { 674 qcom,entry-name = "master-kernel"; 675 #qcom,smem-state-cells = <1>; 676 }; 677 678 smp2p_cdsp_in: slave-kernel { 679 qcom,entry-name = "slave-kernel"; 680 interrupt-controller; 681 #interrupt-cells = <2>; 682 }; 683 }; 684 685 smp2p-soccp { 686 compatible = "qcom,smp2p"; 687 688 interrupts-extended = <&ipcc IPCC_MPROC_SOCCP 689 IPCC_MPROC_SIGNAL_SMP2P 690 IRQ_TYPE_EDGE_RISING>; 691 692 mboxes = <&ipcc IPCC_MPROC_SOCCP 693 IPCC_MPROC_SIGNAL_SMP2P>; 694 695 qcom,smem = <617>, <616>; 696 qcom,local-pid = <0>; 697 qcom,remote-pid = <19>; 698 699 soccp_smp2p_out: master-kernel { 700 qcom,entry-name = "master-kernel"; 701 #qcom,smem-state-cells = <1>; 702 }; 703 704 soccp_smp2p_in: slave-kernel { 705 qcom,entry-name = "slave-kernel"; 706 interrupt-controller; 707 #interrupt-cells = <2>; 708 }; 709 }; 710 711 soc: soc@0 { 712 compatible = "simple-bus"; 713 #address-cells = <2>; 714 #size-cells = <2>; 715 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 716 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 717 718 gcc: clock-controller@100000 { 719 compatible = "qcom,glymur-gcc"; 720 reg = <0x0 0x00100000 0x0 0x1f9000>; 721 clocks = <&rpmhcc RPMH_CXO_CLK>, /* Board XO source */ 722 <&rpmhcc RPMH_CXO_CLK_A>, /* Board XO_A source */ 723 <&sleep_clk>, /* Sleep */ 724 <0>, /* USB 0 Phy DP0 GMUX */ 725 <0>, /* USB 0 Phy DP1 GMUX */ 726 <0>, /* USB 0 Phy PCIE PIPEGMUX */ 727 <0>, /* USB 0 Phy PIPEGMUX */ 728 <0>, /* USB 0 Phy SYS PCIE PIPEGMUX */ 729 <0>, /* USB 1 Phy DP0 GMUX 2 */ 730 <0>, /* USB 1 Phy DP1 GMUX 2 */ 731 <0>, /* USB 1 Phy PCIE PIPEGMUX */ 732 <0>, /* USB 1 Phy PIPEGMUX */ 733 <0>, /* USB 1 Phy SYS PCIE PIPEGMUX */ 734 <0>, /* USB 2 Phy DP0 GMUX 2 */ 735 <0>, /* USB 2 Phy DP1 GMUX 2 */ 736 <0>, /* USB 2 Phy PCIE PIPEGMUX */ 737 <0>, /* USB 2 Phy PIPEGMUX */ 738 <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ 739 <0>, /* PCIe 3a */ 740 <&pcie3b_phy>, /* PCIe 3b */ 741 <&pcie4_phy>, /* PCIe 4 */ 742 <&pcie5_phy>, /* PCIe 5 */ 743 <&pcie6_phy>, /* PCIe 6 */ 744 <0>, /* QUSB4 0 PHY RX 0 */ 745 <0>, /* QUSB4 0 PHY RX 1 */ 746 <0>, /* QUSB4 1 PHY RX 0 */ 747 <0>, /* QUSB4 1 PHY RX 1 */ 748 <0>, /* QUSB4 2 PHY RX 0 */ 749 <0>, /* QUSB4 2 PHY RX 1 */ 750 <0>, /* UFS PHY RX Symbol 0 */ 751 <0>, /* UFS PHY RX Symbol 1 */ 752 <0>, /* UFS PHY TX Symbol 0 */ 753 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 754 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 755 <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 756 <&usb_mp_qmpphy0 QMP_USB43DP_USB3_PIPE_CLK>, 757 <&usb_mp_qmpphy1 QMP_USB43DP_USB3_PIPE_CLK>, 758 <0>, /* USB4 PHY 0 pcie pipe */ 759 <0>, /* USB4 PHY 0 Max pipe */ 760 <0>, /* USB4 PHY 1 pcie pipe */ 761 <0>, /* USB4 PHY 1 Max pipe */ 762 <0>, /* USB4 PHY 2 pcie */ 763 <0>; /* USB4 PHY 2 Max */ 764 #clock-cells = <1>; 765 #reset-cells = <1>; 766 #power-domain-cells = <1>; 767 }; 768 769 gpi_dma2: dma-controller@800000 { 770 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 771 reg = <0x0 0x00800000 0x0 0x60000>; 772 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>; 788 dma-channels = <16>; 789 dma-channel-mask = <0x3f>; 790 #dma-cells = <3>; 791 iommus = <&apps_smmu 0xd76 0x0>; 792 }; 793 794 qupv3_2: geniqup@8c0000 { 795 compatible = "qcom,geni-se-qup"; 796 reg = <0x0 0x008c0000 0x0 0x3000>; 797 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 798 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 799 clock-names = "m-ahb", 800 "s-ahb"; 801 iommus = <&apps_smmu 0xd63 0x0>; 802 #address-cells = <2>; 803 #size-cells = <2>; 804 ranges; 805 806 i2c16: i2c@880000 { 807 compatible = "qcom,geni-i2c"; 808 reg = <0x0 0x00880000 0x0 0x4000>; 809 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 811 clock-names = "se"; 812 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 813 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 814 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 815 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 816 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 817 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 818 interconnect-names = "qup-core", 819 "qup-config", 820 "qup-memory"; 821 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 822 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 823 dma-names = "tx", 824 "rx"; 825 pinctrl-0 = <&qup_i2c16_data_clk>; 826 pinctrl-names = "default"; 827 #address-cells = <1>; 828 #size-cells = <0>; 829 830 status = "disabled"; 831 }; 832 833 spi16: spi@880000 { 834 compatible = "qcom,geni-spi"; 835 reg = <0x0 0x00880000 0x0 0x4000>; 836 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 838 clock-names = "se"; 839 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 840 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 841 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 842 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 843 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 844 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 845 interconnect-names = "qup-core", 846 "qup-config", 847 "qup-memory"; 848 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 849 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 850 dma-names = "tx", 851 "rx"; 852 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 853 pinctrl-names = "default"; 854 #address-cells = <1>; 855 #size-cells = <0>; 856 857 status = "disabled"; 858 }; 859 860 i2c17: i2c@884000 { 861 compatible = "qcom,geni-i2c"; 862 reg = <0x0 0x00884000 0x0 0x4000>; 863 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 865 clock-names = "se"; 866 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 867 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 868 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 869 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 870 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 871 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 872 interconnect-names = "qup-core", 873 "qup-config", 874 "qup-memory"; 875 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 876 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 877 dma-names = "tx", 878 "rx"; 879 pinctrl-0 = <&qup_i2c17_data_clk>; 880 pinctrl-names = "default"; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 884 status = "disabled"; 885 }; 886 887 spi17: spi@884000 { 888 compatible = "qcom,geni-spi"; 889 reg = <0x0 0x00884000 0x0 0x4000>; 890 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 892 clock-names = "se"; 893 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 894 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 895 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 896 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 897 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 898 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 899 interconnect-names = "qup-core", 900 "qup-config", 901 "qup-memory"; 902 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 903 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 904 dma-names = "tx", 905 "rx"; 906 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 907 pinctrl-names = "default"; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 911 status = "disabled"; 912 }; 913 914 i2c18: i2c@888000 { 915 compatible = "qcom,geni-i2c"; 916 reg = <0x0 0x00888000 0x0 0x4000>; 917 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 919 clock-names = "se"; 920 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 921 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 922 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 923 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 924 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 925 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 926 interconnect-names = "qup-core", 927 "qup-config", 928 "qup-memory"; 929 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 930 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 931 dma-names = "tx", 932 "rx"; 933 pinctrl-0 = <&qup_i2c18_data_clk>; 934 pinctrl-names = "default"; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 938 status = "disabled"; 939 }; 940 941 spi18: spi@888000 { 942 compatible = "qcom,geni-spi"; 943 reg = <0x0 0x00888000 0x0 0x4000>; 944 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 946 clock-names = "se"; 947 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 948 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 949 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 950 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 951 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 952 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 953 interconnect-names = "qup-core", 954 "qup-config", 955 "qup-memory"; 956 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 957 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 958 dma-names = "tx", 959 "rx"; 960 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 961 pinctrl-names = "default"; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 965 status = "disabled"; 966 }; 967 968 i2c19: i2c@88c000 { 969 compatible = "qcom,geni-i2c"; 970 reg = <0x0 0x0088c000 0x0 0x4000>; 971 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 972 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 973 clock-names = "se"; 974 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 975 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 976 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 977 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 978 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 979 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 980 interconnect-names = "qup-core", 981 "qup-config", 982 "qup-memory"; 983 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 984 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 985 dma-names = "tx", 986 "rx"; 987 pinctrl-0 = <&qup_i2c19_data_clk>; 988 pinctrl-names = "default"; 989 #address-cells = <1>; 990 #size-cells = <0>; 991 992 status = "disabled"; 993 }; 994 995 spi19: spi@88c000 { 996 compatible = "qcom,geni-spi"; 997 reg = <0x0 0x0088c000 0x0 0x4000>; 998 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1000 clock-names = "se"; 1001 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1002 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1003 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1004 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1005 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1006 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1007 interconnect-names = "qup-core", 1008 "qup-config", 1009 "qup-memory"; 1010 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1011 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1012 dma-names = "tx", 1013 "rx"; 1014 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1015 pinctrl-names = "default"; 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 1019 status = "disabled"; 1020 }; 1021 1022 uart19: serial@88c000 { 1023 compatible = "qcom,geni-uart"; 1024 reg = <0x0 0x0088c000 0x0 0x4000>; 1025 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1027 clock-names = "se"; 1028 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1029 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1030 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1031 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1032 interconnect-names = "qup-core", 1033 "qup-config"; 1034 pinctrl-0 = <&qup_uart19_default>; 1035 pinctrl-names = "default"; 1036 1037 status = "disabled"; 1038 }; 1039 1040 i2c20: i2c@890000 { 1041 compatible = "qcom,geni-i2c"; 1042 reg = <0x0 0x00890000 0x0 0x4000>; 1043 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1045 clock-names = "se"; 1046 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1047 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1048 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1049 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1050 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1051 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1052 interconnect-names = "qup-core", 1053 "qup-config", 1054 "qup-memory"; 1055 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1056 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1057 dma-names = "tx", 1058 "rx"; 1059 pinctrl-0 = <&qup_i2c20_data_clk>; 1060 pinctrl-names = "default"; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 1064 status = "disabled"; 1065 }; 1066 1067 spi20: spi@890000 { 1068 compatible = "qcom,geni-spi"; 1069 reg = <0x0 0x00890000 0x0 0x4000>; 1070 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1071 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1072 clock-names = "se"; 1073 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1074 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1075 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1076 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1077 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1078 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1079 interconnect-names = "qup-core", 1080 "qup-config", 1081 "qup-memory"; 1082 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1083 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1084 dma-names = "tx", 1085 "rx"; 1086 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1087 pinctrl-names = "default"; 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 1091 status = "disabled"; 1092 }; 1093 1094 i2c21: i2c@894000 { 1095 compatible = "qcom,geni-i2c"; 1096 reg = <0x0 0x00894000 0x0 0x4000>; 1097 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1098 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1099 clock-names = "se"; 1100 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1101 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1102 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1103 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1104 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1105 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1106 interconnect-names = "qup-core", 1107 "qup-config", 1108 "qup-memory"; 1109 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1110 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1111 dma-names = "tx", 1112 "rx"; 1113 pinctrl-0 = <&qup_i2c21_data_clk>; 1114 pinctrl-names = "default"; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 1118 status = "disabled"; 1119 }; 1120 1121 spi21: spi@894000 { 1122 compatible = "qcom,geni-spi"; 1123 reg = <0x0 0x00894000 0x0 0x4000>; 1124 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1126 clock-names = "se"; 1127 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1128 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1129 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1130 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1131 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1132 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1133 interconnect-names = "qup-core", 1134 "qup-config", 1135 "qup-memory"; 1136 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1137 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1138 dma-names = "tx", 1139 "rx"; 1140 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1141 pinctrl-names = "default"; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 1145 status = "disabled"; 1146 }; 1147 1148 uart21: serial@894000 { 1149 compatible = "qcom,geni-debug-uart"; 1150 reg = <0x0 0x00894000 0x0 0x4000>; 1151 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1152 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1153 clock-names = "se"; 1154 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1155 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1156 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1157 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1158 interconnect-names = "qup-core", 1159 "qup-config"; 1160 pinctrl-0 = <&qup_uart21_default>; 1161 pinctrl-names = "default"; 1162 }; 1163 1164 i2c22: i2c@898000 { 1165 compatible = "qcom,geni-i2c"; 1166 reg = <0x0 0x00898000 0x0 0x4000>; 1167 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1168 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1169 clock-names = "se"; 1170 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1171 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1172 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1173 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1174 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1175 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1176 interconnect-names = "qup-core", 1177 "qup-config", 1178 "qup-memory"; 1179 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1180 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1181 dma-names = "tx", 1182 "rx"; 1183 pinctrl-0 = <&qup_i2c22_data_clk>; 1184 pinctrl-names = "default"; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 1188 status = "disabled"; 1189 }; 1190 1191 spi22: spi@898000 { 1192 compatible = "qcom,geni-spi"; 1193 reg = <0x0 0x00898000 0x0 0x4000>; 1194 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1195 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1196 clock-names = "se"; 1197 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1198 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1199 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1200 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1201 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1202 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1203 interconnect-names = "qup-core", 1204 "qup-config", 1205 "qup-memory"; 1206 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1207 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1208 dma-names = "tx", 1209 "rx"; 1210 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1211 pinctrl-names = "default"; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 1215 status = "disabled"; 1216 }; 1217 1218 uart22: serial@898000 { 1219 compatible = "qcom,geni-uart"; 1220 reg = <0x0 0x00898000 0x0 0x4000>; 1221 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1222 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1223 clock-names = "se"; 1224 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1225 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1226 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1227 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1228 interconnect-names = "qup-core", 1229 "qup-config"; 1230 pinctrl-0 = <&qup_uart22_default>; 1231 pinctrl-names = "default"; 1232 1233 status = "disabled"; 1234 }; 1235 1236 i2c23: i2c@89c000 { 1237 compatible = "qcom,geni-i2c"; 1238 reg = <0x0 0x0089c000 0x0 0x4000>; 1239 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1240 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1241 clock-names = "se"; 1242 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1243 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1244 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1245 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1246 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1247 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1248 interconnect-names = "qup-core", 1249 "qup-config", 1250 "qup-memory"; 1251 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1252 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1253 dma-names = "tx", 1254 "rx"; 1255 pinctrl-0 = <&qup_i2c23_data_clk>; 1256 pinctrl-names = "default"; 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 1260 status = "disabled"; 1261 }; 1262 1263 spi23: spi@89c000 { 1264 compatible = "qcom,geni-spi"; 1265 reg = <0x0 0x0089c000 0x0 0x4000>; 1266 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1267 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1268 clock-names = "se"; 1269 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1270 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1271 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1272 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1273 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1274 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1275 interconnect-names = "qup-core", 1276 "qup-config", 1277 "qup-memory"; 1278 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1279 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1280 dma-names = "tx", 1281 "rx"; 1282 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1283 pinctrl-names = "default"; 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 1287 status = "disabled"; 1288 }; 1289 }; 1290 1291 gpi_dma1: dma-controller@a00000 { 1292 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 1293 reg = <0x0 0x00a00000 0x0 0x60000>; 1294 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1306 <GIC_ESPI 124 IRQ_TYPE_LEVEL_HIGH>, 1307 <GIC_ESPI 125 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_ESPI 126 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_ESPI 127 IRQ_TYPE_LEVEL_HIGH>; 1310 dma-channels = <16>; 1311 dma-channel-mask = <0x3f>; 1312 #dma-cells = <3>; 1313 iommus = <&apps_smmu 0xcb6 0x0>; 1314 }; 1315 1316 qupv3_1: geniqup@ac0000 { 1317 compatible = "qcom,geni-se-qup"; 1318 reg = <0x0 0x00ac0000 0x0 0x3000>; 1319 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1320 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1321 clock-names = "m-ahb", 1322 "s-ahb"; 1323 iommus = <&apps_smmu 0xca3 0x0>; 1324 #address-cells = <2>; 1325 #size-cells = <2>; 1326 ranges; 1327 1328 i2c8: i2c@a80000 { 1329 compatible = "qcom,geni-i2c"; 1330 reg = <0x0 0x00a80000 0x0 0x4000>; 1331 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1332 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1333 clock-names = "se"; 1334 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1335 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1336 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1337 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1338 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1339 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1340 interconnect-names = "qup-core", 1341 "qup-config", 1342 "qup-memory"; 1343 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1344 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1345 dma-names = "tx", 1346 "rx"; 1347 pinctrl-0 = <&qup_i2c8_data_clk>; 1348 pinctrl-names = "default"; 1349 #address-cells = <1>; 1350 #size-cells = <0>; 1351 1352 status = "disabled"; 1353 }; 1354 1355 spi8: spi@a80000 { 1356 compatible = "qcom,geni-spi"; 1357 reg = <0x0 0x00a80000 0x0 0x4000>; 1358 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1359 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1360 clock-names = "se"; 1361 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1362 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1363 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1364 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1365 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1366 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1367 interconnect-names = "qup-core", 1368 "qup-config", 1369 "qup-memory"; 1370 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1371 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1372 dma-names = "tx", 1373 "rx"; 1374 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1375 pinctrl-names = "default"; 1376 #address-cells = <1>; 1377 #size-cells = <0>; 1378 1379 status = "disabled"; 1380 }; 1381 1382 i2c9: i2c@a84000 { 1383 compatible = "qcom,geni-i2c"; 1384 reg = <0x0 0x00a84000 0x0 0x4000>; 1385 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1386 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1387 clock-names = "se"; 1388 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1389 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1390 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1391 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1392 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1393 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1394 interconnect-names = "qup-core", 1395 "qup-config", 1396 "qup-memory"; 1397 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1398 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1399 dma-names = "tx", 1400 "rx"; 1401 pinctrl-0 = <&qup_i2c9_data_clk>; 1402 pinctrl-names = "default"; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 1406 status = "disabled"; 1407 }; 1408 1409 spi9: spi@a84000 { 1410 compatible = "qcom,geni-spi"; 1411 reg = <0x0 0x00a84000 0x0 0x4000>; 1412 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1413 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1414 clock-names = "se"; 1415 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1416 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1417 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1418 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1419 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1420 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1421 interconnect-names = "qup-core", 1422 "qup-config", 1423 "qup-memory"; 1424 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1425 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1426 dma-names = "tx", 1427 "rx"; 1428 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1429 pinctrl-names = "default"; 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 1433 status = "disabled"; 1434 }; 1435 1436 i2c10: i2c@a88000 { 1437 compatible = "qcom,geni-i2c"; 1438 reg = <0x0 0x00a88000 0x0 0x4000>; 1439 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1440 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1441 clock-names = "se"; 1442 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1443 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1444 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1445 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1446 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1447 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1448 interconnect-names = "qup-core", 1449 "qup-config", 1450 "qup-memory"; 1451 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1452 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1453 dma-names = "tx", 1454 "rx"; 1455 pinctrl-0 = <&qup_i2c10_data_clk>; 1456 pinctrl-names = "default"; 1457 #address-cells = <1>; 1458 #size-cells = <0>; 1459 1460 status = "disabled"; 1461 }; 1462 1463 spi10: spi@a88000 { 1464 compatible = "qcom,geni-spi"; 1465 reg = <0x0 0x00a88000 0x0 0x4000>; 1466 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1467 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1468 clock-names = "se"; 1469 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1470 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1471 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1472 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1473 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1474 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1475 interconnect-names = "qup-core", 1476 "qup-config", 1477 "qup-memory"; 1478 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1479 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1480 dma-names = "tx", 1481 "rx"; 1482 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1483 pinctrl-names = "default"; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 1487 status = "disabled"; 1488 }; 1489 1490 i2c11: i2c@a8c000 { 1491 compatible = "qcom,geni-i2c"; 1492 reg = <0x0 0x00a8c000 0x0 0x4000>; 1493 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1494 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1495 clock-names = "se"; 1496 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1497 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1498 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1499 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1500 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1501 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1502 interconnect-names = "qup-core", 1503 "qup-config", 1504 "qup-memory"; 1505 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1506 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1507 dma-names = "tx", 1508 "rx"; 1509 pinctrl-0 = <&qup_i2c11_data_clk>; 1510 pinctrl-names = "default"; 1511 #address-cells = <1>; 1512 #size-cells = <0>; 1513 1514 status = "disabled"; 1515 }; 1516 1517 spi11: spi@a8c000 { 1518 compatible = "qcom,geni-spi"; 1519 reg = <0x0 0x00a8c000 0x0 0x4000>; 1520 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1521 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1522 clock-names = "se"; 1523 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1524 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1525 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1526 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1527 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1528 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1529 interconnect-names = "qup-core", 1530 "qup-config", 1531 "qup-memory"; 1532 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1533 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1534 dma-names = "tx", 1535 "rx"; 1536 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1537 pinctrl-names = "default"; 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 1541 status = "disabled"; 1542 }; 1543 1544 i2c12: i2c@a90000 { 1545 compatible = "qcom,geni-i2c"; 1546 reg = <0x0 0x00a90000 0x0 0x4000>; 1547 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1548 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1549 clock-names = "se"; 1550 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1551 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1552 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1553 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1554 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1555 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1556 interconnect-names = "qup-core", 1557 "qup-config", 1558 "qup-memory"; 1559 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1560 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1561 dma-names = "tx", 1562 "rx"; 1563 pinctrl-0 = <&qup_i2c12_data_clk>; 1564 pinctrl-names = "default"; 1565 #address-cells = <1>; 1566 #size-cells = <0>; 1567 1568 status = "disabled"; 1569 }; 1570 1571 spi12: spi@a90000 { 1572 compatible = "qcom,geni-spi"; 1573 reg = <0x0 0x00a90000 0x0 0x4000>; 1574 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1575 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1576 clock-names = "se"; 1577 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1578 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1579 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1580 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1581 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1582 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1583 interconnect-names = "qup-core", 1584 "qup-config", 1585 "qup-memory"; 1586 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1587 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1588 dma-names = "tx", 1589 "rx"; 1590 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1591 pinctrl-names = "default"; 1592 #address-cells = <1>; 1593 #size-cells = <0>; 1594 1595 status = "disabled"; 1596 }; 1597 1598 i2c13: i2c@a94000 { 1599 compatible = "qcom,geni-i2c"; 1600 reg = <0x0 0x00a94000 0x0 0x4000>; 1601 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1602 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1603 clock-names = "se"; 1604 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1605 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1606 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1607 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1608 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1609 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1610 interconnect-names = "qup-core", 1611 "qup-config", 1612 "qup-memory"; 1613 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1614 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1615 dma-names = "tx", 1616 "rx"; 1617 pinctrl-0 = <&qup_i2c13_data_clk>; 1618 pinctrl-names = "default"; 1619 #address-cells = <1>; 1620 #size-cells = <0>; 1621 1622 status = "disabled"; 1623 }; 1624 1625 spi13: spi@a94000 { 1626 compatible = "qcom,geni-spi"; 1627 reg = <0x0 0x00a94000 0x0 0x4000>; 1628 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1629 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1630 clock-names = "se"; 1631 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1632 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1633 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1634 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1635 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1636 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1637 interconnect-names = "qup-core", 1638 "qup-config", 1639 "qup-memory"; 1640 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1641 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1642 dma-names = "tx", 1643 "rx"; 1644 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1645 pinctrl-names = "default"; 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 1649 status = "disabled"; 1650 }; 1651 1652 i2c14: i2c@a98000 { 1653 compatible = "qcom,geni-i2c"; 1654 reg = <0x0 0x00a98000 0x0 0x4000>; 1655 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1656 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1657 clock-names = "se"; 1658 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1659 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1660 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1661 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1662 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1663 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1664 interconnect-names = "qup-core", 1665 "qup-config", 1666 "qup-memory"; 1667 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1668 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1669 dma-names = "tx", 1670 "rx"; 1671 pinctrl-0 = <&qup_i2c14_data_clk>; 1672 pinctrl-names = "default"; 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 1676 status = "disabled"; 1677 }; 1678 1679 spi14: spi@a98000 { 1680 compatible = "qcom,geni-spi"; 1681 reg = <0x0 0x00a98000 0x0 0x4000>; 1682 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1683 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1684 clock-names = "se"; 1685 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1686 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1687 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1688 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1689 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1690 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1691 interconnect-names = "qup-core", 1692 "qup-config", 1693 "qup-memory"; 1694 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1695 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1696 dma-names = "tx", 1697 "rx"; 1698 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1699 pinctrl-names = "default"; 1700 #address-cells = <1>; 1701 #size-cells = <0>; 1702 1703 status = "disabled"; 1704 }; 1705 1706 uart14: serial@a98000 { 1707 compatible = "qcom,geni-uart"; 1708 reg = <0x0 0x00a98000 0x0 0x4000>; 1709 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1710 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1711 clock-names = "se"; 1712 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1713 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1714 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1715 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1716 interconnect-names = "qup-core", 1717 "qup-config"; 1718 pinctrl-0 = <&qup_uart14_default>; 1719 pinctrl-names = "default"; 1720 1721 status = "disabled"; 1722 }; 1723 1724 i2c15: i2c@a9c000 { 1725 compatible = "qcom,geni-i2c"; 1726 reg = <0x0 0x00a9c000 0x0 0x4000>; 1727 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1728 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1729 clock-names = "se"; 1730 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1731 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1732 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1733 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1734 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1735 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1736 interconnect-names = "qup-core", 1737 "qup-config", 1738 "qup-memory"; 1739 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1740 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1741 dma-names = "tx", 1742 "rx"; 1743 pinctrl-0 = <&qup_i2c15_data_clk>; 1744 pinctrl-names = "default"; 1745 #address-cells = <1>; 1746 #size-cells = <0>; 1747 1748 status = "disabled"; 1749 }; 1750 1751 spi15: spi@a9c000 { 1752 compatible = "qcom,geni-spi"; 1753 reg = <0x0 0x00a9c000 0x0 0x4000>; 1754 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1755 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1756 clock-names = "se"; 1757 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1758 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1759 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1760 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1761 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1762 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1763 interconnect-names = "qup-core", 1764 "qup-config", 1765 "qup-memory"; 1766 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1767 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1768 dma-names = "tx", 1769 "rx"; 1770 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1771 pinctrl-names = "default"; 1772 #address-cells = <1>; 1773 #size-cells = <0>; 1774 1775 status = "disabled"; 1776 }; 1777 }; 1778 1779 gpi_dma0: dma-controller@b00000 { 1780 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 1781 reg = <0x0 0x00b00000 0x0 0x60000>; 1782 interrupts = <GIC_ESPI 76 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_ESPI 77 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_ESPI 78 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_ESPI 79 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_ESPI 80 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_ESPI 81 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_ESPI 82 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_ESPI 83 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_ESPI 84 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_ESPI 85 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_ESPI 86 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_ESPI 87 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_ESPI 88 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_ESPI 89 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_ESPI 90 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_ESPI 91 IRQ_TYPE_LEVEL_HIGH>; 1798 dma-channels = <16>; 1799 dma-channel-mask = <0x3f>; 1800 #dma-cells = <3>; 1801 iommus = <&apps_smmu 0xd36 0x0>; 1802 }; 1803 1804 qupv3_0: geniqup@bc0000 { 1805 compatible = "qcom,geni-se-qup"; 1806 reg = <0x0 0x00bc0000 0x0 0x3000>; 1807 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1808 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1809 clock-names = "m-ahb", 1810 "s-ahb"; 1811 iommus = <&apps_smmu 0xd23 0x0>; 1812 #address-cells = <2>; 1813 #size-cells = <2>; 1814 ranges; 1815 1816 i2c0: i2c@b80000 { 1817 compatible = "qcom,geni-i2c"; 1818 reg = <0x0 0x00b80000 0x0 0x4000>; 1819 interrupts = <GIC_ESPI 92 IRQ_TYPE_LEVEL_HIGH>; 1820 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1821 clock-names = "se"; 1822 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1823 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1824 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1825 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1826 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1827 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1828 interconnect-names = "qup-core", 1829 "qup-config", 1830 "qup-memory"; 1831 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1832 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1833 dma-names = "tx", 1834 "rx"; 1835 pinctrl-0 = <&qup_i2c0_data_clk>; 1836 pinctrl-names = "default"; 1837 #address-cells = <1>; 1838 #size-cells = <0>; 1839 1840 status = "disabled"; 1841 }; 1842 1843 spi0: spi@b80000 { 1844 compatible = "qcom,geni-spi"; 1845 reg = <0x0 0x00b80000 0x0 0x4000>; 1846 interrupts = <GIC_SPI 1052 IRQ_TYPE_LEVEL_HIGH>; 1847 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1848 clock-names = "se"; 1849 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1850 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1851 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1852 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1853 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1854 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1855 interconnect-names = "qup-core", 1856 "qup-config", 1857 "qup-memory"; 1858 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1859 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1860 dma-names = "tx", 1861 "rx"; 1862 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1863 pinctrl-names = "default"; 1864 #address-cells = <1>; 1865 #size-cells = <0>; 1866 1867 status = "disabled"; 1868 }; 1869 1870 i2c1: i2c@b84000 { 1871 compatible = "qcom,geni-i2c"; 1872 reg = <0x0 0x00b84000 0x0 0x4000>; 1873 interrupts = <GIC_SPI 1053 IRQ_TYPE_LEVEL_HIGH>; 1874 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1875 clock-names = "se"; 1876 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1877 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1878 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1879 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1880 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1881 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1882 interconnect-names = "qup-core", 1883 "qup-config", 1884 "qup-memory"; 1885 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1886 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1887 dma-names = "tx", 1888 "rx"; 1889 pinctrl-0 = <&qup_i2c1_data_clk>; 1890 pinctrl-names = "default"; 1891 #address-cells = <1>; 1892 #size-cells = <0>; 1893 1894 status = "disabled"; 1895 }; 1896 1897 spi1: spi@b84000 { 1898 compatible = "qcom,geni-spi"; 1899 reg = <0x0 0x00b84000 0x0 0x4000>; 1900 interrupts = <GIC_SPI 1053 IRQ_TYPE_LEVEL_HIGH>; 1901 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1902 clock-names = "se"; 1903 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1904 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1905 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1906 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1907 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1908 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1909 interconnect-names = "qup-core", 1910 "qup-config", 1911 "qup-memory"; 1912 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1913 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1914 dma-names = "tx", 1915 "rx"; 1916 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1917 pinctrl-names = "default"; 1918 #address-cells = <1>; 1919 #size-cells = <0>; 1920 1921 status = "disabled"; 1922 }; 1923 1924 i2c2: i2c@b88000 { 1925 compatible = "qcom,geni-i2c"; 1926 reg = <0x0 0x00b88000 0x0 0x4000>; 1927 interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>; 1928 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1929 clock-names = "se"; 1930 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1931 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1932 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1933 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1934 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1935 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1936 interconnect-names = "qup-core", 1937 "qup-config", 1938 "qup-memory"; 1939 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1940 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1941 dma-names = "tx", 1942 "rx"; 1943 pinctrl-0 = <&qup_i2c2_data_clk>; 1944 pinctrl-names = "default"; 1945 #address-cells = <1>; 1946 #size-cells = <0>; 1947 1948 status = "disabled"; 1949 }; 1950 1951 spi2: spi@b88000 { 1952 compatible = "qcom,geni-spi"; 1953 reg = <0x0 0x00b88000 0x0 0x4000>; 1954 interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>; 1955 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1956 clock-names = "se"; 1957 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1958 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1959 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1960 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1961 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1962 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1963 interconnect-names = "qup-core", 1964 "qup-config", 1965 "qup-memory"; 1966 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1967 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1968 dma-names = "tx", 1969 "rx"; 1970 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1971 pinctrl-names = "default"; 1972 #address-cells = <1>; 1973 #size-cells = <0>; 1974 1975 status = "disabled"; 1976 }; 1977 1978 uart2: serial@b88000 { 1979 compatible = "qcom,geni-uart"; 1980 reg = <0x0 0x00b88000 0x0 0x4000>; 1981 interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>; 1982 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1983 clock-names = "se"; 1984 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1985 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1986 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1987 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1988 interconnect-names = "qup-core", 1989 "qup-config"; 1990 pinctrl-0 = <&qup_uart2_default>; 1991 pinctrl-names = "default"; 1992 1993 status = "disabled"; 1994 }; 1995 1996 i2c3: i2c@b8c000 { 1997 compatible = "qcom,geni-i2c"; 1998 reg = <0x0 0x00b8c000 0x0 0x4000>; 1999 interrupts = <GIC_ESPI 95 IRQ_TYPE_LEVEL_HIGH>; 2000 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2001 clock-names = "se"; 2002 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2003 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2004 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2005 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2006 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2007 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2008 interconnect-names = "qup-core", 2009 "qup-config", 2010 "qup-memory"; 2011 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2012 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2013 dma-names = "tx", 2014 "rx"; 2015 pinctrl-0 = <&qup_i2c3_data_clk>; 2016 pinctrl-names = "default"; 2017 #address-cells = <1>; 2018 #size-cells = <0>; 2019 2020 status = "disabled"; 2021 }; 2022 2023 spi3: spi@b8c000 { 2024 compatible = "qcom,geni-spi"; 2025 reg = <0x0 0x00b8c000 0x0 0x4000>; 2026 interrupts = <GIC_SPI 1055 IRQ_TYPE_LEVEL_HIGH>; 2027 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2028 clock-names = "se"; 2029 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2030 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2031 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2032 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2033 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2034 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2035 interconnect-names = "qup-core", 2036 "qup-config", 2037 "qup-memory"; 2038 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2039 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2040 dma-names = "tx", 2041 "rx"; 2042 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2043 pinctrl-names = "default"; 2044 #address-cells = <1>; 2045 #size-cells = <0>; 2046 2047 status = "disabled"; 2048 }; 2049 2050 i2c4: i2c@b90000 { 2051 compatible = "qcom,geni-i2c"; 2052 reg = <0x0 0x00b90000 0x0 0x4000>; 2053 interrupts = <GIC_ESPI 96 IRQ_TYPE_LEVEL_HIGH>; 2054 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2055 clock-names = "se"; 2056 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2057 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2058 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2059 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2060 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2061 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2062 interconnect-names = "qup-core", 2063 "qup-config", 2064 "qup-memory"; 2065 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2066 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2067 dma-names = "tx", 2068 "rx"; 2069 pinctrl-0 = <&qup_i2c4_data_clk>; 2070 pinctrl-names = "default"; 2071 #address-cells = <1>; 2072 #size-cells = <0>; 2073 2074 status = "disabled"; 2075 }; 2076 2077 spi4: spi@b90000 { 2078 compatible = "qcom,geni-spi"; 2079 reg = <0x0 0x00b90000 0x0 0x4000>; 2080 interrupts = <GIC_SPI 1056 IRQ_TYPE_LEVEL_HIGH>; 2081 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2082 clock-names = "se"; 2083 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2084 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2085 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2086 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2087 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2088 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2089 interconnect-names = "qup-core", 2090 "qup-config", 2091 "qup-memory"; 2092 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2093 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2094 dma-names = "tx", 2095 "rx"; 2096 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2097 pinctrl-names = "default"; 2098 #address-cells = <1>; 2099 #size-cells = <0>; 2100 2101 status = "disabled"; 2102 }; 2103 2104 i2c5: i2c@b94000 { 2105 compatible = "qcom,geni-i2c"; 2106 reg = <0x0 0x00b94000 0x0 0x4000>; 2107 interrupts = <GIC_ESPI 97 IRQ_TYPE_LEVEL_HIGH>; 2108 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2109 clock-names = "se"; 2110 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2111 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2112 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2113 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2114 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2115 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2116 interconnect-names = "qup-core", 2117 "qup-config", 2118 "qup-memory"; 2119 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2120 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2121 dma-names = "tx", 2122 "rx"; 2123 pinctrl-0 = <&qup_i2c5_data_clk>; 2124 pinctrl-names = "default"; 2125 #address-cells = <1>; 2126 #size-cells = <0>; 2127 2128 status = "disabled"; 2129 }; 2130 2131 spi5: spi@b94000 { 2132 compatible = "qcom,geni-spi"; 2133 reg = <0x0 0x00b94000 0x0 0x4000>; 2134 interrupts = <GIC_SPI 1057 IRQ_TYPE_LEVEL_HIGH>; 2135 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2136 clock-names = "se"; 2137 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2138 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2139 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2140 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2141 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2142 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2143 interconnect-names = "qup-core", 2144 "qup-config", 2145 "qup-memory"; 2146 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2147 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2148 dma-names = "tx", 2149 "rx"; 2150 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2151 pinctrl-names = "default"; 2152 #address-cells = <1>; 2153 #size-cells = <0>; 2154 2155 status = "disabled"; 2156 }; 2157 2158 i2c6: i2c@b98000 { 2159 compatible = "qcom,geni-i2c"; 2160 reg = <0x0 0x00b98000 0x0 0x4000>; 2161 interrupts = <GIC_SPI 1058 IRQ_TYPE_LEVEL_HIGH>; 2162 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2163 clock-names = "se"; 2164 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2165 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2166 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2167 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2168 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2169 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2170 interconnect-names = "qup-core", 2171 "qup-config", 2172 "qup-memory"; 2173 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2174 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2175 dma-names = "tx", 2176 "rx"; 2177 pinctrl-0 = <&qup_i2c6_data_clk>; 2178 pinctrl-names = "default"; 2179 #address-cells = <1>; 2180 #size-cells = <0>; 2181 2182 status = "disabled"; 2183 }; 2184 2185 spi6: spi@b98000 { 2186 compatible = "qcom,geni-spi"; 2187 reg = <0x0 0x00b98000 0x0 0x4000>; 2188 interrupts = <GIC_SPI 1058 IRQ_TYPE_LEVEL_HIGH>; 2189 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2190 clock-names = "se"; 2191 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2192 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2193 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2194 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2195 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2196 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2197 interconnect-names = "qup-core", 2198 "qup-config", 2199 "qup-memory"; 2200 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2201 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2202 dma-names = "tx", 2203 "rx"; 2204 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2205 pinctrl-names = "default"; 2206 #address-cells = <1>; 2207 #size-cells = <0>; 2208 2209 status = "disabled"; 2210 }; 2211 2212 i2c7: i2c@b9c000 { 2213 compatible = "qcom,geni-i2c"; 2214 reg = <0x0 0x00b9c000 0x0 0x4000>; 2215 interrupts = <GIC_SPI 1059 IRQ_TYPE_LEVEL_HIGH>; 2216 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2217 clock-names = "se"; 2218 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2219 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2220 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2221 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2222 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2223 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2224 interconnect-names = "qup-core", 2225 "qup-config", 2226 "qup-memory"; 2227 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2228 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2229 dma-names = "tx", 2230 "rx"; 2231 pinctrl-0 = <&qup_i2c7_data_clk>; 2232 pinctrl-names = "default"; 2233 #address-cells = <1>; 2234 #size-cells = <0>; 2235 2236 status = "disabled"; 2237 }; 2238 2239 spi7: spi@b9c000 { 2240 compatible = "qcom,geni-spi"; 2241 reg = <0x0 0x00b9c000 0x0 0x4000>; 2242 interrupts = <GIC_SPI 1059 IRQ_TYPE_LEVEL_HIGH>; 2243 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2244 clock-names = "se"; 2245 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2246 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2247 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2248 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2249 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2250 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2251 interconnect-names = "qup-core", 2252 "qup-config", 2253 "qup-memory"; 2254 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2255 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2256 dma-names = "tx", 2257 "rx"; 2258 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2259 pinctrl-names = "default"; 2260 #address-cells = <1>; 2261 #size-cells = <0>; 2262 2263 status = "disabled"; 2264 }; 2265 }; 2266 2267 usb_hs_phy: phy@fa0000 { 2268 compatible = "qcom,glymur-m31-eusb2-phy", 2269 "qcom,sm8750-m31-eusb2-phy"; 2270 reg = <0x0 0x00fa0000 0x0 0x154>; 2271 #phy-cells = <0>; 2272 2273 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2274 clock-names = "ref"; 2275 2276 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 2277 2278 status = "disabled"; 2279 }; 2280 2281 usb_mp_hsphy0: phy@fa1000 { 2282 compatible = "qcom,glymur-m31-eusb2-phy", 2283 "qcom,sm8750-m31-eusb2-phy"; 2284 2285 reg = <0x0 0x00fa1000 0x0 0x29c>; 2286 #phy-cells = <0>; 2287 2288 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2289 clock-names = "ref"; 2290 2291 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2292 2293 status = "disabled"; 2294 }; 2295 2296 usb_mp_hsphy1: phy@fa2000 { 2297 compatible = "qcom,glymur-m31-eusb2-phy", 2298 "qcom,sm8750-m31-eusb2-phy"; 2299 2300 reg = <0x0 0x00fa2000 0x0 0x29c>; 2301 #phy-cells = <0>; 2302 2303 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 2304 clock-names = "ref"; 2305 2306 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2307 2308 status = "disabled"; 2309 }; 2310 2311 usb_mp_qmpphy0: phy@fa3000 { 2312 compatible = "qcom,glymur-qmp-usb3-uni-phy"; 2313 reg = <0x0 0x00fa3000 0x0 0x2000>; 2314 2315 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2316 <&tcsr TCSR_USB3_0_CLKREF_EN>, 2317 <&rpmhcc RPMH_CXO_CLK>, 2318 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2319 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2320 clock-names = "aux", 2321 "clkref", 2322 "ref", 2323 "com_aux", 2324 "pipe"; 2325 2326 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; 2327 2328 resets = <&gcc GCC_USB3_MP_SS0_PHY_BCR>, 2329 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2330 reset-names = "phy", 2331 "phy_phy"; 2332 2333 clock-output-names = "usb3_uni_phy_0_pipe_clk_src"; 2334 #clock-cells = <0>; 2335 #phy-cells = <0>; 2336 2337 status = "disabled"; 2338 }; 2339 2340 usb_mp_qmpphy1: phy@fa5000 { 2341 compatible = "qcom,glymur-qmp-usb3-uni-phy"; 2342 reg = <0x0 0x00fa5000 0x0 0x2000>; 2343 2344 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2345 <&tcsr TCSR_USB3_1_CLKREF_EN>, 2346 <&rpmhcc RPMH_CXO_CLK>, 2347 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2348 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2349 clock-names = "aux", 2350 "clkref", 2351 "ref", 2352 "com_aux", 2353 "pipe"; 2354 2355 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; 2356 2357 resets = <&gcc GCC_USB3_MP_SS1_PHY_BCR>, 2358 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2359 reset-names = "phy", 2360 "phy_phy"; 2361 2362 clock-output-names = "usb3_uni_phy_1_pipe_clk_src"; 2363 2364 #clock-cells = <0>; 2365 #phy-cells = <0>; 2366 2367 status = "disabled"; 2368 }; 2369 2370 mdss_dp3_phy: phy@faac00 { 2371 compatible = "qcom,glymur-dp-phy"; 2372 reg = <0x0 0x00faac00 0x0 0x1d0>, 2373 <0x0 0x00faa400 0x0 0x128>, 2374 <0x0 0x00faa800 0x0 0x128>, 2375 <0x0 0x00faa000 0x0 0x358>; 2376 2377 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 2378 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2379 <&tcsr TCSR_EDP_CLKREF_EN>; 2380 clock-names = "aux", 2381 "cfg_ahb", 2382 "ref"; 2383 2384 power-domains = <&rpmhpd RPMHPD_MX>; 2385 2386 #clock-cells = <1>; 2387 #phy-cells = <0>; 2388 2389 status = "disabled"; 2390 }; 2391 2392 usb_0_hsphy: phy@fd3000 { 2393 compatible = "qcom,glymur-m31-eusb2-phy", 2394 "qcom,sm8750-m31-eusb2-phy"; 2395 2396 reg = <0x0 0x00fd3000 0x0 0x29c>; 2397 #phy-cells = <0>; 2398 2399 clocks = <&rpmhcc RPMH_CXO_CLK>; 2400 clock-names = "ref"; 2401 2402 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2403 2404 status = "disabled"; 2405 }; 2406 2407 usb_0_qmpphy: phy@fd5000 { 2408 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 2409 reg = <0x0 0x00fd5000 0x0 0x8000>; 2410 2411 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2412 <&rpmhcc RPMH_CXO_CLK>, 2413 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2414 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2415 clock-names = "aux", 2416 "ref", 2417 "com_aux", 2418 "usb3_pipe"; 2419 2420 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2421 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 2422 2423 reset-names = "phy", 2424 "common"; 2425 2426 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2427 2428 #clock-cells = <1>; 2429 #phy-cells = <1>; 2430 2431 mode-switch; 2432 orientation-switch; 2433 2434 status = "disabled"; 2435 2436 ports { 2437 #address-cells = <1>; 2438 #size-cells = <0>; 2439 2440 port@0 { 2441 reg = <0>; 2442 2443 usb_0_qmpphy_out: endpoint { 2444 }; 2445 }; 2446 2447 port@1 { 2448 reg = <1>; 2449 2450 usb_0_qmpphy_usb_ss_in: endpoint { 2451 remote-endpoint = <&usb_0_dwc3_ss>; 2452 }; 2453 }; 2454 2455 port@2 { 2456 reg = <2>; 2457 2458 usb_dp_qmpphy_dp_in: endpoint { 2459 remote-endpoint = <&mdss_dp0_out>; 2460 }; 2461 }; 2462 }; 2463 }; 2464 2465 usb_1_hsphy: phy@fdd000 { 2466 compatible = "qcom,glymur-m31-eusb2-phy", 2467 "qcom,sm8750-m31-eusb2-phy"; 2468 2469 reg = <0x0 0x00fdd000 0x0 0x29c>; 2470 #phy-cells = <0>; 2471 2472 clocks = <&rpmhcc RPMH_CXO_CLK>; 2473 clock-names = "ref"; 2474 2475 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2476 2477 status = "disabled"; 2478 }; 2479 2480 usb_1_qmpphy: phy@fde000 { 2481 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 2482 reg = <0x0 0x00fde000 0x0 0x8000>; 2483 2484 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2485 <&rpmhcc RPMH_CXO_CLK>, 2486 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2487 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, 2488 <&tcsr TCSR_USB4_1_CLKREF_EN>; 2489 clock-names = "aux", 2490 "ref", 2491 "com_aux", 2492 "usb3_pipe", 2493 "clkref"; 2494 2495 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2496 2497 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2498 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2499 reset-names = "phy", 2500 "common"; 2501 2502 #clock-cells = <1>; 2503 #phy-cells = <1>; 2504 2505 mode-switch; 2506 orientation-switch; 2507 2508 status = "disabled"; 2509 2510 ports { 2511 #address-cells = <1>; 2512 #size-cells = <0>; 2513 2514 port@0 { 2515 reg = <0>; 2516 2517 usb_1_qmpphy_out: endpoint { 2518 }; 2519 }; 2520 2521 port@1 { 2522 reg = <1>; 2523 2524 usb_1_qmpphy_usb_ss_in: endpoint { 2525 remote-endpoint = <&usb_1_dwc3_ss>; 2526 }; 2527 }; 2528 2529 port@2 { 2530 reg = <2>; 2531 2532 usb_1_qmpphy_dp_in: endpoint { 2533 remote-endpoint = <&mdss_dp1_out>; 2534 }; 2535 }; 2536 }; 2537 }; 2538 2539 2540 /* cluster0 */ 2541 bwmon_cluster0: pmu@100c400 { 2542 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2543 reg = <0x0 0x0100c400 0x0 0x600>; 2544 2545 interrupts = <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>; 2546 2547 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2548 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2549 2550 operating-points-v2 = <&cpu_bwmon_opp_table>; 2551 2552 cpu_bwmon_opp_table: opp-table { 2553 compatible = "operating-points-v2"; 2554 2555 opp-0 { 2556 opp-peak-kBps = <800000>; 2557 }; 2558 2559 opp-1 { 2560 opp-peak-kBps = <2188800>; 2561 }; 2562 2563 opp-2 { 2564 opp-peak-kBps = <5414400>; 2565 }; 2566 2567 opp-3 { 2568 opp-peak-kBps = <6220800>; 2569 }; 2570 2571 opp-4 { 2572 opp-peak-kBps = <6835200>; 2573 }; 2574 2575 opp-5 { 2576 opp-peak-kBps = <8371200>; 2577 }; 2578 2579 opp-6 { 2580 opp-peak-kBps = <10944000>; 2581 }; 2582 2583 opp-7 { 2584 opp-peak-kBps = <12748800>; 2585 }; 2586 2587 opp-8 { 2588 opp-peak-kBps = <14745600>; 2589 }; 2590 2591 opp-9 { 2592 opp-peak-kBps = <16896000>; 2593 }; 2594 2595 opp-10 { 2596 opp-peak-kBps = <19046400>; 2597 }; 2598 2599 opp-11 { 2600 opp-peak-kBps = <21332000>; 2601 }; 2602 }; 2603 }; 2604 2605 /* cluster1 */ 2606 bwmon_cluster1: pmu@100d400 { 2607 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2608 reg = <0x0 0x0100d400 0x0 0x600>; 2609 2610 interrupts = <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>; 2611 2612 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2613 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2614 2615 operating-points-v2 = <&cpu_bwmon_opp_table>; 2616 }; 2617 2618 /* cluster2 */ 2619 bwmon_cluster2: pmu@100e400 { 2620 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2621 reg = <0x0 0x0100e400 0x0 0x600>; 2622 2623 interrupts = <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>; 2624 2625 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2626 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2627 2628 operating-points-v2 = <&cpu_bwmon_opp_table>; 2629 }; 2630 cnoc_main: interconnect@1500000 { 2631 compatible = "qcom,glymur-cnoc-main"; 2632 reg = <0x0 0x01500000 0x0 0x17080>; 2633 qcom,bcm-voters = <&apps_bcm_voter>; 2634 #interconnect-cells = <2>; 2635 }; 2636 2637 config_noc: interconnect@1600000 { 2638 compatible = "qcom,glymur-cnoc-cfg"; 2639 reg = <0x0 0x01600000 0x0 0x6600>; 2640 qcom,bcm-voters = <&apps_bcm_voter>; 2641 #interconnect-cells = <2>; 2642 }; 2643 2644 system_noc: interconnect@1680000 { 2645 compatible = "qcom,glymur-system-noc"; 2646 reg = <0x0 0x01680000 0x0 0x1c080>; 2647 qcom,bcm-voters = <&apps_bcm_voter>; 2648 #interconnect-cells = <2>; 2649 }; 2650 2651 pcie_west_anoc: interconnect@16c0000 { 2652 compatible = "qcom,glymur-pcie-west-anoc"; 2653 reg = <0x0 0x016c0000 0x0 0xf580>; 2654 qcom,bcm-voters = <&apps_bcm_voter>; 2655 #interconnect-cells = <2>; 2656 clocks = <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>, 2657 <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>, 2658 <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>, 2659 <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; 2660 }; 2661 2662 pcie_east_anoc: interconnect@16d0000 { 2663 compatible = "qcom,glymur-pcie-east-anoc"; 2664 reg = <0x0 0x016d0000 0x0 0xf300>; 2665 qcom,bcm-voters = <&apps_bcm_voter>; 2666 #interconnect-cells = <2>; 2667 clocks = <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; 2668 }; 2669 2670 aggre1_noc: interconnect@16e0000 { 2671 compatible = "qcom,glymur-aggre1-noc"; 2672 reg = <0x0 0x016e0000 0x0 0x14400>; 2673 qcom,bcm-voters = <&apps_bcm_voter>; 2674 #interconnect-cells = <2>; 2675 }; 2676 2677 aggre2_noc: interconnect@1720000 { 2678 compatible = "qcom,glymur-aggre2-noc"; 2679 reg = <0x0 0x01720000 0x0 0x14400>; 2680 qcom,bcm-voters = <&apps_bcm_voter>; 2681 #interconnect-cells = <2>; 2682 clocks = <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 2683 <&gcc GCC_AGGRE_USB4_2_AXI_CLK>, 2684 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 2685 }; 2686 2687 aggre3_noc: interconnect@1700000 { 2688 compatible = "qcom,glymur-aggre3-noc"; 2689 reg = <0x0 0x01700000 0x0 0x1d400>; 2690 qcom,bcm-voters = <&apps_bcm_voter>; 2691 #interconnect-cells = <2>; 2692 }; 2693 2694 aggre4_noc: interconnect@1740000 { 2695 compatible = "qcom,glymur-aggre4-noc"; 2696 reg = <0x0 0x01740000 0x0 0x14400>; 2697 qcom,bcm-voters = <&apps_bcm_voter>; 2698 #interconnect-cells = <2>; 2699 clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2700 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2701 <&gcc GCC_AGGRE_USB4_0_AXI_CLK>, 2702 <&gcc GCC_AGGRE_USB4_1_AXI_CLK>; 2703 }; 2704 2705 mmss_noc: interconnect@1780000 { 2706 compatible = "qcom,glymur-mmss-noc"; 2707 reg = <0x0 0x01780000 0x0 0x5b800>; 2708 qcom,bcm-voters = <&apps_bcm_voter>; 2709 #interconnect-cells = <2>; 2710 }; 2711 2712 pcie_east_slv_noc: interconnect@1900000 { 2713 compatible = "qcom,glymur-pcie-east-slv-noc"; 2714 reg = <0x0 0x01900000 0x0 0xe080>; 2715 qcom,bcm-voters = <&apps_bcm_voter>; 2716 #interconnect-cells = <2>; 2717 }; 2718 2719 pcie_west_slv_noc: interconnect@1920000 { 2720 compatible = "qcom,glymur-pcie-west-slv-noc"; 2721 reg = <0x0 0x01920000 0x0 0xf180>; 2722 qcom,bcm-voters = <&apps_bcm_voter>; 2723 #interconnect-cells = <2>; 2724 }; 2725 2726 pcie4: pci@1bf0000 { 2727 device_type = "pci"; 2728 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 2729 reg = <0x0 0x01bf0000 0x0 0x3000>, 2730 <0x0 0x78000000 0x0 0xf20>, 2731 <0x0 0x78000f40 0x0 0xa8>, 2732 <0x0 0x78001000 0x0 0x4000>, 2733 <0x0 0x78005000 0x0 0x100000>, 2734 <0x0 0x01bf3000 0x0 0x1000>; 2735 reg-names = "parf", 2736 "dbi", 2737 "elbi", 2738 "atu", 2739 "config", 2740 "mhi"; 2741 #address-cells = <3>; 2742 #size-cells = <2>; 2743 ranges = <0x01000000 0x0 0x00000000 0x0 0x78105000 0x0 0x100000>, 2744 <0x02000000 0x0 0x78205000 0x0 0x78205000 0x0 0x1dfb000>, 2745 <0x03000000 0x7 0x80000000 0x7 0x80000000 0x0 0x20000000>; 2746 bus-range = <0x00 0xff>; 2747 2748 dma-coherent; 2749 2750 linux,pci-domain = <4>; 2751 num-lanes = <2>; 2752 2753 operating-points-v2 = <&pcie4_opp_table>; 2754 2755 msi-map = <0x0 &gic_its 0xc0000 0x10000>; 2756 iommu-map = <0x0 &pcie_smmu 0x40000 0x10000>; 2757 2758 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 2759 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2760 <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2761 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 2762 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, 2763 <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>, 2764 <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>, 2765 <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>, 2766 <GIC_SPI 944 IRQ_TYPE_LEVEL_HIGH>; 2767 interrupt-names = "msi0", 2768 "msi1", 2769 "msi2", 2770 "msi3", 2771 "msi4", 2772 "msi5", 2773 "msi6", 2774 "msi7", 2775 "global"; 2776 2777 #interrupt-cells = <1>; 2778 interrupt-map-mask = <0 0 0 0x7>; 2779 interrupt-map = <0 0 0 1 &intc 0 0 0 513 IRQ_TYPE_LEVEL_HIGH>, 2780 <0 0 0 2 &intc 0 0 0 514 IRQ_TYPE_LEVEL_HIGH>, 2781 <0 0 0 3 &intc 0 0 0 515 IRQ_TYPE_LEVEL_HIGH>, 2782 <0 0 0 4 &intc 0 0 0 516 IRQ_TYPE_LEVEL_HIGH>; 2783 2784 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2785 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2786 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 2787 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 2788 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 2789 <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>; 2790 clock-names = "aux", 2791 "cfg", 2792 "bus_master", 2793 "bus_slave", 2794 "slave_q2a", 2795 "noc_aggr"; 2796 2797 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 2798 assigned-clock-rates = <19200000>; 2799 2800 interconnects = <&pcie_west_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 2801 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2802 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2803 &pcie_west_slv_noc SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; 2804 interconnect-names = "pcie-mem", 2805 "cpu-pcie"; 2806 2807 resets = <&gcc GCC_PCIE_4_BCR>, 2808 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 2809 reset-names = "pci", 2810 "link_down"; 2811 2812 power-domains = <&gcc GCC_PCIE_4_GDSC>; 2813 2814 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 2815 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 2816 2817 status = "disabled"; 2818 2819 pcie4_opp_table: opp-table { 2820 compatible = "operating-points-v2"; 2821 2822 /* GEN 1 x1 */ 2823 opp-2500000-1 { 2824 opp-hz = /bits/ 64 <2500000>; 2825 required-opps = <&rpmhpd_opp_low_svs>; 2826 opp-peak-kBps = <250000 1>; 2827 opp-level = <1>; 2828 }; 2829 2830 /* GEN 1 x2 */ 2831 opp-5000000-1 { 2832 opp-hz = /bits/ 64 <5000000>; 2833 required-opps = <&rpmhpd_opp_low_svs>; 2834 opp-peak-kBps = <500000 1>; 2835 opp-level = <1>; 2836 }; 2837 2838 /* GEN 2 x1 */ 2839 opp-5000000-2 { 2840 opp-hz = /bits/ 64 <5000000>; 2841 required-opps = <&rpmhpd_opp_low_svs>; 2842 opp-peak-kBps = <500000 1>; 2843 opp-level = <2>; 2844 }; 2845 2846 /* GEN 2 x2 */ 2847 opp-10000000-2 { 2848 opp-hz = /bits/ 64 <10000000>; 2849 required-opps = <&rpmhpd_opp_low_svs>; 2850 opp-peak-kBps = <1000000 1>; 2851 opp-level = <2>; 2852 }; 2853 2854 /* GEN 3 x1 */ 2855 opp-8000000-3 { 2856 opp-hz = /bits/ 64 <8000000>; 2857 required-opps = <&rpmhpd_opp_low_svs>; 2858 opp-peak-kBps = <984500 1>; 2859 opp-level = <3>; 2860 }; 2861 2862 /* GEN 3 x2 */ 2863 opp-16000000-3 { 2864 opp-hz = /bits/ 64 <16000000>; 2865 required-opps = <&rpmhpd_opp_low_svs>; 2866 opp-peak-kBps = <1969000 1>; 2867 opp-level = <3>; 2868 }; 2869 2870 /* GEN 4 x1 */ 2871 opp-16000000-4 { 2872 opp-hz = /bits/ 64 <16000000>; 2873 required-opps = <&rpmhpd_opp_low_svs>; 2874 opp-peak-kBps = <1969000 1>; 2875 opp-level = <4>; 2876 }; 2877 2878 /* GEN 4 x2 */ 2879 opp-32000000-4 { 2880 opp-hz = /bits/ 64 <32000000>; 2881 required-opps = <&rpmhpd_opp_low_svs>; 2882 opp-peak-kBps = <3938000 1>; 2883 opp-level = <4>; 2884 }; 2885 2886 }; 2887 2888 pcie4_port0: pcie@0 { 2889 device_type = "pci"; 2890 reg = <0x0 0x0 0x0 0x0 0x0>; 2891 bus-range = <0x01 0xff>; 2892 2893 phys = <&pcie4_phy>; 2894 2895 #address-cells = <3>; 2896 #size-cells = <2>; 2897 ranges; 2898 }; 2899 }; 2900 2901 pcie4_phy: phy@1bf6000 { 2902 compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; 2903 reg = <0x0 0x01bf6000 0x0 0x2000>; 2904 2905 clocks = <&gcc GCC_PCIE_PHY_4_AUX_CLK>, 2906 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2907 <&tcsr TCSR_PCIE_2_CLKREF_EN>, 2908 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 2909 <&gcc GCC_PCIE_4_PIPE_CLK>, 2910 <&gcc GCC_PCIE_4_PIPE_DIV2_CLK>; 2911 clock-names = "aux", 2912 "cfg_ahb", 2913 "ref", 2914 "rchng", 2915 "pipe", 2916 "pipediv2"; 2917 2918 resets = <&gcc GCC_PCIE_4_PHY_BCR>, 2919 <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; 2920 reset-names = "phy", 2921 "phy_nocsr"; 2922 2923 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 2924 assigned-clock-rates = <100000000>; 2925 2926 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 2927 2928 #clock-cells = <0>; 2929 clock-output-names = "pcie4_pipe_clk"; 2930 2931 #phy-cells = <0>; 2932 2933 status = "disabled"; 2934 }; 2935 2936 pcie5: pci@1b40000 { 2937 device_type = "pci"; 2938 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 2939 reg = <0x0 0x01b40000 0x0 0x3000>, 2940 <0x0 0x7a000000 0x0 0xf20>, 2941 <0x0 0x7a000f40 0x0 0xa8>, 2942 <0x0 0x7a001000 0x0 0x4000>, 2943 <0x0 0x7a100000 0x0 0x100000>, 2944 <0x0 0x01b43000 0x0 0x1000>; 2945 reg-names = "parf", 2946 "dbi", 2947 "elbi", 2948 "atu", 2949 "config", 2950 "mhi"; 2951 #address-cells = <3>; 2952 #size-cells = <2>; 2953 ranges = <0x01000000 0x0 0x00000000 0x0 0x7a200000 0x0 0x100000>, 2954 <0x02000000 0x0 0x7a300000 0x0 0x7a300000 0x0 0x3d00000>, 2955 <0x03000000 0x7 0xa0000000 0x7 0xa0000000 0x0 0x40000000>; 2956 bus-range = <0x00 0xff>; 2957 2958 dma-coherent; 2959 2960 linux,pci-domain = <5>; 2961 num-lanes = <4>; 2962 2963 operating-points-v2 = <&pcie5_opp_table>; 2964 2965 msi-map = <0x0 &gic_its 0xd0000 0x10000>; 2966 iommu-map = <0x0 &pcie_smmu 0x50000 0x10000>; 2967 2968 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 2969 <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 2970 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>, 2971 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>, 2972 <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>, 2973 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2974 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2975 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>, 2976 <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>; 2977 interrupt-names = "msi0", 2978 "msi1", 2979 "msi2", 2980 "msi3", 2981 "msi4", 2982 "msi5", 2983 "msi6", 2984 "msi7", 2985 "global"; 2986 2987 #interrupt-cells = <1>; 2988 interrupt-map-mask = <0 0 0 0x7>; 2989 interrupt-map = <0 0 0 1 &intc 0 0 0 526 IRQ_TYPE_LEVEL_HIGH>, 2990 <0 0 0 2 &intc 0 0 0 428 IRQ_TYPE_LEVEL_HIGH>, 2991 <0 0 0 3 &intc 0 0 0 429 IRQ_TYPE_LEVEL_HIGH>, 2992 <0 0 0 4 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>; 2993 2994 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 2995 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 2996 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, 2997 <&gcc GCC_PCIE_5_SLV_AXI_CLK>, 2998 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, 2999 <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; 3000 clock-names = "aux", 3001 "cfg", 3002 "bus_master", 3003 "bus_slave", 3004 "slave_q2a", 3005 "noc_aggr"; 3006 3007 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; 3008 assigned-clock-rates = <19200000>; 3009 3010 interconnects = <&pcie_east_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS 3011 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3012 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3013 &pcie_east_slv_noc SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; 3014 interconnect-names = "pcie-mem", 3015 "cpu-pcie"; 3016 3017 resets = <&gcc GCC_PCIE_5_BCR>, 3018 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; 3019 reset-names = "pci", 3020 "link_down"; 3021 3022 power-domains = <&gcc GCC_PCIE_5_GDSC>; 3023 3024 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3025 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3026 eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3027 3028 status = "disabled"; 3029 3030 pcie5_opp_table: opp-table { 3031 compatible = "operating-points-v2"; 3032 3033 /* GEN 1 x1 */ 3034 opp-2500000-1 { 3035 opp-hz = /bits/ 64 <2500000>; 3036 required-opps = <&rpmhpd_opp_low_svs>; 3037 opp-peak-kBps = <250000 1>; 3038 opp-level = <1>; 3039 }; 3040 3041 /* GEN 1 x2 */ 3042 opp-5000000-1 { 3043 opp-hz = /bits/ 64 <5000000>; 3044 required-opps = <&rpmhpd_opp_low_svs>; 3045 opp-peak-kBps = <500000 1>; 3046 opp-level = <1>; 3047 }; 3048 3049 /* GEN 1 x4 */ 3050 opp-10000000-1 { 3051 opp-hz = /bits/ 64 <10000000>; 3052 required-opps = <&rpmhpd_opp_low_svs>; 3053 opp-peak-kBps = <1000000 1>; 3054 opp-level = <1>; 3055 }; 3056 3057 /* GEN 2 x1 */ 3058 opp-5000000-2 { 3059 opp-hz = /bits/ 64 <5000000>; 3060 required-opps = <&rpmhpd_opp_low_svs>; 3061 opp-peak-kBps = <500000 1>; 3062 opp-level = <2>; 3063 }; 3064 3065 /* GEN 2 x2 */ 3066 opp-10000000-2 { 3067 opp-hz = /bits/ 64 <10000000>; 3068 required-opps = <&rpmhpd_opp_low_svs>; 3069 opp-peak-kBps = <1000000 1>; 3070 opp-level = <2>; 3071 }; 3072 3073 /* GEN 2 x4 */ 3074 opp-20000000-2 { 3075 opp-hz = /bits/ 64 <20000000>; 3076 required-opps = <&rpmhpd_opp_low_svs>; 3077 opp-peak-kBps = <2000000 1>; 3078 opp-level = <2>; 3079 }; 3080 3081 /* GEN 3 x1 */ 3082 opp-8000000-3 { 3083 opp-hz = /bits/ 64 <8000000>; 3084 required-opps = <&rpmhpd_opp_low_svs>; 3085 opp-peak-kBps = <984500 1>; 3086 opp-level = <3>; 3087 }; 3088 3089 /* GEN 3 x2 */ 3090 opp-16000000-3 { 3091 opp-hz = /bits/ 64 <16000000>; 3092 required-opps = <&rpmhpd_opp_low_svs>; 3093 opp-peak-kBps = <1969000 1>; 3094 opp-level = <3>; 3095 }; 3096 3097 /* GEN 3 x4 */ 3098 opp-32000000-3 { 3099 opp-hz = /bits/ 64 <32000000>; 3100 required-opps = <&rpmhpd_opp_low_svs>; 3101 opp-peak-kBps = <3938000 1>; 3102 opp-level = <3>; 3103 }; 3104 3105 /* GEN 4 x1 */ 3106 opp-16000000-4 { 3107 opp-hz = /bits/ 64 <16000000>; 3108 required-opps = <&rpmhpd_opp_svs>; 3109 opp-peak-kBps = <1969000 1>; 3110 opp-level = <4>; 3111 }; 3112 3113 /* GEN 4 x2 */ 3114 opp-32000000-4 { 3115 opp-hz = /bits/ 64 <32000000>; 3116 required-opps = <&rpmhpd_opp_svs>; 3117 opp-peak-kBps = <3938000 1>; 3118 opp-level = <4>; 3119 }; 3120 3121 /* GEN 4 x4 */ 3122 opp-64000000-4 { 3123 opp-hz = /bits/ 64 <64000000>; 3124 required-opps = <&rpmhpd_opp_svs>; 3125 opp-peak-kBps = <7876000 1>; 3126 opp-level = <4>; 3127 }; 3128 3129 /* GEN 5 x1 */ 3130 opp-32000000-5 { 3131 opp-hz = /bits/ 64 <32000000>; 3132 required-opps = <&rpmhpd_opp_nom>; 3133 opp-peak-kBps = <3938000 1>; 3134 opp-level = <5>; 3135 }; 3136 3137 /* GEN 5 x2 */ 3138 opp-64000000-5 { 3139 opp-hz = /bits/ 64 <64000000>; 3140 required-opps = <&rpmhpd_opp_nom>; 3141 opp-peak-kBps = <7876000 1>; 3142 opp-level = <5>; 3143 }; 3144 3145 /* GEN 5 x4 */ 3146 opp-128000000-5 { 3147 opp-hz = /bits/ 64 <128000000>; 3148 required-opps = <&rpmhpd_opp_nom>; 3149 opp-peak-kBps = <15753000 1>; 3150 opp-level = <5>; 3151 }; 3152 }; 3153 3154 pcie5_port0: pcie@0 { 3155 device_type = "pci"; 3156 reg = <0x0 0x0 0x0 0x0 0x0>; 3157 bus-range = <0x01 0xff>; 3158 3159 phys = <&pcie5_phy>; 3160 3161 #address-cells = <3>; 3162 #size-cells = <2>; 3163 ranges; 3164 }; 3165 }; 3166 3167 pcie5_phy: phy@1b50000 { 3168 compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; 3169 reg = <0x0 0x01b50000 0x0 0x10000>; 3170 3171 clocks = <&gcc GCC_PCIE_PHY_5_AUX_CLK>, 3172 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3173 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 3174 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, 3175 <&gcc GCC_PCIE_5_PIPE_CLK>, 3176 <&gcc GCC_PCIE_5_PIPE_DIV2_CLK>; 3177 clock-names = "aux", 3178 "cfg_ahb", 3179 "ref", 3180 "rchng", 3181 "pipe", 3182 "pipediv2"; 3183 3184 resets = <&gcc GCC_PCIE_5_PHY_BCR>, 3185 <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; 3186 reset-names = "phy", 3187 "phy_nocsr"; 3188 3189 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; 3190 assigned-clock-rates = <100000000>; 3191 3192 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; 3193 3194 #clock-cells = <0>; 3195 clock-output-names = "pcie5_pipe_clk"; 3196 3197 #phy-cells = <0>; 3198 3199 status = "disabled"; 3200 }; 3201 3202 pcie6: pci@1c00000 { 3203 device_type = "pci"; 3204 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 3205 reg = <0x0 0x01c00000 0x0 0x3000>, 3206 <0x0 0x7e000000 0x0 0xf20>, 3207 <0x0 0x7e000f40 0x0 0xa8>, 3208 <0x0 0x7e001000 0x0 0x4000>, 3209 <0x0 0x7e100000 0x0 0x100000>, 3210 <0x0 0x01c03000 0x0 0x1000>; 3211 reg-names = "parf", 3212 "dbi", 3213 "elbi", 3214 "atu", 3215 "config", 3216 "mhi"; 3217 #address-cells = <3>; 3218 #size-cells = <2>; 3219 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, 3220 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>, 3221 <0x03000000 0x7 0xe0000000 0x7 0xe0000000 0x0 0x20000000>; 3222 bus-range = <0x00 0xff>; 3223 3224 dma-coherent; 3225 3226 linux,pci-domain = <6>; 3227 num-lanes = <2>; 3228 3229 operating-points-v2 = <&pcie6_opp_table>; 3230 3231 msi-map = <0x0 &gic_its 0xe0000 0x10000>; 3232 iommu-map = <0x0 &pcie_smmu 0x60000 0x10000>; 3233 3234 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 3235 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 3236 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 3237 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 3238 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 3239 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 3240 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 3241 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 3242 <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>; 3243 interrupt-names = "msi0", 3244 "msi1", 3245 "msi2", 3246 "msi3", 3247 "msi4", 3248 "msi5", 3249 "msi6", 3250 "msi7", 3251 "global"; 3252 3253 #interrupt-cells = <1>; 3254 interrupt-map-mask = <0 0 0 0x7>; 3255 interrupt-map = <0 0 0 1 &intc 0 0 0 472 IRQ_TYPE_LEVEL_HIGH>, 3256 <0 0 0 2 &intc 0 0 0 473 IRQ_TYPE_LEVEL_HIGH>, 3257 <0 0 0 3 &intc 0 0 0 474 IRQ_TYPE_LEVEL_HIGH>, 3258 <0 0 0 4 &intc 0 0 0 475 IRQ_TYPE_LEVEL_HIGH>; 3259 3260 clocks = <&gcc GCC_PCIE_6_AUX_CLK>, 3261 <&gcc GCC_PCIE_6_CFG_AHB_CLK>, 3262 <&gcc GCC_PCIE_6_MSTR_AXI_CLK>, 3263 <&gcc GCC_PCIE_6_SLV_AXI_CLK>, 3264 <&gcc GCC_PCIE_6_SLV_Q2A_AXI_CLK>, 3265 <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; 3266 clock-names = "aux", 3267 "cfg", 3268 "bus_master", 3269 "bus_slave", 3270 "slave_q2a", 3271 "noc_aggr"; 3272 3273 assigned-clocks = <&gcc GCC_PCIE_6_AUX_CLK>; 3274 assigned-clock-rates = <19200000>; 3275 3276 interconnects = <&pcie_west_anoc MASTER_PCIE_6 QCOM_ICC_TAG_ALWAYS 3277 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3278 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3279 &pcie_west_slv_noc SLAVE_PCIE_6 QCOM_ICC_TAG_ALWAYS>; 3280 interconnect-names = "pcie-mem", 3281 "cpu-pcie"; 3282 3283 resets = <&gcc GCC_PCIE_6_BCR>, 3284 <&gcc GCC_PCIE_6_LINK_DOWN_BCR>; 3285 reset-names = "pci", 3286 "link_down"; 3287 3288 power-domains = <&gcc GCC_PCIE_6_GDSC>; 3289 3290 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3291 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 3292 3293 status = "disabled"; 3294 3295 pcie6_opp_table: opp-table { 3296 compatible = "operating-points-v2"; 3297 3298 /* GEN 1 x1 */ 3299 opp-2500000-1 { 3300 opp-hz = /bits/ 64 <2500000>; 3301 required-opps = <&rpmhpd_opp_low_svs>; 3302 opp-peak-kBps = <250000 1>; 3303 opp-level = <1>; 3304 }; 3305 3306 /* GEN 1 x2 */ 3307 opp-5000000-1 { 3308 opp-hz = /bits/ 64 <5000000>; 3309 required-opps = <&rpmhpd_opp_low_svs>; 3310 opp-peak-kBps = <500000 1>; 3311 opp-level = <1>; 3312 }; 3313 3314 /* GEN 2 x1 */ 3315 opp-5000000-2 { 3316 opp-hz = /bits/ 64 <5000000>; 3317 required-opps = <&rpmhpd_opp_low_svs>; 3318 opp-peak-kBps = <500000 1>; 3319 opp-level = <2>; 3320 }; 3321 3322 /* GEN 2 x2 */ 3323 opp-10000000-2 { 3324 opp-hz = /bits/ 64 <10000000>; 3325 required-opps = <&rpmhpd_opp_low_svs>; 3326 opp-peak-kBps = <1000000 1>; 3327 opp-level = <2>; 3328 }; 3329 3330 /* GEN 3 x1 */ 3331 opp-8000000-3 { 3332 opp-hz = /bits/ 64 <8000000>; 3333 required-opps = <&rpmhpd_opp_low_svs>; 3334 opp-peak-kBps = <984500 1>; 3335 opp-level = <3>; 3336 }; 3337 3338 /* GEN 3 x2 */ 3339 opp-16000000-3 { 3340 opp-hz = /bits/ 64 <16000000>; 3341 required-opps = <&rpmhpd_opp_low_svs>; 3342 opp-peak-kBps = <1969000 1>; 3343 opp-level = <3>; 3344 }; 3345 3346 /* GEN 4 x1 */ 3347 opp-16000000-4 { 3348 opp-hz = /bits/ 64 <16000000>; 3349 required-opps = <&rpmhpd_opp_low_svs>; 3350 opp-peak-kBps = <1969000 1>; 3351 opp-level = <4>; 3352 }; 3353 3354 /* GEN 4 x2 */ 3355 opp-32000000-4 { 3356 opp-hz = /bits/ 64 <32000000>; 3357 required-opps = <&rpmhpd_opp_low_svs>; 3358 opp-peak-kBps = <3938000 1>; 3359 opp-level = <4>; 3360 }; 3361 3362 }; 3363 3364 pcie6_port0: pcie@0 { 3365 device_type = "pci"; 3366 reg = <0x0 0x0 0x0 0x0 0x0>; 3367 bus-range = <0x01 0xff>; 3368 3369 phys = <&pcie6_phy>; 3370 3371 #address-cells = <3>; 3372 #size-cells = <2>; 3373 ranges; 3374 }; 3375 }; 3376 3377 pcie6_phy: phy@1c06000 { 3378 compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; 3379 reg = <0x0 0x01c06000 0x0 0x2000>; 3380 3381 clocks = <&gcc GCC_PCIE_PHY_6_AUX_CLK>, 3382 <&gcc GCC_PCIE_6_CFG_AHB_CLK>, 3383 <&tcsr TCSR_PCIE_4_CLKREF_EN>, 3384 <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>, 3385 <&gcc GCC_PCIE_6_PIPE_CLK>, 3386 <&gcc GCC_PCIE_6_PIPE_DIV2_CLK>; 3387 clock-names = "aux", 3388 "cfg_ahb", 3389 "ref", 3390 "rchng", 3391 "pipe", 3392 "pipediv2"; 3393 3394 resets = <&gcc GCC_PCIE_6_PHY_BCR>, 3395 <&gcc GCC_PCIE_6_NOCSR_COM_PHY_BCR>; 3396 reset-names = "phy", 3397 "phy_nocsr"; 3398 3399 assigned-clocks = <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>; 3400 assigned-clock-rates = <100000000>; 3401 3402 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 3403 3404 #clock-cells = <0>; 3405 clock-output-names = "pcie6_pipe_clk"; 3406 3407 #phy-cells = <0>; 3408 3409 status = "disabled"; 3410 }; 3411 3412 pcie3b: pci@1b80000 { 3413 device_type = "pci"; 3414 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 3415 reg = <0x0 0x01b80000 0x0 0x3000>, 3416 <0x0 0x74000000 0x0 0xf20>, 3417 <0x0 0x74000f40 0x0 0xa8>, 3418 <0x0 0x74001000 0x0 0x4000>, 3419 <0x0 0x74100000 0x0 0x100000>, 3420 <0x0 0x01b83000 0x0 0x1000>; 3421 reg-names = "parf", 3422 "dbi", 3423 "elbi", 3424 "atu", 3425 "config", 3426 "mhi"; 3427 #address-cells = <3>; 3428 #size-cells = <2>; 3429 ranges = <0x01000000 0x0 0x00000000 0x0 0x74200000 0x0 0x100000>, 3430 <0x02000000 0x0 0x74300000 0x0 0x74300000 0x0 0x3d00000>, 3431 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; 3432 bus-range = <0x00 0xff>; 3433 3434 dma-coherent; 3435 3436 linux,pci-domain = <7>; 3437 num-lanes = <4>; 3438 3439 operating-points-v2 = <&pcie3b_opp_table>; 3440 3441 msi-map = <0x0 &gic_its 0xf0000 0x10000>; 3442 iommu-map = <0x0 &pcie_smmu 0x70000 0x10000>; 3443 3444 interrupts = <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 3445 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 3446 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3447 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3448 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3449 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3450 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3451 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 3452 <GIC_SPI 943 IRQ_TYPE_LEVEL_HIGH>; 3453 interrupt-names = "msi0", 3454 "msi1", 3455 "msi2", 3456 "msi3", 3457 "msi4", 3458 "msi5", 3459 "msi6", 3460 "msi7", 3461 "global"; 3462 3463 #interrupt-cells = <1>; 3464 interrupt-map-mask = <0 0 0 0x7>; 3465 interrupt-map = <0 0 0 1 &intc 0 0 0 831 IRQ_TYPE_LEVEL_HIGH>, 3466 <0 0 0 2 &intc 0 0 0 832 IRQ_TYPE_LEVEL_HIGH>, 3467 <0 0 0 3 &intc 0 0 0 833 IRQ_TYPE_LEVEL_HIGH>, 3468 <0 0 0 4 &intc 0 0 0 834 IRQ_TYPE_LEVEL_HIGH>; 3469 3470 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 3471 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 3472 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 3473 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 3474 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 3475 <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>; 3476 clock-names = "aux", 3477 "cfg", 3478 "bus_master", 3479 "bus_slave", 3480 "slave_q2a", 3481 "noc_aggr"; 3482 3483 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 3484 assigned-clock-rates = <19200000>; 3485 3486 interconnects = <&pcie_west_anoc MASTER_PCIE_3B QCOM_ICC_TAG_ALWAYS 3487 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3488 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3489 &pcie_west_slv_noc SLAVE_PCIE_3B QCOM_ICC_TAG_ALWAYS>; 3490 interconnect-names = "pcie-mem", 3491 "cpu-pcie"; 3492 3493 resets = <&gcc GCC_PCIE_3B_BCR>, 3494 <&gcc GCC_PCIE_3B_LINK_DOWN_BCR>; 3495 reset-names = "pci", 3496 "link_down"; 3497 3498 power-domains = <&gcc GCC_PCIE_3B_GDSC>; 3499 3500 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3501 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3502 eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3503 3504 status = "disabled"; 3505 3506 pcie3b_opp_table: opp-table { 3507 compatible = "operating-points-v2"; 3508 3509 /* GEN 1 x1 */ 3510 opp-2500000-1 { 3511 opp-hz = /bits/ 64 <2500000>; 3512 required-opps = <&rpmhpd_opp_low_svs>; 3513 opp-peak-kBps = <250000 1>; 3514 opp-level = <1>; 3515 }; 3516 3517 /* GEN 1 x2 */ 3518 opp-5000000-1 { 3519 opp-hz = /bits/ 64 <5000000>; 3520 required-opps = <&rpmhpd_opp_low_svs>; 3521 opp-peak-kBps = <500000 1>; 3522 opp-level = <1>; 3523 }; 3524 3525 /* GEN 1 x4 */ 3526 opp-10000000-1 { 3527 opp-hz = /bits/ 64 <10000000>; 3528 required-opps = <&rpmhpd_opp_low_svs>; 3529 opp-peak-kBps = <1000000 1>; 3530 opp-level = <1>; 3531 }; 3532 3533 /* GEN 2 x1 */ 3534 opp-5000000-2 { 3535 opp-hz = /bits/ 64 <5000000>; 3536 required-opps = <&rpmhpd_opp_low_svs>; 3537 opp-peak-kBps = <500000 1>; 3538 opp-level = <2>; 3539 }; 3540 3541 /* GEN 2 x2 */ 3542 opp-10000000-2 { 3543 opp-hz = /bits/ 64 <10000000>; 3544 required-opps = <&rpmhpd_opp_low_svs>; 3545 opp-peak-kBps = <1000000 1>; 3546 opp-level = <2>; 3547 }; 3548 3549 /* GEN 2 x4 */ 3550 opp-20000000-2 { 3551 opp-hz = /bits/ 64 <20000000>; 3552 required-opps = <&rpmhpd_opp_low_svs>; 3553 opp-peak-kBps = <2000000 1>; 3554 opp-level = <2>; 3555 }; 3556 3557 /* GEN 3 x1 */ 3558 opp-8000000-3 { 3559 opp-hz = /bits/ 64 <8000000>; 3560 required-opps = <&rpmhpd_opp_low_svs>; 3561 opp-peak-kBps = <984500 1>; 3562 opp-level = <3>; 3563 }; 3564 3565 /* GEN 3 x2 */ 3566 opp-16000000-3 { 3567 opp-hz = /bits/ 64 <16000000>; 3568 required-opps = <&rpmhpd_opp_low_svs>; 3569 opp-peak-kBps = <1969000 1>; 3570 opp-level = <3>; 3571 }; 3572 3573 /* GEN 3 x4 */ 3574 opp-32000000-3 { 3575 opp-hz = /bits/ 64 <32000000>; 3576 required-opps = <&rpmhpd_opp_low_svs>; 3577 opp-peak-kBps = <3938000 1>; 3578 opp-level = <3>; 3579 }; 3580 3581 /* GEN 4 x1 */ 3582 opp-16000000-4 { 3583 opp-hz = /bits/ 64 <16000000>; 3584 required-opps = <&rpmhpd_opp_svs>; 3585 opp-peak-kBps = <1969000 1>; 3586 opp-level = <4>; 3587 }; 3588 3589 /* GEN 4 x2 */ 3590 opp-32000000-4 { 3591 opp-hz = /bits/ 64 <32000000>; 3592 required-opps = <&rpmhpd_opp_svs>; 3593 opp-peak-kBps = <3938000 1>; 3594 opp-level = <4>; 3595 }; 3596 3597 /* GEN 4 x4 */ 3598 opp-64000000-4 { 3599 opp-hz = /bits/ 64 <64000000>; 3600 required-opps = <&rpmhpd_opp_svs>; 3601 opp-peak-kBps = <7876000 1>; 3602 opp-level = <4>; 3603 }; 3604 3605 /* GEN 5 x1 */ 3606 opp-32000000-5 { 3607 opp-hz = /bits/ 64 <32000000>; 3608 required-opps = <&rpmhpd_opp_nom>; 3609 opp-peak-kBps = <3938000 1>; 3610 opp-level = <5>; 3611 }; 3612 3613 /* GEN 5 x2 */ 3614 opp-64000000-5 { 3615 opp-hz = /bits/ 64 <64000000>; 3616 required-opps = <&rpmhpd_opp_nom>; 3617 opp-peak-kBps = <7876000 1>; 3618 opp-level = <5>; 3619 }; 3620 3621 /* GEN 5 x4 */ 3622 opp-128000000-5 { 3623 opp-hz = /bits/ 64 <128000000>; 3624 required-opps = <&rpmhpd_opp_nom>; 3625 opp-peak-kBps = <15753000 1>; 3626 opp-level = <5>; 3627 }; 3628 }; 3629 3630 pcie3b_port0: pcie@0 { 3631 device_type = "pci"; 3632 reg = <0x0 0x0 0x0 0x0 0x0>; 3633 bus-range = <0x01 0xff>; 3634 3635 phys = <&pcie3b_phy>; 3636 3637 #address-cells = <3>; 3638 #size-cells = <2>; 3639 ranges; 3640 }; 3641 }; 3642 3643 pcie3b_phy: phy@f10000 { 3644 compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; 3645 reg = <0x0 0x00f10000 0x0 0x10000>; 3646 3647 clocks = <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, 3648 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 3649 <&tcsr TCSR_PCIE_3_CLKREF_EN>, 3650 <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, 3651 <&gcc GCC_PCIE_3B_PIPE_CLK>, 3652 <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; 3653 clock-names = "aux", 3654 "cfg_ahb", 3655 "ref", 3656 "rchng", 3657 "pipe", 3658 "pipediv2"; 3659 3660 resets = <&gcc GCC_PCIE_3B_PHY_BCR>, 3661 <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; 3662 reset-names = "phy", 3663 "phy_nocsr"; 3664 3665 assigned-clocks = <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; 3666 assigned-clock-rates = <100000000>; 3667 3668 power-domains = <&gcc GCC_PCIE_3B_PHY_GDSC>; 3669 3670 #clock-cells = <0>; 3671 clock-output-names = "pcie3b_pipe_clk"; 3672 3673 #phy-cells = <0>; 3674 3675 status = "disabled"; 3676 }; 3677 3678 tcsr_mutex: hwlock@1f40000 { 3679 compatible = "qcom,tcsr-mutex"; 3680 reg = <0x0 0x01f40000 0x0 0x20000>; 3681 3682 #hwlock-cells = <1>; 3683 }; 3684 3685 tcsr: clock-controller@1fd5000 { 3686 compatible = "qcom,glymur-tcsr", 3687 "syscon"; 3688 reg = <0x0 0x1fd5000 0x0 0x21000>; 3689 clocks = <&rpmhcc RPMH_CXO_CLK>; 3690 #clock-cells = <1>; 3691 #reset-cells = <1>; 3692 }; 3693 3694 hsc_noc: interconnect@2000000 { 3695 compatible = "qcom,glymur-hscnoc"; 3696 reg = <0x0 0x02000000 0x0 0x93a080>; 3697 qcom,bcm-voters = <&apps_bcm_voter>; 3698 #interconnect-cells = <2>; 3699 }; 3700 3701 ipcc: mailbox@3e04000 { 3702 compatible = "qcom,glymur-ipcc", "qcom,ipcc"; 3703 reg = <0x0 0x03e04000 0x0 0x1000>; 3704 3705 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3706 interrupt-controller; 3707 #interrupt-cells = <3>; 3708 3709 #mbox-cells = <2>; 3710 }; 3711 3712 lpass_lpiaon_noc: interconnect@7400000 { 3713 compatible = "qcom,glymur-lpass-lpiaon-noc"; 3714 reg = <0x0 0x07400000 0x0 0x19080>; 3715 qcom,bcm-voters = <&apps_bcm_voter>; 3716 #interconnect-cells = <2>; 3717 }; 3718 3719 lpass_lpicx_noc: interconnect@7420000 { 3720 compatible = "qcom,glymur-lpass-lpicx-noc"; 3721 reg = <0x0 0x07420000 0x0 0x44080>; 3722 qcom,bcm-voters = <&apps_bcm_voter>; 3723 #interconnect-cells = <2>; 3724 }; 3725 3726 lpass_ag_noc: interconnect@7e40000 { 3727 compatible = "qcom,glymur-lpass-ag-noc"; 3728 reg = <0x0 0x07e40000 0x0 0xe080>; 3729 qcom,bcm-voters = <&apps_bcm_voter>; 3730 #interconnect-cells = <2>; 3731 }; 3732 3733 usb_2_hsphy: phy@88e0000 { 3734 compatible = "qcom,glymur-m31-eusb2-phy", 3735 "qcom,sm8750-m31-eusb2-phy"; 3736 3737 reg = <0x0 0x088e0000 0x0 0x29c>; 3738 #phy-cells = <0>; 3739 3740 clocks = <&tcsr TCSR_USB2_4_CLKREF_EN>; 3741 clock-names = "ref"; 3742 3743 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 3744 3745 status = "disabled"; 3746 }; 3747 3748 usb_2_qmpphy: phy@88e1000 { 3749 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 3750 reg = <0x0 0x088e1000 0x0 0x8000>; 3751 3752 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 3753 <&rpmhcc RPMH_CXO_CLK>, 3754 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 3755 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>, 3756 <&tcsr TCSR_USB4_2_CLKREF_EN>; 3757 clock-names = "aux", 3758 "ref", 3759 "com_aux", 3760 "usb3_pipe", 3761 "clkref"; 3762 3763 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 3764 3765 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 3766 <&gcc GCC_USB3PHY_PHY_TERT_BCR>; 3767 reset-names = "phy", 3768 "common"; 3769 3770 #clock-cells = <1>; 3771 #phy-cells = <1>; 3772 3773 mode-switch; 3774 orientation-switch; 3775 3776 status = "disabled"; 3777 3778 ports { 3779 #address-cells = <1>; 3780 #size-cells = <0>; 3781 3782 port@0 { 3783 reg = <0>; 3784 3785 usb_2_qmpphy_out: endpoint { 3786 }; 3787 }; 3788 3789 port@1 { 3790 reg = <1>; 3791 3792 usb_2_qmpphy_usb_ss_in: endpoint { 3793 remote-endpoint = <&usb_2_dwc3_ss>; 3794 }; 3795 }; 3796 3797 port@2 { 3798 reg = <2>; 3799 3800 usb_2_qmpphy_dp_in: endpoint { 3801 remote-endpoint = <&mdss_dp2_out>; 3802 }; 3803 }; 3804 }; 3805 }; 3806 3807 usb_0: usb@a600000 { 3808 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 3809 reg = <0x0 0x0a600000 0x0 0xfc100>; 3810 3811 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3812 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3813 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3814 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3815 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3816 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 3817 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 3818 clock-names = "cfg_noc", 3819 "core", 3820 "iface", 3821 "sleep", 3822 "mock_utmi", 3823 "noc_aggr_north", 3824 "noc_aggr_south"; 3825 3826 interrupts-extended = <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 3827 <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 3828 <&pdc 90 IRQ_TYPE_EDGE_BOTH>, 3829 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 3830 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3831 interrupt-names = "dwc_usb3", 3832 "pwr_event", 3833 "dp_hs_phy_irq", 3834 "dm_hs_phy_irq", 3835 "ss_phy_irq"; 3836 3837 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3838 resets = <&gcc GCC_USB30_PRIM_BCR>; 3839 3840 iommus = <&apps_smmu 0x1420 0x0>; 3841 phys = <&usb_0_hsphy>, 3842 <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 3843 phy-names = "usb2-phy", 3844 "usb3-phy"; 3845 3846 snps,hird-threshold = /bits/ 8 <0x0>; 3847 snps,dis-u1-entry-quirk; 3848 snps,dis-u2-entry-quirk; 3849 snps,is-utmi-l1-suspend; 3850 snps,usb3_lpm_capable; 3851 snps,has-lpm-erratum; 3852 tx-fifo-resize; 3853 snps,dis_u2_susphy_quirk; 3854 snps,dis_enblslpm_quirk; 3855 3856 usb-role-switch; 3857 3858 status = "disabled"; 3859 3860 ports { 3861 #address-cells = <1>; 3862 #size-cells = <0>; 3863 3864 port@0 { 3865 reg = <0>; 3866 3867 usb_0_dwc3_hs: endpoint { 3868 }; 3869 }; 3870 3871 port@1 { 3872 reg = <1>; 3873 3874 usb_0_dwc3_ss: endpoint { 3875 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; 3876 }; 3877 }; 3878 }; 3879 }; 3880 3881 usb_1: usb@a800000 { 3882 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 3883 reg = <0x0 0x0a800000 0x0 0xfc100>; 3884 3885 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3886 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3887 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3888 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3889 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3890 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 3891 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 3892 clock-names = "cfg_noc", 3893 "core", 3894 "iface", 3895 "sleep", 3896 "mock_utmi", 3897 "noc_aggr_north", 3898 "noc_aggr_south"; 3899 3900 interrupts-extended = <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, 3901 <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 3902 <&pdc 88 IRQ_TYPE_EDGE_BOTH>, 3903 <&pdc 87 IRQ_TYPE_EDGE_BOTH>, 3904 <&pdc 76 IRQ_TYPE_EDGE_BOTH>; 3905 interrupt-names = "dwc_usb3", 3906 "pwr_event", 3907 "dp_hs_phy_irq", 3908 "dm_hs_phy_irq", 3909 "ss_phy_irq"; 3910 3911 resets = <&gcc GCC_USB30_SEC_BCR>; 3912 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3913 3914 iommus = <&apps_smmu 0x1460 0x0>; 3915 3916 phys = <&usb_1_hsphy>, 3917 <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3918 phy-names = "usb2-phy", 3919 "usb3-phy"; 3920 3921 snps,hird-threshold = /bits/ 8 <0x0>; 3922 snps,dis-u1-entry-quirk; 3923 snps,dis-u2-entry-quirk; 3924 snps,is-utmi-l1-suspend; 3925 snps,usb3_lpm_capable; 3926 snps,has-lpm-erratum; 3927 tx-fifo-resize; 3928 snps,dis_u2_susphy_quirk; 3929 snps,dis_enblslpm_quirk; 3930 3931 status = "disabled"; 3932 3933 ports { 3934 #address-cells = <1>; 3935 #size-cells = <0>; 3936 3937 port@0 { 3938 reg = <0>; 3939 3940 usb_1_dwc3_hs: endpoint { 3941 }; 3942 }; 3943 3944 port@1 { 3945 reg = <1>; 3946 3947 usb_1_dwc3_ss: endpoint { 3948 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 3949 }; 3950 }; 3951 }; 3952 }; 3953 3954 usb_2: usb@a000000 { 3955 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 3956 reg = <0x0 0x0a000000 0x0 0xfc100>; 3957 3958 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 3959 <&gcc GCC_USB30_TERT_MASTER_CLK>, 3960 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 3961 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 3962 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 3963 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 3964 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 3965 clock-names = "cfg_noc", 3966 "core", 3967 "iface", 3968 "sleep", 3969 "mock_utmi", 3970 "noc_aggr_north", 3971 "noc_aggr_south"; 3972 3973 interrupts-extended = <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>, 3974 <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 3975 <&pdc 89 IRQ_TYPE_EDGE_BOTH>, 3976 <&pdc 81 IRQ_TYPE_EDGE_BOTH>, 3977 <&pdc 75 IRQ_TYPE_EDGE_BOTH>; 3978 interrupt-names = "dwc_usb3", 3979 "pwr_event", 3980 "dp_hs_phy_irq", 3981 "dm_hs_phy_irq", 3982 "ss_phy_irq"; 3983 3984 resets = <&gcc GCC_USB30_TERT_BCR>; 3985 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 3986 3987 iommus = <&apps_smmu 0x420 0x0>; 3988 3989 phys = <&usb_2_hsphy>, 3990 <&usb_2_qmpphy QMP_USB43DP_USB3_PHY>; 3991 phy-names = "usb2-phy", 3992 "usb3-phy"; 3993 3994 snps,hird-threshold = /bits/ 8 <0x0>; 3995 snps,dis-u1-entry-quirk; 3996 snps,dis-u2-entry-quirk; 3997 snps,is-utmi-l1-suspend; 3998 snps,usb3_lpm_capable; 3999 snps,has-lpm-erratum; 4000 tx-fifo-resize; 4001 snps,dis_u2_susphy_quirk; 4002 snps,dis_enblslpm_quirk; 4003 4004 status = "disabled"; 4005 4006 ports { 4007 #address-cells = <1>; 4008 #size-cells = <0>; 4009 4010 port@0 { 4011 reg = <0>; 4012 4013 usb_2_dwc3_hs: endpoint { 4014 }; 4015 }; 4016 4017 port@1 { 4018 reg = <1>; 4019 4020 usb_2_dwc3_ss: endpoint { 4021 remote-endpoint = <&usb_2_qmpphy_usb_ss_in>; 4022 }; 4023 }; 4024 }; 4025 }; 4026 4027 usb_hs: usb@a2f8800 { 4028 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4029 reg = <0x0 0x0a200000 0x0 0xfc100>; 4030 4031 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4032 <&gcc GCC_USB20_MASTER_CLK>, 4033 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4034 <&gcc GCC_USB20_SLEEP_CLK>, 4035 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4036 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4037 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4038 clock-names = "cfg_noc", 4039 "core", 4040 "iface", 4041 "sleep", 4042 "mock_utmi", 4043 "noc_aggr_north", 4044 "noc_aggr_south"; 4045 4046 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4047 <&gcc GCC_USB20_MASTER_CLK>; 4048 assigned-clock-rates = <19200000>, <200000000>; 4049 4050 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4051 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 4052 <&pdc 92 IRQ_TYPE_EDGE_BOTH>, 4053 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 4054 <&intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 4055 interrupt-names = "dwc_usb3", 4056 "pwr_event", 4057 "dp_hs_phy_irq", 4058 "dm_hs_phy_irq", 4059 "hs_phy_irq"; 4060 4061 resets = <&gcc GCC_USB20_PRIM_BCR>; 4062 4063 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 4064 required-opps = <&rpmhpd_opp_nom>; 4065 4066 iommus = <&apps_smmu 0x0ce0 0x0>; 4067 4068 interconnects = <&aggre3_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 4069 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4070 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4071 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4072 interconnect-names = "usb-ddr", 4073 "apps-usb"; 4074 4075 phys = <&usb_hs_phy>; 4076 phy-names = "usb2-phy"; 4077 4078 snps,hird-threshold = /bits/ 8 <0x0>; 4079 snps,dis-u1-entry-quirk; 4080 snps,dis-u2-entry-quirk; 4081 snps,is-utmi-l1-suspend; 4082 snps,usb3_lpm_capable; 4083 snps,has-lpm-erratum; 4084 tx-fifo-resize; 4085 snps,dis_u2_susphy_quirk; 4086 snps,dis_enblslpm_quirk; 4087 4088 dr_mode = "host"; 4089 4090 maximum-speed = "high-speed"; 4091 4092 status = "disabled"; 4093 }; 4094 4095 usb_mp: usb@a400000 { 4096 compatible = "qcom,glymur-dwc3-mp", "qcom,snps-dwc3"; 4097 reg = <0x0 0x0a400000 0x0 0xfc100>; 4098 4099 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 4100 <&gcc GCC_USB30_MP_MASTER_CLK>, 4101 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 4102 <&gcc GCC_USB30_MP_SLEEP_CLK>, 4103 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4104 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4105 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4106 clock-names = "cfg_noc", 4107 "core", 4108 "iface", 4109 "sleep", 4110 "mock_utmi", 4111 "noc_aggr_north", 4112 "noc_aggr_south"; 4113 4114 interrupts-extended = <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 4115 <&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4116 <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 4117 <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 4118 <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 4119 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>, 4120 <&pdc 11 IRQ_TYPE_LEVEL_HIGH>, 4121 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 4122 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>, 4123 <&pdc 78 IRQ_TYPE_LEVEL_HIGH>, 4124 <&pdc 77 IRQ_TYPE_LEVEL_HIGH>; 4125 interrupt-names = "dwc_usb3", 4126 "pwr_event_1", 4127 "pwr_event_2", 4128 "hs_phy_1", 4129 "hs_phy_2", 4130 "dp_hs_phy_1", 4131 "dm_hs_phy_1", 4132 "dp_hs_phy_2", 4133 "dm_hs_phy_2", 4134 "ss_phy_1", 4135 "ss_phy_2"; 4136 4137 resets = <&gcc GCC_USB30_MP_BCR>; 4138 power-domains = <&gcc GCC_USB30_MP_GDSC>; 4139 4140 iommus = <&apps_smmu 0xda0 0x0>; 4141 4142 phys = <&usb_mp_hsphy0>, 4143 <&usb_mp_qmpphy0>, 4144 <&usb_mp_hsphy1>, 4145 <&usb_mp_qmpphy1>; 4146 phy-names = "usb2-0", 4147 "usb3-0", 4148 "usb2-1", 4149 "usb3-1"; 4150 4151 snps,hird-threshold = /bits/ 8 <0x0>; 4152 snps,dis-u1-entry-quirk; 4153 snps,dis-u2-entry-quirk; 4154 snps,is-utmi-l1-suspend; 4155 snps,usb3_lpm_capable; 4156 snps,has-lpm-erratum; 4157 tx-fifo-resize; 4158 snps,dis_u2_susphy_quirk; 4159 snps,dis_enblslpm_quirk; 4160 4161 dr_mode = "host"; 4162 4163 status = "disabled"; 4164 }; 4165 4166 mdss: display-subsystem@ae00000 { 4167 compatible = "qcom,glymur-mdss"; 4168 reg = <0x0 0x0ae00000 0x0 0x1000>; 4169 reg-names = "mdss"; 4170 4171 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4172 4173 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4174 <&gcc GCC_DISP_HF_AXI_CLK>, 4175 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4176 4177 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 4178 4179 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 4180 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4181 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4182 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4183 interconnect-names = "mdp0-mem", 4184 "cpu-cfg"; 4185 4186 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 4187 4188 iommus = <&apps_smmu 0x1de0 0x2>; 4189 4190 interrupt-controller; 4191 #interrupt-cells = <1>; 4192 4193 #address-cells = <2>; 4194 #size-cells = <2>; 4195 ranges; 4196 4197 status = "disabled"; 4198 4199 mdss_mdp: display-controller@ae01000 { 4200 compatible = "qcom,glymur-dpu"; 4201 reg = <0x0 0x0ae01000 0x0 0x93000>, 4202 <0x0 0x0aeb0000 0x0 0x3000>; 4203 reg-names = "mdp", 4204 "vbif"; 4205 4206 interrupts-extended = <&mdss 0>; 4207 4208 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4209 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4210 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 4211 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4212 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4213 clock-names = "nrt_bus", 4214 "iface", 4215 "lut", 4216 "core", 4217 "vsync"; 4218 4219 operating-points-v2 = <&mdp_opp_table>; 4220 4221 power-domains = <&rpmhpd RPMHPD_MMCX>; 4222 4223 ports { 4224 #address-cells = <1>; 4225 #size-cells = <0>; 4226 4227 port@0 { 4228 reg = <0>; 4229 4230 dpu_intf0_out: endpoint { 4231 remote-endpoint = <&mdss_dp0_in>; 4232 }; 4233 }; 4234 4235 port@4 { 4236 reg = <4>; 4237 4238 mdss_intf4_out: endpoint { 4239 remote-endpoint = <&mdss_dp1_in>; 4240 }; 4241 }; 4242 4243 port@5 { 4244 reg = <5>; 4245 4246 mdss_intf5_out: endpoint { 4247 remote-endpoint = <&mdss_dp3_in>; 4248 }; 4249 }; 4250 4251 port@6 { 4252 reg = <6>; 4253 4254 mdss_intf6_out: endpoint { 4255 remote-endpoint = <&mdss_dp2_in>; 4256 }; 4257 }; 4258 }; 4259 4260 mdp_opp_table: opp-table { 4261 compatible = "operating-points-v2"; 4262 4263 opp-156000000 { 4264 opp-hz = /bits/ 64 <156000000>; 4265 required-opps = <&rpmhpd_opp_low_svs_d1>; 4266 }; 4267 4268 opp-205000000 { 4269 opp-hz = /bits/ 64 <205000000>; 4270 required-opps = <&rpmhpd_opp_low_svs>; 4271 }; 4272 4273 opp-337000000 { 4274 opp-hz = /bits/ 64 <337000000>; 4275 required-opps = <&rpmhpd_opp_svs>; 4276 }; 4277 4278 opp-417000000 { 4279 opp-hz = /bits/ 64 <417000000>; 4280 required-opps = <&rpmhpd_opp_svs_l1>; 4281 }; 4282 4283 opp-532000000 { 4284 opp-hz = /bits/ 64 <532000000>; 4285 required-opps = <&rpmhpd_opp_nom>; 4286 }; 4287 4288 opp-600000000 { 4289 opp-hz = /bits/ 64 <600000000>; 4290 required-opps = <&rpmhpd_opp_nom_l1>; 4291 }; 4292 4293 opp-660000000 { 4294 opp-hz = /bits/ 64 <660000000>; 4295 required-opps = <&rpmhpd_opp_turbo>; 4296 }; 4297 4298 opp-717000000 { 4299 opp-hz = /bits/ 64 <717000000>; 4300 required-opps = <&rpmhpd_opp_turbo_l1>; 4301 }; 4302 }; 4303 }; 4304 4305 mdss_dp0: displayport-controller@af54000 { 4306 compatible = "qcom,glymur-dp"; 4307 reg = <0x0 0xaf54000 0x0 0x200>, 4308 <0x0 0xaf54200 0x0 0x200>, 4309 <0x0 0xaf55000 0x0 0xc00>, 4310 <0x0 0xaf56000 0x0 0x400>, 4311 <0x0 0xaf57000 0x0 0x400>, 4312 <0x0 0xaf58000 0x0 0x400>, 4313 <0x0 0xaf59000 0x0 0x400>, 4314 <0x0 0xaf5a000 0x0 0x600>, 4315 <0x0 0xaf5b000 0x0 0x600>; 4316 4317 interrupts-extended = <&mdss 12>; 4318 4319 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4320 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 4321 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 4322 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4323 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 4324 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 4325 clock-names = "core_iface", 4326 "core_aux", 4327 "ctrl_link", 4328 "ctrl_link_iface", 4329 "stream_pixel", 4330 "stream_1_pixel"; 4331 4332 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4333 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 4334 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 4335 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4336 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4337 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4338 4339 operating-points-v2 = <&mdss_dp0_opp_table>; 4340 4341 power-domains = <&rpmhpd RPMHPD_MMCX>; 4342 4343 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 4344 phy-names = "dp"; 4345 4346 #sound-dai-cells = <0>; 4347 4348 status = "disabled"; 4349 4350 ports { 4351 #address-cells = <1>; 4352 #size-cells = <0>; 4353 4354 port@0 { 4355 reg = <0>; 4356 4357 mdss_dp0_in: endpoint { 4358 remote-endpoint = <&dpu_intf0_out>; 4359 }; 4360 }; 4361 4362 port@1 { 4363 reg = <1>; 4364 4365 mdss_dp0_out: endpoint { 4366 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 4367 }; 4368 }; 4369 }; 4370 4371 mdss_dp0_opp_table: opp-table { 4372 compatible = "operating-points-v2"; 4373 4374 opp-270000000 { 4375 opp-hz = /bits/ 64 <270000000>; 4376 required-opps = <&rpmhpd_opp_low_svs>; 4377 }; 4378 4379 opp-540000000 { 4380 opp-hz = /bits/ 64 <540000000>; 4381 required-opps = <&rpmhpd_opp_svs>; 4382 }; 4383 4384 opp-675000000 { 4385 opp-hz = /bits/ 64 <675000000>; 4386 required-opps = <&rpmhpd_opp_svs_l1>; 4387 }; 4388 4389 opp-810000000 { 4390 opp-hz = /bits/ 64 <810000000>; 4391 required-opps = <&rpmhpd_opp_nom>; 4392 }; 4393 }; 4394 }; 4395 4396 mdss_dp1: displayport-controller@af5c000 { 4397 compatible = "qcom,glymur-dp"; 4398 reg = <0x0 0xaf5c000 0x0 0x200>, 4399 <0x0 0xaf5c200 0x0 0x200>, 4400 <0x0 0xaf5d000 0x0 0xc00>, 4401 <0x0 0xaf5e000 0x0 0x400>, 4402 <0x0 0xaf5f000 0x0 0x400>, 4403 <0x0 0xaf60000 0x0 0x400>, 4404 <0x0 0xaf61000 0x0 0x400>, 4405 <0x0 0xaf62000 0x0 0x600>, 4406 <0x0 0xaf63000 0x0 0x600>; 4407 4408 interrupts-extended = <&mdss 13>; 4409 4410 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4411 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, 4412 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, 4413 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4414 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 4415 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 4416 clock-names = "core_iface", 4417 "core_aux", 4418 "ctrl_link", 4419 "ctrl_link_iface", 4420 "stream_pixel", 4421 "stream_1_pixel"; 4422 4423 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4424 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 4425 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 4426 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4427 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4428 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4429 4430 operating-points-v2 = <&mdss_dp0_opp_table>; 4431 4432 power-domains = <&rpmhpd RPMHPD_MMCX>; 4433 4434 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4435 phy-names = "dp"; 4436 4437 #sound-dai-cells = <0>; 4438 4439 status = "disabled"; 4440 4441 ports { 4442 #address-cells = <1>; 4443 #size-cells = <0>; 4444 4445 port@0 { 4446 reg = <0>; 4447 4448 mdss_dp1_in: endpoint { 4449 remote-endpoint = <&mdss_intf4_out>; 4450 }; 4451 }; 4452 4453 port@1 { 4454 reg = <1>; 4455 4456 mdss_dp1_out: endpoint { 4457 remote-endpoint = <&usb_1_qmpphy_dp_in>; 4458 }; 4459 }; 4460 }; 4461 }; 4462 4463 mdss_dp2: displayport-controller@af64000 { 4464 compatible = "qcom,glymur-dp"; 4465 reg = <0x0 0x0af64000 0x0 0x200>, 4466 <0x0 0x0af64200 0x0 0x200>, 4467 <0x0 0x0af65000 0x0 0xc00>, 4468 <0x0 0x0af66000 0x0 0x400>, 4469 <0x0 0x0af67000 0x0 0x400>, 4470 <0x0 0x0af68000 0x0 0x400>, 4471 <0x0 0x0af69000 0x0 0x400>, 4472 <0x0 0x0af6a000 0x0 0x600>, 4473 <0x0 0x0af6b000 0x0 0x600>; 4474 4475 interrupts-extended = <&mdss 14>; 4476 4477 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4478 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 4479 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, 4480 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4481 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 4482 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 4483 clock-names = "core_iface", 4484 "core_aux", 4485 "ctrl_link", 4486 "ctrl_link_iface", 4487 "stream_pixel", 4488 "stream_1_pixel"; 4489 4490 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4491 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 4492 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 4493 assigned-clock-parents = <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4494 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4495 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4496 4497 operating-points-v2 = <&mdss_dp0_opp_table>; 4498 4499 power-domains = <&rpmhpd RPMHPD_MMCX>; 4500 4501 phys = <&usb_2_qmpphy QMP_USB43DP_DP_PHY>; 4502 phy-names = "dp"; 4503 4504 #sound-dai-cells = <0>; 4505 4506 status = "disabled"; 4507 4508 ports { 4509 #address-cells = <1>; 4510 #size-cells = <0>; 4511 4512 port@0 { 4513 reg = <0>; 4514 mdss_dp2_in: endpoint { 4515 remote-endpoint = <&mdss_intf6_out>; 4516 }; 4517 }; 4518 4519 port@1 { 4520 reg = <1>; 4521 4522 mdss_dp2_out: endpoint { 4523 remote-endpoint = <&usb_2_qmpphy_dp_in>; 4524 }; 4525 }; 4526 }; 4527 }; 4528 4529 mdss_dp3: displayport-controller@af6c000 { 4530 compatible = "qcom,glymur-dp"; 4531 reg = <0x0 0x0af6c000 0x0 0x200>, 4532 <0x0 0x0af6c200 0x0 0x200>, 4533 <0x0 0x0af6d000 0x0 0xc00>, 4534 <0x0 0x0af6e000 0x0 0x400>, 4535 <0x0 0x0af6f000 0x0 0x400>, 4536 <0x0 0x0af70000 0x0 0x400>, 4537 <0x0 0x0af71000 0x0 0x400>, 4538 <0x0 0x0af72000 0x0 0x600>, 4539 <0x0 0x0af73000 0x0 0x600>; 4540 4541 interrupts-extended = <&mdss 15>; 4542 4543 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4544 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 4545 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, 4546 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4547 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4548 clock-names = "core_iface", 4549 "core_aux", 4550 "ctrl_link", 4551 "ctrl_link_iface", 4552 "stream_pixel"; 4553 4554 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4555 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4556 assigned-clock-parents = <&mdss_dp3_phy 0>, 4557 <&mdss_dp3_phy 1>; 4558 4559 operating-points-v2 = <&mdss_dp0_opp_table>; 4560 4561 power-domains = <&rpmhpd RPMHPD_MMCX>; 4562 4563 phys = <&mdss_dp3_phy>; 4564 phy-names = "dp"; 4565 4566 #sound-dai-cells = <0>; 4567 4568 status = "disabled"; 4569 4570 ports { 4571 #address-cells = <1>; 4572 #size-cells = <0>; 4573 4574 port@0 { 4575 reg = <0>; 4576 4577 mdss_dp3_in: endpoint { 4578 remote-endpoint = <&mdss_intf5_out>; 4579 }; 4580 }; 4581 4582 port@1 { 4583 reg = <1>; 4584 4585 mdss_dp3_out: endpoint { 4586 }; 4587 }; 4588 }; 4589 }; 4590 }; 4591 4592 dispcc: clock-controller@af00000 { 4593 compatible = "qcom,glymur-dispcc"; 4594 reg = <0x0 0x0af00000 0x0 0x20000>; 4595 clocks = <&rpmhcc RPMH_CXO_CLK>, 4596 <&sleep_clk>, 4597 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ 4598 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4599 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ 4600 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4601 <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ 4602 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4603 <&mdss_dp3_phy 0>, /* dp3 */ 4604 <&mdss_dp3_phy 1>, 4605 <0>, /* dsi0 */ 4606 <0>, 4607 <0>, /* dsi1 */ 4608 <0>, 4609 <0>, 4610 <0>, 4611 <0>, 4612 <0>; 4613 power-domains = <&rpmhpd RPMHPD_MMCX>; 4614 required-opps = <&rpmhpd_opp_low_svs>; 4615 #clock-cells = <1>; 4616 #reset-cells = <1>; 4617 #power-domain-cells = <1>; 4618 }; 4619 4620 pdc: interrupt-controller@b220000 { 4621 compatible = "qcom,glymur-pdc", "qcom,pdc"; 4622 reg = <0x0 0x0b220000 0x0 0x10000>; 4623 qcom,pdc-ranges = <0 745 51>, 4624 <51 527 47>, 4625 <98 609 32>, 4626 <130 717 12>, 4627 <142 251 5>, 4628 <147 796 16>, 4629 <171 4104 36>; 4630 #interrupt-cells = <2>; 4631 interrupt-parent = <&intc>; 4632 interrupt-controller; 4633 }; 4634 4635 tsens0: thermal-sensor@c22c000 { 4636 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4637 reg = <0x0 0x0c22c000 0x0 0x1000>, 4638 <0x0 0x0c222000 0x0 0x1000>; 4639 4640 interrupts = <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 4641 <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 4642 interrupt-names = "uplow", 4643 "critical"; 4644 4645 #qcom,sensors = <13>; 4646 4647 #thermal-sensor-cells = <1>; 4648 }; 4649 4650 tsens1: thermal-sensor@c22d000 { 4651 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4652 reg = <0x0 0x0c22d000 0x0 0x1000>, 4653 <0x0 0x0c223000 0x0 0x1000>; 4654 4655 interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 4656 <GIC_SPI 862 IRQ_TYPE_LEVEL_HIGH>; 4657 interrupt-names = "uplow", 4658 "critical"; 4659 4660 #qcom,sensors = <9>; 4661 4662 #thermal-sensor-cells = <1>; 4663 }; 4664 4665 tsens2: thermal-sensor@c22e000 { 4666 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4667 reg = <0x0 0x0c22e000 0x0 0x1000>, 4668 <0x0 0x0c224000 0x0 0x1000>; 4669 4670 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 4671 <GIC_SPI 863 IRQ_TYPE_LEVEL_HIGH>; 4672 interrupt-names = "uplow", 4673 "critical"; 4674 4675 #qcom,sensors = <13>; 4676 4677 #thermal-sensor-cells = <1>; 4678 }; 4679 4680 tsens3: thermal-sensor@c22f000 { 4681 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4682 reg = <0x0 0x0c22f000 0x0 0x1000>, 4683 <0x0 0x0c225000 0x0 0x1000>; 4684 4685 interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 4686 <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>; 4687 interrupt-names = "uplow", 4688 "critical"; 4689 4690 #qcom,sensors = <8>; 4691 4692 #thermal-sensor-cells = <1>; 4693 }; 4694 4695 tsens4: thermal-sensor@c230000 { 4696 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4697 reg = <0x0 0x0c230000 0x0 0x1000>, 4698 <0x0 0x0c226000 0x0 0x1000>; 4699 4700 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 4701 <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 4702 interrupt-names = "uplow", 4703 "critical"; 4704 4705 #qcom,sensors = <13>; 4706 4707 #thermal-sensor-cells = <1>; 4708 }; 4709 4710 tsens5: thermal-sensor@c231000 { 4711 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4712 reg = <0x0 0x0c231000 0x0 0x1000>, 4713 <0x0 0x0c227000 0x0 0x1000>; 4714 4715 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>, 4716 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>; 4717 interrupt-names = "uplow", 4718 "critical"; 4719 4720 #qcom,sensors = <8>; 4721 4722 #thermal-sensor-cells = <1>; 4723 }; 4724 4725 tsens6: thermal-sensor@c232000 { 4726 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4727 reg = <0x0 0x0c232000 0x0 0x1000>, 4728 <0x0 0x0c228000 0x0 0x1000>; 4729 4730 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>, 4731 <GIC_SPI 815 IRQ_TYPE_LEVEL_HIGH>; 4732 interrupt-names = "uplow", 4733 "critical"; 4734 4735 #qcom,sensors = <13>; 4736 4737 #thermal-sensor-cells = <1>; 4738 }; 4739 4740 tsens7: thermal-sensor@c233000 { 4741 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4742 reg = <0x0 0x0c233000 0x0 0x1000>, 4743 <0x0 0x0c229000 0x0 0x1000>; 4744 4745 interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>, 4746 <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 4747 interrupt-names = "uplow", 4748 "critical"; 4749 4750 #qcom,sensors = <15>; 4751 4752 #thermal-sensor-cells = <1>; 4753 }; 4754 4755 aoss_qmp: power-management@c300000 { 4756 compatible = "qcom,glymur-aoss-qmp", "qcom,aoss-qmp"; 4757 reg = <0x0 0x0c300000 0x0 0x400>; 4758 interrupt-parent = <&ipcc>; 4759 interrupts-extended = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 4760 IRQ_TYPE_EDGE_RISING>; 4761 mboxes = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4762 4763 #clock-cells = <0>; 4764 }; 4765 4766 sram@c30f000 { 4767 compatible = "qcom,rpmh-stats"; 4768 reg = <0x0 0x0c30f000 0x0 0x400>; 4769 }; 4770 4771 arbiter@c400000 { 4772 compatible = "qcom,glymur-spmi-pmic-arb"; 4773 reg = <0x0 0x0c400000 0x0 0x3000>, 4774 <0x0 0x0c900000 0x0 0x400000>, 4775 <0x0 0x0c4c0000 0x0 0x400000>, 4776 <0x0 0x0c403000 0x0 0x8000>; 4777 reg-names = "core", 4778 "chnls", 4779 "obsrvr", 4780 "chnl_map"; 4781 #address-cells = <2>; 4782 #size-cells = <2>; 4783 ranges; 4784 qcom,channel = <0>; 4785 qcom,ee = <0>; 4786 4787 spmi_bus0: spmi@c426000 { 4788 reg = <0x0 0x0c426000 0x0 0x4000>, 4789 <0x0 0x0c8c0000 0x0 0x10000>, 4790 <0x0 0x0c42a000 0x0 0x8000>; 4791 reg-names = "cnfg", 4792 "intr", 4793 "chnl_owner"; 4794 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4795 interrupt-names = "periph_irq"; 4796 interrupt-controller; 4797 #interrupt-cells = <4>; 4798 #address-cells = <2>; 4799 #size-cells = <0>; 4800 }; 4801 4802 spmi_bus1: spmi@c437000 { 4803 reg = <0x0 0x0c437000 0x0 0x4000>, 4804 <0x0 0x0c8d0000 0x0 0x10000>, 4805 <0x0 0x0c43b000 0x0 0x8000>; 4806 reg-names = "cnfg", 4807 "intr", 4808 "chnl_owner"; 4809 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 4810 interrupt-names = "periph_irq"; 4811 interrupt-controller; 4812 #interrupt-cells = <4>; 4813 #address-cells = <2>; 4814 #size-cells = <0>; 4815 }; 4816 4817 spmi_bus2: spmi@c48000 { 4818 reg = <0x0 0x0c448000 0x0 0x4000>, 4819 <0x0 0x0c8e0000 0x0 0x10000>, 4820 <0x0 0x0c44c000 0x0 0x8000>; 4821 reg-names = "cnfg", 4822 "intr", 4823 "chnl_owner"; 4824 interrupts-extended = <&pdc 72 IRQ_TYPE_LEVEL_HIGH>; 4825 interrupt-names = "periph_irq"; 4826 interrupt-controller; 4827 #interrupt-cells = <4>; 4828 #address-cells = <2>; 4829 #size-cells = <0>; 4830 }; 4831 }; 4832 4833 tlmm: pinctrl@f100000 { 4834 compatible = "qcom,glymur-tlmm"; 4835 reg = <0x0 0x0f100000 0x0 0xf00000>; 4836 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4837 gpio-controller; 4838 #gpio-cells = <2>; 4839 interrupt-controller; 4840 #interrupt-cells = <2>; 4841 gpio-ranges = <&tlmm 0 0 249>; 4842 wakeup-parent = <&pdc>; 4843 4844 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4845 /* SDA, SCL */ 4846 pins = "gpio0", "gpio1"; 4847 function = "qup0_se0"; 4848 drive-strength = <2>; 4849 bias-pull-up = <2200>; 4850 }; 4851 4852 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4853 /* SDA, SCL */ 4854 pins = "gpio4", "gpio5"; 4855 function = "qup0_se1"; 4856 drive-strength = <2>; 4857 bias-pull-up = <2200>; 4858 }; 4859 4860 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4861 /* SDA, SCL */ 4862 pins = "gpio8", "gpio9"; 4863 function = "qup0_se2"; 4864 drive-strength = <2>; 4865 bias-pull-up = <2200>; 4866 }; 4867 4868 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4869 /* SDA, SCL */ 4870 pins = "gpio12", "gpio13"; 4871 function = "qup0_se3"; 4872 drive-strength = <2>; 4873 bias-pull-up = <2200>; 4874 }; 4875 4876 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4877 /* SDA, SCL */ 4878 pins = "gpio16", "gpio17"; 4879 function = "qup0_se4"; 4880 drive-strength = <2>; 4881 bias-pull-up = <2200>; 4882 }; 4883 4884 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4885 /* SDA, SCL */ 4886 pins = "gpio20", "gpio21"; 4887 function = "qup0_se5"; 4888 drive-strength = <2>; 4889 bias-pull-up = <2200>; 4890 }; 4891 4892 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4893 /* SDA, SCL */ 4894 pins = "gpio6", "gpio7"; 4895 function = "qup0_se6"; 4896 drive-strength = <2>; 4897 bias-pull-up = <2200>; 4898 }; 4899 4900 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4901 /* SDA, SCL */ 4902 pins = "gpio14", "gpio15"; 4903 function = "qup0_se7"; 4904 drive-strength = <2>; 4905 bias-pull-up = <2200>; 4906 }; 4907 4908 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4909 /* SDA, SCL */ 4910 pins = "gpio32", "gpio33"; 4911 function = "qup1_se0"; 4912 drive-strength = <2>; 4913 bias-pull-up = <2200>; 4914 }; 4915 4916 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4917 /* SDA, SCL */ 4918 pins = "gpio36", "gpio37"; 4919 function = "qup1_se1"; 4920 drive-strength = <2>; 4921 bias-pull-up = <2200>; 4922 }; 4923 4924 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4925 /* SDA, SCL */ 4926 pins = "gpio40", "gpio41"; 4927 function = "qup1_se2"; 4928 drive-strength = <2>; 4929 bias-pull-up = <2200>; 4930 }; 4931 4932 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4933 /* SDA, SCL */ 4934 pins = "gpio44", "gpio45"; 4935 function = "qup1_se3"; 4936 drive-strength = <2>; 4937 bias-pull-up = <2200>; 4938 }; 4939 4940 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4941 /* SDA, SCL */ 4942 pins = "gpio48", "gpio49"; 4943 function = "qup1_se4"; 4944 drive-strength = <2>; 4945 bias-pull-up = <2200>; 4946 }; 4947 4948 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4949 /* SDA, SCL */ 4950 pins = "gpio52", "gpio53"; 4951 function = "qup1_se5"; 4952 drive-strength = <2>; 4953 bias-pull-up = <2200>; 4954 }; 4955 4956 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4957 /* SDA, SCL */ 4958 pins = "gpio56", "gpio57"; 4959 function = "qup1_se6"; 4960 drive-strength = <2>; 4961 bias-pull-up = <2200>; 4962 }; 4963 4964 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4965 /* SDA, SCL */ 4966 pins = "gpio54", "gpio55"; 4967 function = "qup1_se7"; 4968 drive-strength = <2>; 4969 bias-pull-up = <2200>; 4970 }; 4971 4972 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 4973 /* SDA, SCL */ 4974 pins = "gpio64", "gpio65"; 4975 function = "qup2_se0"; 4976 drive-strength = <2>; 4977 bias-pull-up = <2200>; 4978 }; 4979 4980 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 4981 /* SDA, SCL */ 4982 pins = "gpio68", "gpio69"; 4983 function = "qup2_se1"; 4984 drive-strength = <2>; 4985 bias-pull-up = <2200>; 4986 }; 4987 4988 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 4989 /* SDA, SCL */ 4990 pins = "gpio72", "gpio73"; 4991 function = "qup2_se2"; 4992 drive-strength = <2>; 4993 bias-pull-up = <2200>; 4994 }; 4995 4996 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 4997 /* SDA, SCL */ 4998 pins = "gpio76", "gpio77"; 4999 function = "qup2_se3"; 5000 drive-strength = <2>; 5001 bias-pull-up = <2200>; 5002 }; 5003 5004 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 5005 /* SDA, SCL */ 5006 pins = "gpio80", "gpio81"; 5007 function = "qup2_se4"; 5008 drive-strength = <2>; 5009 bias-pull-up = <2200>; 5010 }; 5011 5012 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 5013 /* SDA, SCL */ 5014 pins = "gpio84", "gpio85"; 5015 function = "qup2_se5"; 5016 drive-strength = <2>; 5017 bias-pull-up = <2200>; 5018 }; 5019 5020 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 5021 /* SDA, SCL */ 5022 pins = "gpio88", "gpio89"; 5023 function = "qup2_se6"; 5024 drive-strength = <2>; 5025 bias-pull-up = <2200>; 5026 }; 5027 5028 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 5029 /* SDA, SCL */ 5030 pins = "gpio80", "gpio81"; 5031 function = "qup2_se7"; 5032 drive-strength = <2>; 5033 bias-pull-up = <2200>; 5034 }; 5035 5036 qup_spi0_cs: qup-spi0-cs-state { 5037 pins = "gpio3"; 5038 function = "qup0_se0"; 5039 drive-strength = <6>; 5040 bias-disable; 5041 }; 5042 5043 qup_spi0_data_clk: qup-spi0-data-clk-state { 5044 /* MISO, MOSI, CLK */ 5045 pins = "gpio0", "gpio1", "gpio2"; 5046 function = "qup0_se0"; 5047 drive-strength = <6>; 5048 bias-disable; 5049 }; 5050 5051 qup_spi1_cs: qup-spi1-cs-state { 5052 pins = "gpio7"; 5053 function = "qup0_se1"; 5054 drive-strength = <6>; 5055 bias-disable; 5056 }; 5057 5058 qup_spi1_data_clk: qup-spi1-data-clk-state { 5059 /* MISO, MOSI, CLK */ 5060 pins = "gpio4", "gpio5", "gpio6"; 5061 function = "qup0_se1"; 5062 drive-strength = <6>; 5063 bias-disable; 5064 }; 5065 5066 qup_spi2_cs: qup-spi2-cs-state { 5067 pins = "gpio11"; 5068 function = "qup0_se2"; 5069 drive-strength = <6>; 5070 bias-disable; 5071 }; 5072 5073 qup_spi2_data_clk: qup-spi2-data-clk-state { 5074 /* MISO, MOSI, CLK */ 5075 pins = "gpio8", "gpio9", "gpio10"; 5076 function = "qup0_se2"; 5077 drive-strength = <6>; 5078 bias-disable; 5079 }; 5080 5081 qup_spi3_cs: qup-spi3-cs-state { 5082 pins = "gpio15"; 5083 function = "qup0_se3"; 5084 drive-strength = <6>; 5085 bias-disable; 5086 }; 5087 5088 qup_spi3_data_clk: qup-spi3-data-clk-state { 5089 /* MISO, MOSI, CLK */ 5090 pins = "gpio12", "gpio13", "gpio14"; 5091 function = "qup0_se3"; 5092 drive-strength = <6>; 5093 bias-disable; 5094 }; 5095 5096 qup_spi4_cs: qup-spi4-cs-state { 5097 pins = "gpio19"; 5098 function = "qup0_se4"; 5099 drive-strength = <6>; 5100 bias-disable; 5101 }; 5102 5103 qup_spi4_data_clk: qup-spi4-data-clk-state { 5104 /* MISO, MOSI, CLK */ 5105 pins = "gpio16", "gpio17", "gpio18"; 5106 function = "qup0_se4"; 5107 drive-strength = <6>; 5108 bias-disable; 5109 }; 5110 5111 qup_spi5_cs: qup-spi5-cs-state { 5112 pins = "gpio23"; 5113 function = "qup0_se5"; 5114 drive-strength = <6>; 5115 bias-disable; 5116 }; 5117 5118 qup_spi5_data_clk: qup-spi5-data-clk-state { 5119 /* MISO, MOSI, CLK */ 5120 pins = "gpio20", "gpio21", "gpio22"; 5121 function = "qup0_se5"; 5122 drive-strength = <6>; 5123 bias-disable; 5124 }; 5125 5126 qup_spi6_cs: qup-spi6-cs-state { 5127 pins = "gpio5"; 5128 function = "qup0_se6"; 5129 drive-strength = <6>; 5130 bias-disable; 5131 }; 5132 5133 qup_spi6_data_clk: qup-spi6-data-clk-state { 5134 /* MISO, MOSI, CLK */ 5135 pins = "gpio6", "gpio7", "gpio4"; 5136 function = "qup0_se6"; 5137 drive-strength = <6>; 5138 bias-disable; 5139 }; 5140 5141 qup_spi7_cs: qup-spi7-cs-state { 5142 pins = "gpio13"; 5143 function = "qup0_se7"; 5144 drive-strength = <6>; 5145 bias-disable; 5146 }; 5147 5148 qup_spi7_data_clk: qup-spi7-data-clk-state { 5149 /* MISO, MOSI, CLK */ 5150 pins = "gpio14", "gpio15", "gpio12"; 5151 function = "qup0_se7"; 5152 drive-strength = <6>; 5153 bias-disable; 5154 }; 5155 5156 qup_spi8_cs: qup-spi8-cs-state { 5157 pins = "gpio35"; 5158 function = "qup1_se0"; 5159 drive-strength = <6>; 5160 bias-disable; 5161 }; 5162 5163 qup_spi8_data_clk: qup-spi8-data-clk-state { 5164 /* MISO, MOSI, CLK */ 5165 pins = "gpio32", "gpio33", "gpio34"; 5166 function = "qup1_se0"; 5167 drive-strength = <6>; 5168 bias-disable; 5169 }; 5170 5171 qup_spi9_cs: qup-spi9-cs-state { 5172 pins = "gpio39"; 5173 function = "qup1_se1"; 5174 drive-strength = <6>; 5175 bias-disable; 5176 }; 5177 5178 qup_spi9_data_clk: qup-spi9-data-clk-state { 5179 /* MISO, MOSI, CLK */ 5180 pins = "gpio36", "gpio37", "gpio38"; 5181 function = "qup1_se1"; 5182 drive-strength = <6>; 5183 bias-disable; 5184 }; 5185 5186 qup_spi10_cs: qup-spi10-cs-state { 5187 pins = "gpio43"; 5188 function = "qup1_se2"; 5189 drive-strength = <6>; 5190 bias-disable; 5191 }; 5192 5193 qup_spi10_data_clk: qup-spi10-data-clk-state { 5194 /* MISO, MOSI, CLK */ 5195 pins = "gpio40", "gpio41", "gpio42"; 5196 function = "qup1_se2"; 5197 drive-strength = <6>; 5198 bias-disable; 5199 }; 5200 5201 qup_spi11_cs: qup-spi11-cs-state { 5202 pins = "gpio47"; 5203 function = "qup1_se3"; 5204 drive-strength = <6>; 5205 bias-disable; 5206 }; 5207 5208 qup_spi11_data_clk: qup-spi11-data-clk-state { 5209 pins = "gpio44", "gpio45", "gpio46"; 5210 function = "qup1_se3"; 5211 drive-strength = <6>; 5212 bias-disable; 5213 }; 5214 5215 qup_spi12_cs: qup-spi12-cs-state { 5216 pins = "gpio51"; 5217 function = "qup1_se4"; 5218 drive-strength = <6>; 5219 bias-disable; 5220 }; 5221 5222 qup_spi12_data_clk: qup-spi12-data-clk-state { 5223 /* MISO, MOSI, CLK */ 5224 pins = "gpio48", "gpio49", "gpio50"; 5225 function = "qup1_se4"; 5226 drive-strength = <6>; 5227 bias-disable; 5228 }; 5229 5230 qup_spi13_cs: qup-spi13-cs-state { 5231 pins = "gpio55"; 5232 function = "qup1_se5"; 5233 drive-strength = <6>; 5234 bias-disable; 5235 }; 5236 5237 qup_spi13_data_clk: qup-spi13-data-clk-state { 5238 /* MISO, MOSI, CLK */ 5239 pins = "gpio52", "gpio53", "gpio54"; 5240 function = "qup1_se5"; 5241 drive-strength = <6>; 5242 bias-disable; 5243 }; 5244 5245 qup_spi14_cs: qup-spi14-cs-state { 5246 pins = "gpio59"; 5247 function = "qup1_se6"; 5248 drive-strength = <6>; 5249 bias-disable; 5250 }; 5251 5252 qup_spi14_data_clk: qup-spi14-data-clk-state { 5253 /* MISO, MOSI, CLK */ 5254 pins = "gpio56", "gpio57", "gpio58"; 5255 function = "qup1_se6"; 5256 drive-strength = <6>; 5257 bias-disable; 5258 }; 5259 5260 qup_spi15_cs: qup-spi15-cs-state { 5261 pins = "gpio53"; 5262 function = "qup1_se7"; 5263 drive-strength = <6>; 5264 bias-disable; 5265 }; 5266 5267 qup_spi15_data_clk: qup-spi15-data-clk-state { 5268 /* MISO, MOSI, CLK */ 5269 pins = "gpio54", "gpio55", "gpio52"; 5270 function = "qup1_se7"; 5271 drive-strength = <6>; 5272 bias-disable; 5273 }; 5274 5275 qup_spi16_cs: qup-spi16-cs-state { 5276 pins = "gpio67"; 5277 function = "qup2_se0"; 5278 drive-strength = <6>; 5279 bias-disable; 5280 }; 5281 5282 qup_spi16_data_clk: qup-spi16-data-clk-state { 5283 /* MISO, MOSI, CLK */ 5284 pins = "gpio64", "gpio65", "gpio66"; 5285 function = "qup2_se0"; 5286 drive-strength = <6>; 5287 bias-disable; 5288 }; 5289 5290 qup_spi17_cs: qup-spi17-cs-state { 5291 pins = "gpio71"; 5292 function = "qup2_se1"; 5293 drive-strength = <6>; 5294 bias-disable; 5295 }; 5296 5297 qup_spi17_data_clk: qup-spi17-data-clk-state { 5298 /* MISO, MOSI, CLK */ 5299 pins = "gpio68", "gpio69", "gpio70"; 5300 function = "qup2_se1"; 5301 drive-strength = <6>; 5302 bias-disable; 5303 }; 5304 5305 qup_spi18_cs: qup-spi18-cs-state { 5306 pins = "gpio75"; 5307 function = "qup2_se2"; 5308 drive-strength = <6>; 5309 bias-disable; 5310 }; 5311 5312 qup_spi18_data_clk: qup-spi18-data-clk-state { 5313 /* MISO, MOSI, CLK */ 5314 pins = "gpio72", "gpio73", "gpio74"; 5315 function = "qup2_se2"; 5316 drive-strength = <6>; 5317 bias-disable; 5318 }; 5319 5320 qup_spi19_cs: qup-spi19-cs-state { 5321 pins = "gpio79"; 5322 function = "qup2_se3"; 5323 drive-strength = <6>; 5324 bias-disable; 5325 }; 5326 5327 qup_spi19_data_clk: qup-spi19-data-clk-state { 5328 /* MISO, MOSI, CLK */ 5329 pins = "gpio76", "gpio77", "gpio78"; 5330 function = "qup2_se3"; 5331 drive-strength = <6>; 5332 bias-disable; 5333 }; 5334 5335 qup_spi20_cs: qup-spi20-cs-state { 5336 pins = "gpio83"; 5337 function = "qup2_se4"; 5338 drive-strength = <6>; 5339 bias-disable; 5340 }; 5341 5342 qup_spi20_data_clk: qup-spi20-data-clk-state { 5343 /* MISO, MOSI, CLK */ 5344 pins = "gpio80", "gpio81", "gpio82"; 5345 function = "qup2_se4"; 5346 drive-strength = <6>; 5347 bias-disable; 5348 }; 5349 5350 qup_spi21_cs: qup-spi21-cs-state { 5351 pins = "gpio87"; 5352 function = "qup2_se5"; 5353 drive-strength = <6>; 5354 bias-disable; 5355 }; 5356 5357 qup_spi21_data_clk: qup-spi21-data-clk-state { 5358 /* MISO, MOSI, CLK */ 5359 pins = "gpio84", "gpio85", "gpio86"; 5360 function = "qup2_se5"; 5361 drive-strength = <6>; 5362 bias-disable; 5363 }; 5364 5365 qup_spi22_cs: qup-spi22-cs-state { 5366 pins = "gpio91"; 5367 function = "qup2_se6"; 5368 drive-strength = <6>; 5369 bias-disable; 5370 }; 5371 5372 qup_spi22_data_clk: qup-spi22-data-clk-state { 5373 /* MISO, MOSI, CLK */ 5374 pins = "gpio88", "gpio89", "gpio90"; 5375 function = "qup2_se6"; 5376 drive-strength = <6>; 5377 bias-disable; 5378 }; 5379 5380 qup_spi23_cs: qup-spi23-cs-state { 5381 pins = "gpio83"; 5382 function = "qup2_se7"; 5383 drive-strength = <6>; 5384 bias-disable; 5385 }; 5386 5387 qup_spi23_data_clk: qup-spi23-data-clk-state { 5388 /* MISO, MOSI, CLK */ 5389 pins = "gpio80", "gpio81", "gpio82"; 5390 function = "qup2_se7"; 5391 drive-strength = <6>; 5392 bias-disable; 5393 }; 5394 5395 qup_uart2_default: qup-uart2-default-state { 5396 tx-pins { 5397 pins = "gpio10"; 5398 function = "qup0_se2"; 5399 drive-strength = <2>; 5400 bias-disable; 5401 }; 5402 5403 rx-pins { 5404 pins = "gpio11"; 5405 function = "qup0_se2"; 5406 drive-strength = <2>; 5407 bias-disable; 5408 }; 5409 }; 5410 5411 qup_uart14_default: qup-uart14-default-state { 5412 cts-pins { 5413 pins = "gpio56"; 5414 function = "qup1_se6"; 5415 drive-strength = <2>; 5416 bias-disable; 5417 }; 5418 5419 rts-pins { 5420 pins = "gpio57"; 5421 function = "qup1_se6"; 5422 drive-strength = <2>; 5423 bias-disable; 5424 }; 5425 5426 tx-pins { 5427 pins = "gpio58"; 5428 function = "qup1_se6"; 5429 drive-strength = <2>; 5430 bias-disable; 5431 }; 5432 5433 rx-pins { 5434 pins = "gpio59"; 5435 function = "qup1_se6"; 5436 drive-strength = <2>; 5437 bias-disable; 5438 }; 5439 }; 5440 5441 qup_uart19_default: qup-uart19-default-state { 5442 cts-pins { 5443 pins = "gpio76"; 5444 function = "qup2_se3"; 5445 drive-strength = <2>; 5446 bias-disable; 5447 }; 5448 5449 rts-pins { 5450 pins = "gpio77"; 5451 function = "qup2_se3"; 5452 drive-strength = <2>; 5453 bias-disable; 5454 }; 5455 5456 tx-pins { 5457 pins = "gpio78"; 5458 function = "qup2_se3"; 5459 drive-strength = <2>; 5460 bias-disable; 5461 }; 5462 5463 rx-pins { 5464 pins = "gpio79"; 5465 function = "qup2_se3"; 5466 drive-strength = <2>; 5467 bias-disable; 5468 }; 5469 }; 5470 5471 qup_uart21_default: qup-uart21-default-state { 5472 tx-pins { 5473 pins = "gpio86"; 5474 function = "qup2_se5"; 5475 drive-strength = <2>; 5476 bias-disable; 5477 }; 5478 5479 rx-pins { 5480 pins = "gpio87"; 5481 function = "qup2_se5"; 5482 drive-strength = <2>; 5483 bias-disable; 5484 }; 5485 }; 5486 5487 qup_uart22_default: qup-uart22-default-state { 5488 tx-pins { 5489 pins = "gpio90"; 5490 function = "qup2_se6"; 5491 drive-strength = <2>; 5492 bias-disable; 5493 }; 5494 5495 rx-pins { 5496 pins = "gpio91"; 5497 function = "qup2_se6"; 5498 drive-strength = <2>; 5499 bias-disable; 5500 }; 5501 }; 5502 }; 5503 5504 apps_smmu: iommu@15000000 { 5505 compatible = "qcom,glymur-smmu-500", 5506 "qcom,smmu-500", 5507 "arm,mmu-500"; 5508 reg = <0x0 0x15000000 0x0 0x100000>; 5509 5510 #iommu-cells = <2>; 5511 #global-interrupts = <1>; 5512 5513 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5514 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5515 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5516 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5517 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5518 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5519 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5520 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5521 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5522 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5523 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5524 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5525 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5526 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5527 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5528 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5529 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5530 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5531 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5532 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5533 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5534 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5535 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5536 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5537 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5538 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5539 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5540 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5541 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5542 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5543 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5544 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5545 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5546 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5547 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5548 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5549 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5550 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5551 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5552 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5553 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5554 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5555 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5556 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5557 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5558 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5559 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5560 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5561 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5562 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5563 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5564 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5565 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5566 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5567 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5568 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5569 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5570 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5571 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5572 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5573 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5574 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5575 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5576 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5577 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5578 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5579 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5580 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5581 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5582 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5583 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5584 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5585 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5586 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5587 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5588 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5589 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5590 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5591 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5592 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5593 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5594 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5595 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5596 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5597 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5598 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5599 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5600 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5601 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5602 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5603 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5604 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5605 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5606 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5607 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5608 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5609 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 5610 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 5611 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 5612 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 5613 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 5614 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 5615 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, 5616 <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>, 5617 <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, 5618 <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>, 5619 <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 5620 <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 5621 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 5622 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 5623 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 5624 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 5625 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>; 5626 5627 dma-coherent; 5628 }; 5629 5630 pcie_smmu: iommu@15480000 { 5631 compatible = "arm,smmu-v3"; 5632 reg = <0x0 0x15480000 0x0 0x20000>; 5633 interrupts = <GIC_SPI 964 IRQ_TYPE_LEVEL_HIGH>, 5634 <GIC_SPI 962 IRQ_TYPE_LEVEL_HIGH>, 5635 <GIC_SPI 960 IRQ_TYPE_LEVEL_HIGH>; 5636 interrupt-names = "eventq", "cmdq-sync", "gerror"; 5637 dma-coherent; 5638 #iommu-cells = <1>; 5639 }; 5640 5641 intc: interrupt-controller@17000000 { 5642 compatible = "arm,gic-v3"; 5643 reg = <0x0 0x17000000 0x0 0x10000>, 5644 <0x0 0x17080000 0x0 0x480000>; 5645 5646 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5647 5648 #interrupt-cells = <3>; 5649 interrupt-controller; 5650 5651 #address-cells = <2>; 5652 #size-cells = <2>; 5653 ranges; 5654 5655 gic_its: msi-controller@17040000 { 5656 compatible = "arm,gic-v3-its"; 5657 reg = <0x0 0x17040000 0x0 0x40000>; 5658 5659 msi-controller; 5660 #msi-cells = <1>; 5661 }; 5662 }; 5663 5664 watchdog@17600000 { 5665 compatible = "qcom,apss-wdt-glymur", "qcom,kpss-wdt"; 5666 reg = <0x0 0x17600000 0x0 0x1000>; 5667 clocks = <&sleep_clk>; 5668 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5669 }; 5670 5671 pdp0_mbox: mailbox@17610000 { 5672 compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; 5673 reg = <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; 5674 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 5675 #mbox-cells = <1>; 5676 }; 5677 5678 timer@17810000 { 5679 compatible = "arm,armv7-timer-mem"; 5680 reg = <0x0 0x17810000 0x0 0x1000>; 5681 #address-cells = <2>; 5682 #size-cells = <1>; 5683 ranges = <0x0 0x0 0x0 0x0 0x20000000>; 5684 5685 frame@17811000 { 5686 reg = <0x0 0x17811000 0x1000>, 5687 <0x0 0x17812000 0x1000>; 5688 5689 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5690 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5691 5692 frame-number = <0>; 5693 }; 5694 5695 frame@17813000 { 5696 reg = <0x0 0x17813000 0x1000>; 5697 5698 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5699 5700 frame-number = <1>; 5701 5702 status = "disabled"; 5703 }; 5704 5705 frame@17815000 { 5706 reg = <0x0 0x17815000 0x1000>; 5707 5708 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5709 5710 frame-number = <2>; 5711 5712 status = "disabled"; 5713 }; 5714 5715 frame@17817000 { 5716 reg = <0x0 0x17817000 0x1000>; 5717 5718 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5719 5720 frame-number = <3>; 5721 5722 status = "disabled"; 5723 }; 5724 5725 frame@17819000 { 5726 reg = <0x0 0x17819000 0x1000>; 5727 5728 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5729 5730 frame-number = <4>; 5731 5732 status = "disabled"; 5733 }; 5734 5735 frame@1781b000 { 5736 reg = <0x0 0x1781b000 0x1000>; 5737 5738 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5739 5740 frame-number = <5>; 5741 5742 status = "disabled"; 5743 }; 5744 5745 frame@1781d000 { 5746 reg = <0x0 0x1781d000 0x1000>; 5747 5748 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5749 5750 frame-number = <6>; 5751 5752 status = "disabled"; 5753 }; 5754 }; 5755 5756 apps_rsc: rsc@18900000 { 5757 compatible = "qcom,rpmh-rsc"; 5758 label = "apps_rsc"; 5759 reg = <0x0 0x18900000 0x0 0x10000>, 5760 <0x0 0x18910000 0x0 0x10000>, 5761 <0x0 0x18920000 0x0 0x10000>; 5762 reg-names = "drv-0", 5763 "drv-1", 5764 "drv-2"; 5765 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5766 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5767 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5768 qcom,tcs-offset = <0xd00>; 5769 qcom,drv-id = <2>; 5770 qcom,tcs-config = <ACTIVE_TCS 2>, 5771 <SLEEP_TCS 3>, 5772 <WAKE_TCS 3>, 5773 <CONTROL_TCS 0>; 5774 power-domains = <&system_pd>; 5775 5776 apps_bcm_voter: bcm-voter { 5777 compatible = "qcom,bcm-voter"; 5778 }; 5779 5780 rpmhcc: clock-controller { 5781 compatible = "qcom,glymur-rpmh-clk"; 5782 5783 clocks = <&xo_board>; 5784 clock-names = "xo"; 5785 5786 #clock-cells = <1>; 5787 }; 5788 5789 rpmhpd: power-controller { 5790 compatible = "qcom,glymur-rpmhpd"; 5791 5792 operating-points-v2 = <&rpmhpd_opp_table>; 5793 5794 #power-domain-cells = <1>; 5795 5796 rpmhpd_opp_table: opp-table { 5797 compatible = "operating-points-v2"; 5798 5799 rpmhpd_opp_ret: opp-16 { 5800 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5801 }; 5802 5803 rpmhpd_opp_min_svs: opp-48 { 5804 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5805 }; 5806 5807 rpmhpd_opp_low_svs_d2: opp-52 { 5808 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 5809 }; 5810 5811 rpmhpd_opp_low_svs_d1: opp-56 { 5812 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 5813 }; 5814 5815 rpmhpd_opp_low_svs_d0: opp-60 { 5816 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 5817 }; 5818 5819 rpmhpd_opp_low_svs: opp-64 { 5820 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5821 }; 5822 5823 rpmhpd_opp_low_svs_l1: opp-80 { 5824 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 5825 }; 5826 5827 rpmhpd_opp_svs: opp-128 { 5828 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5829 }; 5830 5831 rpmhpd_opp_svs_l0: opp-144 { 5832 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 5833 }; 5834 5835 rpmhpd_opp_svs_l1: opp-192 { 5836 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5837 }; 5838 5839 rpmhpd_opp_nom: opp-256 { 5840 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5841 }; 5842 5843 rpmhpd_opp_nom_l1: opp-320 { 5844 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5845 }; 5846 5847 rpmhpd_opp_nom_l2: opp-336 { 5848 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5849 }; 5850 5851 rpmhpd_opp_turbo: opp-384 { 5852 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5853 }; 5854 5855 rpmhpd_opp_turbo_l1: opp-416 { 5856 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5857 }; 5858 }; 5859 }; 5860 }; 5861 5862 nsi_noc: interconnect@1d600000 { 5863 compatible = "qcom,glymur-nsinoc"; 5864 reg = <0x0 0x1d600000 0x0 0x14080>; 5865 qcom,bcm-voters = <&apps_bcm_voter>; 5866 #interconnect-cells = <2>; 5867 }; 5868 5869 oobm_ss_noc: interconnect@1f300000 { 5870 compatible = "qcom,glymur-oobm-ss-noc"; 5871 reg = <0x0 0x1f300000 0x0 0x49a00>; 5872 qcom,bcm-voters = <&apps_bcm_voter>; 5873 #interconnect-cells = <2>; 5874 }; 5875 5876 system-cache-controller@20400000 { 5877 compatible = "qcom,glymur-llcc"; 5878 reg = <0x0 0x21800000 0x0 0x100000>, 5879 <0x0 0x21a00000 0x0 0x100000>, 5880 <0x0 0x21c00000 0x0 0x100000>, 5881 <0x0 0x21e00000 0x0 0x100000>, 5882 <0x0 0x22800000 0x0 0x100000>, 5883 <0x0 0x22a00000 0x0 0x100000>, 5884 <0x0 0x22c00000 0x0 0x100000>, 5885 <0x0 0x22e00000 0x0 0x100000>, 5886 <0x0 0x23800000 0x0 0x100000>, 5887 <0x0 0x23a00000 0x0 0x100000>, 5888 <0x0 0x23c00000 0x0 0x100000>, 5889 <0x0 0x23e00000 0x0 0x100000>, 5890 <0x0 0x20400000 0x0 0x100000>, 5891 <0x0 0x20600000 0x0 0x100000>; 5892 reg-names = "llcc0_base", 5893 "llcc1_base", 5894 "llcc2_base", 5895 "llcc3_base", 5896 "llcc4_base", 5897 "llcc5_base", 5898 "llcc6_base", 5899 "llcc7_base", 5900 "llcc8_base", 5901 "llcc9_base", 5902 "llcc10_base", 5903 "llcc11_base", 5904 "llcc_broadcast_base", 5905 "llcc_broadcast_and_base"; 5906 5907 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 5908 }; 5909 5910 nsp_noc: interconnect@320c0000 { 5911 compatible = "qcom,glymur-nsp-noc"; 5912 reg = <0x0 0x320c0000 0x0 0x21280>; 5913 qcom,bcm-voters = <&apps_bcm_voter>; 5914 #interconnect-cells = <2>; 5915 }; 5916 5917 imem: sram@81e08000 { 5918 compatible = "mmio-sram"; 5919 reg = <0x0 0x81e08600 0x0 0x300>; 5920 5921 #address-cells = <1>; 5922 #size-cells = <1>; 5923 ranges = <0x0 0x0 0x81e08600 0x300>; 5924 5925 cpu_scp_lpri0: scp-sram-section@0 { 5926 compatible = "arm,scmi-shmem"; 5927 reg = <0x0 0x180>; 5928 }; 5929 5930 cpu_scp_lpri1: scp-sram-section@180 { 5931 compatible = "arm,scmi-shmem"; 5932 reg = <0x180 0x180>; 5933 }; 5934 }; 5935 }; 5936 5937 timer { 5938 compatible = "arm,armv8-timer"; 5939 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 5940 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 5941 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 5942 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 5943 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 5944 }; 5945 5946 thermal_zones: thermal-zones { 5947 aoss-0-thermal { 5948 thermal-sensors = <&tsens0 0>; 5949 5950 trips { 5951 aoss-0-critical { 5952 temperature = <115000>; 5953 hysteresis = <1000>; 5954 type = "critical"; 5955 }; 5956 }; 5957 }; 5958 5959 cpu-0-0-0-thermal { 5960 thermal-sensors = <&tsens0 1>; 5961 5962 trips { 5963 cpu-0-0-0-critical { 5964 temperature = <115000>; 5965 hysteresis = <1000>; 5966 type = "critical"; 5967 }; 5968 }; 5969 }; 5970 5971 cpu-0-0-1-thermal { 5972 thermal-sensors = <&tsens0 2>; 5973 5974 trips { 5975 cpu-0-0-1-critical { 5976 temperature = <115000>; 5977 hysteresis = <1000>; 5978 type = "critical"; 5979 }; 5980 }; 5981 }; 5982 5983 cpu-0-1-0-thermal { 5984 thermal-sensors = <&tsens0 3>; 5985 5986 trips { 5987 cpu-0-1-0-critical { 5988 temperature = <115000>; 5989 hysteresis = <1000>; 5990 type = "critical"; 5991 }; 5992 }; 5993 }; 5994 5995 cpu-0-1-1-thermal { 5996 thermal-sensors = <&tsens0 4>; 5997 5998 trips { 5999 cpu-0-1-1-critical { 6000 temperature = <115000>; 6001 hysteresis = <1000>; 6002 type = "critical"; 6003 }; 6004 }; 6005 }; 6006 6007 cpu-0-2-0-thermal { 6008 thermal-sensors = <&tsens0 5>; 6009 6010 trips { 6011 cpu-0-2-0-critical { 6012 temperature = <115000>; 6013 hysteresis = <1000>; 6014 type = "critical"; 6015 }; 6016 }; 6017 }; 6018 6019 cpu-0-2-1-thermal { 6020 thermal-sensors = <&tsens0 6>; 6021 6022 trips { 6023 cpu-0-2-1-critical { 6024 temperature = <115000>; 6025 hysteresis = <1000>; 6026 type = "critical"; 6027 }; 6028 }; 6029 }; 6030 6031 cpu-0-3-0-thermal { 6032 thermal-sensors = <&tsens0 7>; 6033 6034 trips { 6035 cpu-0-3-0-critical { 6036 temperature = <115000>; 6037 hysteresis = <1000>; 6038 type = "critical"; 6039 }; 6040 }; 6041 }; 6042 6043 cpu-0-3-1-thermal { 6044 thermal-sensors = <&tsens0 8>; 6045 6046 trips { 6047 cpu-0-3-1-critical { 6048 temperature = <115000>; 6049 hysteresis = <1000>; 6050 type = "critical"; 6051 }; 6052 }; 6053 }; 6054 6055 cpu-0-4-0-thermal { 6056 thermal-sensors = <&tsens0 9>; 6057 6058 trips { 6059 cpu-0-4-0-critical { 6060 temperature = <115000>; 6061 hysteresis = <1000>; 6062 type = "critical"; 6063 }; 6064 }; 6065 }; 6066 6067 cpu-0-4-1-thermal { 6068 thermal-sensors = <&tsens0 10>; 6069 6070 trips { 6071 cpu-0-4-1-critical { 6072 temperature = <115000>; 6073 hysteresis = <1000>; 6074 type = "critical"; 6075 }; 6076 }; 6077 }; 6078 6079 cpu-0-5-0-thermal { 6080 thermal-sensors = <&tsens0 11>; 6081 6082 trips { 6083 cpu-0-5-0-critical { 6084 temperature = <115000>; 6085 hysteresis = <1000>; 6086 type = "critical"; 6087 }; 6088 }; 6089 }; 6090 6091 cpu-0-5-1-thermal { 6092 thermal-sensors = <&tsens0 12>; 6093 6094 trips { 6095 cpu-0-5-1-critical { 6096 temperature = <115000>; 6097 hysteresis = <1000>; 6098 type = "critical"; 6099 }; 6100 }; 6101 }; 6102 6103 aoss-1-thermal { 6104 thermal-sensors = <&tsens1 0>; 6105 6106 trips { 6107 aoss-1-critical { 6108 temperature = <115000>; 6109 hysteresis = <1000>; 6110 type = "critical"; 6111 }; 6112 }; 6113 }; 6114 6115 cpullc-0-0-thermal { 6116 thermal-sensors = <&tsens1 1>; 6117 6118 trips { 6119 cpullc-0-0-critical { 6120 temperature = <115000>; 6121 hysteresis = <1000>; 6122 type = "critical"; 6123 }; 6124 }; 6125 }; 6126 6127 cpullc-0-1-thermal { 6128 thermal-sensors = <&tsens1 2>; 6129 6130 trips { 6131 cpullc-0-1-critical { 6132 temperature = <115000>; 6133 hysteresis = <1000>; 6134 type = "critical"; 6135 }; 6136 }; 6137 }; 6138 6139 qmx-0-0-thermal { 6140 thermal-sensors = <&tsens1 3>; 6141 6142 trips { 6143 qmx-0-0-critical { 6144 temperature = <115000>; 6145 hysteresis = <1000>; 6146 type = "critical"; 6147 }; 6148 }; 6149 }; 6150 6151 qmx-0-1-thermal { 6152 thermal-sensors = <&tsens1 4>; 6153 6154 trips { 6155 qmx-0-1-critical { 6156 temperature = <115000>; 6157 hysteresis = <1000>; 6158 type = "critical"; 6159 }; 6160 }; 6161 }; 6162 6163 qmx-0-2-thermal { 6164 thermal-sensors = <&tsens1 5>; 6165 6166 trips { 6167 qmx-0-2-critical { 6168 temperature = <115000>; 6169 hysteresis = <1000>; 6170 type = "critical"; 6171 }; 6172 }; 6173 }; 6174 6175 ddr-0-thermal { 6176 thermal-sensors = <&tsens1 6>; 6177 6178 trips { 6179 ddr-0-critical { 6180 temperature = <115000>; 6181 hysteresis = <1000>; 6182 type = "critical"; 6183 }; 6184 }; 6185 }; 6186 6187 thermal_video_0: video-0-thermal { 6188 thermal-sensors = <&tsens1 7>; 6189 6190 trips { 6191 video-0-critical { 6192 temperature = <115000>; 6193 hysteresis = <1000>; 6194 type = "critical"; 6195 }; 6196 }; 6197 }; 6198 6199 thermal_video_1: video-1-thermal { 6200 thermal-sensors = <&tsens1 8>; 6201 6202 trips { 6203 video-1-critical { 6204 temperature = <115000>; 6205 hysteresis = <1000>; 6206 type = "critical"; 6207 }; 6208 }; 6209 }; 6210 6211 aoss-2-thermal { 6212 thermal-sensors = <&tsens2 0>; 6213 6214 trips { 6215 aoss-2-critical { 6216 temperature = <115000>; 6217 hysteresis = <1000>; 6218 type = "critical"; 6219 }; 6220 }; 6221 }; 6222 6223 cpu-1-0-0-thermal { 6224 thermal-sensors = <&tsens2 1>; 6225 6226 trips { 6227 cpu-1-0-0-critical { 6228 temperature = <115000>; 6229 hysteresis = <1000>; 6230 type = "critical"; 6231 }; 6232 }; 6233 }; 6234 6235 cpu-1-0-1-thermal { 6236 thermal-sensors = <&tsens2 2>; 6237 6238 trips { 6239 cpu-1-0-1-critical { 6240 temperature = <115000>; 6241 hysteresis = <1000>; 6242 type = "critical"; 6243 }; 6244 }; 6245 }; 6246 6247 cpu-1-1-0-thermal { 6248 thermal-sensors = <&tsens2 3>; 6249 6250 trips { 6251 cpu-1-1-0-critical { 6252 temperature = <115000>; 6253 hysteresis = <1000>; 6254 type = "critical"; 6255 }; 6256 }; 6257 }; 6258 6259 cpu-1-1-1-thermal { 6260 thermal-sensors = <&tsens2 4>; 6261 6262 trips { 6263 cpu-1-1-1-critical { 6264 temperature = <115000>; 6265 hysteresis = <1000>; 6266 type = "critical"; 6267 }; 6268 }; 6269 }; 6270 6271 cpu-1-2-0-thermal { 6272 thermal-sensors = <&tsens2 5>; 6273 6274 trips { 6275 cpu-1-2-0-critical { 6276 temperature = <115000>; 6277 hysteresis = <1000>; 6278 type = "critical"; 6279 }; 6280 }; 6281 }; 6282 6283 cpu-1-2-1-thermal { 6284 thermal-sensors = <&tsens2 6>; 6285 6286 trips { 6287 cpu-1-2-1-critical { 6288 temperature = <115000>; 6289 hysteresis = <1000>; 6290 type = "critical"; 6291 }; 6292 }; 6293 }; 6294 6295 cpu-1-3-0-thermal { 6296 thermal-sensors = <&tsens2 7>; 6297 6298 trips { 6299 cpu-1-3-0-critical { 6300 temperature = <115000>; 6301 hysteresis = <1000>; 6302 type = "critical"; 6303 }; 6304 }; 6305 }; 6306 6307 cpu-1-3-1-thermal { 6308 thermal-sensors = <&tsens2 8>; 6309 6310 trips { 6311 cpu-1-3-1-critical { 6312 temperature = <115000>; 6313 hysteresis = <1000>; 6314 type = "critical"; 6315 }; 6316 }; 6317 }; 6318 6319 cpu-1-4-0-thermal { 6320 thermal-sensors = <&tsens2 9>; 6321 6322 trips { 6323 cpu-1-4-0-critical { 6324 temperature = <115000>; 6325 hysteresis = <1000>; 6326 type = "critical"; 6327 }; 6328 }; 6329 }; 6330 6331 cpu-1-4-1-thermal { 6332 thermal-sensors = <&tsens2 10>; 6333 6334 trips { 6335 cpu-1-4-1-critical { 6336 temperature = <115000>; 6337 hysteresis = <1000>; 6338 type = "critical"; 6339 }; 6340 }; 6341 }; 6342 6343 cpu-1-5-0-thermal { 6344 thermal-sensors = <&tsens2 11>; 6345 6346 trips { 6347 cpu-1-5-0-critical { 6348 temperature = <115000>; 6349 hysteresis = <1000>; 6350 type = "critical"; 6351 }; 6352 }; 6353 }; 6354 6355 cpu-1-5-1-thermal { 6356 thermal-sensors = <&tsens2 12>; 6357 6358 trips { 6359 cpu-1-5-1-critical { 6360 temperature = <115000>; 6361 hysteresis = <1000>; 6362 type = "critical"; 6363 }; 6364 }; 6365 }; 6366 6367 aoss-3-thermal { 6368 thermal-sensors = <&tsens3 0>; 6369 6370 trips { 6371 aoss-3-critical { 6372 temperature = <115000>; 6373 hysteresis = <1000>; 6374 type = "critical"; 6375 }; 6376 }; 6377 }; 6378 6379 cpullc-1-0-thermal { 6380 thermal-sensors = <&tsens3 1>; 6381 6382 trips { 6383 cpullc-1-0-critical { 6384 temperature = <115000>; 6385 hysteresis = <1000>; 6386 type = "critical"; 6387 }; 6388 }; 6389 }; 6390 6391 cpullc-1-1-thermal { 6392 thermal-sensors = <&tsens3 2>; 6393 6394 trips { 6395 cpullc-1-1-critical { 6396 temperature = <115000>; 6397 hysteresis = <1000>; 6398 type = "critical"; 6399 }; 6400 }; 6401 }; 6402 6403 qmx-1-0-thermal { 6404 thermal-sensors = <&tsens3 3>; 6405 6406 trips { 6407 qmx-1-0-critical { 6408 temperature = <115000>; 6409 hysteresis = <1000>; 6410 type = "critical"; 6411 }; 6412 }; 6413 }; 6414 6415 qmx-1-1-thermal { 6416 thermal-sensors = <&tsens3 4>; 6417 6418 trips { 6419 qmx-1-1-critical { 6420 temperature = <115000>; 6421 hysteresis = <1000>; 6422 type = "critical"; 6423 }; 6424 }; 6425 }; 6426 6427 qmx-1-2-thermal { 6428 thermal-sensors = <&tsens3 5>; 6429 6430 trips { 6431 qmx-1-2-critical { 6432 temperature = <115000>; 6433 hysteresis = <1000>; 6434 type = "critical"; 6435 }; 6436 }; 6437 }; 6438 6439 qmx-1-3-thermal { 6440 thermal-sensors = <&tsens3 6>; 6441 6442 trips { 6443 qmx-1-3-critical { 6444 temperature = <115000>; 6445 hysteresis = <1000>; 6446 type = "critical"; 6447 }; 6448 }; 6449 }; 6450 6451 qmx-1-4-thermal { 6452 thermal-sensors = <&tsens3 7>; 6453 6454 trips { 6455 qmx-1-4-critical { 6456 temperature = <115000>; 6457 hysteresis = <1000>; 6458 type = "critical"; 6459 }; 6460 }; 6461 }; 6462 6463 aoss-4-thermal { 6464 thermal-sensors = <&tsens4 0>; 6465 6466 trips { 6467 aoss-4-critical { 6468 temperature = <115000>; 6469 hysteresis = <1000>; 6470 type = "critical"; 6471 }; 6472 }; 6473 }; 6474 6475 thermal_cpu_2_0_0: cpu-2-0-0-thermal { 6476 thermal-sensors = <&tsens4 1>; 6477 6478 trips { 6479 cpu-2-0-0-critical { 6480 temperature = <115000>; 6481 hysteresis = <1000>; 6482 type = "critical"; 6483 }; 6484 }; 6485 }; 6486 6487 thermal_cpu_2_0_1: cpu-2-0-1-thermal { 6488 thermal-sensors = <&tsens4 2>; 6489 6490 trips { 6491 cpu-2-0-1-critical { 6492 temperature = <115000>; 6493 hysteresis = <1000>; 6494 type = "critical"; 6495 }; 6496 }; 6497 }; 6498 6499 thermal_cpu_2_1_0: cpu-2-1-0-thermal { 6500 thermal-sensors = <&tsens4 3>; 6501 6502 trips { 6503 cpu-2-1-0-critical { 6504 temperature = <115000>; 6505 hysteresis = <1000>; 6506 type = "critical"; 6507 }; 6508 }; 6509 }; 6510 6511 thermal_cpu_2_1_1: cpu-2-1-1-thermal { 6512 thermal-sensors = <&tsens4 4>; 6513 6514 trips { 6515 cpu-2-1-1-critical { 6516 temperature = <115000>; 6517 hysteresis = <1000>; 6518 type = "critical"; 6519 }; 6520 }; 6521 }; 6522 6523 thermal_cpu_2_2_0: cpu-2-2-0-thermal { 6524 thermal-sensors = <&tsens4 5>; 6525 6526 trips { 6527 cpu-2-2-0-critical { 6528 temperature = <115000>; 6529 hysteresis = <1000>; 6530 type = "critical"; 6531 }; 6532 }; 6533 }; 6534 6535 thermal_cpu_2_2_1: cpu-2-2-1-thermal { 6536 thermal-sensors = <&tsens4 6>; 6537 6538 trips { 6539 cpu-2-2-1-critical { 6540 temperature = <115000>; 6541 hysteresis = <1000>; 6542 type = "critical"; 6543 }; 6544 }; 6545 }; 6546 6547 thermal_cpu_2_3_0: cpu-2-3-0-thermal { 6548 thermal-sensors = <&tsens4 7>; 6549 6550 trips { 6551 cpu-2-3-0-critical { 6552 temperature = <115000>; 6553 hysteresis = <1000>; 6554 type = "critical"; 6555 }; 6556 }; 6557 }; 6558 6559 thermal_cpu_2_3_1: cpu-2-3-1-thermal { 6560 thermal-sensors = <&tsens4 8>; 6561 6562 trips { 6563 cpu-2-3-1-critical { 6564 temperature = <115000>; 6565 hysteresis = <1000>; 6566 type = "critical"; 6567 }; 6568 }; 6569 }; 6570 6571 thermal_cpu_2_4_0: cpu-2-4-0-thermal { 6572 thermal-sensors = <&tsens4 9>; 6573 6574 trips { 6575 cpu-2-4-0-critical { 6576 temperature = <115000>; 6577 hysteresis = <1000>; 6578 type = "critical"; 6579 }; 6580 }; 6581 }; 6582 6583 thermal_cpu_2_4_1: cpu-2-4-1-thermal { 6584 thermal-sensors = <&tsens4 10>; 6585 6586 trips { 6587 cpu-2-4-1-critical { 6588 temperature = <115000>; 6589 hysteresis = <1000>; 6590 type = "critical"; 6591 }; 6592 }; 6593 }; 6594 6595 thermal_cpu_2_5_0: cpu-2-5-0-thermal { 6596 thermal-sensors = <&tsens4 11>; 6597 6598 trips { 6599 cpu-2-5-0-critical { 6600 temperature = <115000>; 6601 hysteresis = <1000>; 6602 type = "critical"; 6603 }; 6604 }; 6605 }; 6606 6607 thermal_cpu_2_5_1: cpu-2-5-1-thermal { 6608 thermal-sensors = <&tsens4 12>; 6609 6610 trips { 6611 cpu-2-5-1-critical { 6612 temperature = <115000>; 6613 hysteresis = <1000>; 6614 type = "critical"; 6615 }; 6616 }; 6617 }; 6618 6619 aoss-5-thermal { 6620 thermal-sensors = <&tsens5 0>; 6621 6622 trips { 6623 aoss-5-critical { 6624 temperature = <115000>; 6625 hysteresis = <1000>; 6626 type = "critical"; 6627 }; 6628 }; 6629 }; 6630 6631 thermal_cpullc_2_0: cpullc-2-0-thermal { 6632 thermal-sensors = <&tsens5 1>; 6633 6634 trips { 6635 cpullc-2-0-critical { 6636 temperature = <115000>; 6637 hysteresis = <1000>; 6638 type = "critical"; 6639 }; 6640 }; 6641 }; 6642 6643 thermal_cpuillc_2_1: cpuillc-2-1-thermal { 6644 thermal-sensors = <&tsens5 2>; 6645 6646 trips { 6647 cpullc-2-1-critical { 6648 temperature = <115000>; 6649 hysteresis = <1000>; 6650 type = "critical"; 6651 }; 6652 }; 6653 }; 6654 6655 thermal_qmx_2_0: qmx-2-0-thermal { 6656 thermal-sensors = <&tsens5 3>; 6657 6658 trips { 6659 qmx-2-0-critical { 6660 temperature = <115000>; 6661 hysteresis = <1000>; 6662 type = "critical"; 6663 }; 6664 }; 6665 }; 6666 6667 thermal_qmx_2_1: qmx-2-1-thermal { 6668 thermal-sensors = <&tsens5 4>; 6669 6670 trips { 6671 qmx-2-1-critical { 6672 temperature = <115000>; 6673 hysteresis = <1000>; 6674 type = "critical"; 6675 }; 6676 }; 6677 }; 6678 6679 thermal_qmx_2_2: qmx-2-2-thermal { 6680 thermal-sensors = <&tsens5 5>; 6681 6682 trips { 6683 qmx-2-2-critical { 6684 temperature = <115000>; 6685 hysteresis = <1000>; 6686 type = "critical"; 6687 }; 6688 }; 6689 }; 6690 6691 thermal_qmx_2_3: qmx-2-3-thermal { 6692 thermal-sensors = <&tsens5 6>; 6693 6694 trips { 6695 qmx-2-3-critical { 6696 temperature = <115000>; 6697 hysteresis = <1000>; 6698 type = "critical"; 6699 }; 6700 }; 6701 }; 6702 6703 thermal_qmx_2_4: qmx-2-4-thermal { 6704 thermal-sensors = <&tsens5 7>; 6705 6706 trips { 6707 qmx-2-4-critical { 6708 temperature = <115000>; 6709 hysteresis = <1000>; 6710 type = "critical"; 6711 }; 6712 }; 6713 }; 6714 6715 thermal_aoss_6: aoss-6-thermal { 6716 thermal-sensors = <&tsens6 0>; 6717 6718 trips { 6719 aoss-6-critical { 6720 temperature = <115000>; 6721 hysteresis = <1000>; 6722 type = "critical"; 6723 }; 6724 }; 6725 }; 6726 6727 thermal_nsphvx_0: nsphvx-0-thermal { 6728 thermal-sensors = <&tsens6 1>; 6729 6730 trips { 6731 nsphvx-0-critical { 6732 temperature = <115000>; 6733 hysteresis = <1000>; 6734 type = "critical"; 6735 }; 6736 }; 6737 }; 6738 6739 thermal_nsphvx_1: nsphvx-1-thermal { 6740 thermal-sensors = <&tsens6 2>; 6741 6742 trips { 6743 nsphvx-1-critical { 6744 temperature = <115000>; 6745 hysteresis = <1000>; 6746 type = "critical"; 6747 }; 6748 }; 6749 }; 6750 6751 thermal_nsphvx_2: nsphvx-2-thermal { 6752 thermal-sensors = <&tsens6 3>; 6753 6754 trips { 6755 nsphvx-2-critical { 6756 temperature = <115000>; 6757 hysteresis = <1000>; 6758 type = "critical"; 6759 }; 6760 }; 6761 }; 6762 6763 thermal_nsphvx_3: nsphvx-3-thermal { 6764 thermal-sensors = <&tsens6 4>; 6765 6766 trips { 6767 nsphvx-3-critical { 6768 temperature = <115000>; 6769 hysteresis = <1000>; 6770 type = "critical"; 6771 }; 6772 }; 6773 }; 6774 6775 thermal_nsphmx_0: nsphmx-0-thermal { 6776 thermal-sensors = <&tsens6 5>; 6777 6778 trips { 6779 nsphmx-0-critical { 6780 temperature = <115000>; 6781 hysteresis = <1000>; 6782 type = "critical"; 6783 }; 6784 }; 6785 }; 6786 6787 thermal_nsphmx_1: nsphmx-1-thermal { 6788 thermal-sensors = <&tsens6 6>; 6789 6790 trips { 6791 nsphmx-1-critical { 6792 temperature = <115000>; 6793 hysteresis = <1000>; 6794 type = "critical"; 6795 }; 6796 }; 6797 }; 6798 6799 thermal_nsphmx_2: nsphmx-2-thermal { 6800 thermal-sensors = <&tsens6 7>; 6801 6802 trips { 6803 nsphmx-2-critical { 6804 temperature = <115000>; 6805 hysteresis = <1000>; 6806 type = "critical"; 6807 }; 6808 }; 6809 }; 6810 6811 thermal_nsphmx_3: nsphmx-3-thermal { 6812 thermal-sensors = <&tsens6 8>; 6813 6814 trips { 6815 nsphmx-3-critical { 6816 temperature = <115000>; 6817 hysteresis = <1000>; 6818 type = "critical"; 6819 }; 6820 }; 6821 }; 6822 6823 thermal_camera_0: camera-0-thermal { 6824 thermal-sensors = <&tsens6 9>; 6825 6826 trips { 6827 camera-0-critical { 6828 temperature = <115000>; 6829 hysteresis = <1000>; 6830 type = "critical"; 6831 }; 6832 }; 6833 }; 6834 6835 thermal_camera_1: camera-1-thermal { 6836 thermal-sensors = <&tsens6 10>; 6837 6838 trips { 6839 camera-1-critical { 6840 temperature = <115000>; 6841 hysteresis = <1000>; 6842 type = "critical"; 6843 }; 6844 }; 6845 }; 6846 6847 thermal_ddr_1: ddr-1-thermal { 6848 thermal-sensors = <&tsens6 11>; 6849 6850 trips { 6851 ddr-1-critical { 6852 temperature = <115000>; 6853 hysteresis = <1000>; 6854 type = "critical"; 6855 }; 6856 }; 6857 }; 6858 6859 thermal_ddr_2: ddr-2-thermal { 6860 thermal-sensors = <&tsens6 12>; 6861 6862 trips { 6863 ddr-2-critical { 6864 temperature = <115000>; 6865 hysteresis = <1000>; 6866 type = "critical"; 6867 }; 6868 }; 6869 }; 6870 6871 thermal_aoss_7: aoss-7-thermal { 6872 thermal-sensors = <&tsens7 0>; 6873 6874 trips { 6875 aoss-7-critical { 6876 temperature = <115000>; 6877 hysteresis = <1000>; 6878 type = "critical"; 6879 }; 6880 }; 6881 }; 6882 6883 thermal_gpu_0_0: gpu-0-0-thermal { 6884 thermal-sensors = <&tsens7 1>; 6885 6886 trips { 6887 trip-point0 { 6888 temperature = <90000>; 6889 hysteresis = <5000>; 6890 type = "hot"; 6891 }; 6892 6893 gpu-0-0-critical { 6894 temperature = <115000>; 6895 hysteresis = <1000>; 6896 type = "critical"; 6897 }; 6898 }; 6899 }; 6900 6901 thermal_gpu_0_1: gpu-0-1-thermal { 6902 thermal-sensors = <&tsens7 2>; 6903 6904 trips { 6905 trip-point0 { 6906 temperature = <90000>; 6907 hysteresis = <5000>; 6908 type = "hot"; 6909 }; 6910 6911 gpu-0-1-critical { 6912 temperature = <115000>; 6913 hysteresis = <1000>; 6914 type = "critical"; 6915 }; 6916 }; 6917 }; 6918 6919 thermal_gpu_0_2: gpu-0-2-thermal { 6920 thermal-sensors = <&tsens7 3>; 6921 6922 trips { 6923 trip-point0 { 6924 temperature = <90000>; 6925 hysteresis = <5000>; 6926 type = "hot"; 6927 }; 6928 6929 gpu-0-2-critical { 6930 temperature = <115000>; 6931 hysteresis = <1000>; 6932 type = "critical"; 6933 }; 6934 }; 6935 }; 6936 6937 thermal_gpu_1_0: gpu-1-0-thermal { 6938 thermal-sensors = <&tsens7 4>; 6939 6940 trips { 6941 trip-point0 { 6942 temperature = <90000>; 6943 hysteresis = <5000>; 6944 type = "hot"; 6945 }; 6946 6947 gpu-1-0-critical { 6948 temperature = <115000>; 6949 hysteresis = <1000>; 6950 type = "critical"; 6951 }; 6952 }; 6953 }; 6954 6955 thermal_gpu_1_1: gpu-1-1-thermal { 6956 thermal-sensors = <&tsens7 5>; 6957 6958 trips { 6959 trip-point0 { 6960 temperature = <90000>; 6961 hysteresis = <5000>; 6962 type = "hot"; 6963 }; 6964 6965 gpu-1-1-critical { 6966 temperature = <115000>; 6967 hysteresis = <1000>; 6968 type = "critical"; 6969 }; 6970 }; 6971 }; 6972 6973 thermal_gpu_1_2: gpu-1-2-thermal { 6974 thermal-sensors = <&tsens7 6>; 6975 6976 trips { 6977 trip-point0 { 6978 temperature = <90000>; 6979 hysteresis = <5000>; 6980 type = "hot"; 6981 }; 6982 6983 gpu-1-2-critical { 6984 temperature = <115000>; 6985 hysteresis = <1000>; 6986 type = "critical"; 6987 }; 6988 }; 6989 }; 6990 6991 thermal_gpu_2_0: gpu-2-0-thermal { 6992 thermal-sensors = <&tsens7 7>; 6993 6994 trips { 6995 trip-point0 { 6996 temperature = <90000>; 6997 hysteresis = <5000>; 6998 type = "hot"; 6999 }; 7000 7001 gpu-2-0-critical { 7002 temperature = <115000>; 7003 hysteresis = <1000>; 7004 type = "critical"; 7005 }; 7006 }; 7007 }; 7008 7009 thermal_gpu_2_1: gpu-2-1-thermal { 7010 thermal-sensors = <&tsens7 8>; 7011 7012 trips { 7013 trip-point0 { 7014 temperature = <90000>; 7015 hysteresis = <5000>; 7016 type = "hot"; 7017 }; 7018 7019 gpu-2-1-critical { 7020 temperature = <115000>; 7021 hysteresis = <1000>; 7022 type = "critical"; 7023 }; 7024 }; 7025 }; 7026 7027 thermal_gpu_2_2: gpu-2-2-thermal { 7028 thermal-sensors = <&tsens7 9>; 7029 7030 trips { 7031 trip-point0 { 7032 temperature = <90000>; 7033 hysteresis = <5000>; 7034 type = "hot"; 7035 }; 7036 7037 gpu-2-2-critical { 7038 temperature = <115000>; 7039 hysteresis = <1000>; 7040 type = "critical"; 7041 }; 7042 }; 7043 }; 7044 7045 thermal_gpu_3_0: gpu-3-0-thermal { 7046 thermal-sensors = <&tsens7 10>; 7047 7048 trips { 7049 trip-point0 { 7050 temperature = <90000>; 7051 hysteresis = <5000>; 7052 type = "hot"; 7053 }; 7054 7055 gpu-3-0-critical { 7056 temperature = <115000>; 7057 hysteresis = <1000>; 7058 type = "critical"; 7059 }; 7060 }; 7061 }; 7062 7063 thermal_gpu_3_1: gpu-3-1-thermal { 7064 thermal-sensors = <&tsens7 11>; 7065 7066 trips { 7067 trip-point0 { 7068 temperature = <90000>; 7069 hysteresis = <5000>; 7070 type = "hot"; 7071 }; 7072 7073 gpu-3-1-critical { 7074 temperature = <115000>; 7075 hysteresis = <1000>; 7076 type = "critical"; 7077 }; 7078 }; 7079 }; 7080 7081 thermal_gpu_3_2: gpu-3-2-thermal { 7082 thermal-sensors = <&tsens7 12>; 7083 7084 trips { 7085 trip-point0 { 7086 temperature = <90000>; 7087 hysteresis = <5000>; 7088 type = "hot"; 7089 }; 7090 7091 gpu-3-2-critical { 7092 temperature = <115000>; 7093 hysteresis = <1000>; 7094 type = "critical"; 7095 }; 7096 }; 7097 }; 7098 7099 thermal_gpuss_0: gpuss-0-thermal { 7100 thermal-sensors = <&tsens7 13>; 7101 7102 trips { 7103 trip-point0 { 7104 temperature = <90000>; 7105 hysteresis = <5000>; 7106 type = "hot"; 7107 }; 7108 7109 gpuss-0-critical { 7110 temperature = <115000>; 7111 hysteresis = <1000>; 7112 type = "critical"; 7113 }; 7114 }; 7115 }; 7116 7117 thermal_gpuss_1: gpuss-1-thermal { 7118 thermal-sensors = <&tsens7 14>; 7119 7120 trips { 7121 trip-point0 { 7122 temperature = <90000>; 7123 hysteresis = <5000>; 7124 type = "hot"; 7125 }; 7126 7127 gpuss-1-critical { 7128 temperature = <115000>; 7129 hysteresis = <1000>; 7130 type = "critical"; 7131 }; 7132 }; 7133 }; 7134 }; 7135}; 7136