1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,qcs8300-gcc.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/clock/qcom,sa8775p-camcc.h> 9#include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 10#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 11#include <dt-bindings/clock/qcom,sa8775p-videocc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/soc/qcom,gpr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 clocks { 31 xo_board_clk: xo-board-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <38400000>; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <32000>; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a78c"; 51 reg = <0x0 0x0>; 52 enable-method = "psci"; 53 next-level-cache = <&l2_0>; 54 power-domains = <&cpu_pd0>; 55 power-domain-names = "psci"; 56 capacity-dmips-mhz = <1946>; 57 dynamic-power-coefficient = <472>; 58 qcom,freq-domain = <&cpufreq_hw 0>; 59 operating-points-v2 = <&cpu0_opp_table>; 60 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 61 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 62 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 63 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 64 65 l2_0: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&l3_0>; 70 }; 71 }; 72 73 cpu1: cpu@100 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a78c"; 76 reg = <0x0 0x100>; 77 enable-method = "psci"; 78 next-level-cache = <&l2_1>; 79 power-domains = <&cpu_pd1>; 80 power-domain-names = "psci"; 81 capacity-dmips-mhz = <1946>; 82 dynamic-power-coefficient = <472>; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 operating-points-v2 = <&cpu0_opp_table>; 85 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 86 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 87 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 88 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 89 90 l2_1: l2-cache { 91 compatible = "cache"; 92 cache-level = <2>; 93 cache-unified; 94 next-level-cache = <&l3_0>; 95 }; 96 }; 97 98 cpu2: cpu@200 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a78c"; 101 reg = <0x0 0x200>; 102 enable-method = "psci"; 103 next-level-cache = <&l2_2>; 104 power-domains = <&cpu_pd2>; 105 power-domain-names = "psci"; 106 capacity-dmips-mhz = <1946>; 107 dynamic-power-coefficient = <507>; 108 qcom,freq-domain = <&cpufreq_hw 2>; 109 operating-points-v2 = <&cpu2_opp_table>; 110 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 111 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 112 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 113 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 114 115 l2_2: l2-cache { 116 compatible = "cache"; 117 cache-level = <2>; 118 cache-unified; 119 next-level-cache = <&l3_0>; 120 }; 121 }; 122 123 cpu3: cpu@300 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a78c"; 126 reg = <0x0 0x300>; 127 enable-method = "psci"; 128 next-level-cache = <&l2_3>; 129 power-domains = <&cpu_pd3>; 130 power-domain-names = "psci"; 131 capacity-dmips-mhz = <1946>; 132 dynamic-power-coefficient = <507>; 133 qcom,freq-domain = <&cpufreq_hw 2>; 134 operating-points-v2 = <&cpu2_opp_table>; 135 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 136 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 137 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 138 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 139 140 l2_3: l2-cache { 141 compatible = "cache"; 142 cache-level = <2>; 143 cache-unified; 144 next-level-cache = <&l3_0>; 145 }; 146 }; 147 148 cpu4: cpu@10000 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a55"; 151 reg = <0x0 0x10000>; 152 enable-method = "psci"; 153 next-level-cache = <&l2_4>; 154 power-domains = <&cpu_pd4>; 155 power-domain-names = "psci"; 156 capacity-dmips-mhz = <1024>; 157 dynamic-power-coefficient = <100>; 158 qcom,freq-domain = <&cpufreq_hw 1>; 159 operating-points-v2 = <&cpu4_opp_table>; 160 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 161 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 162 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 163 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 164 165 l2_4: l2-cache { 166 compatible = "cache"; 167 cache-level = <2>; 168 cache-unified; 169 next-level-cache = <&l3_1>; 170 }; 171 }; 172 173 cpu5: cpu@10100 { 174 device_type = "cpu"; 175 compatible = "arm,cortex-a55"; 176 reg = <0x0 0x10100>; 177 enable-method = "psci"; 178 next-level-cache = <&l2_5>; 179 power-domains = <&cpu_pd5>; 180 power-domain-names = "psci"; 181 capacity-dmips-mhz = <1024>; 182 dynamic-power-coefficient = <100>; 183 qcom,freq-domain = <&cpufreq_hw 1>; 184 operating-points-v2 = <&cpu4_opp_table>; 185 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 186 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 187 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 188 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 189 190 l2_5: l2-cache { 191 compatible = "cache"; 192 cache-level = <2>; 193 cache-unified; 194 next-level-cache = <&l3_1>; 195 }; 196 }; 197 198 cpu6: cpu@10200 { 199 device_type = "cpu"; 200 compatible = "arm,cortex-a55"; 201 reg = <0x0 0x10200>; 202 enable-method = "psci"; 203 next-level-cache = <&l2_6>; 204 power-domains = <&cpu_pd6>; 205 power-domain-names = "psci"; 206 capacity-dmips-mhz = <1024>; 207 dynamic-power-coefficient = <100>; 208 qcom,freq-domain = <&cpufreq_hw 1>; 209 operating-points-v2 = <&cpu4_opp_table>; 210 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 211 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 212 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 213 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 214 215 l2_6: l2-cache { 216 compatible = "cache"; 217 cache-level = <2>; 218 cache-unified; 219 next-level-cache = <&l3_1>; 220 }; 221 }; 222 223 cpu7: cpu@10300 { 224 device_type = "cpu"; 225 compatible = "arm,cortex-a55"; 226 reg = <0x0 0x10300>; 227 enable-method = "psci"; 228 next-level-cache = <&l2_7>; 229 power-domains = <&cpu_pd7>; 230 power-domain-names = "psci"; 231 capacity-dmips-mhz = <1024>; 232 dynamic-power-coefficient = <100>; 233 qcom,freq-domain = <&cpufreq_hw 1>; 234 operating-points-v2 = <&cpu4_opp_table>; 235 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 236 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 237 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 238 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 239 240 l2_7: l2-cache { 241 compatible = "cache"; 242 cache-level = <2>; 243 cache-unified; 244 next-level-cache = <&l3_1>; 245 }; 246 }; 247 248 cpu-map { 249 cluster0 { 250 core0 { 251 cpu = <&cpu0>; 252 }; 253 254 core1 { 255 cpu = <&cpu1>; 256 }; 257 258 core2 { 259 cpu = <&cpu2>; 260 }; 261 262 core3 { 263 cpu = <&cpu3>; 264 }; 265 }; 266 267 cluster1 { 268 core0 { 269 cpu = <&cpu4>; 270 }; 271 272 core1 { 273 cpu = <&cpu5>; 274 }; 275 276 core2 { 277 cpu = <&cpu6>; 278 }; 279 280 core3 { 281 cpu = <&cpu7>; 282 }; 283 }; 284 }; 285 286 l3_0: l3-cache-0 { 287 compatible = "cache"; 288 cache-level = <3>; 289 cache-unified; 290 }; 291 292 l3_1: l3-cache-1 { 293 compatible = "cache"; 294 cache-level = <3>; 295 cache-unified; 296 }; 297 298 idle-states { 299 entry-method = "psci"; 300 301 little_cpu_sleep_0: cpu-sleep-0-0 { 302 compatible = "arm,idle-state"; 303 idle-state-name = "silver-power-collapse"; 304 arm,psci-suspend-param = <0x40000003>; 305 entry-latency-us = <449>; 306 exit-latency-us = <801>; 307 min-residency-us = <1574>; 308 local-timer-stop; 309 }; 310 311 little_cpu_sleep_1: cpu-sleep-0-1 { 312 compatible = "arm,idle-state"; 313 idle-state-name = "silver-rail-power-collapse"; 314 arm,psci-suspend-param = <0x40000004>; 315 entry-latency-us = <602>; 316 exit-latency-us = <961>; 317 min-residency-us = <4288>; 318 local-timer-stop; 319 }; 320 321 big_cpu_sleep_0: cpu-sleep-1-0 { 322 compatible = "arm,idle-state"; 323 idle-state-name = "gold-power-collapse"; 324 arm,psci-suspend-param = <0x40000003>; 325 entry-latency-us = <549>; 326 exit-latency-us = <901>; 327 min-residency-us = <1774>; 328 local-timer-stop; 329 }; 330 331 big_cpu_sleep_1: cpu-sleep-1-1 { 332 compatible = "arm,idle-state"; 333 idle-state-name = "gold-rail-power-collapse"; 334 arm,psci-suspend-param = <0x40000004>; 335 entry-latency-us = <702>; 336 exit-latency-us = <1061>; 337 min-residency-us = <4488>; 338 local-timer-stop; 339 }; 340 }; 341 342 domain-idle-states { 343 silver_cluster_sleep: cluster-sleep-0 { 344 compatible = "domain-idle-state"; 345 arm,psci-suspend-param = <0x41000044>; 346 entry-latency-us = <2552>; 347 exit-latency-us = <2848>; 348 min-residency-us = <5908>; 349 }; 350 351 gold_cluster_sleep: cluster-sleep-1 { 352 compatible = "domain-idle-state"; 353 arm,psci-suspend-param = <0x41000044>; 354 entry-latency-us = <2752>; 355 exit-latency-us = <3048>; 356 min-residency-us = <6118>; 357 }; 358 359 system_sleep: domain-sleep { 360 compatible = "domain-idle-state"; 361 arm,psci-suspend-param = <0x42000144>; 362 entry-latency-us = <3263>; 363 exit-latency-us = <6562>; 364 min-residency-us = <9987>; 365 }; 366 }; 367 }; 368 369 cpu0_opp_table: opp-table-cpu0 { 370 compatible = "operating-points-v2"; 371 opp-shared; 372 373 opp-902400000 { 374 opp-hz = /bits/ 64 <902400000>; 375 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 376 }; 377 378 opp-1017600000 { 379 opp-hz = /bits/ 64 <1017600000>; 380 opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; 381 }; 382 383 opp-1190400000 { 384 opp-hz = /bits/ 64 <1190400000>; 385 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 386 }; 387 388 opp-1267200000 { 389 opp-hz = /bits/ 64 <1267200000>; 390 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 391 }; 392 393 opp-1344000000 { 394 opp-hz = /bits/ 64 <1344000000>; 395 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 396 }; 397 398 opp-1420800000 { 399 opp-hz = /bits/ 64 <1420800000>; 400 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 401 }; 402 403 opp-1497600000 { 404 opp-hz = /bits/ 64 <1497600000>; 405 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 406 }; 407 408 opp-1574400000 { 409 opp-hz = /bits/ 64 <1574400000>; 410 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 411 }; 412 413 opp-1670400000 { 414 opp-hz = /bits/ 64 <1670400000>; 415 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 416 }; 417 418 opp-1747200000 { 419 opp-hz = /bits/ 64 <1747200000>; 420 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 421 }; 422 423 opp-1824000000 { 424 opp-hz = /bits/ 64 <1824000000>; 425 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 426 }; 427 428 opp-1900800000 { 429 opp-hz = /bits/ 64 <1900800000>; 430 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 431 }; 432 433 opp-1977600000 { 434 opp-hz = /bits/ 64 <1977600000>; 435 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 436 }; 437 438 opp-2054400000 { 439 opp-hz = /bits/ 64 <2054400000>; 440 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 441 }; 442 443 opp-2112000000 { 444 opp-hz = /bits/ 64 <2112000000>; 445 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 446 }; 447 448 }; 449 450 cpu2_opp_table: opp-table-cpu2 { 451 compatible = "operating-points-v2"; 452 opp-shared; 453 454 opp-940800000 { 455 opp-hz = /bits/ 64 <940800000>; 456 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 457 }; 458 459 opp-1094400000 { 460 opp-hz = /bits/ 64 <1094400000>; 461 opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; 462 }; 463 464 opp-1267200000 { 465 opp-hz = /bits/ 64 <1267200000>; 466 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 467 }; 468 469 opp-1344000000 { 470 opp-hz = /bits/ 64 <1344000000>; 471 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 472 }; 473 474 opp-1420800000 { 475 opp-hz = /bits/ 64 <1420800000>; 476 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 477 }; 478 479 opp-1497600000 { 480 opp-hz = /bits/ 64 <1497600000>; 481 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 482 }; 483 484 opp-1574400000 { 485 opp-hz = /bits/ 64 <1574400000>; 486 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 487 }; 488 489 opp-1632000000 { 490 opp-hz = /bits/ 64 <1632000000>; 491 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 492 }; 493 494 opp-1708800000 { 495 opp-hz = /bits/ 64 <1708800000>; 496 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 497 }; 498 499 opp-1804800000 { 500 opp-hz = /bits/ 64 <1804800000>; 501 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 502 }; 503 504 opp-1900800000 { 505 opp-hz = /bits/ 64 <1900800000>; 506 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 507 }; 508 509 opp-1977600000 { 510 opp-hz = /bits/ 64 <1977600000>; 511 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 512 }; 513 514 opp-2054400000 { 515 opp-hz = /bits/ 64 <2054400000>; 516 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 517 }; 518 519 opp-2131200000 { 520 opp-hz = /bits/ 64 <2131200000>; 521 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 522 }; 523 524 opp-2208000000 { 525 opp-hz = /bits/ 64 <2208000000>; 526 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 527 }; 528 529 opp-2284800000 { 530 opp-hz = /bits/ 64 <2284800000>; 531 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 532 }; 533 534 opp-2361600000 { 535 opp-hz = /bits/ 64 <2361600000>; 536 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 537 }; 538 539 }; 540 541 cpu4_opp_table: opp-table-cpu4 { 542 compatible = "operating-points-v2"; 543 opp-shared; 544 545 opp-844800000 { 546 opp-hz = /bits/ 64 <844800000>; 547 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 548 }; 549 550 opp-1113600000 { 551 opp-hz = /bits/ 64 <1113600000>; 552 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 553 }; 554 555 opp-1209600000 { 556 opp-hz = /bits/ 64 <1209600000>; 557 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 558 }; 559 560 opp-1305600000 { 561 opp-hz = /bits/ 64 <1305600000>; 562 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 563 }; 564 565 opp-1382400000 { 566 opp-hz = /bits/ 64 <1382400000>; 567 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 568 }; 569 570 opp-1459200000 { 571 opp-hz = /bits/ 64 <1459200000>; 572 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 573 }; 574 575 opp-1497600000 { 576 opp-hz = /bits/ 64 <1497600000>; 577 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 578 }; 579 580 opp-1574400000 { 581 opp-hz = /bits/ 64 <1574400000>; 582 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 583 }; 584 585 opp-1651200000 { 586 opp-hz = /bits/ 64 <1651200000>; 587 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 588 }; 589 590 opp-1728000000 { 591 opp-hz = /bits/ 64 <1728000000>; 592 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 593 }; 594 595 opp-1804800000 { 596 opp-hz = /bits/ 64 <1804800000>; 597 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 598 }; 599 600 opp-1881600000 { 601 opp-hz = /bits/ 64 <1881600000>; 602 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 603 }; 604 605 opp-1958400000 { 606 opp-hz = /bits/ 64 <1958400000>; 607 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 608 }; 609 }; 610 611 dummy_eud: dummy-sink { 612 compatible = "arm,coresight-dummy-sink"; 613 614 in-ports { 615 port { 616 eud_in: endpoint { 617 remote-endpoint = <&swao_rep_out1>; 618 }; 619 }; 620 }; 621 }; 622 623 firmware { 624 scm: scm { 625 compatible = "qcom,scm-qcs8300", "qcom,scm"; 626 qcom,dload-mode = <&tcsr 0x13000>; 627 }; 628 }; 629 630 memory@80000000 { 631 device_type = "memory"; 632 /* We expect the bootloader to fill in the size */ 633 reg = <0x0 0x80000000 0x0 0x0>; 634 }; 635 636 clk_virt: interconnect-0 { 637 compatible = "qcom,qcs8300-clk-virt"; 638 #interconnect-cells = <2>; 639 qcom,bcm-voters = <&apps_bcm_voter>; 640 }; 641 642 mc_virt: interconnect-1 { 643 compatible = "qcom,qcs8300-mc-virt"; 644 #interconnect-cells = <2>; 645 qcom,bcm-voters = <&apps_bcm_voter>; 646 }; 647 648 qup_opp_table: opp-table-qup { 649 compatible = "operating-points-v2"; 650 651 opp-120000000 { 652 opp-hz = /bits/ 64 <120000000>; 653 required-opps = <&rpmhpd_opp_svs_l1>; 654 }; 655 }; 656 657 pmu-a55 { 658 compatible = "arm,cortex-a55-pmu"; 659 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 660 }; 661 662 pmu-a78 { 663 compatible = "arm,cortex-a78-pmu"; 664 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 665 }; 666 667 psci { 668 compatible = "arm,psci-1.0"; 669 method = "smc"; 670 671 cpu_pd0: power-domain-cpu0 { 672 #power-domain-cells = <0>; 673 power-domains = <&cluster_pd0>; 674 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 675 }; 676 677 cpu_pd1: power-domain-cpu1 { 678 #power-domain-cells = <0>; 679 power-domains = <&cluster_pd0>; 680 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 681 }; 682 683 cpu_pd2: power-domain-cpu2 { 684 #power-domain-cells = <0>; 685 power-domains = <&cluster_pd0>; 686 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 687 }; 688 689 cpu_pd3: power-domain-cpu3 { 690 #power-domain-cells = <0>; 691 power-domains = <&cluster_pd0>; 692 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 693 }; 694 695 cpu_pd4: power-domain-cpu4 { 696 #power-domain-cells = <0>; 697 power-domains = <&cluster_pd1>; 698 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 699 }; 700 701 cpu_pd5: power-domain-cpu5 { 702 #power-domain-cells = <0>; 703 power-domains = <&cluster_pd1>; 704 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 705 }; 706 707 cpu_pd6: power-domain-cpu6 { 708 #power-domain-cells = <0>; 709 power-domains = <&cluster_pd1>; 710 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 711 }; 712 713 cpu_pd7: power-domain-cpu7 { 714 #power-domain-cells = <0>; 715 power-domains = <&cluster_pd1>; 716 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 717 }; 718 719 cluster_pd0: power-domain-cluster0 { 720 #power-domain-cells = <0>; 721 power-domains = <&system_pd>; 722 domain-idle-states = <&gold_cluster_sleep>; 723 }; 724 725 cluster_pd1: power-domain-cluster1 { 726 #power-domain-cells = <0>; 727 power-domains = <&system_pd>; 728 domain-idle-states = <&silver_cluster_sleep>; 729 }; 730 731 system_pd: power-domain-system { 732 #power-domain-cells = <0>; 733 domain-idle-states = <&system_sleep>; 734 }; 735 }; 736 737 reserved-memory { 738 #address-cells = <2>; 739 #size-cells = <2>; 740 ranges; 741 742 aop_image_mem: aop-image-region@90800000 { 743 reg = <0x0 0x90800000 0x0 0x60000>; 744 no-map; 745 }; 746 747 aop_cmd_db_mem: aop-cmd-db-region@90860000 { 748 compatible = "qcom,cmd-db"; 749 reg = <0x0 0x90860000 0x0 0x20000>; 750 no-map; 751 }; 752 753 smem_mem: smem@90900000 { 754 compatible = "qcom,smem"; 755 reg = <0x0 0x90900000 0x0 0x200000>; 756 no-map; 757 hwlocks = <&tcsr_mutex 3>; 758 }; 759 760 lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 { 761 reg = <0x0 0x93b00000 0x0 0xf00000>; 762 no-map; 763 }; 764 765 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap-region@94a00000 { 766 reg = <0x0 0x94a00000 0x0 0x800000>; 767 no-map; 768 }; 769 770 camera_mem: camera-region@95200000 { 771 reg = <0x0 0x95200000 0x0 0x500000>; 772 no-map; 773 }; 774 775 adsp_mem: adsp-region@95c00000 { 776 no-map; 777 reg = <0x0 0x95c00000 0x0 0x1e00000>; 778 }; 779 780 q6_adsp_dtb_mem: q6-adsp-dtb-region@97a00000 { 781 reg = <0x0 0x97a00000 0x0 0x80000>; 782 no-map; 783 }; 784 785 q6_gpdsp_dtb_mem: q6-gpdsp-dtb-region@97a80000 { 786 reg = <0x0 0x97a80000 0x0 0x80000>; 787 no-map; 788 }; 789 790 gpdsp_mem: gpdsp-region@97b00000 { 791 reg = <0x0 0x97b00000 0x0 0x1e00000>; 792 no-map; 793 }; 794 795 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@99900000 { 796 reg = <0x0 0x99900000 0x0 0x80000>; 797 no-map; 798 }; 799 800 cdsp_mem: cdsp-region@99980000 { 801 reg = <0x0 0x99980000 0x0 0x1e00000>; 802 no-map; 803 }; 804 805 gpu_microcode_mem: gpu-microcode-region@9b780000 { 806 reg = <0x0 0x9b780000 0x0 0x2000>; 807 no-map; 808 }; 809 810 cvp_mem: cvp-region@9b782000 { 811 reg = <0x0 0x9b782000 0x0 0x700000>; 812 no-map; 813 }; 814 815 video_mem: video-region@9be82000 { 816 reg = <0x0 0x9be82000 0x0 0x700000>; 817 no-map; 818 }; 819 }; 820 821 smp2p-adsp { 822 compatible = "qcom,smp2p"; 823 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 824 IPCC_MPROC_SIGNAL_SMP2P 825 IRQ_TYPE_EDGE_RISING>; 826 mboxes = <&ipcc IPCC_CLIENT_LPASS 827 IPCC_MPROC_SIGNAL_SMP2P>; 828 829 qcom,smem = <443>, <429>; 830 qcom,local-pid = <0>; 831 qcom,remote-pid = <2>; 832 833 smp2p_adsp_in: slave-kernel { 834 qcom,entry-name = "slave-kernel"; 835 interrupt-controller; 836 #interrupt-cells = <2>; 837 }; 838 839 smp2p_adsp_out: master-kernel { 840 qcom,entry-name = "master-kernel"; 841 #qcom,smem-state-cells = <1>; 842 }; 843 }; 844 845 smp2p-cdsp { 846 compatible = "qcom,smp2p"; 847 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 848 IPCC_MPROC_SIGNAL_SMP2P 849 IRQ_TYPE_EDGE_RISING>; 850 mboxes = <&ipcc IPCC_CLIENT_CDSP 851 IPCC_MPROC_SIGNAL_SMP2P>; 852 853 qcom,smem = <94>, <432>; 854 qcom,local-pid = <0>; 855 qcom,remote-pid = <5>; 856 857 smp2p_cdsp_in: slave-kernel { 858 qcom,entry-name = "slave-kernel"; 859 interrupt-controller; 860 #interrupt-cells = <2>; 861 }; 862 863 smp2p_cdsp_out: master-kernel { 864 qcom,entry-name = "master-kernel"; 865 #qcom,smem-state-cells = <1>; 866 }; 867 }; 868 869 smp2p-gpdsp { 870 compatible = "qcom,smp2p"; 871 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 872 IPCC_MPROC_SIGNAL_SMP2P 873 IRQ_TYPE_EDGE_RISING>; 874 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 875 IPCC_MPROC_SIGNAL_SMP2P>; 876 877 qcom,smem = <617>, <616>; 878 qcom,local-pid = <0>; 879 qcom,remote-pid = <17>; 880 881 smp2p_gpdsp_in: slave-kernel { 882 qcom,entry-name = "slave-kernel"; 883 interrupt-controller; 884 #interrupt-cells = <2>; 885 }; 886 887 smp2p_gpdsp_out: master-kernel { 888 qcom,entry-name = "master-kernel"; 889 #qcom,smem-state-cells = <1>; 890 }; 891 }; 892 893 soc: soc@0 { 894 compatible = "simple-bus"; 895 ranges = <0 0 0 0 0x10 0>; 896 #address-cells = <2>; 897 #size-cells = <2>; 898 899 gcc: clock-controller@100000 { 900 compatible = "qcom,qcs8300-gcc"; 901 reg = <0x0 0x00100000 0x0 0xc7018>; 902 #clock-cells = <1>; 903 #reset-cells = <1>; 904 #power-domain-cells = <1>; 905 clocks = <&rpmhcc RPMH_CXO_CLK>, 906 <&sleep_clk>, 907 <0>, 908 <0>, 909 <0>, 910 <0>, 911 <0>, 912 <0>, 913 <0>, 914 <0>; 915 }; 916 917 ipcc: mailbox@408000 { 918 compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; 919 reg = <0x0 0x408000 0x0 0x1000>; 920 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 921 interrupt-controller; 922 #interrupt-cells = <3>; 923 #mbox-cells = <2>; 924 }; 925 926 qfprom: efuse@784000 { 927 compatible = "qcom,qcs8300-qfprom", "qcom,qfprom"; 928 reg = <0x0 0x00784000 0x0 0x2410>; 929 #address-cells = <1>; 930 #size-cells = <1>; 931 932 gpu_speed_bin: gpu_speed_bin@240c { 933 reg = <0x240c 0x1>; 934 bits = <0 8>; 935 }; 936 }; 937 938 gpi_dma0: dma-controller@900000 { 939 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 940 reg = <0x0 0x900000 0x0 0x60000>; 941 #dma-cells = <3>; 942 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 954 iommus = <&apps_smmu 0x416 0x0>; 955 dma-channels = <12>; 956 dma-channel-mask = <0xfff>; 957 dma-coherent; 958 status = "disabled"; 959 }; 960 961 qupv3_id_0: geniqup@9c0000 { 962 compatible = "qcom,geni-se-qup"; 963 reg = <0x0 0x9c0000 0x0 0x2000>; 964 ranges; 965 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 966 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 967 clock-names = "m-ahb", 968 "s-ahb"; 969 #address-cells = <2>; 970 #size-cells = <2>; 971 iommus = <&apps_smmu 0x403 0x0>; 972 dma-coherent; 973 status = "disabled"; 974 975 i2c0: i2c@980000 { 976 compatible = "qcom,geni-i2c"; 977 reg = <0x0 0x980000 0x0 0x4000>; 978 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 979 clock-names = "se"; 980 pinctrl-0 = <&qup_i2c0_data_clk>; 981 pinctrl-names = "default"; 982 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 983 #address-cells = <1>; 984 #size-cells = <0>; 985 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 986 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 987 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 988 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 989 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 990 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 991 interconnect-names = "qup-core", 992 "qup-config", 993 "qup-memory"; 994 power-domains = <&rpmhpd RPMHPD_CX>; 995 required-opps = <&rpmhpd_opp_low_svs>; 996 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 997 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 998 dma-names = "tx", 999 "rx"; 1000 status = "disabled"; 1001 }; 1002 1003 spi0: spi@980000 { 1004 compatible = "qcom,geni-spi"; 1005 reg = <0x0 0x980000 0x0 0x4000>; 1006 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1007 clock-names = "se"; 1008 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1009 pinctrl-names = "default"; 1010 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1014 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1015 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1016 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1017 interconnect-names = "qup-core", 1018 "qup-config"; 1019 power-domains = <&rpmhpd RPMHPD_CX>; 1020 operating-points-v2 = <&qup_opp_table>; 1021 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1022 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1023 dma-names = "tx", 1024 "rx"; 1025 status = "disabled"; 1026 }; 1027 1028 uart0: serial@980000 { 1029 compatible = "qcom,geni-uart"; 1030 reg = <0x0 0x980000 0x0 0x4000>; 1031 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1032 clock-names = "se"; 1033 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, 1034 <&qup_uart0_tx>, <&qup_uart0_rx>; 1035 pinctrl-names = "default"; 1036 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1037 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1038 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1039 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1040 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1041 interconnect-names = "qup-core", 1042 "qup-config"; 1043 power-domains = <&rpmhpd RPMHPD_CX>; 1044 operating-points-v2 = <&qup_opp_table>; 1045 status = "disabled"; 1046 }; 1047 1048 i2c1: i2c@984000 { 1049 compatible = "qcom,geni-i2c"; 1050 reg = <0x0 0x984000 0x0 0x4000>; 1051 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1052 clock-names = "se"; 1053 pinctrl-0 = <&qup_i2c1_data_clk>; 1054 pinctrl-names = "default"; 1055 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1056 #address-cells = <1>; 1057 #size-cells = <0>; 1058 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1059 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1060 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1061 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1062 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1063 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1064 interconnect-names = "qup-core", 1065 "qup-config", 1066 "qup-memory"; 1067 power-domains = <&rpmhpd RPMHPD_CX>; 1068 required-opps = <&rpmhpd_opp_low_svs>; 1069 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1070 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1071 dma-names = "tx", 1072 "rx"; 1073 status = "disabled"; 1074 }; 1075 1076 spi1: spi@984000 { 1077 compatible = "qcom,geni-spi"; 1078 reg = <0x0 0x984000 0x0 0x4000>; 1079 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1080 clock-names = "se"; 1081 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1082 pinctrl-names = "default"; 1083 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1087 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1088 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1089 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1090 interconnect-names = "qup-core", 1091 "qup-config"; 1092 power-domains = <&rpmhpd RPMHPD_CX>; 1093 operating-points-v2 = <&qup_opp_table>; 1094 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1095 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1096 dma-names = "tx", 1097 "rx"; 1098 status = "disabled"; 1099 }; 1100 1101 uart1: serial@984000 { 1102 compatible = "qcom,geni-uart"; 1103 reg = <0x0 0x984000 0x0 0x4000>; 1104 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1105 clock-names = "se"; 1106 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, 1107 <&qup_uart1_tx>, <&qup_uart1_rx>; 1108 pinctrl-names = "default"; 1109 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1110 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1111 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1112 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1113 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1114 interconnect-names = "qup-core", 1115 "qup-config"; 1116 power-domains = <&rpmhpd RPMHPD_CX>; 1117 operating-points-v2 = <&qup_opp_table>; 1118 status = "disabled"; 1119 }; 1120 1121 i2c2: i2c@988000 { 1122 compatible = "qcom,geni-i2c"; 1123 reg = <0x0 0x988000 0x0 0x4000>; 1124 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1125 clock-names = "se"; 1126 pinctrl-0 = <&qup_i2c2_data_clk>; 1127 pinctrl-names = "default"; 1128 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1129 #address-cells = <1>; 1130 #size-cells = <0>; 1131 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1132 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1133 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1134 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1135 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1136 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1137 interconnect-names = "qup-core", 1138 "qup-config", 1139 "qup-memory"; 1140 power-domains = <&rpmhpd RPMHPD_CX>; 1141 required-opps = <&rpmhpd_opp_low_svs>; 1142 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1143 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1144 dma-names = "tx", 1145 "rx"; 1146 status = "disabled"; 1147 }; 1148 1149 spi2: spi@988000 { 1150 compatible = "qcom,geni-spi"; 1151 reg = <0x0 0x988000 0x0 0x4000>; 1152 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1153 clock-names = "se"; 1154 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1155 pinctrl-names = "default"; 1156 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1160 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1161 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1162 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1163 interconnect-names = "qup-core", 1164 "qup-config"; 1165 power-domains = <&rpmhpd RPMHPD_CX>; 1166 operating-points-v2 = <&qup_opp_table>; 1167 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1168 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1169 dma-names = "tx", 1170 "rx"; 1171 status = "disabled"; 1172 }; 1173 1174 uart2: serial@988000 { 1175 compatible = "qcom,geni-uart"; 1176 reg = <0x0 0x988000 0x0 0x4000>; 1177 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1178 clock-names = "se"; 1179 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, 1180 <&qup_uart2_tx>, <&qup_uart2_rx>; 1181 pinctrl-names = "default"; 1182 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1183 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1184 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1185 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1186 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1187 interconnect-names = "qup-core", 1188 "qup-config"; 1189 power-domains = <&rpmhpd RPMHPD_CX>; 1190 operating-points-v2 = <&qup_opp_table>; 1191 status = "disabled"; 1192 }; 1193 1194 i2c3: i2c@98c000 { 1195 compatible = "qcom,geni-i2c"; 1196 reg = <0x0 0x98c000 0x0 0x4000>; 1197 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1198 clock-names = "se"; 1199 pinctrl-0 = <&qup_i2c3_data_clk>; 1200 pinctrl-names = "default"; 1201 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1205 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1206 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1207 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1208 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1209 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1210 interconnect-names = "qup-core", 1211 "qup-config", 1212 "qup-memory"; 1213 power-domains = <&rpmhpd RPMHPD_CX>; 1214 required-opps = <&rpmhpd_opp_low_svs>; 1215 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1216 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1217 dma-names = "tx", 1218 "rx"; 1219 status = "disabled"; 1220 }; 1221 1222 spi3: spi@98c000 { 1223 compatible = "qcom,geni-spi"; 1224 reg = <0x0 0x98c000 0x0 0x4000>; 1225 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1226 clock-names = "se"; 1227 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1228 pinctrl-names = "default"; 1229 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1233 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1234 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1235 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1236 interconnect-names = "qup-core", 1237 "qup-config"; 1238 power-domains = <&rpmhpd RPMHPD_CX>; 1239 operating-points-v2 = <&qup_opp_table>; 1240 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1241 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1242 dma-names = "tx", 1243 "rx"; 1244 status = "disabled"; 1245 }; 1246 1247 uart3: serial@98c000 { 1248 compatible = "qcom,geni-uart"; 1249 reg = <0x0 0x98c000 0x0 0x4000>; 1250 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1251 clock-names = "se"; 1252 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, 1253 <&qup_uart3_tx>, <&qup_uart3_rx>; 1254 pinctrl-names = "default"; 1255 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1256 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1257 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1258 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1259 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1260 interconnect-names = "qup-core", 1261 "qup-config"; 1262 power-domains = <&rpmhpd RPMHPD_CX>; 1263 operating-points-v2 = <&qup_opp_table>; 1264 status = "disabled"; 1265 }; 1266 1267 i2c4: i2c@990000 { 1268 compatible = "qcom,geni-i2c"; 1269 reg = <0x0 0x990000 0x0 0x4000>; 1270 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1271 clock-names = "se"; 1272 pinctrl-0 = <&qup_i2c4_data_clk>; 1273 pinctrl-names = "default"; 1274 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1278 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1279 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1280 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1281 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1282 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1283 interconnect-names = "qup-core", 1284 "qup-config", 1285 "qup-memory"; 1286 power-domains = <&rpmhpd RPMHPD_CX>; 1287 required-opps = <&rpmhpd_opp_low_svs>; 1288 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1289 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1290 dma-names = "tx", 1291 "rx"; 1292 status = "disabled"; 1293 }; 1294 1295 spi4: spi@990000 { 1296 compatible = "qcom,geni-spi"; 1297 reg = <0x0 0x990000 0x0 0x4000>; 1298 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1299 clock-names = "se"; 1300 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1301 pinctrl-names = "default"; 1302 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1303 #address-cells = <1>; 1304 #size-cells = <0>; 1305 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1306 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1307 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1308 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1309 interconnect-names = "qup-core", 1310 "qup-config"; 1311 power-domains = <&rpmhpd RPMHPD_CX>; 1312 operating-points-v2 = <&qup_opp_table>; 1313 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1314 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1315 dma-names = "tx", 1316 "rx"; 1317 status = "disabled"; 1318 }; 1319 1320 uart4: serial@990000 { 1321 compatible = "qcom,geni-uart"; 1322 reg = <0x0 0x990000 0x0 0x4000>; 1323 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1324 clock-names = "se"; 1325 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, 1326 <&qup_uart4_tx>, <&qup_uart4_rx>; 1327 pinctrl-names = "default"; 1328 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1329 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1330 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1331 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1332 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1333 interconnect-names = "qup-core", 1334 "qup-config"; 1335 power-domains = <&rpmhpd RPMHPD_CX>; 1336 operating-points-v2 = <&qup_opp_table>; 1337 status = "disabled"; 1338 }; 1339 1340 i2c5: i2c@994000 { 1341 compatible = "qcom,geni-i2c"; 1342 reg = <0x0 0x994000 0x0 0x4000>; 1343 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1344 clock-names = "se"; 1345 pinctrl-0 = <&qup_i2c5_data_clk>; 1346 pinctrl-names = "default"; 1347 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1351 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1352 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1353 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1354 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1355 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1356 interconnect-names = "qup-core", 1357 "qup-config", 1358 "qup-memory"; 1359 power-domains = <&rpmhpd RPMHPD_CX>; 1360 required-opps = <&rpmhpd_opp_low_svs>; 1361 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1362 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1363 dma-names = "tx", 1364 "rx"; 1365 status = "disabled"; 1366 }; 1367 1368 spi5: spi@994000 { 1369 compatible = "qcom,geni-spi"; 1370 reg = <0x0 0x994000 0x0 0x4000>; 1371 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1372 clock-names = "se"; 1373 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1374 pinctrl-names = "default"; 1375 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1376 #address-cells = <1>; 1377 #size-cells = <0>; 1378 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1379 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1380 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1381 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1382 interconnect-names = "qup-core", 1383 "qup-config"; 1384 power-domains = <&rpmhpd RPMHPD_CX>; 1385 operating-points-v2 = <&qup_opp_table>; 1386 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1387 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1388 dma-names = "tx", 1389 "rx"; 1390 status = "disabled"; 1391 }; 1392 1393 uart5: serial@994000 { 1394 compatible = "qcom,geni-uart"; 1395 reg = <0x0 0x994000 0x0 0x4000>; 1396 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1397 clock-names = "se"; 1398 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, 1399 <&qup_uart5_tx>, <&qup_uart5_rx>; 1400 pinctrl-names = "default"; 1401 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1402 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1403 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1404 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1405 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1406 interconnect-names = "qup-core", 1407 "qup-config"; 1408 power-domains = <&rpmhpd RPMHPD_CX>; 1409 operating-points-v2 = <&qup_opp_table>; 1410 status = "disabled"; 1411 }; 1412 1413 i2c6: i2c@998000 { 1414 compatible = "qcom,geni-i2c"; 1415 reg = <0x0 0x998000 0x0 0x4000>; 1416 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1417 clock-names = "se"; 1418 pinctrl-0 = <&qup_i2c6_data_clk>; 1419 pinctrl-names = "default"; 1420 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1424 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1425 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1426 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1427 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1428 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1429 interconnect-names = "qup-core", 1430 "qup-config", 1431 "qup-memory"; 1432 power-domains = <&rpmhpd RPMHPD_CX>; 1433 required-opps = <&rpmhpd_opp_low_svs>; 1434 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1435 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1436 dma-names = "tx", 1437 "rx"; 1438 status = "disabled"; 1439 }; 1440 1441 spi6: spi@998000 { 1442 compatible = "qcom,geni-spi"; 1443 reg = <0x0 0x998000 0x0 0x4000>; 1444 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1445 clock-names = "se"; 1446 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1447 pinctrl-names = "default"; 1448 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1452 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1453 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1454 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1455 interconnect-names = "qup-core", 1456 "qup-config"; 1457 power-domains = <&rpmhpd RPMHPD_CX>; 1458 operating-points-v2 = <&qup_opp_table>; 1459 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1460 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1461 dma-names = "tx", 1462 "rx"; 1463 status = "disabled"; 1464 }; 1465 1466 uart6: serial@998000 { 1467 compatible = "qcom,geni-uart"; 1468 reg = <0x0 0x998000 0x0 0x4000>; 1469 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1470 clock-names = "se"; 1471 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, 1472 <&qup_uart6_tx>, <&qup_uart6_rx>; 1473 pinctrl-names = "default"; 1474 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1475 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1476 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1477 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1478 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1479 interconnect-names = "qup-core", 1480 "qup-config"; 1481 power-domains = <&rpmhpd RPMHPD_CX>; 1482 operating-points-v2 = <&qup_opp_table>; 1483 status = "disabled"; 1484 }; 1485 1486 uart7: serial@99c000 { 1487 compatible = "qcom,geni-debug-uart"; 1488 reg = <0x0 0x0099c000 0x0 0x4000>; 1489 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1490 clock-names = "se"; 1491 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1492 pinctrl-names = "default"; 1493 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1494 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1495 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1496 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1497 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1498 interconnect-names = "qup-core", 1499 "qup-config"; 1500 power-domains = <&rpmhpd RPMHPD_CX>; 1501 operating-points-v2 = <&qup_opp_table>; 1502 status = "disabled"; 1503 }; 1504 }; 1505 1506 gpi_dma1: dma-controller@a00000 { 1507 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 1508 reg = <0x0 0xa00000 0x0 0x60000>; 1509 #dma-cells = <3>; 1510 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1522 iommus = <&apps_smmu 0x456 0x0>; 1523 dma-channels = <12>; 1524 dma-channel-mask = <0xfff>; 1525 dma-coherent; 1526 status = "disabled"; 1527 }; 1528 1529 qupv3_id_1: geniqup@ac0000 { 1530 compatible = "qcom,geni-se-qup"; 1531 reg = <0x0 0xac0000 0x0 0x2000>; 1532 ranges; 1533 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1534 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1535 clock-names = "m-ahb", 1536 "s-ahb"; 1537 #address-cells = <2>; 1538 #size-cells = <2>; 1539 iommus = <&apps_smmu 0x443 0x0>; 1540 dma-coherent; 1541 status = "disabled"; 1542 1543 i2c8: i2c@a80000 { 1544 compatible = "qcom,geni-i2c"; 1545 reg = <0x0 0xa80000 0x0 0x4000>; 1546 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1547 clock-names = "se"; 1548 pinctrl-0 = <&qup_i2c8_data_clk>; 1549 pinctrl-names = "default"; 1550 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1551 #address-cells = <1>; 1552 #size-cells = <0>; 1553 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1554 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1555 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1556 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1557 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1558 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1559 interconnect-names = "qup-core", 1560 "qup-config", 1561 "qup-memory"; 1562 power-domains = <&rpmhpd RPMHPD_CX>; 1563 required-opps = <&rpmhpd_opp_low_svs>; 1564 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1565 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1566 dma-names = "tx", 1567 "rx"; 1568 status = "disabled"; 1569 }; 1570 1571 spi8: spi@a80000 { 1572 compatible = "qcom,geni-spi"; 1573 reg = <0x0 0xa80000 0x0 0x4000>; 1574 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1575 clock-names = "se"; 1576 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1577 pinctrl-names = "default"; 1578 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1579 #address-cells = <1>; 1580 #size-cells = <0>; 1581 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1582 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1583 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1584 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1585 interconnect-names = "qup-core", 1586 "qup-config"; 1587 power-domains = <&rpmhpd RPMHPD_CX>; 1588 operating-points-v2 = <&qup_opp_table>; 1589 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1590 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1591 dma-names = "tx", 1592 "rx"; 1593 status = "disabled"; 1594 }; 1595 1596 uart8: serial@a80000 { 1597 compatible = "qcom,geni-uart"; 1598 reg = <0x0 0xa80000 0x0 0x4000>; 1599 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1600 clock-names = "se"; 1601 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, 1602 <&qup_uart8_tx>, <&qup_uart8_rx>; 1603 pinctrl-names = "default"; 1604 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1605 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1606 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1607 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1608 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1609 interconnect-names = "qup-core", 1610 "qup-config"; 1611 power-domains = <&rpmhpd RPMHPD_CX>; 1612 operating-points-v2 = <&qup_opp_table>; 1613 status = "disabled"; 1614 }; 1615 1616 i2c9: i2c@a84000 { 1617 compatible = "qcom,geni-i2c"; 1618 reg = <0x0 0xa84000 0x0 0x4000>; 1619 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1620 clock-names = "se"; 1621 pinctrl-0 = <&qup_i2c9_data_clk>; 1622 pinctrl-names = "default"; 1623 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1624 #address-cells = <1>; 1625 #size-cells = <0>; 1626 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1627 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1628 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1629 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1630 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1631 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1632 interconnect-names = "qup-core", 1633 "qup-config", 1634 "qup-memory"; 1635 power-domains = <&rpmhpd RPMHPD_CX>; 1636 required-opps = <&rpmhpd_opp_low_svs>; 1637 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1638 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1639 dma-names = "tx", 1640 "rx"; 1641 status = "disabled"; 1642 }; 1643 1644 spi9: spi@a84000 { 1645 compatible = "qcom,geni-spi"; 1646 reg = <0x0 0xa84000 0x0 0x4000>; 1647 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1648 clock-names = "se"; 1649 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1650 pinctrl-names = "default"; 1651 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1652 #address-cells = <1>; 1653 #size-cells = <0>; 1654 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1655 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1656 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1657 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1658 interconnect-names = "qup-core", 1659 "qup-config"; 1660 power-domains = <&rpmhpd RPMHPD_CX>; 1661 operating-points-v2 = <&qup_opp_table>; 1662 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1663 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1664 dma-names = "tx", 1665 "rx"; 1666 status = "disabled"; 1667 }; 1668 1669 uart9: serial@a84000 { 1670 compatible = "qcom,geni-uart"; 1671 reg = <0x0 0xa84000 0x0 0x4000>; 1672 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1673 clock-names = "se"; 1674 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, 1675 <&qup_uart9_tx>, <&qup_uart9_rx>; 1676 pinctrl-names = "default"; 1677 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1678 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1679 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1680 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1681 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1682 interconnect-names = "qup-core", 1683 "qup-config"; 1684 power-domains = <&rpmhpd RPMHPD_CX>; 1685 operating-points-v2 = <&qup_opp_table>; 1686 status = "disabled"; 1687 }; 1688 1689 i2c10: i2c@a88000 { 1690 compatible = "qcom,geni-i2c"; 1691 reg = <0x0 0xa88000 0x0 0x4000>; 1692 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1693 clock-names = "se"; 1694 pinctrl-0 = <&qup_i2c10_data_clk>; 1695 pinctrl-names = "default"; 1696 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1697 #address-cells = <1>; 1698 #size-cells = <0>; 1699 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1700 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1701 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1702 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1703 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1704 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1705 interconnect-names = "qup-core", 1706 "qup-config", 1707 "qup-memory"; 1708 power-domains = <&rpmhpd RPMHPD_CX>; 1709 required-opps = <&rpmhpd_opp_low_svs>; 1710 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1711 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1712 dma-names = "tx", 1713 "rx"; 1714 status = "disabled"; 1715 }; 1716 1717 spi10: spi@a88000 { 1718 compatible = "qcom,geni-spi"; 1719 reg = <0x0 0xa88000 0x0 0x4000>; 1720 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1721 clock-names = "se"; 1722 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1723 pinctrl-names = "default"; 1724 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1725 #address-cells = <1>; 1726 #size-cells = <0>; 1727 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1728 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1729 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1730 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1731 interconnect-names = "qup-core", 1732 "qup-config"; 1733 power-domains = <&rpmhpd RPMHPD_CX>; 1734 operating-points-v2 = <&qup_opp_table>; 1735 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1736 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1737 dma-names = "tx", 1738 "rx"; 1739 status = "disabled"; 1740 }; 1741 1742 uart10: serial@a88000 { 1743 compatible = "qcom,geni-uart"; 1744 reg = <0x0 0xa88000 0x0 0x4000>; 1745 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1746 clock-names = "se"; 1747 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, 1748 <&qup_uart10_tx>, <&qup_uart10_rx>; 1749 pinctrl-names = "default"; 1750 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1751 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1752 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1753 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1754 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1755 interconnect-names = "qup-core", 1756 "qup-config"; 1757 power-domains = <&rpmhpd RPMHPD_CX>; 1758 operating-points-v2 = <&qup_opp_table>; 1759 status = "disabled"; 1760 }; 1761 1762 i2c11: i2c@a8c000 { 1763 compatible = "qcom,geni-i2c"; 1764 reg = <0x0 0xa8c000 0x0 0x4000>; 1765 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1766 clock-names = "se"; 1767 pinctrl-0 = <&qup_i2c11_data_clk>; 1768 pinctrl-names = "default"; 1769 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1770 #address-cells = <1>; 1771 #size-cells = <0>; 1772 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1773 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1774 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1775 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1776 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1777 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1778 interconnect-names = "qup-core", 1779 "qup-config", 1780 "qup-memory"; 1781 power-domains = <&rpmhpd RPMHPD_CX>; 1782 required-opps = <&rpmhpd_opp_low_svs>; 1783 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1784 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1785 dma-names = "tx", 1786 "rx"; 1787 status = "disabled"; 1788 }; 1789 1790 uart11: serial@a8c000 { 1791 compatible = "qcom,geni-uart"; 1792 reg = <0x0 0xa8c000 0x0 0x4000>; 1793 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1794 clock-names = "se"; 1795 pinctrl-0 = <&qup_uart11_tx>, <&qup_uart11_rx>; 1796 pinctrl-names = "default"; 1797 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1798 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1799 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1800 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1801 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1802 interconnect-names = "qup-core", 1803 "qup-config"; 1804 power-domains = <&rpmhpd RPMHPD_CX>; 1805 operating-points-v2 = <&qup_opp_table>; 1806 status = "disabled"; 1807 }; 1808 1809 i2c12: i2c@a90000 { 1810 compatible = "qcom,geni-i2c"; 1811 reg = <0x0 0xa90000 0x0 0x4000>; 1812 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1813 clock-names = "se"; 1814 pinctrl-0 = <&qup_i2c12_data_clk>; 1815 pinctrl-names = "default"; 1816 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1817 #address-cells = <1>; 1818 #size-cells = <0>; 1819 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1820 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1821 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1822 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1823 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1824 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1825 interconnect-names = "qup-core", 1826 "qup-config", 1827 "qup-memory"; 1828 power-domains = <&rpmhpd RPMHPD_CX>; 1829 required-opps = <&rpmhpd_opp_low_svs>; 1830 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1831 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1832 dma-names = "tx", 1833 "rx"; 1834 status = "disabled"; 1835 }; 1836 1837 spi12: spi@a90000 { 1838 compatible = "qcom,geni-spi"; 1839 reg = <0x0 0xa90000 0x0 0x4000>; 1840 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1841 clock-names = "se"; 1842 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1843 pinctrl-names = "default"; 1844 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1845 #address-cells = <1>; 1846 #size-cells = <0>; 1847 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1848 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1849 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1850 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1851 interconnect-names = "qup-core", 1852 "qup-config"; 1853 power-domains = <&rpmhpd RPMHPD_CX>; 1854 operating-points-v2 = <&qup_opp_table>; 1855 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1856 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1857 dma-names = "tx", 1858 "rx"; 1859 status = "disabled"; 1860 }; 1861 1862 uart12: serial@a90000 { 1863 compatible = "qcom,geni-uart"; 1864 reg = <0x0 0xa90000 0x0 0x4000>; 1865 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1866 clock-names = "se"; 1867 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, 1868 <&qup_uart12_tx>, <&qup_uart12_rx>; 1869 pinctrl-names = "default"; 1870 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1871 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1872 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1873 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1874 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1875 interconnect-names = "qup-core", 1876 "qup-config"; 1877 power-domains = <&rpmhpd RPMHPD_CX>; 1878 operating-points-v2 = <&qup_opp_table>; 1879 status = "disabled"; 1880 }; 1881 1882 i2c13: i2c@a94000 { 1883 compatible = "qcom,geni-i2c"; 1884 reg = <0x0 0xa94000 0x0 0x4000>; 1885 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1886 clock-names = "se"; 1887 pinctrl-0 = <&qup_i2c13_data_clk>; 1888 pinctrl-names = "default"; 1889 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1890 #address-cells = <1>; 1891 #size-cells = <0>; 1892 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1893 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1894 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1895 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1896 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1897 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1898 interconnect-names = "qup-core", 1899 "qup-config", 1900 "qup-memory"; 1901 power-domains = <&rpmhpd RPMHPD_CX>; 1902 required-opps = <&rpmhpd_opp_low_svs>; 1903 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1904 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1905 dma-names = "tx", 1906 "rx"; 1907 status = "disabled"; 1908 }; 1909 1910 spi13: spi@a94000 { 1911 compatible = "qcom,geni-spi"; 1912 reg = <0x0 0xa94000 0x0 0x4000>; 1913 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1914 clock-names = "se"; 1915 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1916 pinctrl-names = "default"; 1917 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1918 #address-cells = <1>; 1919 #size-cells = <0>; 1920 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1921 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1922 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1923 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1924 interconnect-names = "qup-core", 1925 "qup-config"; 1926 power-domains = <&rpmhpd RPMHPD_CX>; 1927 operating-points-v2 = <&qup_opp_table>; 1928 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1929 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1930 dma-names = "tx", 1931 "rx"; 1932 status = "disabled"; 1933 }; 1934 1935 uart13: serial@a94000 { 1936 compatible = "qcom,geni-uart"; 1937 reg = <0x0 0xa94000 0x0 0x4000>; 1938 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1939 clock-names = "se"; 1940 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, 1941 <&qup_uart13_tx>, <&qup_uart13_rx>; 1942 pinctrl-names = "default"; 1943 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1944 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1945 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1946 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1947 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1948 interconnect-names = "qup-core", 1949 "qup-config"; 1950 power-domains = <&rpmhpd RPMHPD_CX>; 1951 operating-points-v2 = <&qup_opp_table>; 1952 status = "disabled"; 1953 }; 1954 1955 i2c14: i2c@a98000 { 1956 compatible = "qcom,geni-i2c"; 1957 reg = <0x0 0xa98000 0x0 0x4000>; 1958 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1959 clock-names = "se"; 1960 pinctrl-0 = <&qup_i2c14_data_clk>; 1961 pinctrl-names = "default"; 1962 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1963 #address-cells = <1>; 1964 #size-cells = <0>; 1965 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1966 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1967 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1968 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1969 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1970 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1971 interconnect-names = "qup-core", 1972 "qup-config", 1973 "qup-memory"; 1974 power-domains = <&rpmhpd RPMHPD_CX>; 1975 required-opps = <&rpmhpd_opp_low_svs>; 1976 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1977 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1978 dma-names = "tx", 1979 "rx"; 1980 status = "disabled"; 1981 }; 1982 1983 spi14: spi@a98000 { 1984 compatible = "qcom,geni-spi"; 1985 reg = <0x0 0xa98000 0x0 0x4000>; 1986 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1987 clock-names = "se"; 1988 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1989 pinctrl-names = "default"; 1990 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1991 #address-cells = <1>; 1992 #size-cells = <0>; 1993 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1994 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1995 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1996 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1997 interconnect-names = "qup-core", 1998 "qup-config"; 1999 power-domains = <&rpmhpd RPMHPD_CX>; 2000 operating-points-v2 = <&qup_opp_table>; 2001 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2002 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2003 dma-names = "tx", 2004 "rx"; 2005 status = "disabled"; 2006 }; 2007 2008 uart14: serial@a98000 { 2009 compatible = "qcom,geni-uart"; 2010 reg = <0x0 0xa98000 0x0 0x4000>; 2011 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2012 clock-names = "se"; 2013 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, 2014 <&qup_uart14_tx>, <&qup_uart14_rx>; 2015 pinctrl-names = "default"; 2016 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2017 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2018 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2019 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2020 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2021 interconnect-names = "qup-core", 2022 "qup-config"; 2023 power-domains = <&rpmhpd RPMHPD_CX>; 2024 operating-points-v2 = <&qup_opp_table>; 2025 status = "disabled"; 2026 }; 2027 2028 i2c15: i2c@a9c000 { 2029 compatible = "qcom,geni-i2c"; 2030 reg = <0x0 0xa9c000 0x0 0x4000>; 2031 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2032 clock-names = "se"; 2033 pinctrl-0 = <&qup_i2c15_data_clk>; 2034 pinctrl-names = "default"; 2035 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2036 #address-cells = <1>; 2037 #size-cells = <0>; 2038 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2039 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2040 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2041 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2042 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2043 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2044 interconnect-names = "qup-core", 2045 "qup-config", 2046 "qup-memory"; 2047 power-domains = <&rpmhpd RPMHPD_CX>; 2048 required-opps = <&rpmhpd_opp_low_svs>; 2049 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2050 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2051 dma-names = "tx", 2052 "rx"; 2053 status = "disabled"; 2054 }; 2055 2056 spi15: spi@a9c000 { 2057 compatible = "qcom,geni-spi"; 2058 reg = <0x0 0xa9c000 0x0 0x4000>; 2059 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2060 clock-names = "se"; 2061 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2062 pinctrl-names = "default"; 2063 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2064 #address-cells = <1>; 2065 #size-cells = <0>; 2066 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2067 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2068 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2069 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2070 interconnect-names = "qup-core", 2071 "qup-config"; 2072 power-domains = <&rpmhpd RPMHPD_CX>; 2073 operating-points-v2 = <&qup_opp_table>; 2074 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2075 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2076 dma-names = "tx", 2077 "rx"; 2078 status = "disabled"; 2079 }; 2080 2081 uart15: serial@a9c000 { 2082 compatible = "qcom,geni-uart"; 2083 reg = <0x0 0xa9c000 0x0 0x4000>; 2084 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2085 clock-names = "se"; 2086 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, 2087 <&qup_uart15_tx>, <&qup_uart15_rx>; 2088 pinctrl-names = "default"; 2089 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2090 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2091 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2092 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2093 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2094 interconnect-names = "qup-core", 2095 "qup-config"; 2096 power-domains = <&rpmhpd RPMHPD_CX>; 2097 operating-points-v2 = <&qup_opp_table>; 2098 status = "disabled"; 2099 }; 2100 }; 2101 2102 gpi_dma3: dma-controller@b00000 { 2103 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 2104 reg = <0x0 0xb00000 0x0 0x60000>; 2105 #dma-cells = <3>; 2106 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>; 2110 iommus = <&apps_smmu 0x56 0x0>; 2111 dma-channels = <4>; 2112 dma-channel-mask = <0xf>; 2113 dma-coherent; 2114 status = "disabled"; 2115 }; 2116 2117 qupv3_id_3: geniqup@bc0000 { 2118 compatible = "qcom,geni-se-qup"; 2119 reg = <0x0 0xbc0000 0x0 0x2000>; 2120 ranges; 2121 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 2122 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 2123 clock-names = "m-ahb", 2124 "s-ahb"; 2125 #address-cells = <2>; 2126 #size-cells = <2>; 2127 iommus = <&apps_smmu 0x43 0x0>; 2128 dma-coherent; 2129 status = "disabled"; 2130 2131 i2c16: i2c@b80000 { 2132 compatible = "qcom,geni-i2c"; 2133 reg = <0x0 0xb80000 0x0 0x4000>; 2134 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2135 clock-names = "se"; 2136 pinctrl-0 = <&qup_i2c16_data_clk>; 2137 pinctrl-names = "default"; 2138 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2139 #address-cells = <1>; 2140 #size-cells = <0>; 2141 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2142 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2143 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2144 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2145 <&aggre2_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2146 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2147 interconnect-names = "qup-core", 2148 "qup-config", 2149 "qup-memory"; 2150 power-domains = <&rpmhpd RPMHPD_CX>; 2151 required-opps = <&rpmhpd_opp_low_svs>; 2152 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, 2153 <&gpi_dma3 1 0 QCOM_GPI_I2C>; 2154 dma-names = "tx", 2155 "rx"; 2156 status = "disabled"; 2157 }; 2158 2159 spi16: spi@b80000 { 2160 compatible = "qcom,geni-spi"; 2161 reg = <0x0 0xb80000 0x0 0x4000>; 2162 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2163 clock-names = "se"; 2164 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 2165 pinctrl-names = "default"; 2166 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2167 #address-cells = <1>; 2168 #size-cells = <0>; 2169 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2170 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2171 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2172 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2173 interconnect-names = "qup-core", 2174 "qup-config"; 2175 power-domains = <&rpmhpd RPMHPD_CX>; 2176 operating-points-v2 = <&qup_opp_table>; 2177 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, 2178 <&gpi_dma3 1 0 QCOM_GPI_SPI>; 2179 dma-names = "tx", 2180 "rx"; 2181 status = "disabled"; 2182 }; 2183 2184 uart16: serial@b80000 { 2185 compatible = "qcom,geni-uart"; 2186 reg = <0x0 0xb80000 0x0 0x4000>; 2187 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2188 clock-names = "se"; 2189 pinctrl-0 = <&qup_uart16_cts>, <&qup_uart16_rts>, 2190 <&qup_uart16_tx>, <&qup_uart16_rx>; 2191 pinctrl-names = "default"; 2192 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2193 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2194 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2195 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2196 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2197 interconnect-names = "qup-core", 2198 "qup-config"; 2199 power-domains = <&rpmhpd RPMHPD_CX>; 2200 operating-points-v2 = <&qup_opp_table>; 2201 status = "disabled"; 2202 }; 2203 }; 2204 2205 rng: rng@10d2000 { 2206 compatible = "qcom,qcs8300-trng", "qcom,trng"; 2207 reg = <0x0 0x010d2000 0x0 0x1000>; 2208 }; 2209 2210 config_noc: interconnect@14c0000 { 2211 compatible = "qcom,qcs8300-config-noc"; 2212 reg = <0x0 0x014c0000 0x0 0x13080>; 2213 #interconnect-cells = <2>; 2214 qcom,bcm-voters = <&apps_bcm_voter>; 2215 }; 2216 2217 system_noc: interconnect@1680000 { 2218 compatible = "qcom,qcs8300-system-noc"; 2219 reg = <0x0 0x01680000 0x0 0x15080>; 2220 #interconnect-cells = <2>; 2221 qcom,bcm-voters = <&apps_bcm_voter>; 2222 }; 2223 2224 aggre1_noc: interconnect@16c0000 { 2225 compatible = "qcom,qcs8300-aggre1-noc"; 2226 reg = <0x0 0x016c0000 0x0 0x17080>; 2227 #interconnect-cells = <2>; 2228 qcom,bcm-voters = <&apps_bcm_voter>; 2229 }; 2230 2231 aggre2_noc: interconnect@1700000 { 2232 compatible = "qcom,qcs8300-aggre2-noc"; 2233 reg = <0x0 0x01700000 0x0 0x1a080>; 2234 #interconnect-cells = <2>; 2235 qcom,bcm-voters = <&apps_bcm_voter>; 2236 }; 2237 2238 pcie_anoc: interconnect@1760000 { 2239 compatible = "qcom,qcs8300-pcie-anoc"; 2240 reg = <0x0 0x01760000 0x0 0xc080>; 2241 #interconnect-cells = <2>; 2242 qcom,bcm-voters = <&apps_bcm_voter>; 2243 }; 2244 2245 gpdsp_anoc: interconnect@1780000 { 2246 compatible = "qcom,qcs8300-gpdsp-anoc"; 2247 reg = <0x0 0x01780000 0x0 0xd080>; 2248 #interconnect-cells = <2>; 2249 qcom,bcm-voters = <&apps_bcm_voter>; 2250 }; 2251 2252 mmss_noc: interconnect@17a0000 { 2253 compatible = "qcom,qcs8300-mmss-noc"; 2254 reg = <0x0 0x017a0000 0x0 0x40000>; 2255 #interconnect-cells = <2>; 2256 qcom,bcm-voters = <&apps_bcm_voter>; 2257 }; 2258 2259 ufs_mem_hc: ufs@1d84000 { 2260 compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2261 reg = <0x0 0x01d84000 0x0 0x3000>; 2262 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2263 phys = <&ufs_mem_phy>; 2264 phy-names = "ufsphy"; 2265 lanes-per-direction = <2>; 2266 #reset-cells = <1>; 2267 resets = <&gcc GCC_UFS_PHY_BCR>; 2268 reset-names = "rst"; 2269 2270 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2271 required-opps = <&rpmhpd_opp_nom>; 2272 2273 iommus = <&apps_smmu 0x100 0x0>; 2274 dma-coherent; 2275 2276 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2277 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2278 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2279 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2280 interconnect-names = "ufs-ddr", 2281 "cpu-ufs"; 2282 2283 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2284 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2285 <&gcc GCC_UFS_PHY_AHB_CLK>, 2286 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2287 <&rpmhcc RPMH_CXO_CLK>, 2288 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2289 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2290 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2291 clock-names = "core_clk", 2292 "bus_aggr_clk", 2293 "iface_clk", 2294 "core_clk_unipro", 2295 "ref_clk", 2296 "tx_lane0_sync_clk", 2297 "rx_lane0_sync_clk", 2298 "rx_lane1_sync_clk"; 2299 freq-table-hz = <75000000 300000000>, 2300 <0 0>, 2301 <0 0>, 2302 <75000000 300000000>, 2303 <0 0>, 2304 <0 0>, 2305 <0 0>, 2306 <0 0>; 2307 qcom,ice = <&ice>; 2308 status = "disabled"; 2309 }; 2310 2311 ufs_mem_phy: phy@1d87000 { 2312 compatible = "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy"; 2313 reg = <0x0 0x01d87000 0x0 0xe10>; 2314 /* 2315 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 2316 * enables the CXO clock to eDP *and* UFS PHY. 2317 */ 2318 clocks = <&rpmhcc RPMH_CXO_CLK>, 2319 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2320 <&gcc GCC_EDP_REF_CLKREF_EN>; 2321 clock-names = "ref", 2322 "ref_aux", 2323 "qref"; 2324 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2325 2326 resets = <&ufs_mem_hc 0>; 2327 reset-names = "ufsphy"; 2328 2329 #phy-cells = <0>; 2330 status = "disabled"; 2331 }; 2332 2333 cryptobam: dma-controller@1dc4000 { 2334 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2335 reg = <0x0 0x01dc4000 0x0 0x28000>; 2336 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2337 #dma-cells = <1>; 2338 qcom,ee = <0>; 2339 qcom,controlled-remotely; 2340 num-channels = <20>; 2341 qcom,num-ees = <4>; 2342 iommus = <&apps_smmu 0x480 0x00>, 2343 <&apps_smmu 0x481 0x00>; 2344 }; 2345 2346 ice: crypto@1d88000 { 2347 compatible = "qcom,qcs8300-inline-crypto-engine", 2348 "qcom,inline-crypto-engine"; 2349 reg = <0x0 0x01d88000 0x0 0x18000>; 2350 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2351 }; 2352 2353 tcsr_mutex: hwlock@1f40000 { 2354 compatible = "qcom,tcsr-mutex"; 2355 reg = <0x0 0x01f40000 0x0 0x20000>; 2356 #hwlock-cells = <1>; 2357 }; 2358 2359 tcsr: syscon@1fc0000 { 2360 compatible = "qcom,qcs8300-tcsr", "syscon"; 2361 reg = <0x0 0x1fc0000 0x0 0x30000>; 2362 }; 2363 2364 remoteproc_adsp: remoteproc@3000000 { 2365 compatible = "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas"; 2366 reg = <0x0 0x3000000 0x0 0x00100>; 2367 2368 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2369 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2370 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2371 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2372 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2373 interrupt-names = "wdog", 2374 "fatal", 2375 "ready", 2376 "handover", 2377 "stop-ack"; 2378 2379 clocks = <&rpmhcc RPMH_CXO_CLK>; 2380 clock-names = "xo"; 2381 2382 power-domains = <&rpmhpd RPMHPD_LCX>, 2383 <&rpmhpd RPMHPD_LMX>; 2384 power-domain-names = "lcx", 2385 "lmx"; 2386 2387 memory-region = <&adsp_mem>; 2388 2389 qcom,qmp = <&aoss_qmp>; 2390 2391 qcom,smem-states = <&smp2p_adsp_out 0>; 2392 qcom,smem-state-names = "stop"; 2393 2394 status = "disabled"; 2395 2396 remoteproc_adsp_glink: glink-edge { 2397 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2398 IPCC_MPROC_SIGNAL_GLINK_QMP 2399 IRQ_TYPE_EDGE_RISING>; 2400 mboxes = <&ipcc IPCC_CLIENT_LPASS 2401 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2402 2403 label = "lpass"; 2404 qcom,remote-pid = <2>; 2405 2406 fastrpc { 2407 compatible = "qcom,fastrpc"; 2408 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2409 label = "adsp"; 2410 memory-region = <&adsp_rpc_remote_heap_mem>; 2411 qcom,vmids = <QCOM_SCM_VMID_LPASS 2412 QCOM_SCM_VMID_ADSP_HEAP>; 2413 #address-cells = <1>; 2414 #size-cells = <0>; 2415 2416 compute-cb@3 { 2417 compatible = "qcom,fastrpc-compute-cb"; 2418 reg = <3>; 2419 iommus = <&apps_smmu 0x2003 0x0>; 2420 dma-coherent; 2421 }; 2422 2423 compute-cb@4 { 2424 compatible = "qcom,fastrpc-compute-cb"; 2425 reg = <4>; 2426 iommus = <&apps_smmu 0x2004 0x0>; 2427 dma-coherent; 2428 }; 2429 2430 compute-cb@5 { 2431 compatible = "qcom,fastrpc-compute-cb"; 2432 reg = <5>; 2433 iommus = <&apps_smmu 0x2005 0x0>; 2434 dma-coherent; 2435 }; 2436 }; 2437 2438 gpr { 2439 compatible = "qcom,gpr"; 2440 qcom,glink-channels = "adsp_apps"; 2441 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2442 qcom,intents = <512 20>; 2443 #address-cells = <1>; 2444 #size-cells = <0>; 2445 2446 q6apm: service@1 { 2447 compatible = "qcom,q6apm"; 2448 reg = <GPR_APM_MODULE_IID>; 2449 #sound-dai-cells = <0>; 2450 qcom,protection-domain = "avs/audio", 2451 "msm/adsp/audio_pd"; 2452 2453 q6apmbedai: bedais { 2454 compatible = "qcom,q6apm-lpass-dais"; 2455 #sound-dai-cells = <1>; 2456 }; 2457 2458 q6apmdai: dais { 2459 compatible = "qcom,q6apm-dais"; 2460 iommus = <&apps_smmu 0x2001 0x0>; 2461 }; 2462 }; 2463 2464 q6prm: service@2 { 2465 compatible = "qcom,q6prm"; 2466 reg = <GPR_PRM_MODULE_IID>; 2467 qcom,protection-domain = "avs/audio", 2468 "msm/adsp/audio_pd"; 2469 2470 q6prmcc: clock-controller { 2471 compatible = "qcom,q6prm-lpass-clocks"; 2472 #clock-cells = <2>; 2473 }; 2474 }; 2475 }; 2476 }; 2477 }; 2478 2479 lpass_ag_noc: interconnect@3c40000 { 2480 compatible = "qcom,qcs8300-lpass-ag-noc"; 2481 reg = <0x0 0x03c40000 0x0 0x17200>; 2482 #interconnect-cells = <2>; 2483 qcom,bcm-voters = <&apps_bcm_voter>; 2484 }; 2485 2486 stm@4002000 { 2487 compatible = "arm,coresight-stm", "arm,primecell"; 2488 reg = <0x0 0x04002000 0x0 0x1000>, 2489 <0x0 0x16280000 0x0 0x180000>; 2490 reg-names = "stm-base", 2491 "stm-stimulus-base"; 2492 2493 clocks = <&aoss_qmp>; 2494 clock-names = "apb_pclk"; 2495 2496 out-ports { 2497 port { 2498 stm_out: endpoint { 2499 remote-endpoint = <&funnel0_in7>; 2500 }; 2501 }; 2502 }; 2503 }; 2504 2505 tpda@4004000 { 2506 compatible = "qcom,coresight-tpda", "arm,primecell"; 2507 reg = <0x0 0x04004000 0x0 0x1000>; 2508 2509 clocks = <&aoss_qmp>; 2510 clock-names = "apb_pclk"; 2511 2512 in-ports { 2513 #address-cells = <1>; 2514 #size-cells = <0>; 2515 2516 port@1 { 2517 reg = <1>; 2518 2519 qdss_tpda_in1: endpoint { 2520 remote-endpoint = <&qdss_tpdm1_out>; 2521 }; 2522 }; 2523 }; 2524 2525 out-ports { 2526 port { 2527 qdss_tpda_out: endpoint { 2528 remote-endpoint = <&funnel0_in6>; 2529 }; 2530 }; 2531 }; 2532 }; 2533 2534 tpdm@400f000 { 2535 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2536 reg = <0x0 0x0400f000 0x0 0x1000>; 2537 2538 clocks = <&aoss_qmp>; 2539 clock-names = "apb_pclk"; 2540 2541 qcom,cmb-element-bits = <32>; 2542 qcom,cmb-msrs-num = <32>; 2543 2544 out-ports { 2545 port { 2546 qdss_tpdm1_out: endpoint { 2547 remote-endpoint = <&qdss_tpda_in1>; 2548 }; 2549 }; 2550 }; 2551 }; 2552 2553 funnel@4041000 { 2554 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2555 reg = <0x0 0x04041000 0x0 0x1000>; 2556 2557 clocks = <&aoss_qmp>; 2558 clock-names = "apb_pclk"; 2559 2560 in-ports { 2561 #address-cells = <1>; 2562 #size-cells = <0>; 2563 2564 port@6 { 2565 reg = <6>; 2566 2567 funnel0_in6: endpoint { 2568 remote-endpoint = <&qdss_tpda_out>; 2569 }; 2570 }; 2571 2572 port@7 { 2573 reg = <7>; 2574 2575 funnel0_in7: endpoint { 2576 remote-endpoint = <&stm_out>; 2577 }; 2578 }; 2579 }; 2580 2581 out-ports { 2582 port { 2583 funnel0_out: endpoint { 2584 remote-endpoint = <&qdss_funnel_in0>; 2585 }; 2586 }; 2587 }; 2588 }; 2589 2590 funnel@4042000 { 2591 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2592 reg = <0x0 0x04042000 0x0 0x1000>; 2593 2594 clocks = <&aoss_qmp>; 2595 clock-names = "apb_pclk"; 2596 2597 in-ports { 2598 #address-cells = <1>; 2599 #size-cells = <0>; 2600 2601 port@4 { 2602 reg = <4>; 2603 2604 funnel1_in4: endpoint { 2605 remote-endpoint = <&apss_funnel1_out>; 2606 }; 2607 }; 2608 2609 port@5 { 2610 reg = <5>; 2611 2612 funnel1_in5: endpoint { 2613 remote-endpoint = <&dlct0_funnel_out>; 2614 }; 2615 }; 2616 2617 port@6 { 2618 reg = <6>; 2619 2620 funnel1_in6: endpoint { 2621 remote-endpoint = <&dlmm_funnel_out>; 2622 }; 2623 }; 2624 2625 port@7 { 2626 reg = <7>; 2627 2628 funnel1_in7: endpoint { 2629 remote-endpoint = <&dlst_ch_funnel_out>; 2630 }; 2631 }; 2632 }; 2633 2634 out-ports { 2635 port { 2636 funnel1_out: endpoint { 2637 remote-endpoint = <&qdss_funnel_in1>; 2638 }; 2639 }; 2640 }; 2641 }; 2642 2643 funnel@4045000 { 2644 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2645 reg = <0x0 0x04045000 0x0 0x1000>; 2646 2647 clocks = <&aoss_qmp>; 2648 clock-names = "apb_pclk"; 2649 2650 in-ports { 2651 #address-cells = <1>; 2652 #size-cells = <0>; 2653 2654 port@0 { 2655 reg = <0>; 2656 2657 qdss_funnel_in0: endpoint { 2658 remote-endpoint = <&funnel0_out>; 2659 }; 2660 }; 2661 2662 port@1 { 2663 reg = <1>; 2664 2665 qdss_funnel_in1: endpoint { 2666 remote-endpoint = <&funnel1_out>; 2667 }; 2668 }; 2669 }; 2670 2671 out-ports { 2672 port { 2673 qdss_funnel_out: endpoint { 2674 remote-endpoint = <&aoss_funnel_in7>; 2675 }; 2676 }; 2677 }; 2678 }; 2679 2680 tpdm@4841000 { 2681 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2682 reg = <0x0 0x04841000 0x0 0x1000>; 2683 2684 clocks = <&aoss_qmp>; 2685 clock-names = "apb_pclk"; 2686 2687 qcom,cmb-element-bits = <32>; 2688 qcom,cmb-msrs-num = <32>; 2689 2690 out-ports { 2691 port { 2692 prng_tpdm_out: endpoint { 2693 remote-endpoint = <&dlct0_tpda_in19>; 2694 }; 2695 }; 2696 }; 2697 }; 2698 2699 tpdm@4850000 { 2700 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2701 reg = <0x0 0x04850000 0x0 0x1000>; 2702 2703 clocks = <&aoss_qmp>; 2704 clock-names = "apb_pclk"; 2705 2706 qcom,cmb-element-bits = <64>; 2707 qcom,cmb-msrs-num = <32>; 2708 qcom,dsb-element-bits = <32>; 2709 qcom,dsb-msrs-num = <32>; 2710 2711 out-ports { 2712 port { 2713 pimem_tpdm_out: endpoint { 2714 remote-endpoint = <&dlct0_tpda_in25>; 2715 }; 2716 }; 2717 }; 2718 }; 2719 2720 tpdm@4860000 { 2721 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2722 reg = <0x0 0x04860000 0x0 0x1000>; 2723 2724 clocks = <&aoss_qmp>; 2725 clock-names = "apb_pclk"; 2726 2727 qcom,dsb-element-bits = <32>; 2728 qcom,dsb-msrs-num = <32>; 2729 2730 out-ports { 2731 port { 2732 dlst_ch_tpdm0_out: endpoint { 2733 remote-endpoint = <&dlst_ch_tpda_in8>; 2734 }; 2735 }; 2736 }; 2737 }; 2738 2739 tpda@4864000 { 2740 compatible = "qcom,coresight-tpda", "arm,primecell"; 2741 reg = <0x0 0x04864000 0x0 0x1000>; 2742 2743 clocks = <&aoss_qmp>; 2744 clock-names = "apb_pclk"; 2745 2746 in-ports { 2747 #address-cells = <1>; 2748 #size-cells = <0>; 2749 2750 port@8 { 2751 reg = <8>; 2752 2753 dlst_ch_tpda_in8: endpoint { 2754 remote-endpoint = <&dlst_ch_tpdm0_out>; 2755 }; 2756 }; 2757 }; 2758 2759 out-ports { 2760 port { 2761 dlst_ch_tpda_out: endpoint { 2762 remote-endpoint = <&dlst_ch_funnel_in0>; 2763 }; 2764 }; 2765 }; 2766 }; 2767 2768 funnel@4865000 { 2769 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2770 reg = <0x0 0x04865000 0x0 0x1000>; 2771 2772 clocks = <&aoss_qmp>; 2773 clock-names = "apb_pclk"; 2774 2775 in-ports { 2776 #address-cells = <1>; 2777 #size-cells = <0>; 2778 2779 port@0 { 2780 reg = <0>; 2781 2782 dlst_ch_funnel_in0: endpoint { 2783 remote-endpoint = <&dlst_ch_tpda_out>; 2784 }; 2785 }; 2786 2787 port@4 { 2788 reg = <4>; 2789 2790 dlst_ch_funnel_in4: endpoint { 2791 remote-endpoint = <&dlst_funnel_out>; 2792 }; 2793 }; 2794 2795 port@6 { 2796 reg = <6>; 2797 2798 dlst_ch_funnel_in6: endpoint { 2799 remote-endpoint = <&gdsp_funnel_out>; 2800 }; 2801 }; 2802 }; 2803 2804 out-ports { 2805 port { 2806 dlst_ch_funnel_out: endpoint { 2807 remote-endpoint = <&funnel1_in7>; 2808 }; 2809 }; 2810 }; 2811 }; 2812 2813 tpdm@4980000 { 2814 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2815 reg = <0x0 0x04980000 0x0 0x1000>; 2816 2817 clocks = <&aoss_qmp>; 2818 clock-names = "apb_pclk"; 2819 2820 qcom,dsb-element-bits = <32>; 2821 qcom,dsb-msrs-num = <32>; 2822 2823 out-ports { 2824 port { 2825 turing2_tpdm_out: endpoint { 2826 remote-endpoint = <&turing2_funnel_in0>; 2827 }; 2828 }; 2829 }; 2830 }; 2831 2832 funnel@4983000 { 2833 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2834 reg = <0x0 0x04983000 0x0 0x1000>; 2835 2836 clocks = <&aoss_qmp>; 2837 clock-names = "apb_pclk"; 2838 2839 in-ports { 2840 port { 2841 turing2_funnel_in0: endpoint { 2842 remote-endpoint = <&turing2_tpdm_out>; 2843 }; 2844 }; 2845 }; 2846 2847 out-ports { 2848 port { 2849 turing2_funnel_out0: endpoint { 2850 remote-endpoint = <&gdsp_tpda_in5>; 2851 }; 2852 }; 2853 }; 2854 }; 2855 2856 tpdm@4ac0000 { 2857 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2858 reg = <0x0 0x04ac0000 0x0 0x1000>; 2859 2860 clocks = <&aoss_qmp>; 2861 clock-names = "apb_pclk"; 2862 2863 qcom,dsb-element-bits = <32>; 2864 qcom,dsb-msrs-num = <32>; 2865 2866 out-ports { 2867 port { 2868 dlmm_tpdm0_out: endpoint { 2869 remote-endpoint = <&dlmm_tpda_in27>; 2870 }; 2871 }; 2872 }; 2873 }; 2874 2875 tpda@4ac4000 { 2876 compatible = "qcom,coresight-tpda", "arm,primecell"; 2877 reg = <0x0 0x04ac4000 0x0 0x1000>; 2878 2879 clocks = <&aoss_qmp>; 2880 clock-names = "apb_pclk"; 2881 2882 in-ports { 2883 #address-cells = <1>; 2884 #size-cells = <0>; 2885 2886 port@1b { 2887 reg = <27>; 2888 2889 dlmm_tpda_in27: endpoint { 2890 remote-endpoint = <&dlmm_tpdm0_out>; 2891 }; 2892 }; 2893 }; 2894 2895 out-ports { 2896 port { 2897 dlmm_tpda_out: endpoint { 2898 remote-endpoint = <&dlmm_funnel_in0>; 2899 }; 2900 }; 2901 }; 2902 }; 2903 2904 funnel@4ac5000 { 2905 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2906 reg = <0x0 0x04ac5000 0x0 0x1000>; 2907 2908 clocks = <&aoss_qmp>; 2909 clock-names = "apb_pclk"; 2910 2911 in-ports { 2912 port { 2913 dlmm_funnel_in0: endpoint { 2914 remote-endpoint = <&dlmm_tpda_out>; 2915 }; 2916 }; 2917 }; 2918 2919 out-ports { 2920 port { 2921 dlmm_funnel_out: endpoint { 2922 remote-endpoint = <&funnel1_in6>; 2923 }; 2924 }; 2925 }; 2926 }; 2927 2928 tpdm@4ad0000 { 2929 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2930 reg = <0x0 0x04ad0000 0x0 0x1000>; 2931 2932 clocks = <&aoss_qmp>; 2933 clock-names = "apb_pclk"; 2934 2935 qcom,dsb-element-bits = <32>; 2936 qcom,dsb-msrs-num = <32>; 2937 2938 out-ports { 2939 port { 2940 dlct0_tpdm0_out: endpoint { 2941 remote-endpoint = <&dlct0_tpda_in26>; 2942 }; 2943 }; 2944 }; 2945 }; 2946 2947 tpda@4ad3000 { 2948 compatible = "qcom,coresight-tpda", "arm,primecell"; 2949 reg = <0x0 0x04ad3000 0x0 0x1000>; 2950 2951 clocks = <&aoss_qmp>; 2952 clock-names = "apb_pclk"; 2953 2954 in-ports { 2955 #address-cells = <1>; 2956 #size-cells = <0>; 2957 2958 port@13 { 2959 reg = <19>; 2960 2961 dlct0_tpda_in19: endpoint { 2962 remote-endpoint = <&prng_tpdm_out>; 2963 }; 2964 }; 2965 2966 port@19 { 2967 reg = <25>; 2968 2969 dlct0_tpda_in25: endpoint { 2970 remote-endpoint = <&pimem_tpdm_out>; 2971 }; 2972 }; 2973 2974 port@1a { 2975 reg = <26>; 2976 2977 dlct0_tpda_in26: endpoint { 2978 remote-endpoint = <&dlct0_tpdm0_out>; 2979 }; 2980 }; 2981 }; 2982 2983 out-ports { 2984 port { 2985 dlct0_tpda_out: endpoint { 2986 remote-endpoint = <&dlct0_funnel_in0>; 2987 }; 2988 }; 2989 }; 2990 }; 2991 2992 funnel@4ad4000 { 2993 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2994 reg = <0x0 0x04ad4000 0x0 0x1000>; 2995 2996 clocks = <&aoss_qmp>; 2997 clock-names = "apb_pclk"; 2998 2999 in-ports { 3000 #address-cells = <1>; 3001 #size-cells = <0>; 3002 3003 port@0 { 3004 reg = <0>; 3005 3006 dlct0_funnel_in0: endpoint { 3007 remote-endpoint = <&dlct0_tpda_out>; 3008 }; 3009 }; 3010 3011 port@4 { 3012 reg = <4>; 3013 3014 dlct0_funnel_in4: endpoint { 3015 remote-endpoint = <&ddr_funnel5_out>; 3016 }; 3017 }; 3018 }; 3019 3020 out-ports { 3021 port { 3022 dlct0_funnel_out: endpoint { 3023 remote-endpoint = <&funnel1_in5>; 3024 }; 3025 }; 3026 }; 3027 }; 3028 3029 funnel@4b04000 { 3030 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3031 reg = <0x0 0x04b04000 0x0 0x1000>; 3032 3033 clocks = <&aoss_qmp>; 3034 clock-names = "apb_pclk"; 3035 3036 in-ports { 3037 #address-cells = <1>; 3038 #size-cells = <0>; 3039 3040 port@6 { 3041 reg = <6>; 3042 3043 aoss_funnel_in6: endpoint { 3044 remote-endpoint = <&aoss_tpda_out>; 3045 }; 3046 }; 3047 3048 port@7 { 3049 reg = <7>; 3050 3051 aoss_funnel_in7: endpoint { 3052 remote-endpoint = <&qdss_funnel_out>; 3053 }; 3054 }; 3055 }; 3056 3057 out-ports { 3058 port { 3059 aoss_funnel_out: endpoint { 3060 remote-endpoint = <&etf0_in>; 3061 }; 3062 }; 3063 }; 3064 }; 3065 3066 tmc_etf: tmc@4b05000 { 3067 compatible = "arm,coresight-tmc", "arm,primecell"; 3068 reg = <0x0 0x04b05000 0x0 0x1000>; 3069 3070 clocks = <&aoss_qmp>; 3071 clock-names = "apb_pclk"; 3072 3073 in-ports { 3074 port { 3075 etf0_in: endpoint { 3076 remote-endpoint = <&aoss_funnel_out>; 3077 }; 3078 }; 3079 }; 3080 3081 out-ports { 3082 port { 3083 etf0_out: endpoint { 3084 remote-endpoint = <&swao_rep_in>; 3085 }; 3086 }; 3087 }; 3088 }; 3089 3090 replicator@4b06000 { 3091 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3092 reg = <0x0 0x04b06000 0x0 0x1000>; 3093 3094 clocks = <&aoss_qmp>; 3095 clock-names = "apb_pclk"; 3096 3097 in-ports { 3098 port { 3099 swao_rep_in: endpoint { 3100 remote-endpoint = <&etf0_out>; 3101 }; 3102 }; 3103 }; 3104 3105 out-ports { 3106 #address-cells = <1>; 3107 #size-cells = <0>; 3108 3109 port@1 { 3110 reg = <1>; 3111 3112 swao_rep_out1: endpoint { 3113 remote-endpoint = <&eud_in>; 3114 }; 3115 }; 3116 }; 3117 }; 3118 3119 tpda@4b08000 { 3120 compatible = "qcom,coresight-tpda", "arm,primecell"; 3121 reg = <0x0 0x04b08000 0x0 0x1000>; 3122 3123 clocks = <&aoss_qmp>; 3124 clock-names = "apb_pclk"; 3125 3126 in-ports { 3127 #address-cells = <1>; 3128 #size-cells = <0>; 3129 3130 port@0 { 3131 reg = <0>; 3132 3133 aoss_tpda_in0: endpoint { 3134 remote-endpoint = <&aoss_tpdm0_out>; 3135 }; 3136 }; 3137 3138 port@1 { 3139 reg = <1>; 3140 3141 aoss_tpda_in1: endpoint { 3142 remote-endpoint = <&aoss_tpdm1_out>; 3143 }; 3144 }; 3145 3146 port@2 { 3147 reg = <2>; 3148 3149 aoss_tpda_in2: endpoint { 3150 remote-endpoint = <&aoss_tpdm2_out>; 3151 }; 3152 }; 3153 3154 port@3 { 3155 reg = <3>; 3156 3157 aoss_tpda_in3: endpoint { 3158 remote-endpoint = <&aoss_tpdm3_out>; 3159 }; 3160 }; 3161 3162 port@4 { 3163 reg = <4>; 3164 3165 aoss_tpda_in4: endpoint { 3166 remote-endpoint = <&aoss_tpdm4_out>; 3167 }; 3168 }; 3169 }; 3170 3171 out-ports { 3172 port { 3173 aoss_tpda_out: endpoint { 3174 remote-endpoint = <&aoss_funnel_in6>; 3175 }; 3176 }; 3177 }; 3178 }; 3179 3180 tpdm@4b09000 { 3181 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3182 reg = <0x0 0x04b09000 0x0 0x1000>; 3183 3184 clocks = <&aoss_qmp>; 3185 clock-names = "apb_pclk"; 3186 3187 qcom,cmb-element-bits = <64>; 3188 qcom,cmb-msrs-num = <32>; 3189 3190 out-ports { 3191 port { 3192 aoss_tpdm0_out: endpoint { 3193 remote-endpoint = <&aoss_tpda_in0>; 3194 }; 3195 }; 3196 }; 3197 }; 3198 3199 tpdm@4b0a000 { 3200 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3201 reg = <0x0 0x04b0a000 0x0 0x1000>; 3202 3203 clocks = <&aoss_qmp>; 3204 clock-names = "apb_pclk"; 3205 3206 qcom,cmb-element-bits = <64>; 3207 qcom,cmb-msrs-num = <32>; 3208 3209 out-ports { 3210 port { 3211 aoss_tpdm1_out: endpoint { 3212 remote-endpoint = <&aoss_tpda_in1>; 3213 }; 3214 }; 3215 }; 3216 }; 3217 3218 tpdm@4b0b000 { 3219 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3220 reg = <0x0 0x04b0b000 0x0 0x1000>; 3221 3222 clocks = <&aoss_qmp>; 3223 clock-names = "apb_pclk"; 3224 3225 qcom,cmb-element-bits = <64>; 3226 qcom,cmb-msrs-num = <32>; 3227 3228 out-ports { 3229 port { 3230 aoss_tpdm2_out: endpoint { 3231 remote-endpoint = <&aoss_tpda_in2>; 3232 }; 3233 }; 3234 }; 3235 }; 3236 3237 tpdm@4b0c000 { 3238 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3239 reg = <0x0 0x04b0c000 0x0 0x1000>; 3240 3241 clocks = <&aoss_qmp>; 3242 clock-names = "apb_pclk"; 3243 3244 qcom,cmb-element-bits = <64>; 3245 qcom,cmb-msrs-num = <32>; 3246 3247 out-ports { 3248 port { 3249 aoss_tpdm3_out: endpoint { 3250 remote-endpoint = <&aoss_tpda_in3>; 3251 }; 3252 }; 3253 }; 3254 }; 3255 3256 tpdm@4b0d000 { 3257 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3258 reg = <0x0 0x04b0d000 0x0 0x1000>; 3259 3260 clocks = <&aoss_qmp>; 3261 clock-names = "apb_pclk"; 3262 3263 qcom,dsb-element-bits = <32>; 3264 qcom,dsb-msrs-num = <32>; 3265 3266 out-ports { 3267 port { 3268 aoss_tpdm4_out: endpoint { 3269 remote-endpoint = <&aoss_tpda_in4>; 3270 }; 3271 }; 3272 }; 3273 }; 3274 3275 cti@4b13000 { 3276 compatible = "arm,coresight-cti", "arm,primecell"; 3277 reg = <0x0 0x04b13000 0x0 0x1000>; 3278 3279 clocks = <&aoss_qmp>; 3280 clock-names = "apb_pclk"; 3281 }; 3282 3283 tpdm@4b80000 { 3284 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3285 reg = <0x0 0x04b80000 0x0 0x1000>; 3286 3287 clocks = <&aoss_qmp>; 3288 clock-names = "apb_pclk"; 3289 3290 qcom,dsb-element-bits = <32>; 3291 qcom,dsb-msrs-num = <32>; 3292 3293 out-ports { 3294 port { 3295 turing0_tpdm0_out: endpoint { 3296 remote-endpoint = <&turing0_tpda_in0>; 3297 }; 3298 }; 3299 }; 3300 }; 3301 3302 tpda@4b86000 { 3303 compatible = "qcom,coresight-tpda", "arm,primecell"; 3304 reg = <0x0 0x04b86000 0x0 0x1000>; 3305 3306 clocks = <&aoss_qmp>; 3307 clock-names = "apb_pclk"; 3308 3309 in-ports { 3310 port { 3311 turing0_tpda_in0: endpoint { 3312 remote-endpoint = <&turing0_tpdm0_out>; 3313 }; 3314 }; 3315 }; 3316 3317 out-ports { 3318 port { 3319 turing0_tpda_out: endpoint { 3320 remote-endpoint = <&turing0_funnel_in0>; 3321 }; 3322 }; 3323 }; 3324 }; 3325 3326 funnel@4b87000 { 3327 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3328 reg = <0x0 0x04b87000 0x0 0x1000>; 3329 3330 clocks = <&aoss_qmp>; 3331 clock-names = "apb_pclk"; 3332 3333 in-ports { 3334 port { 3335 turing0_funnel_in0: endpoint { 3336 remote-endpoint = <&turing0_tpda_out>; 3337 }; 3338 }; 3339 }; 3340 3341 out-ports { 3342 port { 3343 turing0_funnel_out: endpoint { 3344 remote-endpoint = <&gdsp_funnel_in4>; 3345 }; 3346 }; 3347 }; 3348 }; 3349 3350 cti@4b8b000 { 3351 compatible = "arm,coresight-cti", "arm,primecell"; 3352 reg = <0x0 0x04b8b000 0x0 0x1000>; 3353 3354 clocks = <&aoss_qmp>; 3355 clock-names = "apb_pclk"; 3356 }; 3357 3358 tpdm@4c40000 { 3359 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3360 reg = <0x0 0x04c40000 0x0 0x1000>; 3361 3362 clocks = <&aoss_qmp>; 3363 clock-names = "apb_pclk"; 3364 3365 qcom,dsb-element-bits = <32>; 3366 qcom,dsb-msrs-num = <32>; 3367 3368 out-ports { 3369 port { 3370 gdsp_tpdm0_out: endpoint { 3371 remote-endpoint = <&gdsp_tpda_in8>; 3372 }; 3373 }; 3374 }; 3375 }; 3376 3377 tpda@4c44000 { 3378 compatible = "qcom,coresight-tpda", "arm,primecell"; 3379 reg = <0x0 0x04c44000 0x0 0x1000>; 3380 3381 clocks = <&aoss_qmp>; 3382 clock-names = "apb_pclk"; 3383 3384 in-ports { 3385 #address-cells = <1>; 3386 #size-cells = <0>; 3387 3388 port@5 { 3389 reg = <5>; 3390 3391 gdsp_tpda_in5: endpoint { 3392 remote-endpoint = <&turing2_funnel_out0>; 3393 }; 3394 }; 3395 3396 port@8 { 3397 reg = <8>; 3398 3399 gdsp_tpda_in8: endpoint { 3400 remote-endpoint = <&gdsp_tpdm0_out>; 3401 }; 3402 }; 3403 }; 3404 3405 out-ports { 3406 port { 3407 gdsp_tpda_out: endpoint { 3408 remote-endpoint = <&gdsp_funnel_in0>; 3409 }; 3410 }; 3411 }; 3412 }; 3413 3414 funnel@4c45000 { 3415 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3416 reg = <0x0 0x04c45000 0x0 0x1000>; 3417 3418 clocks = <&aoss_qmp>; 3419 clock-names = "apb_pclk"; 3420 3421 in-ports { 3422 #address-cells = <1>; 3423 #size-cells = <0>; 3424 3425 port@0 { 3426 reg = <0>; 3427 3428 gdsp_funnel_in0: endpoint { 3429 remote-endpoint = <&gdsp_tpda_out>; 3430 }; 3431 }; 3432 3433 port@4 { 3434 reg = <4>; 3435 3436 gdsp_funnel_in4: endpoint { 3437 remote-endpoint = <&turing0_funnel_out>; 3438 }; 3439 }; 3440 }; 3441 3442 out-ports { 3443 port { 3444 gdsp_funnel_out: endpoint { 3445 remote-endpoint = <&dlst_ch_funnel_in6>; 3446 }; 3447 }; 3448 }; 3449 }; 3450 3451 tpdm@4c50000 { 3452 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3453 reg = <0x0 0x04c50000 0x0 0x1000>; 3454 3455 clocks = <&aoss_qmp>; 3456 clock-names = "apb_pclk"; 3457 3458 qcom,dsb-element-bits = <32>; 3459 qcom,dsb-msrs-num = <32>; 3460 3461 out-ports { 3462 port { 3463 dlst_tpdm0_out: endpoint { 3464 remote-endpoint = <&dlst_tpda_in8>; 3465 }; 3466 }; 3467 }; 3468 }; 3469 3470 tpda@4c54000 { 3471 compatible = "qcom,coresight-tpda", "arm,primecell"; 3472 reg = <0x0 0x04c54000 0x0 0x1000>; 3473 3474 clocks = <&aoss_qmp>; 3475 clock-names = "apb_pclk"; 3476 3477 in-ports { 3478 #address-cells = <1>; 3479 #size-cells = <0>; 3480 3481 port@8 { 3482 reg = <8>; 3483 3484 dlst_tpda_in8: endpoint { 3485 remote-endpoint = <&dlst_tpdm0_out>; 3486 }; 3487 }; 3488 }; 3489 3490 out-ports { 3491 port { 3492 dlst_tpda_out: endpoint { 3493 remote-endpoint = <&dlst_funnel_in0>; 3494 }; 3495 }; 3496 }; 3497 }; 3498 3499 funnel@4c55000 { 3500 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3501 reg = <0x0 0x04c55000 0x0 0x1000>; 3502 3503 clocks = <&aoss_qmp>; 3504 clock-names = "apb_pclk"; 3505 3506 in-ports { 3507 port { 3508 dlst_funnel_in0: endpoint { 3509 remote-endpoint = <&dlst_tpda_out>; 3510 }; 3511 }; 3512 }; 3513 3514 out-ports { 3515 port { 3516 dlst_funnel_out: endpoint { 3517 remote-endpoint = <&dlst_ch_funnel_in4>; 3518 }; 3519 }; 3520 }; 3521 }; 3522 3523 tpdm@4e00000 { 3524 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3525 reg = <0x0 0x04e00000 0x0 0x1000>; 3526 3527 clocks = <&aoss_qmp>; 3528 clock-names = "apb_pclk"; 3529 3530 qcom,dsb-element-bits = <32>; 3531 qcom,dsb-msrs-num = <32>; 3532 qcom,cmb-element-bits = <32>; 3533 qcom,cmb-msrs-num = <32>; 3534 3535 out-ports { 3536 port { 3537 ddr_tpdm3_out: endpoint { 3538 remote-endpoint = <&ddr_tpda_in4>; 3539 }; 3540 }; 3541 }; 3542 }; 3543 3544 tpda@4e03000 { 3545 compatible = "qcom,coresight-tpda", "arm,primecell"; 3546 reg = <0x0 0x04e03000 0x0 0x1000>; 3547 3548 clocks = <&aoss_qmp>; 3549 clock-names = "apb_pclk"; 3550 3551 in-ports { 3552 #address-cells = <1>; 3553 #size-cells = <0>; 3554 3555 port@0 { 3556 reg = <0>; 3557 3558 ddr_tpda_in0: endpoint { 3559 remote-endpoint = <&ddr_funnel0_out0>; 3560 }; 3561 }; 3562 3563 port@1 { 3564 reg = <1>; 3565 3566 ddr_tpda_in1: endpoint { 3567 remote-endpoint = <&ddr_funnel1_out0>; 3568 }; 3569 }; 3570 3571 port@4 { 3572 reg = <4>; 3573 3574 ddr_tpda_in4: endpoint { 3575 remote-endpoint = <&ddr_tpdm3_out>; 3576 }; 3577 }; 3578 }; 3579 3580 out-ports { 3581 port { 3582 ddr_tpda_out: endpoint { 3583 remote-endpoint = <&ddr_funnel5_in0>; 3584 }; 3585 }; 3586 }; 3587 }; 3588 3589 funnel@4e04000 { 3590 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3591 reg = <0x0 0x04e04000 0x0 0x1000>; 3592 3593 clocks = <&aoss_qmp>; 3594 clock-names = "apb_pclk"; 3595 3596 in-ports { 3597 port { 3598 ddr_funnel5_in0: endpoint { 3599 remote-endpoint = <&ddr_tpda_out>; 3600 }; 3601 }; 3602 }; 3603 3604 out-ports { 3605 port { 3606 ddr_funnel5_out: endpoint { 3607 remote-endpoint = <&dlct0_funnel_in4>; 3608 }; 3609 }; 3610 }; 3611 }; 3612 3613 tpdm@4e10000 { 3614 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3615 reg = <0x0 0x04e10000 0x0 0x1000>; 3616 3617 clocks = <&aoss_qmp>; 3618 clock-names = "apb_pclk"; 3619 3620 qcom,dsb-element-bits = <32>; 3621 qcom,dsb-msrs-num = <32>; 3622 3623 out-ports { 3624 port { 3625 ddr_tpdm0_out: endpoint { 3626 remote-endpoint = <&ddr_funnel0_in0>; 3627 }; 3628 }; 3629 }; 3630 }; 3631 3632 funnel@4e12000 { 3633 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3634 reg = <0x0 0x04e12000 0x0 0x1000>; 3635 3636 clocks = <&aoss_qmp>; 3637 clock-names = "apb_pclk"; 3638 3639 in-ports { 3640 port { 3641 ddr_funnel0_in0: endpoint { 3642 remote-endpoint = <&ddr_tpdm0_out>; 3643 }; 3644 }; 3645 }; 3646 3647 out-ports { 3648 port { 3649 ddr_funnel0_out0: endpoint { 3650 remote-endpoint = <&ddr_tpda_in0>; 3651 }; 3652 }; 3653 }; 3654 }; 3655 3656 tpdm@4e20000 { 3657 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3658 reg = <0x0 0x04e20000 0x0 0x1000>; 3659 3660 clocks = <&aoss_qmp>; 3661 clock-names = "apb_pclk"; 3662 3663 qcom,dsb-element-bits = <32>; 3664 qcom,dsb-msrs-num = <32>; 3665 3666 out-ports { 3667 port { 3668 ddr_tpdm1_out: endpoint { 3669 remote-endpoint = <&ddr_funnel1_in0>; 3670 }; 3671 }; 3672 }; 3673 }; 3674 3675 funnel@4e22000 { 3676 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3677 reg = <0x0 0x04e22000 0x0 0x1000>; 3678 3679 clocks = <&aoss_qmp>; 3680 clock-names = "apb_pclk"; 3681 3682 in-ports { 3683 port { 3684 ddr_funnel1_in0: endpoint { 3685 remote-endpoint = <&ddr_tpdm1_out>; 3686 }; 3687 }; 3688 }; 3689 3690 out-ports { 3691 port { 3692 ddr_funnel1_out0: endpoint { 3693 remote-endpoint = <&ddr_tpda_in1>; 3694 }; 3695 }; 3696 }; 3697 }; 3698 3699 etm@6040000 { 3700 compatible = "arm,primecell"; 3701 reg = <0x0 0x06040000 0x0 0x1000>; 3702 cpu = <&cpu0>; 3703 3704 clocks = <&aoss_qmp>; 3705 clock-names = "apb_pclk"; 3706 3707 arm,coresight-loses-context-with-cpu; 3708 qcom,skip-power-up; 3709 3710 out-ports { 3711 port { 3712 etm0_out: endpoint { 3713 remote-endpoint = <&apss_funnel0_in0>; 3714 }; 3715 }; 3716 }; 3717 }; 3718 3719 etm@6140000 { 3720 compatible = "arm,primecell"; 3721 reg = <0x0 0x06140000 0x0 0x1000>; 3722 cpu = <&cpu1>; 3723 3724 clocks = <&aoss_qmp>; 3725 clock-names = "apb_pclk"; 3726 3727 arm,coresight-loses-context-with-cpu; 3728 qcom,skip-power-up; 3729 3730 out-ports { 3731 port { 3732 etm1_out: endpoint { 3733 remote-endpoint = <&apss_funnel0_in1>; 3734 }; 3735 }; 3736 }; 3737 }; 3738 3739 etm@6240000 { 3740 compatible = "arm,primecell"; 3741 reg = <0x0 0x06240000 0x0 0x1000>; 3742 cpu = <&cpu2>; 3743 3744 clocks = <&aoss_qmp>; 3745 clock-names = "apb_pclk"; 3746 3747 arm,coresight-loses-context-with-cpu; 3748 qcom,skip-power-up; 3749 3750 out-ports { 3751 port { 3752 etm2_out: endpoint { 3753 remote-endpoint = <&apss_funnel0_in2>; 3754 }; 3755 }; 3756 }; 3757 }; 3758 3759 etm@6340000 { 3760 compatible = "arm,primecell"; 3761 reg = <0x0 0x06340000 0x0 0x1000>; 3762 cpu = <&cpu3>; 3763 3764 clocks = <&aoss_qmp>; 3765 clock-names = "apb_pclk"; 3766 3767 arm,coresight-loses-context-with-cpu; 3768 qcom,skip-power-up; 3769 3770 out-ports { 3771 port { 3772 etm3_out: endpoint { 3773 remote-endpoint = <&apss_funnel0_in3>; 3774 }; 3775 }; 3776 }; 3777 }; 3778 3779 etm@6440000 { 3780 compatible = "arm,primecell"; 3781 reg = <0x0 0x06440000 0x0 0x1000>; 3782 cpu = <&cpu4>; 3783 3784 clocks = <&aoss_qmp>; 3785 clock-names = "apb_pclk"; 3786 3787 arm,coresight-loses-context-with-cpu; 3788 qcom,skip-power-up; 3789 3790 out-ports { 3791 port { 3792 etm4_out: endpoint { 3793 remote-endpoint = <&apss_funnel0_in4>; 3794 }; 3795 }; 3796 }; 3797 }; 3798 3799 etm@6540000 { 3800 compatible = "arm,primecell"; 3801 reg = <0x0 0x06540000 0x0 0x1000>; 3802 cpu = <&cpu5>; 3803 3804 clocks = <&aoss_qmp>; 3805 clock-names = "apb_pclk"; 3806 3807 arm,coresight-loses-context-with-cpu; 3808 qcom,skip-power-up; 3809 3810 out-ports { 3811 port { 3812 etm5_out: endpoint { 3813 remote-endpoint = <&apss_funnel0_in5>; 3814 }; 3815 }; 3816 }; 3817 }; 3818 3819 etm@6640000 { 3820 compatible = "arm,primecell"; 3821 reg = <0x0 0x06640000 0x0 0x1000>; 3822 cpu = <&cpu6>; 3823 3824 clocks = <&aoss_qmp>; 3825 clock-names = "apb_pclk"; 3826 3827 arm,coresight-loses-context-with-cpu; 3828 qcom,skip-power-up; 3829 3830 out-ports { 3831 port { 3832 etm6_out: endpoint { 3833 remote-endpoint = <&apss_funnel0_in6>; 3834 }; 3835 }; 3836 }; 3837 }; 3838 3839 etm@6740000 { 3840 compatible = "arm,primecell"; 3841 reg = <0x0 0x06740000 0x0 0x1000>; 3842 cpu = <&cpu7>; 3843 3844 clocks = <&aoss_qmp>; 3845 clock-names = "apb_pclk"; 3846 3847 arm,coresight-loses-context-with-cpu; 3848 qcom,skip-power-up; 3849 3850 out-ports { 3851 port { 3852 etm7_out: endpoint { 3853 remote-endpoint = <&apss_funnel0_in7>; 3854 }; 3855 }; 3856 }; 3857 }; 3858 3859 funnel@6800000 { 3860 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3861 reg = <0x0 0x06800000 0x0 0x1000>; 3862 3863 clocks = <&aoss_qmp>; 3864 clock-names = "apb_pclk"; 3865 3866 in-ports { 3867 #address-cells = <1>; 3868 #size-cells = <0>; 3869 3870 port@0 { 3871 reg = <0>; 3872 3873 apss_funnel0_in0: endpoint { 3874 remote-endpoint = <&etm0_out>; 3875 }; 3876 }; 3877 3878 port@1 { 3879 reg = <1>; 3880 3881 apss_funnel0_in1: endpoint { 3882 remote-endpoint = <&etm1_out>; 3883 }; 3884 }; 3885 3886 port@2 { 3887 reg = <2>; 3888 3889 apss_funnel0_in2: endpoint { 3890 remote-endpoint = <&etm2_out>; 3891 }; 3892 }; 3893 3894 port@3 { 3895 reg = <3>; 3896 3897 apss_funnel0_in3: endpoint { 3898 remote-endpoint = <&etm3_out>; 3899 }; 3900 }; 3901 3902 port@4 { 3903 reg = <4>; 3904 3905 apss_funnel0_in4: endpoint { 3906 remote-endpoint = <&etm4_out>; 3907 }; 3908 }; 3909 3910 port@5 { 3911 reg = <5>; 3912 3913 apss_funnel0_in5: endpoint { 3914 remote-endpoint = <&etm5_out>; 3915 }; 3916 }; 3917 3918 port@6 { 3919 reg = <6>; 3920 3921 apss_funnel0_in6: endpoint { 3922 remote-endpoint = <&etm6_out>; 3923 }; 3924 }; 3925 3926 port@7 { 3927 reg = <7>; 3928 3929 apss_funnel0_in7: endpoint { 3930 remote-endpoint = <&etm7_out>; 3931 }; 3932 }; 3933 }; 3934 3935 out-ports { 3936 port { 3937 apss_funnel0_out: endpoint { 3938 remote-endpoint = <&apss_funnel1_in0>; 3939 }; 3940 }; 3941 }; 3942 }; 3943 3944 funnel@6810000 { 3945 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3946 reg = <0x0 0x06810000 0x0 0x1000>; 3947 3948 clocks = <&aoss_qmp>; 3949 clock-names = "apb_pclk"; 3950 3951 in-ports { 3952 #address-cells = <1>; 3953 #size-cells = <0>; 3954 3955 port@0 { 3956 reg = <0>; 3957 3958 apss_funnel1_in0: endpoint { 3959 remote-endpoint = <&apss_funnel0_out>; 3960 }; 3961 }; 3962 3963 port@3 { 3964 reg = <3>; 3965 3966 apss_funnel1_in3: endpoint { 3967 remote-endpoint = <&apss_tpda_out>; 3968 }; 3969 }; 3970 }; 3971 3972 out-ports { 3973 port { 3974 apss_funnel1_out: endpoint { 3975 remote-endpoint = <&funnel1_in4>; 3976 }; 3977 }; 3978 }; 3979 }; 3980 3981 cti@682b000 { 3982 compatible = "arm,coresight-cti", "arm,primecell"; 3983 reg = <0x0 0x0682b000 0x0 0x1000>; 3984 3985 clocks = <&aoss_qmp>; 3986 clock-names = "apb_pclk"; 3987 }; 3988 3989 tpdm@6860000 { 3990 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3991 reg = <0x0 0x06860000 0x0 0x1000>; 3992 3993 clocks = <&aoss_qmp>; 3994 clock-names = "apb_pclk"; 3995 3996 qcom,cmb-element-bits = <64>; 3997 qcom,cmb-msrs-num = <32>; 3998 3999 out-ports { 4000 port { 4001 apss_tpdm3_out: endpoint { 4002 remote-endpoint = <&apss_tpda_in3>; 4003 }; 4004 }; 4005 }; 4006 }; 4007 4008 tpdm@6861000 { 4009 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4010 reg = <0x0 0x06861000 0x0 0x1000>; 4011 4012 clocks = <&aoss_qmp>; 4013 clock-names = "apb_pclk"; 4014 4015 qcom,dsb-element-bits = <32>; 4016 qcom,dsb-msrs-num = <32>; 4017 4018 out-ports { 4019 port { 4020 apss_tpdm4_out: endpoint { 4021 remote-endpoint = <&apss_tpda_in4>; 4022 }; 4023 }; 4024 }; 4025 }; 4026 4027 tpda@6863000 { 4028 compatible = "qcom,coresight-tpda", "arm,primecell"; 4029 reg = <0x0 0x06863000 0x0 0x1000>; 4030 4031 clocks = <&aoss_qmp>; 4032 clock-names = "apb_pclk"; 4033 4034 in-ports { 4035 #address-cells = <1>; 4036 #size-cells = <0>; 4037 4038 port@0 { 4039 reg = <0>; 4040 4041 apss_tpda_in0: endpoint { 4042 remote-endpoint = <&apss_tpdm0_out>; 4043 }; 4044 }; 4045 4046 port@1 { 4047 reg = <1>; 4048 4049 apss_tpda_in1: endpoint { 4050 remote-endpoint = <&apss_tpdm1_out>; 4051 }; 4052 }; 4053 4054 port@2 { 4055 reg = <2>; 4056 4057 apss_tpda_in2: endpoint { 4058 remote-endpoint = <&apss_tpdm2_out>; 4059 }; 4060 }; 4061 4062 port@3 { 4063 reg = <3>; 4064 4065 apss_tpda_in3: endpoint { 4066 remote-endpoint = <&apss_tpdm3_out>; 4067 }; 4068 }; 4069 4070 port@4 { 4071 reg = <4>; 4072 4073 apss_tpda_in4: endpoint { 4074 remote-endpoint = <&apss_tpdm4_out>; 4075 }; 4076 }; 4077 }; 4078 4079 out-ports { 4080 port { 4081 apss_tpda_out: endpoint { 4082 remote-endpoint = <&apss_funnel1_in3>; 4083 }; 4084 }; 4085 }; 4086 }; 4087 4088 tpdm@68a0000 { 4089 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4090 reg = <0x0 0x068a0000 0x0 0x1000>; 4091 4092 clocks = <&aoss_qmp>; 4093 clock-names = "apb_pclk"; 4094 4095 qcom,cmb-element-bits = <32>; 4096 qcom,cmb-msrs-num = <32>; 4097 4098 out-ports { 4099 port { 4100 apss_tpdm1_out: endpoint { 4101 remote-endpoint = <&apss_tpda_in1>; 4102 }; 4103 }; 4104 }; 4105 }; 4106 4107 tpdm@68b0000 { 4108 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4109 reg = <0x0 0x068b0000 0x0 0x1000>; 4110 4111 clocks = <&aoss_qmp>; 4112 clock-names = "apb_pclk"; 4113 4114 qcom,cmb-element-bits = <32>; 4115 qcom,cmb-msrs-num = <32>; 4116 4117 out-ports { 4118 port { 4119 apss_tpdm0_out: endpoint { 4120 remote-endpoint = <&apss_tpda_in0>; 4121 }; 4122 }; 4123 }; 4124 }; 4125 4126 tpdm@68c0000 { 4127 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4128 reg = <0x0 0x068c0000 0x0 0x1000>; 4129 4130 clocks = <&aoss_qmp>; 4131 clock-names = "apb_pclk"; 4132 4133 qcom,dsb-element-bits = <32>; 4134 qcom,dsb-msrs-num = <32>; 4135 4136 out-ports { 4137 port { 4138 apss_tpdm2_out: endpoint { 4139 remote-endpoint = <&apss_tpda_in2>; 4140 }; 4141 }; 4142 }; 4143 }; 4144 4145 cti@68e0000 { 4146 compatible = "arm,coresight-cti", "arm,primecell"; 4147 reg = <0x0 0x068e0000 0x0 0x1000>; 4148 4149 clocks = <&aoss_qmp>; 4150 clock-names = "apb_pclk"; 4151 }; 4152 4153 cti@68f0000 { 4154 compatible = "arm,coresight-cti", "arm,primecell"; 4155 reg = <0x0 0x068f0000 0x0 0x1000>; 4156 4157 clocks = <&aoss_qmp>; 4158 clock-names = "apb_pclk"; 4159 }; 4160 4161 cti@6900000 { 4162 compatible = "arm,coresight-cti", "arm,primecell"; 4163 reg = <0x0 0x06900000 0x0 0x1000>; 4164 4165 clocks = <&aoss_qmp>; 4166 clock-names = "apb_pclk"; 4167 }; 4168 4169 sdhc_1: mmc@87c4000 { 4170 compatible = "qcom,qcs8300-sdhci", "qcom,sdhci-msm-v5"; 4171 reg = <0x0 0x087c4000 0x0 0x1000>, 4172 <0x0 0x087c5000 0x0 0x1000>; 4173 reg-names = "hc", 4174 "cqhci"; 4175 4176 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 4177 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>; 4178 interrupt-names = "hc_irq", 4179 "pwr_irq"; 4180 4181 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 4182 <&gcc GCC_SDCC1_APPS_CLK>, 4183 <&rpmhcc RPMH_CXO_CLK>; 4184 clock-names = "iface", 4185 "core", 4186 "xo"; 4187 4188 resets = <&gcc GCC_SDCC1_BCR>; 4189 4190 power-domains = <&rpmhpd RPMHPD_CX>; 4191 operating-points-v2 = <&sdhc1_opp_table>; 4192 iommus = <&apps_smmu 0x0 0x0>; 4193 interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS 4194 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4195 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4196 &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4197 interconnect-names = "sdhc-ddr", 4198 "cpu-sdhc"; 4199 4200 qcom,dll-config = <0x000f64ee>; 4201 qcom,ddr-config = <0x80040868>; 4202 supports-cqe; 4203 dma-coherent; 4204 4205 status = "disabled"; 4206 4207 sdhc1_opp_table: opp-table { 4208 compatible = "operating-points-v2"; 4209 4210 opp-50000000 { 4211 opp-hz = /bits/ 64 <50000000>; 4212 required-opps = <&rpmhpd_opp_low_svs>; 4213 }; 4214 4215 opp-100000000 { 4216 opp-hz = /bits/ 64 <100000000>; 4217 required-opps = <&rpmhpd_opp_svs>; 4218 }; 4219 4220 opp-200000000 { 4221 opp-hz = /bits/ 64 <200000000>; 4222 required-opps = <&rpmhpd_opp_svs_l1>; 4223 }; 4224 4225 opp-384000000 { 4226 opp-hz = /bits/ 64 <384000000>; 4227 required-opps = <&rpmhpd_opp_nom>; 4228 }; 4229 }; 4230 }; 4231 4232 usb_1_hsphy: phy@8904000 { 4233 compatible = "qcom,qcs8300-usb-hs-phy", 4234 "qcom,usb-snps-hs-7nm-phy"; 4235 reg = <0x0 0x08904000 0x0 0x400>; 4236 4237 clocks = <&rpmhcc RPMH_CXO_CLK>; 4238 clock-names = "ref"; 4239 4240 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 4241 4242 #phy-cells = <0>; 4243 4244 status = "disabled"; 4245 }; 4246 4247 usb_2_hsphy: phy@8906000 { 4248 compatible = "qcom,qcs8300-usb-hs-phy", 4249 "qcom,usb-snps-hs-7nm-phy"; 4250 reg = <0x0 0x08906000 0x0 0x400>; 4251 4252 clocks = <&rpmhcc RPMH_CXO_CLK>; 4253 clock-names = "ref"; 4254 4255 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 4256 4257 #phy-cells = <0>; 4258 4259 status = "disabled"; 4260 }; 4261 4262 usb_qmpphy: phy@8907000 { 4263 compatible = "qcom,qcs8300-qmp-usb3-uni-phy"; 4264 reg = <0x0 0x08907000 0x0 0x2000>; 4265 4266 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4267 <&gcc GCC_USB_CLKREF_EN>, 4268 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4269 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4270 clock-names = "aux", 4271 "ref", 4272 "com_aux", 4273 "pipe"; 4274 4275 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4276 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 4277 reset-names = "phy", "phy_phy"; 4278 4279 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4280 4281 #clock-cells = <0>; 4282 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 4283 4284 #phy-cells = <0>; 4285 4286 status = "disabled"; 4287 }; 4288 4289 serdes0: phy@8909000 { 4290 compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy"; 4291 reg = <0x0 0x08909000 0x0 0x00000e10>; 4292 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4293 clock-names = "sgmi_ref"; 4294 #phy-cells = <0>; 4295 status = "disabled"; 4296 }; 4297 4298 refgen: regulator@891c000 { 4299 compatible = "qcom,qcs8300-refgen-regulator", 4300 "qcom,sm8250-refgen-regulator"; 4301 reg = <0x0 0x0891c000 0x0 0x84>; 4302 }; 4303 4304 gpu: gpu@3d00000 { 4305 compatible = "qcom,adreno-623.0", "qcom,adreno"; 4306 reg = <0x0 0x03d00000 0x0 0x40000>, 4307 <0x0 0x03d9e000 0x0 0x1000>, 4308 <0x0 0x03d61000 0x0 0x800>; 4309 reg-names = "kgsl_3d0_reg_memory", 4310 "cx_mem", 4311 "cx_dbgc"; 4312 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4313 iommus = <&adreno_smmu 0 0xc00>, 4314 <&adreno_smmu 1 0xc00>; 4315 operating-points-v2 = <&gpu_opp_table>; 4316 qcom,gmu = <&gmu>; 4317 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 4318 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4319 interconnect-names = "gfx-mem"; 4320 #cooling-cells = <2>; 4321 4322 nvmem-cells = <&gpu_speed_bin>; 4323 nvmem-cell-names = "speed_bin"; 4324 4325 status = "disabled"; 4326 4327 gpu_zap_shader: zap-shader { 4328 memory-region = <&gpu_microcode_mem>; 4329 }; 4330 4331 gpu_opp_table: opp-table { 4332 compatible = "operating-points-v2"; 4333 4334 opp-877000000 { 4335 opp-hz = /bits/ 64 <877000000>; 4336 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4337 opp-peak-kBps = <12484375>; 4338 opp-supported-hw = <0x1>; 4339 }; 4340 4341 opp-780000000 { 4342 opp-hz = /bits/ 64 <780000000>; 4343 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4344 opp-peak-kBps = <10687500>; 4345 opp-supported-hw = <0x1>; 4346 }; 4347 4348 opp-599000000 { 4349 opp-hz = /bits/ 64 <599000000>; 4350 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4351 opp-peak-kBps = <8171875>; 4352 opp-supported-hw = <0x3>; 4353 }; 4354 4355 opp-479000000 { 4356 opp-hz = /bits/ 64 <479000000>; 4357 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4358 opp-peak-kBps = <5285156>; 4359 opp-supported-hw = <0x3>; 4360 }; 4361 }; 4362 }; 4363 4364 gmu: gmu@3d6a000 { 4365 compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu"; 4366 reg = <0x0 0x03d6a000 0x0 0x34000>, 4367 <0x0 0x03de0000 0x0 0x10000>, 4368 <0x0 0x0b290000 0x0 0x10000>; 4369 reg-names = "gmu", "rscc", "gmu_pdc"; 4370 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4371 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4372 interrupt-names = "hfi", "gmu"; 4373 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4374 <&gpucc GPU_CC_CXO_CLK>, 4375 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4376 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4377 <&gpucc GPU_CC_AHB_CLK>, 4378 <&gpucc GPU_CC_HUB_CX_INT_CLK>; 4379 clock-names = "gmu", 4380 "cxo", 4381 "axi", 4382 "memnoc", 4383 "ahb", 4384 "hub"; 4385 power-domains = <&gpucc GPU_CC_CX_GDSC>, 4386 <&gpucc GPU_CC_GX_GDSC>; 4387 power-domain-names = "cx", 4388 "gx"; 4389 iommus = <&adreno_smmu 5 0xc00>; 4390 operating-points-v2 = <&gmu_opp_table>; 4391 4392 gmu_opp_table: opp-table { 4393 compatible = "operating-points-v2"; 4394 4395 opp-500000000 { 4396 opp-hz = /bits/ 64 <500000000>; 4397 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4398 }; 4399 }; 4400 }; 4401 4402 gpucc: clock-controller@3d90000 { 4403 compatible = "qcom,qcs8300-gpucc"; 4404 reg = <0x0 0x03d90000 0x0 0xa000>; 4405 clocks = <&rpmhcc RPMH_CXO_CLK>, 4406 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 4407 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 4408 clock-names = "bi_tcxo", 4409 "gcc_gpu_gpll0_clk_src", 4410 "gcc_gpu_gpll0_div_clk_src"; 4411 #clock-cells = <1>; 4412 #reset-cells = <1>; 4413 #power-domain-cells = <1>; 4414 }; 4415 4416 adreno_smmu: iommu@3da0000 { 4417 compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu", 4418 "qcom,smmu-500", "arm,mmu-500"; 4419 reg = <0x0 0x3da0000 0x0 0x20000>; 4420 #iommu-cells = <2>; 4421 #global-interrupts = <2>; 4422 4423 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 4424 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 4425 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 4426 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 4427 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 4428 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 4429 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 4430 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 4431 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 4432 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 4433 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 4434 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 4435 4436 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4437 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4438 <&gpucc GPU_CC_AHB_CLK>, 4439 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4440 <&gpucc GPU_CC_CX_GMU_CLK>, 4441 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4442 <&gpucc GPU_CC_HUB_AON_CLK>; 4443 4444 clock-names = "gcc_gpu_memnoc_gfx_clk", 4445 "gcc_gpu_snoc_dvm_gfx_clk", 4446 "gpu_cc_ahb_clk", 4447 "gpu_cc_hlos1_vote_gpu_smmu_clk", 4448 "gpu_cc_cx_gmu_clk", 4449 "gpu_cc_hub_cx_int_clk", 4450 "gpu_cc_hub_aon_clk"; 4451 power-domains = <&gpucc GPU_CC_CX_GDSC>; 4452 dma-coherent; 4453 }; 4454 4455 pmu@9091000 { 4456 compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4457 reg = <0x0 0x9091000 0x0 0x1000>; 4458 4459 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 4460 4461 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 4462 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4463 4464 operating-points-v2 = <&llcc_bwmon_opp_table>; 4465 4466 llcc_bwmon_opp_table: opp-table { 4467 compatible = "operating-points-v2"; 4468 4469 opp-0 { 4470 opp-peak-kBps = <762000>; 4471 }; 4472 4473 opp-1 { 4474 opp-peak-kBps = <1720000>; 4475 }; 4476 4477 opp-2 { 4478 opp-peak-kBps = <2086000>; 4479 }; 4480 4481 opp-3 { 4482 opp-peak-kBps = <2601000>; 4483 }; 4484 4485 opp-4 { 4486 opp-peak-kBps = <2929000>; 4487 }; 4488 4489 opp-5 { 4490 opp-peak-kBps = <5931000>; 4491 }; 4492 4493 opp-6 { 4494 opp-peak-kBps = <6515000>; 4495 }; 4496 4497 opp-7 { 4498 opp-peak-kBps = <7984000>; 4499 }; 4500 4501 opp-8 { 4502 opp-peak-kBps = <10437000>; 4503 }; 4504 4505 opp-9 { 4506 opp-peak-kBps = <12195000>; 4507 }; 4508 }; 4509 }; 4510 4511 pmu@90b5400 { 4512 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; 4513 reg = <0x0 0x90b5400 0x0 0x600>; 4514 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4515 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4516 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4517 4518 operating-points-v2 = <&cpu_bwmon_opp_table>; 4519 4520 cpu_bwmon_opp_table: opp-table { 4521 compatible = "operating-points-v2"; 4522 4523 opp-0 { 4524 opp-peak-kBps = <9155000>; 4525 }; 4526 4527 opp-1 { 4528 opp-peak-kBps = <12298000>; 4529 }; 4530 4531 opp-2 { 4532 opp-peak-kBps = <14236000>; 4533 }; 4534 4535 opp-3 { 4536 opp-peak-kBps = <16265000>; 4537 }; 4538 }; 4539 }; 4540 4541 pmu@90b6400 { 4542 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; 4543 reg = <0x0 0x90b6400 0x0 0x600>; 4544 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4545 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4546 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4547 4548 operating-points-v2 = <&cpu_bwmon_opp_table>; 4549 }; 4550 4551 dc_noc: interconnect@90e0000 { 4552 compatible = "qcom,qcs8300-dc-noc"; 4553 reg = <0x0 0x090e0000 0x0 0x5080>; 4554 #interconnect-cells = <2>; 4555 qcom,bcm-voters = <&apps_bcm_voter>; 4556 }; 4557 4558 gem_noc: interconnect@9100000 { 4559 compatible = "qcom,qcs8300-gem-noc"; 4560 reg = <0x0 0x9100000 0x0 0xf7080>; 4561 #interconnect-cells = <2>; 4562 qcom,bcm-voters = <&apps_bcm_voter>; 4563 }; 4564 4565 llcc: system-cache-controller@9200000 { 4566 compatible = "qcom,qcs8300-llcc"; 4567 reg = <0x0 0x09200000 0x0 0x80000>, 4568 <0x0 0x09300000 0x0 0x80000>, 4569 <0x0 0x09400000 0x0 0x80000>, 4570 <0x0 0x09500000 0x0 0x80000>, 4571 <0x0 0x09a00000 0x0 0x80000>; 4572 reg-names = "llcc0_base", 4573 "llcc1_base", 4574 "llcc2_base", 4575 "llcc3_base", 4576 "llcc_broadcast_base"; 4577 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 4578 }; 4579 4580 usb_1: usb@a600000 { 4581 compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; 4582 reg = <0x0 0x0a600000 0x0 0xfc100>; 4583 4584 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4585 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4586 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4587 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4588 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4589 clock-names = "cfg_noc", 4590 "core", 4591 "iface", 4592 "sleep", 4593 "mock_utmi"; 4594 4595 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4596 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4597 assigned-clock-rates = <19200000>, <200000000>; 4598 4599 interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 4600 <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 4601 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 4602 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4603 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4604 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 4605 interrupt-names = "dwc_usb3", 4606 "pwr_event", 4607 "hs_phy_irq", 4608 "dp_hs_phy_irq", 4609 "dm_hs_phy_irq", 4610 "ss_phy_irq"; 4611 4612 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4613 required-opps = <&rpmhpd_opp_nom>; 4614 4615 resets = <&gcc GCC_USB30_PRIM_BCR>; 4616 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 4617 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4618 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4619 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; 4620 interconnect-names = "usb-ddr", "apps-usb"; 4621 4622 iommus = <&apps_smmu 0x80 0x0>; 4623 phys = <&usb_1_hsphy>, <&usb_qmpphy>; 4624 phy-names = "usb2-phy", "usb3-phy"; 4625 snps,dis_enblslpm_quirk; 4626 snps,dis-u1-entry-quirk; 4627 snps,dis-u2-entry-quirk; 4628 snps,dis_u2_susphy_quirk; 4629 snps,dis_u3_susphy_quirk; 4630 4631 wakeup-source; 4632 4633 status = "disabled"; 4634 }; 4635 4636 usb_2: usb@a400000 { 4637 compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; 4638 reg = <0x0 0x0a400000 0x0 0xfc100>; 4639 4640 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4641 <&gcc GCC_USB20_MASTER_CLK>, 4642 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4643 <&gcc GCC_USB20_SLEEP_CLK>, 4644 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 4645 clock-names = "cfg_noc", 4646 "core", 4647 "iface", 4648 "sleep", 4649 "mock_utmi"; 4650 4651 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4652 <&gcc GCC_USB20_MASTER_CLK>; 4653 assigned-clock-rates = <19200000>, <120000000>; 4654 4655 interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 4656 <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 4657 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 4658 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 4659 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 4660 interrupt-names = "dwc_usb3", 4661 "pwr_event", 4662 "hs_phy_irq", 4663 "dp_hs_phy_irq", 4664 "dm_hs_phy_irq"; 4665 4666 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 4667 required-opps = <&rpmhpd_opp_nom>; 4668 4669 resets = <&gcc GCC_USB20_PRIM_BCR>; 4670 4671 interconnects = <&aggre1_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 4672 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4673 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4674 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; 4675 interconnect-names = "usb-ddr", "apps-usb"; 4676 4677 iommus = <&apps_smmu 0x20 0x0>; 4678 4679 phys = <&usb_2_hsphy>; 4680 phy-names = "usb2-phy"; 4681 maximum-speed = "high-speed"; 4682 4683 snps,dis-u1-entry-quirk; 4684 snps,dis-u2-entry-quirk; 4685 snps,dis_u2_susphy_quirk; 4686 snps,dis_u3_susphy_quirk; 4687 snps,dis_enblslpm_quirk; 4688 4689 qcom,select-utmi-as-pipe-clk; 4690 wakeup-source; 4691 4692 status = "disabled"; 4693 }; 4694 4695 iris: video-codec@aa00000 { 4696 compatible = "qcom,qcs8300-iris"; 4697 4698 reg = <0x0 0x0aa00000 0x0 0xf0000>; 4699 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4700 4701 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 4702 <&videocc VIDEO_CC_MVS0_GDSC>, 4703 <&rpmhpd RPMHPD_MX>, 4704 <&rpmhpd RPMHPD_MMCX>; 4705 power-domain-names = "venus", 4706 "vcodec0", 4707 "mxc", 4708 "mmcx"; 4709 4710 operating-points-v2 = <&iris_opp_table>; 4711 4712 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 4713 <&videocc VIDEO_CC_MVS0C_CLK>, 4714 <&videocc VIDEO_CC_MVS0_CLK>; 4715 clock-names = "iface", 4716 "core", 4717 "vcodec0_core"; 4718 4719 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4720 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4721 <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 4722 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4723 interconnect-names = "cpu-cfg", 4724 "video-mem"; 4725 4726 memory-region = <&video_mem>; 4727 4728 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 4729 reset-names = "bus"; 4730 4731 iommus = <&apps_smmu 0x0880 0x0400>, 4732 <&apps_smmu 0x0887 0x0400>; 4733 dma-coherent; 4734 4735 status = "disabled"; 4736 4737 iris_opp_table: opp-table { 4738 compatible = "operating-points-v2"; 4739 4740 opp-366000000 { 4741 opp-hz = /bits/ 64 <366000000>; 4742 required-opps = <&rpmhpd_opp_svs_l1>, 4743 <&rpmhpd_opp_svs_l1>; 4744 }; 4745 4746 opp-444000000 { 4747 opp-hz = /bits/ 64 <444000000>; 4748 required-opps = <&rpmhpd_opp_nom>, 4749 <&rpmhpd_opp_nom>; 4750 }; 4751 4752 opp-533000000 { 4753 opp-hz = /bits/ 64 <533000000>; 4754 required-opps = <&rpmhpd_opp_turbo>, 4755 <&rpmhpd_opp_turbo>; 4756 }; 4757 4758 opp-560000000 { 4759 opp-hz = /bits/ 64 <560000000>; 4760 required-opps = <&rpmhpd_opp_turbo_l1>, 4761 <&rpmhpd_opp_turbo_l1>; 4762 }; 4763 }; 4764 }; 4765 4766 videocc: clock-controller@abf0000 { 4767 compatible = "qcom,qcs8300-videocc"; 4768 reg = <0x0 0x0abf0000 0x0 0x10000>; 4769 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 4770 <&rpmhcc RPMH_CXO_CLK>, 4771 <&rpmhcc RPMH_CXO_CLK_A>, 4772 <&sleep_clk>; 4773 power-domains = <&rpmhpd RPMHPD_MMCX>; 4774 #clock-cells = <1>; 4775 #reset-cells = <1>; 4776 #power-domain-cells = <1>; 4777 }; 4778 4779 camcc: clock-controller@ade0000 { 4780 compatible = "qcom,qcs8300-camcc"; 4781 reg = <0x0 0x0ade0000 0x0 0x20000>; 4782 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4783 <&rpmhcc RPMH_CXO_CLK>, 4784 <&rpmhcc RPMH_CXO_CLK_A>, 4785 <&sleep_clk>; 4786 power-domains = <&rpmhpd RPMHPD_MMCX>; 4787 #clock-cells = <1>; 4788 #reset-cells = <1>; 4789 #power-domain-cells = <1>; 4790 }; 4791 4792 dispcc: clock-controller@af00000 { 4793 compatible = "qcom,sa8775p-dispcc0"; 4794 reg = <0x0 0x0af00000 0x0 0x20000>; 4795 clocks = <&gcc GCC_DISP_AHB_CLK>, 4796 <&rpmhcc RPMH_CXO_CLK>, 4797 <&rpmhcc RPMH_CXO_CLK_A>, 4798 <&sleep_clk>, 4799 <0>, <0>, <0>, <0>, 4800 <0>, <0>, <0>, <0>; 4801 power-domains = <&rpmhpd RPMHPD_MMCX>; 4802 #clock-cells = <1>; 4803 #reset-cells = <1>; 4804 #power-domain-cells = <1>; 4805 }; 4806 4807 pdc: interrupt-controller@b220000 { 4808 compatible = "qcom,qcs8300-pdc", "qcom,pdc"; 4809 reg = <0x0 0xb220000 0x0 0x30000>, 4810 <0x0 0x17c000f0 0x0 0x64>; 4811 interrupt-parent = <&intc>; 4812 #interrupt-cells = <2>; 4813 interrupt-controller; 4814 qcom,pdc-ranges = <0 480 40>, 4815 <40 140 14>, 4816 <54 263 1>, 4817 <55 306 4>, 4818 <59 312 3>, 4819 <62 374 2>, 4820 <64 434 2>, 4821 <66 438 2>, 4822 <70 520 1>, 4823 <73 523 1>, 4824 <118 568 6>, 4825 <124 609 3>, 4826 <159 638 1>, 4827 <160 720 3>, 4828 <169 728 30>, 4829 <199 416 2>, 4830 <201 449 1>, 4831 <202 89 1>, 4832 <203 451 1>, 4833 <204 462 1>, 4834 <205 264 1>, 4835 <206 579 1>, 4836 <207 653 1>, 4837 <208 656 1>, 4838 <209 659 1>, 4839 <210 122 1>, 4840 <211 699 1>, 4841 <212 705 1>, 4842 <213 450 1>, 4843 <214 643 2>, 4844 <216 646 5>, 4845 <221 390 5>, 4846 <226 700 2>, 4847 <228 440 1>, 4848 <229 663 1>, 4849 <230 524 2>, 4850 <232 612 3>, 4851 <235 723 5>; 4852 }; 4853 4854 aoss_qmp: power-management@c300000 { 4855 compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp"; 4856 reg = <0x0 0x0c300000 0x0 0x400>; 4857 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4858 IPCC_MPROC_SIGNAL_GLINK_QMP 4859 IRQ_TYPE_EDGE_RISING>; 4860 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4861 #clock-cells = <0>; 4862 }; 4863 4864 sram@c3f0000 { 4865 compatible = "qcom,rpmh-stats"; 4866 reg = <0x0 0x0c3f0000 0x0 0x400>; 4867 }; 4868 4869 spmi_bus: spmi@c440000 { 4870 compatible = "qcom,spmi-pmic-arb"; 4871 reg = <0x0 0x0c440000 0x0 0x1100>, 4872 <0x0 0x0c600000 0x0 0x2000000>, 4873 <0x0 0x0e600000 0x0 0x100000>, 4874 <0x0 0x0e700000 0x0 0xa0000>, 4875 <0x0 0x0c40a000 0x0 0x26000>; 4876 reg-names = "core", 4877 "chnls", 4878 "obsrvr", 4879 "intr", 4880 "cnfg"; 4881 qcom,channel = <0>; 4882 qcom,ee = <0>; 4883 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4884 interrupt-names = "periph_irq"; 4885 interrupt-controller; 4886 #interrupt-cells = <4>; 4887 #address-cells = <2>; 4888 #size-cells = <0>; 4889 }; 4890 4891 tlmm: pinctrl@f100000 { 4892 compatible = "qcom,qcs8300-tlmm"; 4893 reg = <0x0 0x0f100000 0x0 0x300000>; 4894 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4895 gpio-controller; 4896 #gpio-cells = <2>; 4897 gpio-ranges = <&tlmm 0 0 134>; 4898 interrupt-controller; 4899 #interrupt-cells = <2>; 4900 wakeup-parent = <&pdc>; 4901 4902 hs0_mi2s_active: hs0-mi2s-active-state { 4903 pins = "gpio106", "gpio107", "gpio108", "gpio109"; 4904 function = "hs0_mi2s"; 4905 drive-strength = <8>; 4906 bias-disable; 4907 }; 4908 4909 mi2s1_active: mi2s1-active-state { 4910 data0-pins { 4911 pins = "gpio100"; 4912 function = "mi2s1_data0"; 4913 drive-strength = <8>; 4914 bias-disable; 4915 }; 4916 4917 data1-pins { 4918 pins = "gpio101"; 4919 function = "mi2s1_data1"; 4920 drive-strength = <8>; 4921 bias-disable; 4922 }; 4923 4924 sclk-pins { 4925 pins = "gpio98"; 4926 function = "mi2s1_sck"; 4927 drive-strength = <8>; 4928 bias-disable; 4929 }; 4930 4931 ws-pins { 4932 pins = "gpio99"; 4933 function = "mi2s1_ws"; 4934 drive-strength = <8>; 4935 bias-disable; 4936 }; 4937 }; 4938 4939 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4940 pins = "gpio17", "gpio18"; 4941 function = "qup0_se0"; 4942 }; 4943 4944 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4945 pins = "gpio19", "gpio20"; 4946 function = "qup0_se1"; 4947 }; 4948 4949 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4950 pins = "gpio33", "gpio34"; 4951 function = "qup0_se2"; 4952 }; 4953 4954 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4955 pins = "gpio25", "gpio26"; 4956 function = "qup0_se3"; 4957 }; 4958 4959 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4960 pins = "gpio29", "gpio30"; 4961 function = "qup0_se4"; 4962 }; 4963 4964 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4965 pins = "gpio21", "gpio22"; 4966 function = "qup0_se5"; 4967 }; 4968 4969 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4970 pins = "gpio80", "gpio81"; 4971 function = "qup0_se6"; 4972 }; 4973 4974 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4975 pins = "gpio37", "gpio38"; 4976 function = "qup1_se0"; 4977 }; 4978 4979 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4980 pins = "gpio39", "gpio40"; 4981 function = "qup1_se1"; 4982 }; 4983 4984 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4985 pins = "gpio84", "gpio85"; 4986 function = "qup1_se2"; 4987 }; 4988 4989 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4990 pins = "gpio41", "gpio42"; 4991 function = "qup1_se3"; 4992 }; 4993 4994 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4995 pins = "gpio45", "gpio46"; 4996 function = "qup1_se4"; 4997 }; 4998 4999 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5000 pins = "gpio49", "gpio50"; 5001 function = "qup1_se5"; 5002 }; 5003 5004 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5005 pins = "gpio89", "gpio90"; 5006 function = "qup1_se6"; 5007 }; 5008 5009 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5010 pins = "gpio91", "gpio92"; 5011 function = "qup1_se7"; 5012 }; 5013 5014 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 5015 pins = "gpio10", "gpio11"; 5016 function = "qup2_se0"; 5017 }; 5018 5019 qup_spi0_data_clk: qup-spi0-data-clk-state { 5020 pins = "gpio17", "gpio18", "gpio19"; 5021 function = "qup0_se0"; 5022 }; 5023 5024 qup_spi0_cs: qup-spi0-cs-state { 5025 pins = "gpio20"; 5026 function = "qup0_se0"; 5027 }; 5028 5029 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 5030 pins = "gpio20"; 5031 function = "gpio"; 5032 }; 5033 5034 qup_spi1_data_clk: qup-spi1-data-clk-state { 5035 pins = "gpio19", "gpio20", "gpio17"; 5036 function = "qup0_se1"; 5037 }; 5038 5039 qup_spi1_cs: qup-spi1-cs-state { 5040 pins = "gpio18"; 5041 function = "qup0_se1"; 5042 }; 5043 5044 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 5045 pins = "gpio18"; 5046 function = "gpio"; 5047 }; 5048 5049 qup_spi2_data_clk: qup-spi2-data-clk-state { 5050 pins = "gpio33", "gpio34", "gpio35"; 5051 function = "qup0_se2"; 5052 }; 5053 5054 qup_spi2_cs: qup-spi2-cs-state { 5055 pins = "gpio36"; 5056 function = "qup0_se2"; 5057 }; 5058 5059 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 5060 pins = "gpio36"; 5061 function = "gpio"; 5062 }; 5063 5064 qup_spi3_data_clk: qup-spi3-data-clk-state { 5065 pins = "gpio25", "gpio26", "gpio27"; 5066 function = "qup0_se3"; 5067 }; 5068 5069 qup_spi3_cs: qup-spi3-cs-state { 5070 pins = "gpio28"; 5071 function = "qup0_se3"; 5072 }; 5073 5074 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 5075 pins = "gpio28"; 5076 function = "gpio"; 5077 }; 5078 5079 qup_spi4_data_clk: qup-spi4-data-clk-state { 5080 pins = "gpio29", "gpio30", "gpio31"; 5081 function = "qup0_se4"; 5082 }; 5083 5084 qup_spi4_cs: qup-spi4-cs-state { 5085 pins = "gpio32"; 5086 function = "qup0_se4"; 5087 }; 5088 5089 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 5090 pins = "gpio32"; 5091 function = "gpio"; 5092 }; 5093 5094 qup_spi5_data_clk: qup-spi5-data-clk-state { 5095 pins = "gpio21", "gpio22", "gpio23"; 5096 function = "qup0_se5"; 5097 }; 5098 5099 qup_spi5_cs: qup-spi5-cs-state { 5100 pins = "gpio24"; 5101 function = "qup0_se5"; 5102 }; 5103 5104 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 5105 pins = "gpio24"; 5106 function = "gpio"; 5107 }; 5108 5109 qup_spi6_data_clk: qup-spi6-data-clk-state { 5110 pins = "gpio80", "gpio81", "gpio82"; 5111 function = "qup0_se6"; 5112 }; 5113 5114 qup_spi6_cs: qup-spi6-cs-state { 5115 pins = "gpio83"; 5116 function = "qup0_se6"; 5117 }; 5118 5119 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 5120 pins = "gpio83"; 5121 function = "gpio"; 5122 }; 5123 5124 qup_spi8_data_clk: qup-spi8-data-clk-state { 5125 pins = "gpio37", "gpio38", "gpio39"; 5126 function = "qup1_se0"; 5127 }; 5128 5129 qup_spi8_cs: qup-spi8-cs-state { 5130 pins = "gpio40"; 5131 function = "qup1_se0"; 5132 }; 5133 5134 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 5135 pins = "gpio40"; 5136 function = "gpio"; 5137 }; 5138 5139 qup_spi9_data_clk: qup-spi9-data-clk-state { 5140 pins = "gpio39", "gpio40", "gpio37"; 5141 function = "qup1_se1"; 5142 }; 5143 5144 qup_spi9_cs: qup-spi9-cs-state { 5145 pins = "gpio38"; 5146 function = "qup1_se1"; 5147 }; 5148 5149 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 5150 pins = "gpio38"; 5151 function = "gpio"; 5152 }; 5153 5154 qup_spi10_data_clk: qup-spi10-data-clk-state { 5155 pins = "gpio84", "gpio85", "gpio86"; 5156 function = "qup1_se2"; 5157 }; 5158 5159 qup_spi10_cs: qup-spi10-cs-state { 5160 pins = "gpio87"; 5161 function = "qup1_se2"; 5162 }; 5163 5164 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 5165 pins = "gpio87"; 5166 function = "gpio"; 5167 }; 5168 5169 qup_spi12_data_clk: qup-spi12-data-clk-state { 5170 pins = "gpio45", "gpio46", "gpio47"; 5171 function = "qup1_se4"; 5172 }; 5173 5174 qup_spi12_cs: qup-spi12-cs-state { 5175 pins = "gpio48"; 5176 function = "qup1_se4"; 5177 }; 5178 5179 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 5180 pins = "gpio48"; 5181 function = "gpio"; 5182 }; 5183 5184 qup_spi13_data_clk: qup-spi13-data-clk-state { 5185 pins = "gpio49", "gpio50", "gpio51"; 5186 function = "qup1_se5"; 5187 }; 5188 5189 qup_spi13_cs: qup-spi13-cs-state { 5190 pins = "gpio52"; 5191 function = "qup1_se5"; 5192 }; 5193 5194 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 5195 pins = "gpio52"; 5196 function = "gpio"; 5197 }; 5198 5199 qup_spi14_data_clk: qup-spi14-data-clk-state { 5200 pins = "gpio89", "gpio90", "gpio91"; 5201 function = "qup1_se6"; 5202 }; 5203 5204 qup_spi14_cs: qup-spi14-cs-state { 5205 pins = "gpio92"; 5206 function = "qup1_se6"; 5207 }; 5208 5209 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 5210 pins = "gpio92"; 5211 function = "gpio"; 5212 }; 5213 5214 qup_spi15_data_clk: qup-spi15-data-clk-state { 5215 pins = "gpio91", "gpio92", "gpio89"; 5216 function = "qup1_se7"; 5217 }; 5218 5219 qup_spi15_cs: qup-spi15-cs-state { 5220 pins = "gpio90"; 5221 function = "qup1_se7"; 5222 }; 5223 5224 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 5225 pins = "gpio90"; 5226 function = "gpio"; 5227 }; 5228 5229 qup_spi16_data_clk: qup-spi16-data-clk-state { 5230 pins = "gpio10", "gpio11", "gpio12"; 5231 function = "qup2_se0"; 5232 }; 5233 5234 qup_spi16_cs: qup-spi16-cs-state { 5235 pins = "gpio13"; 5236 function = "qup2_se0"; 5237 }; 5238 5239 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 5240 pins = "gpio13"; 5241 function = "gpio"; 5242 }; 5243 5244 qup_uart0_cts: qup-uart0-cts-state { 5245 pins = "gpio17"; 5246 function = "qup0_se0"; 5247 }; 5248 5249 qup_uart0_rts: qup-uart0-rts-state { 5250 pins = "gpio18"; 5251 function = "qup0_se0"; 5252 }; 5253 5254 qup_uart0_tx: qup-uart0-tx-state { 5255 pins = "gpio19"; 5256 function = "qup0_se0"; 5257 }; 5258 5259 qup_uart0_rx: qup-uart0-rx-state { 5260 pins = "gpio20"; 5261 function = "qup0_se0"; 5262 }; 5263 5264 qup_uart1_cts: qup-uart1-cts-state { 5265 pins = "gpio19"; 5266 function = "qup0_se1"; 5267 }; 5268 5269 qup_uart1_rts: qup-uart1-rts-state { 5270 pins = "gpio20"; 5271 function = "qup0_se1"; 5272 }; 5273 5274 qup_uart1_tx: qup-uart1-tx-state { 5275 pins = "gpio17"; 5276 function = "qup0_se1"; 5277 }; 5278 5279 qup_uart1_rx: qup-uart1-rx-state { 5280 pins = "gpio18"; 5281 function = "qup0_se1"; 5282 }; 5283 5284 qup_uart2_cts: qup-uart2-cts-state { 5285 pins = "gpio33"; 5286 function = "qup0_se2"; 5287 }; 5288 5289 qup_uart2_rts: qup-uart2-rts-state { 5290 pins = "gpio34"; 5291 function = "qup0_se2"; 5292 }; 5293 5294 qup_uart2_tx: qup-uart2-tx-state { 5295 pins = "gpio35"; 5296 function = "qup0_se2"; 5297 }; 5298 5299 qup_uart2_rx: qup-uart2-rx-state { 5300 pins = "gpio36"; 5301 function = "qup0_se2"; 5302 }; 5303 5304 qup_uart3_cts: qup-uart3-cts-state { 5305 pins = "gpio25"; 5306 function = "qup0_se3"; 5307 }; 5308 5309 qup_uart3_rts: qup-uart3-rts-state { 5310 pins = "gpio26"; 5311 function = "qup0_se3"; 5312 }; 5313 5314 qup_uart3_tx: qup-uart3-tx-state { 5315 pins = "gpio27"; 5316 function = "qup0_se3"; 5317 }; 5318 5319 qup_uart3_rx: qup-uart3-rx-state { 5320 pins = "gpio28"; 5321 function = "qup0_se3"; 5322 }; 5323 5324 qup_uart4_cts: qup-uart4-cts-state { 5325 pins = "gpio29"; 5326 function = "qup0_se4"; 5327 }; 5328 5329 qup_uart4_rts: qup-uart4-rts-state { 5330 pins = "gpio30"; 5331 function = "qup0_se4"; 5332 }; 5333 5334 qup_uart4_tx: qup-uart4-tx-state { 5335 pins = "gpio31"; 5336 function = "qup0_se4"; 5337 }; 5338 5339 qup_uart4_rx: qup-uart4-rx-state { 5340 pins = "gpio32"; 5341 function = "qup0_se4"; 5342 }; 5343 5344 qup_uart5_cts: qup-uart5-cts-state { 5345 pins = "gpio21"; 5346 function = "qup0_se5"; 5347 }; 5348 5349 qup_uart5_rts: qup-uart5-rts-state { 5350 pins = "gpio22"; 5351 function = "qup0_se5"; 5352 }; 5353 5354 qup_uart5_tx: qup-uart5-tx-state { 5355 pins = "gpio23"; 5356 function = "qup0_se5"; 5357 }; 5358 5359 qup_uart5_rx: qup-uart5-rx-state { 5360 pins = "gpio23"; 5361 function = "qup0_se5"; 5362 }; 5363 5364 qup_uart6_cts: qup-uart6-cts-state { 5365 pins = "gpio80"; 5366 function = "qup0_se6"; 5367 }; 5368 5369 qup_uart6_rts: qup-uart6-rts-state { 5370 pins = "gpio81"; 5371 function = "qup0_se6"; 5372 }; 5373 5374 qup_uart6_tx: qup-uart6-tx-state { 5375 pins = "gpio82"; 5376 function = "qup0_se6"; 5377 }; 5378 5379 qup_uart6_rx: qup-uart6-rx-state { 5380 pins = "gpio83"; 5381 function = "qup0_se6"; 5382 }; 5383 5384 qup_uart7_tx: qup-uart7-tx-state { 5385 pins = "gpio43"; 5386 function = "qup0_se7"; 5387 }; 5388 5389 qup_uart7_rx: qup-uart7-rx-state { 5390 pins = "gpio44"; 5391 function = "qup0_se7"; 5392 }; 5393 5394 qup_uart8_cts: qup-uart8-cts-state { 5395 pins = "gpio37"; 5396 function = "qup1_se0"; 5397 }; 5398 5399 qup_uart8_rts: qup-uart8-rts-state { 5400 pins = "gpio38"; 5401 function = "qup1_se0"; 5402 }; 5403 5404 qup_uart8_tx: qup-uart8-tx-state { 5405 pins = "gpio39"; 5406 function = "qup1_se0"; 5407 }; 5408 5409 qup_uart8_rx: qup-uart8-rx-state { 5410 pins = "gpio40"; 5411 function = "qup1_se0"; 5412 }; 5413 5414 qup_uart9_cts: qup-uart9-cts-state { 5415 pins = "gpio39"; 5416 function = "qup1_se1"; 5417 }; 5418 5419 qup_uart9_rts: qup-uart9-rts-state { 5420 pins = "gpio40"; 5421 function = "qup1_se1"; 5422 }; 5423 5424 qup_uart9_tx: qup-uart9-tx-state { 5425 pins = "gpio37"; 5426 function = "qup1_se1"; 5427 }; 5428 5429 qup_uart9_rx: qup-uart9-rx-state { 5430 pins = "gpio38"; 5431 function = "qup1_se1"; 5432 }; 5433 5434 qup_uart10_cts: qup-uart10-cts-state { 5435 pins = "gpio84"; 5436 function = "qup1_se2"; 5437 }; 5438 5439 qup_uart10_rts: qup-uart10-rts-state { 5440 pins = "gpio84"; 5441 function = "qup1_se2"; 5442 }; 5443 5444 qup_uart10_tx: qup-uart10-tx-state { 5445 pins = "gpio85"; 5446 function = "qup1_se2"; 5447 }; 5448 5449 qup_uart10_rx: qup-uart10-rx-state { 5450 pins = "gpio87"; 5451 function = "qup1_se2"; 5452 }; 5453 5454 qup_uart11_tx: qup-uart11-tx-state { 5455 pins = "gpio41"; 5456 function = "qup1_se3"; 5457 }; 5458 5459 qup_uart11_rx: qup-uart11-rx-state { 5460 pins = "gpio42"; 5461 function = "qup1_se3"; 5462 }; 5463 5464 qup_uart12_cts: qup-uart12-cts-state { 5465 pins = "gpio45"; 5466 function = "qup1_se4"; 5467 }; 5468 5469 qup_uart12_rts: qup-uart12-rts-state { 5470 pins = "gpio46"; 5471 function = "qup1_se4"; 5472 }; 5473 5474 qup_uart12_tx: qup-uart12-tx-state { 5475 pins = "gpio47"; 5476 function = "qup1_se4"; 5477 }; 5478 5479 qup_uart12_rx: qup-uart12-rx-state { 5480 pins = "gpio48"; 5481 function = "qup1_se4"; 5482 }; 5483 5484 qup_uart13_cts: qup-uart13-cts-state { 5485 pins = "gpio49"; 5486 function = "qup1_se5"; 5487 }; 5488 5489 qup_uart13_rts: qup-uart13-rts-state { 5490 pins = "gpio50"; 5491 function = "qup1_se5"; 5492 }; 5493 5494 qup_uart13_tx: qup-uart13-tx-state { 5495 pins = "gpio51"; 5496 function = "qup1_se5"; 5497 }; 5498 5499 qup_uart13_rx: qup-uart13-rx-state { 5500 pins = "gpio52"; 5501 function = "qup1_se5"; 5502 }; 5503 5504 qup_uart14_cts: qup-uart14-cts-state { 5505 pins = "gpio89"; 5506 function = "qup1_se6"; 5507 }; 5508 5509 qup_uart14_rts: qup-uart14-rts-state { 5510 pins = "gpio90"; 5511 function = "qup1_se6"; 5512 }; 5513 5514 qup_uart14_tx: qup-uart14-tx-state { 5515 pins = "gpio91"; 5516 function = "qup1_se6"; 5517 }; 5518 5519 qup_uart14_rx: qup-uart14-rx-state { 5520 pins = "gpio92"; 5521 function = "qup1_se6"; 5522 }; 5523 5524 qup_uart15_cts: qup-uart15-cts-state { 5525 pins = "gpio91"; 5526 function = "qup1_se7"; 5527 }; 5528 5529 qup_uart15_rts: qup-uart15-rts-state { 5530 pins = "gpio92"; 5531 function = "qup1_se7"; 5532 }; 5533 5534 qup_uart15_tx: qup-uart15-tx-state { 5535 pins = "gpio89"; 5536 function = "qup1_se7"; 5537 }; 5538 5539 qup_uart15_rx: qup-uart15-rx-state { 5540 pins = "gpio90"; 5541 function = "qup1_se7"; 5542 }; 5543 5544 qup_uart16_cts: qup-uart16-cts-state { 5545 pins = "gpio10"; 5546 function = "qup2_se0"; 5547 }; 5548 5549 qup_uart16_rts: qup-uart16-rts-state { 5550 pins = "gpio11"; 5551 function = "qup2_se0"; 5552 }; 5553 5554 qup_uart16_tx: qup-uart16-tx-state { 5555 pins = "gpio12"; 5556 function = "qup2_se0"; 5557 }; 5558 5559 qup_uart16_rx: qup-uart16-rx-state { 5560 pins = "gpio13"; 5561 function = "qup2_se0"; 5562 }; 5563 5564 sdc1_state_on: sdc1-on-state { 5565 clk-pins { 5566 pins = "sdc1_clk"; 5567 drive-strength = <16>; 5568 bias-disable; 5569 }; 5570 5571 cmd-pins { 5572 pins = "sdc1_cmd"; 5573 drive-strength = <10>; 5574 bias-pull-up; 5575 }; 5576 5577 data-pins { 5578 pins = "sdc1_data"; 5579 drive-strength = <10>; 5580 bias-pull-up; 5581 }; 5582 5583 rclk-pins { 5584 pins = "sdc1_rclk"; 5585 bias-pull-down; 5586 }; 5587 }; 5588 5589 sdc1_state_off: sdc1-off-state { 5590 clk-pins { 5591 pins = "sdc1_clk"; 5592 drive-strength = <2>; 5593 bias-bus-hold; 5594 }; 5595 5596 cmd-pins { 5597 pins = "sdc1_cmd"; 5598 drive-strength = <2>; 5599 bias-bus-hold; 5600 }; 5601 5602 data-pins { 5603 pins = "sdc1_data"; 5604 drive-strength = <2>; 5605 bias-bus-hold; 5606 }; 5607 5608 rclk-pins { 5609 pins = "sdc1_rclk"; 5610 bias-bus-hold; 5611 }; 5612 }; 5613 }; 5614 5615 sram: sram@146d8000 { 5616 compatible = "qcom,qcs8300-imem", "syscon", "simple-mfd"; 5617 reg = <0x0 0x146d8000 0x0 0x1000>; 5618 ranges = <0x0 0x0 0x146d8000 0x1000>; 5619 5620 #address-cells = <1>; 5621 #size-cells = <1>; 5622 5623 pil-reloc@94c { 5624 compatible = "qcom,pil-reloc-info"; 5625 reg = <0x94c 0xc8>; 5626 }; 5627 }; 5628 5629 apps_smmu: iommu@15000000 { 5630 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5631 5632 reg = <0x0 0x15000000 0x0 0x100000>; 5633 #iommu-cells = <2>; 5634 #global-interrupts = <2>; 5635 dma-coherent; 5636 5637 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 5638 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 5639 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5640 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5641 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5642 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5643 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5644 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5645 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5646 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5647 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5648 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5649 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5650 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5651 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5652 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5653 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5654 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5655 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5656 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5657 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5658 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5659 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5660 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5661 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5662 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5663 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5664 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5665 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5666 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5667 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5668 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5669 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5670 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5671 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5672 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5673 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5674 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5675 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5676 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5677 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5678 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5679 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5680 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5681 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5682 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5683 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5684 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5685 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5686 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5687 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5688 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5689 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5690 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5691 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5692 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5693 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5694 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5695 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5696 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5697 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5698 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5699 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5700 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5701 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5702 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5703 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5704 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5705 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5706 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5707 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5708 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5709 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5710 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5711 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5712 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5713 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5714 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5715 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5716 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5717 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5718 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5719 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5720 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5721 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5722 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 5723 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5724 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5725 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5726 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 5727 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5728 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5729 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5730 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5731 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5732 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5733 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5734 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 5735 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 5736 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5737 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 5738 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5739 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5740 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 5741 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 5742 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 5743 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 5744 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5745 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 5746 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 5747 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 5748 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 5749 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 5750 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 5751 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 5752 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 5753 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 5754 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 5755 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 5756 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 5757 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 5758 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 5759 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 5760 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 5761 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 5762 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 5763 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 5764 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 5765 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 5766 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>; 5767 }; 5768 5769 pcie_smmu: iommu@15200000 { 5770 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5771 reg = <0x0 0x15200000 0x0 0x80000>; 5772 #iommu-cells = <2>; 5773 #global-interrupts = <2>; 5774 dma-coherent; 5775 5776 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 5777 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 5778 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 5779 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 5780 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 5781 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 5782 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 5783 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 5784 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 5785 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 5786 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 5787 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 5788 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 5789 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 5790 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 5791 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 5792 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 5793 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 5794 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 5795 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 5796 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 5797 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 5798 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 5799 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 5800 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 5801 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 5802 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 5803 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 5804 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 5805 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 5806 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 5807 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 5808 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 5809 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 5810 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 5811 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 5812 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 5813 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 5814 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 5815 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 5816 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 5817 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 5818 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 5819 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 5820 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 5821 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 5822 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 5823 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 5824 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 5825 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 5826 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 5827 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 5828 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 5829 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 5830 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 5831 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 5832 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 5833 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 5834 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 5835 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 5836 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 5837 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 5838 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 5839 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 5840 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 5841 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 5842 }; 5843 5844 intc: interrupt-controller@17a00000 { 5845 compatible = "arm,gic-v3"; 5846 reg = <0x0 0x17a00000 0x0 0x10000>, 5847 <0x0 0x17a60000 0x0 0x100000>; 5848 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5849 #interrupt-cells = <3>; 5850 interrupt-controller; 5851 #redistributor-regions = <1>; 5852 redistributor-stride = <0x0 0x20000>; 5853 }; 5854 5855 watchdog@17c10000 { 5856 compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt"; 5857 reg = <0x0 0x17c10000 0x0 0x1000>; 5858 clocks = <&sleep_clk>; 5859 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5860 }; 5861 5862 timer@17c20000 { 5863 compatible = "arm,armv7-timer-mem"; 5864 reg = <0x0 0x17c20000 0x0 0x1000>; 5865 ranges = <0x0 0x0 0x0 0x20000000>; 5866 #address-cells = <1>; 5867 #size-cells = <1>; 5868 5869 frame@17c21000 { 5870 reg = <0x17c21000 0x1000>, 5871 <0x17c22000 0x1000>; 5872 frame-number = <0>; 5873 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5874 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5875 }; 5876 5877 frame@17c23000 { 5878 reg = <0x17c23000 0x1000>; 5879 frame-number = <1>; 5880 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5881 status = "disabled"; 5882 }; 5883 5884 frame@17c25000 { 5885 reg = <0x17c25000 0x1000>; 5886 frame-number = <2>; 5887 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5888 status = "disabled"; 5889 }; 5890 5891 frame@17c27000 { 5892 reg = <0x17c27000 0x1000>; 5893 frame-number = <3>; 5894 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5895 status = "disabled"; 5896 }; 5897 5898 frame@17c29000 { 5899 reg = <0x17c29000 0x1000>; 5900 frame-number = <4>; 5901 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5902 status = "disabled"; 5903 }; 5904 5905 frame@17c2b000 { 5906 reg = <0x17c2b000 0x1000>; 5907 frame-number = <5>; 5908 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5909 status = "disabled"; 5910 }; 5911 5912 frame@17c2d000 { 5913 reg = <0x17c2d000 0x1000>; 5914 frame-number = <6>; 5915 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5916 status = "disabled"; 5917 }; 5918 }; 5919 5920 apps_rsc: rsc@18200000 { 5921 compatible = "qcom,rpmh-rsc"; 5922 reg = <0x0 0x18200000 0x0 0x10000>, 5923 <0x0 0x18210000 0x0 0x10000>, 5924 <0x0 0x18220000 0x0 0x10000>; 5925 reg-names = "drv-0", 5926 "drv-1", 5927 "drv-2"; 5928 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5929 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5930 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5931 5932 power-domains = <&system_pd>; 5933 label = "apps_rsc"; 5934 5935 qcom,tcs-offset = <0xd00>; 5936 qcom,drv-id = <2>; 5937 qcom,tcs-config = <ACTIVE_TCS 2>, 5938 <SLEEP_TCS 3>, 5939 <WAKE_TCS 3>, 5940 <CONTROL_TCS 0>; 5941 5942 apps_bcm_voter: bcm-voter { 5943 compatible = "qcom,bcm-voter"; 5944 }; 5945 5946 rpmhcc: clock-controller { 5947 compatible = "qcom,sa8775p-rpmh-clk"; 5948 #clock-cells = <1>; 5949 clocks = <&xo_board_clk>; 5950 clock-names = "xo"; 5951 }; 5952 5953 rpmhpd: power-controller { 5954 compatible = "qcom,qcs8300-rpmhpd"; 5955 #power-domain-cells = <1>; 5956 operating-points-v2 = <&rpmhpd_opp_table>; 5957 5958 rpmhpd_opp_table: opp-table { 5959 compatible = "operating-points-v2"; 5960 5961 rpmhpd_opp_ret: opp-0 { 5962 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5963 }; 5964 5965 rpmhpd_opp_min_svs: opp-1 { 5966 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5967 }; 5968 5969 rpmhpd_opp_low_svs: opp-2 { 5970 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5971 }; 5972 5973 rpmhpd_opp_svs: opp-3 { 5974 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5975 }; 5976 5977 rpmhpd_opp_svs_l1: opp-4 { 5978 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5979 }; 5980 5981 rpmhpd_opp_nom: opp-5 { 5982 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5983 }; 5984 5985 rpmhpd_opp_nom_l1: opp-6 { 5986 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5987 }; 5988 5989 rpmhpd_opp_nom_l2: opp-7 { 5990 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5991 }; 5992 5993 rpmhpd_opp_turbo: opp-8 { 5994 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5995 }; 5996 5997 rpmhpd_opp_turbo_l1: opp-9 { 5998 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5999 }; 6000 }; 6001 }; 6002 }; 6003 6004 epss_l3_cl0: interconnect@18590000 { 6005 compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", 6006 "qcom,epss-l3"; 6007 reg = <0x0 0x18590000 0x0 0x1000>; 6008 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6009 clock-names = "xo", "alternate"; 6010 #interconnect-cells = <1>; 6011 }; 6012 6013 cpufreq_hw: cpufreq@18591000 { 6014 compatible = "qcom,qcs8300-cpufreq-epss", "qcom,cpufreq-epss"; 6015 reg = <0x0 0x18591000 0x0 0x1000>, 6016 <0x0 0x18593000 0x0 0x1000>, 6017 <0x0 0x18594000 0x0 0x1000>; 6018 reg-names = "freq-domain0", 6019 "freq-domain1", 6020 "freq-domain2"; 6021 6022 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6023 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 6024 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 6025 interrupt-names = "dcvsh-irq-0", 6026 "dcvsh-irq-1", 6027 "dcvsh-irq-2"; 6028 6029 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6030 clock-names = "xo", "alternate"; 6031 6032 #freq-domain-cells = <1>; 6033 }; 6034 6035 epss_l3_cl1: interconnect@18592000 { 6036 compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", 6037 "qcom,epss-l3"; 6038 reg = <0x0 0x18592000 0x0 0x1000>; 6039 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6040 clock-names = "xo", "alternate"; 6041 #interconnect-cells = <1>; 6042 }; 6043 6044 remoteproc_gpdsp: remoteproc@20c00000 { 6045 compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas"; 6046 reg = <0x0 0x20c00000 0x0 0x10000>; 6047 6048 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 6049 <&smp2p_gpdsp_in 0 0>, 6050 <&smp2p_gpdsp_in 1 0>, 6051 <&smp2p_gpdsp_in 2 0>, 6052 <&smp2p_gpdsp_in 3 0>; 6053 interrupt-names = "wdog", 6054 "fatal", 6055 "ready", 6056 "handover", 6057 "stop-ack"; 6058 6059 clocks = <&rpmhcc RPMH_CXO_CLK>; 6060 clock-names = "xo"; 6061 6062 power-domains = <&rpmhpd RPMHPD_CX>, 6063 <&rpmhpd RPMHPD_MXC>; 6064 power-domain-names = "cx", 6065 "mxc"; 6066 6067 interconnects = <&gpdsp_anoc MASTER_DSP0 QCOM_ICC_TAG_ALWAYS 6068 &config_noc SLAVE_CLK_CTL QCOM_ICC_TAG_ALWAYS>; 6069 6070 memory-region = <&gpdsp_mem>; 6071 6072 qcom,qmp = <&aoss_qmp>; 6073 6074 qcom,smem-states = <&smp2p_gpdsp_out 0>; 6075 qcom,smem-state-names = "stop"; 6076 6077 status = "disabled"; 6078 6079 glink-edge { 6080 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 6081 IPCC_MPROC_SIGNAL_GLINK_QMP 6082 IRQ_TYPE_EDGE_RISING>; 6083 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 6084 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6085 6086 label = "gpdsp"; 6087 qcom,remote-pid = <17>; 6088 }; 6089 }; 6090 6091 ethernet0: ethernet@23040000 { 6092 compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos"; 6093 reg = <0x0 0x23040000 0x0 0x00010000>, 6094 <0x0 0x23056000 0x0 0x00000100>; 6095 reg-names = "stmmaceth", "rgmii"; 6096 6097 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 6098 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; 6099 interrupt-names = "macirq", "sfty"; 6100 6101 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 6102 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 6103 <&gcc GCC_EMAC0_PTP_CLK>, 6104 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 6105 clock-names = "stmmaceth", 6106 "pclk", 6107 "ptp_ref", 6108 "phyaux"; 6109 power-domains = <&gcc GCC_EMAC0_GDSC>; 6110 6111 phys = <&serdes0>; 6112 phy-names = "serdes"; 6113 6114 iommus = <&apps_smmu 0x120 0xf>; 6115 dma-coherent; 6116 6117 snps,tso; 6118 snps,pbl = <32>; 6119 rx-fifo-depth = <16384>; 6120 tx-fifo-depth = <20480>; 6121 6122 status = "disabled"; 6123 }; 6124 6125 nspa_noc: interconnect@260c0000 { 6126 compatible = "qcom,qcs8300-nspa-noc"; 6127 reg = <0x0 0x260c0000 0x0 0x16080>; 6128 #interconnect-cells = <2>; 6129 qcom,bcm-voters = <&apps_bcm_voter>; 6130 }; 6131 6132 remoteproc_cdsp: remoteproc@26300000 { 6133 compatible = "qcom,qcs8300-cdsp-pas", "qcom,sa8775p-cdsp0-pas"; 6134 reg = <0x0 0x26300000 0x0 0x10000>; 6135 6136 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 6137 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 6138 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 6139 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 6140 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 6141 interrupt-names = "wdog", 6142 "fatal", 6143 "ready", 6144 "handover", 6145 "stop-ack"; 6146 6147 clocks = <&rpmhcc RPMH_CXO_CLK>; 6148 clock-names = "xo"; 6149 6150 power-domains = <&rpmhpd RPMHPD_CX>, 6151 <&rpmhpd RPMHPD_MXC>, 6152 <&rpmhpd RPMHPD_NSP0>; 6153 6154 power-domain-names = "cx", 6155 "mxc", 6156 "nsp"; 6157 6158 interconnects = <&nspa_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 6159 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 6160 6161 memory-region = <&cdsp_mem>; 6162 6163 qcom,qmp = <&aoss_qmp>; 6164 6165 qcom,smem-states = <&smp2p_cdsp_out 0>; 6166 qcom,smem-state-names = "stop"; 6167 6168 status = "disabled"; 6169 6170 glink-edge { 6171 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 6172 IPCC_MPROC_SIGNAL_GLINK_QMP 6173 IRQ_TYPE_EDGE_RISING>; 6174 mboxes = <&ipcc IPCC_CLIENT_CDSP 6175 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6176 6177 label = "cdsp"; 6178 qcom,remote-pid = <5>; 6179 6180 fastrpc { 6181 compatible = "qcom,fastrpc"; 6182 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6183 label = "cdsp"; 6184 #address-cells = <1>; 6185 #size-cells = <0>; 6186 6187 compute-cb@1 { 6188 compatible = "qcom,fastrpc-compute-cb"; 6189 reg = <1>; 6190 iommus = <&apps_smmu 0x19c1 0x0440>, 6191 <&apps_smmu 0x1961 0x0400>; 6192 dma-coherent; 6193 }; 6194 6195 compute-cb@2 { 6196 compatible = "qcom,fastrpc-compute-cb"; 6197 reg = <2>; 6198 iommus = <&apps_smmu 0x19c2 0x0440>, 6199 <&apps_smmu 0x1962 0x0400>; 6200 dma-coherent; 6201 }; 6202 6203 compute-cb@3 { 6204 compatible = "qcom,fastrpc-compute-cb"; 6205 reg = <3>; 6206 iommus = <&apps_smmu 0x19c3 0x0440>, 6207 <&apps_smmu 0x1963 0x0400>; 6208 dma-coherent; 6209 }; 6210 6211 compute-cb@4 { 6212 compatible = "qcom,fastrpc-compute-cb"; 6213 reg = <4>; 6214 iommus = <&apps_smmu 0x19c4 0x0440>, 6215 <&apps_smmu 0x1964 0x0400>; 6216 dma-coherent; 6217 }; 6218 }; 6219 }; 6220 }; 6221 }; 6222 6223 timer { 6224 compatible = "arm,armv8-timer"; 6225 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6226 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6227 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6228 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6229 }; 6230}; 6231