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/linux/drivers/iommu/
H A Dmsm_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
13 #include <linux/io-pgtable.h>
18 #include <linux/iommu.h>
25 #include "msm_iommu_hw-8xxx.h"
54 static int __enable_clocks(struct msm_iommu_dev *iommu) in __enable_clocks() argument
58 ret = clk_enable(iommu->pclk); in __enable_clocks()
62 if (iommu->clk) { in __enable_clocks()
63 ret = clk_enable(iommu->clk); in __enable_clocks()
65 clk_disable(iommu->pclk); in __enable_clocks()
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H A Dmtk_iommu_v1.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for MTK architected m4u v1 implementations
5 * Copyright (c) 2015-2016 MediaTek Inc.
8 * Based on driver/iommu/mtk_iommu.c
14 #include <linux/dma-mapping.h>
18 #include <linux/iommu.h>
30 #include <dt-bindings/memory/mtk-memory-port.h>
31 #include <dt-bindings/memory/mt2701-larb-port.h>
35 #include <asm/dma-iommu.h>
38 #define arm_iommu_attach_device(...) -ENODEV
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H A Dsprd-iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Unisoc IOMMU driver
11 #include <linux/dma-mapping.h>
13 #include <linux/iommu.h>
52 * struct sprd_iommu_device - high-level sprd IOMMU device representation,
55 * @ver: sprd IOMMU IP version
56 * @prot_page_va: protect page base virtual address
57 * @prot_page_pa: protect page base physical address, data would be
59 * @base: mapped base address for accessing registers
61 * @iommu: IOMMU core representation
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H A Dsun50i-iommu.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 // Copyright (C) 2016-2018, Allwinner Technology CO., LTD.
3 // Copyright (C) 2019-2020, Cerno
9 #include <linux/dma-direction.h>
10 #include <linux/dma-mapping.h>
14 #include <linux/iommu.h>
29 #include "iommu-pages.h"
101 struct iommu_device iommu; member
103 /* Lock to modify the IOMMU registers */
107 void __iomem *base; member
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H A Dmtk_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
6 #include <linux/arm-smccc.h>
15 #include <linux/iommu.h>
17 #include <linux/io-pgtable.h>
36 #include <dt-bindings/memory/mtk-memory-port.h>
138 #define STD_AXI_MODE BIT(12) /* For non MM iommu */
139 /* 2 bits: iommu type */
143 /* PM and clock always on. e.g. infra iommu */
152 ((((pdata)->flags) & (mask)) == (_x))
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H A Drockchip-iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for Rockchip
5 * Module Authors: Simon Xue <xxm@rock-chips.com>
13 #include <linux/dma-mapping.h>
17 #include <linux/iommu.h>
30 #include "iommu-pages.h"
39 #define RK_MMU_INT_CLEAR 0x18 /* Acknowledge and re-arm irq */
63 #define RK_MMU_CMD_DISABLE_STALL 3 /* Stop stall re-enables paging */
96 /* list of clocks required by IOMMU */
117 struct iommu_device iommu; member
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/linux/arch/sparc/kernel/
H A Diommu.c1 // SPDX-License-Identifier: GPL-2.0
2 /* iommu.c: Generic sparc64 IOMMU support.
13 #include <linux/dma-map-ops.h>
15 #include <linux/iommu-helper.h>
17 #include <asm/iommu-common.h>
23 #include <asm/iommu.h>
29 ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
31 (*((STC)->strbuf_flushflag) = 0UL)
33 (*((STC)->strbuf_flushflag) != 0UL)
49 /* Must be invoked under the IOMMU lock. */
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H A Dpci_psycho.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <asm/iommu.h>
61 /* Helper function of IOMMU error checking, which checks out
62 * the state of the streaming buffers. The IOMMU lock is
90 * interrogate the IOMMU state to see if it is the cause.
99 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
100 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
101 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
102 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
103 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
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H A Dpsycho_common.c1 // SPDX-License-Identifier: GPL-2.0
39 struct strbuf *strbuf = &pbm->stc; in psycho_check_stc_error()
43 if (!strbuf->strbuf_control) in psycho_check_stc_error()
46 err_base = strbuf->strbuf_err_stat; in psycho_check_stc_error()
47 tag_base = strbuf->strbuf_tag_diag; in psycho_check_stc_error()
48 line_base = strbuf->strbuf_line_diag; in psycho_check_stc_error()
55 * before re-enabling the streaming buffer. If any dirty data in psycho_check_stc_error()
60 control = upa_readq(strbuf->strbuf_control); in psycho_check_stc_error()
61 upa_writeq(control | PSYCHO_STRBUF_CTRL_DENAB, strbuf->strbuf_control); in psycho_check_stc_error()
77 upa_writeq(control, strbuf->strbuf_control); in psycho_check_stc_error()
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H A Dpci_schizo.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <asm/iommu.h>
49 /* IOMMU control register. */
56 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
57 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
58 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
59 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
60 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
61 #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
62 #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
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H A Dpci_fire.c1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_fire.c: Sun4u platform PCI-E controller support.
33 struct iommu *iommu = pbm->iommu; in pci_fire_pbm_iommu_init() local
38 /* No virtual-dma property on these guys, use largest size. */ in pci_fire_pbm_iommu_init()
39 vdma[0] = 0xc0000000; /* base */ in pci_fire_pbm_iommu_init()
45 iommu->iommu_control = pbm->pbm_regs + FIRE_IOMMU_CONTROL; in pci_fire_pbm_iommu_init()
46 iommu->iommu_tsbbase = pbm->pbm_regs + FIRE_IOMMU_TSBBASE; in pci_fire_pbm_iommu_init()
47 iommu->iommu_flush = pbm->pbm_regs + FIRE_IOMMU_FLUSH; in pci_fire_pbm_iommu_init()
48 iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV; in pci_fire_pbm_iommu_init()
53 iommu->write_complete_reg = pbm->controller_regs + 0x410000UL; in pci_fire_pbm_iommu_init()
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H A Dldc.c1 // SPDX-License-Identifier: GPL-2.0
2 /* ldc.c: Logical Domain Channel link-layer protocol driver.
19 #include <asm/iommu-common.h>
22 #include <asm/iommu.h>
40 * When in RAW mode, packets are simply straight 64-byte payloads
70 u8 u_data[LDC_PACKET_SIZE - 8];
74 u8 r_data[LDC_PACKET_SIZE - 8 - 8];
146 struct ldc_iommu iommu; member
177 do { if (lp->cfg.debug & LDC_DEBUG_##TYPE) \
178 printk(KERN_INFO PFX "ID[%lu] " f, lp->id, ## a); \
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H A Dpci_impl.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 #include <asm/iommu.h>
20 * underneath. Each PCI bus module uses an IOMMU (shared by both
21 * PBMs of a controller, or per-PBM), and if a streaming buffer
22 * is present, each PCI bus module has its own. (ie. the IOMMU
29 (*((STC)->strbuf_flushflag) = 0UL)
31 (*((STC)->strbuf_flushflag) != 0UL)
65 /* Physical address base of controller registers. */
68 /* Physical address base of PBM registers. */
74 /* Opaque 32-bit system bus Port ID. */
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/linux/Documentation/ABI/testing/
H A Ddebugfs-intel-iommu1 What: /sys/kernel/debug/iommu/intel/iommu_regset
5 This file dumps all the register contents for each IOMMU device.
11 $ sudo cat /sys/kernel/debug/iommu/intel/iommu_regset
13 IOMMU: dmar0 Register Base Address: 26be37000
24 IOMMU: dmar1 Register Base Address: fed90000
35 IOMMU: dmar2 Register Base Address: fed91000
46 What: /sys/kernel/debug/iommu/intel/ir_translation_struct
57 $ sudo cat /sys/kernel/debug/iommu/intel/ir_translation_struct
59 Remapped Interrupt supported on IOMMU: dmar0
66 Remapped Interrupt supported on IOMMU: dmar1
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/linux/Documentation/devicetree/bindings/misc/
H A Dfsl,qoriq-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
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/linux/drivers/gpu/drm/msm/
H A Dmsm_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
8 #include <linux/io-pgtable.h>
15 struct msm_mmu base; member
25 #define to_msm_iommu(x) container_of(x, struct msm_iommu, base)
28 struct msm_mmu base; member
42 return container_of(mmu, struct msm_iommu_pagetable, base); in to_pagetable()
45 /* based on iommu_pgsize() in iommu.c: */
56 pgsizes = pagetable->pgsize_bitmap & GENMASK(__fls(size), 0); in calc_pgsize()
72 pgsizes = pagetable->pgsize_bitmap & ~GENMASK(pgsize_idx, 0); in calc_pgsize()
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
H A Dgk20a.c30 * 1) If an IOMMU unit has been probed, the IOMMU API is used to make memory
32 * 2) If no IOMMU unit is probed, the DMA API is used to allocate physically
35 * In both cases CPU read and writes are performed by creating a write-combined
52 struct nvkm_instobj base; member
59 #define gk20a_instobj(p) container_of((p), struct gk20a_instobj, base.memory)
65 struct gk20a_instobj base; member
71 container_of(gk20a_instobj(p), struct gk20a_instobj_dma, base)
74 * Used for objects flattened using the IOMMU API
77 struct gk20a_instobj base; member
86 /* array of base.mem->size pages (+ dma_addr_ts) */
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/linux/Documentation/arch/x86/
H A Diommu.rst2 x86 IOMMU Support
7 - Intel: http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-dire…
8 - AMD: https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_3_…
13 -----------
16 device scope relationships between devices and which IOMMU controls
21 - DMAR - Intel DMA Remapping table
22 - DRHD - Intel DMA Remapping Hardware Unit Definition
23 - RMRR - Intel Reserved Memory Region Reporting Structure
24 - IVRS - AMD I/O Virtualization Reporting Structure
25 - IVDB - AMD I/O Virtualization Definition Block
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/linux/drivers/iommu/intel/
H A Dirq_remapping.c1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "DMAR-IR: " fmt
13 #include <linux/irqchip/irq-msi-lib.h>
22 #include <asm/pci-direct.h>
25 #include "iommu.h"
27 #include "../iommu-pages.h"
30 struct intel_iommu *iommu; member
37 struct intel_iommu *iommu; member
44 struct intel_iommu *iommu; member
69 * ->dmar_global_lock
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/linux/drivers/iommu/arm/arm-smmu/
H A Dqcom_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
13 #include <linux/dma-mapping.h>
17 #include <linux/io-64-nonatomic-hi-lo.h>
18 #include <linux/io-pgtable.h>
19 #include <linux/iommu.h>
33 #include "arm-smmu.h"
47 /* IOMMU core code handle */
48 struct iommu_device iommu; member
59 void __iomem *base; member
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/linux/Documentation/devicetree/bindings/pci/
H A Dpci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/pci-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 - Kishon Vijay Abraham I <kishon@kernel.org>
14 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 pattern: "^pcie-ep@"
20 iommu-map:
21 $ref: /schemas/types.yaml#/definitions/uint32-matrix
24 - description: Device ID (see msi-map) base
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/linux/arch/sparc/include/asm/
H A Diommu_64.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* iommu.h: Definitions for the sun5 IOMMU.
20 #include <asm/iommu-common.h>
32 void *table; /* IOTSB table base virtual addr*/
35 u64 dvma_base; /* ranges[3].base */
42 u64 base; member
50 u64 base; member
55 struct iommu { struct
86 volatile unsigned long __flushflag_buf[(64+(64-1)) / sizeof(long)];
89 int iommu_table_init(struct iommu *iommu, int tsbsize, argument
H A Diommu_32.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* iommu.h: Definitions for the sun4m IOMMU.
12 /* The iommu handles all virtual to physical address translations
15 * translated by the on chip SRMMU. The iommu and the srmmu do
18 * Basically the iommu handles all dvma sbus activity.
21 /* The IOMMU registers occupy three pages in IO space. */
24 volatile unsigned long control; /* IOMMU control */
25 volatile unsigned long base; /* Physical base of iopte page table */ member
31 volatile unsigned long afsr; /* Async-fault status register */
32 volatile unsigned long afar; /* Async-fault physical address */
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/linux/arch/sparc/mm/
H A Diommu.c1 // SPDX-License-Identifier: GPL-2.0
3 * iommu.c: IOMMU specific routines for memory management.
15 #include <linux/dma-map-ops.h>
26 #include <asm/iommu.h>
60 struct iommu_struct *iommu; in sbus_iommu_init() local
64 unsigned long base; in sbus_iommu_init() local
67 iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL); in sbus_iommu_init()
68 if (!iommu) { in sbus_iommu_init()
69 prom_printf("Unable to allocate iommu structure\n"); in sbus_iommu_init()
73 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3, in sbus_iommu_init()
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/linux/arch/powerpc/sysdev/
H A Ddart_iommu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 * Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu.
22 #include <linux/dma-mapping.h>
29 #include <asm/iommu.h>
30 #include <asm/pci-bridge.h>
33 #include <asm/ppc-pci.h>
41 /* Mapped base address for the dart */
134 static void dart_cache_sync(unsigned int *base, unsigned int count) in dart_cache_sync() argument
141 unsigned long start = (unsigned long)base; in dart_cache_sync()
182 orig_dp = dp = ((unsigned int*)tbl->it_base) + index; in dart_build()
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