11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
20df4fabeSYong Wu /*
30df4fabeSYong Wu * Copyright (c) 2015-2016 MediaTek Inc.
40df4fabeSYong Wu * Author: Yong Wu <yong.wu@mediatek.com>
50df4fabeSYong Wu */
6946e719cSChengci.Xu #include <linux/arm-smccc.h>
7ef0f0986SYong Wu #include <linux/bitfield.h>
80df4fabeSYong Wu #include <linux/bug.h>
90df4fabeSYong Wu #include <linux/clk.h>
100df4fabeSYong Wu #include <linux/component.h>
110df4fabeSYong Wu #include <linux/device.h>
120df4fabeSYong Wu #include <linux/err.h>
130df4fabeSYong Wu #include <linux/interrupt.h>
140df4fabeSYong Wu #include <linux/io.h>
150df4fabeSYong Wu #include <linux/iommu.h>
160df4fabeSYong Wu #include <linux/iopoll.h>
176a513de3SYong Wu #include <linux/io-pgtable.h>
180df4fabeSYong Wu #include <linux/list.h>
19c2c59456SMiles Chen #include <linux/mfd/syscon.h>
2018d8c74eSYong Wu #include <linux/module.h>
210df4fabeSYong Wu #include <linux/of_address.h>
220df4fabeSYong Wu #include <linux/of_irq.h>
230df4fabeSYong Wu #include <linux/of_platform.h>
24e7629070SYong Wu #include <linux/pci.h>
250df4fabeSYong Wu #include <linux/platform_device.h>
26baf94e6eSYong Wu #include <linux/pm_runtime.h>
27c2c59456SMiles Chen #include <linux/regmap.h>
280df4fabeSYong Wu #include <linux/slab.h>
290df4fabeSYong Wu #include <linux/spinlock.h>
30c2c59456SMiles Chen #include <linux/soc/mediatek/infracfg.h>
31946e719cSChengci.Xu #include <linux/soc/mediatek/mtk_sip_svc.h>
320df4fabeSYong Wu #include <asm/barrier.h>
330df4fabeSYong Wu #include <soc/mediatek/smi.h>
340df4fabeSYong Wu
356a513de3SYong Wu #include <dt-bindings/memory/mtk-memory-port.h>
360df4fabeSYong Wu
370df4fabeSYong Wu #define REG_MMU_PT_BASE_ADDR 0x000
380df4fabeSYong Wu
390df4fabeSYong Wu #define REG_MMU_INVALIDATE 0x020
400df4fabeSYong Wu #define F_ALL_INVLD 0x2
410df4fabeSYong Wu #define F_MMU_INV_RANGE 0x1
420df4fabeSYong Wu
430df4fabeSYong Wu #define REG_MMU_INVLD_START_A 0x024
440df4fabeSYong Wu #define REG_MMU_INVLD_END_A 0x028
450df4fabeSYong Wu
46068c86e9SChao Hao #define REG_MMU_INV_SEL_GEN2 0x02c
47b053bc71SChao Hao #define REG_MMU_INV_SEL_GEN1 0x038
480df4fabeSYong Wu #define F_INVLD_EN0 BIT(0)
490df4fabeSYong Wu #define F_INVLD_EN1 BIT(1)
500df4fabeSYong Wu
5175eed350SChao Hao #define REG_MMU_MISC_CTRL 0x048
524bb2bf4cSChao Hao #define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17))
534bb2bf4cSChao Hao #define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19))
544bb2bf4cSChao Hao
550df4fabeSYong Wu #define REG_MMU_DCM_DIS 0x050
569a87005eSYong Wu #define F_MMU_DCM BIT(8)
579a87005eSYong Wu
5835c1b48dSChao Hao #define REG_MMU_WR_LEN_CTRL 0x054
5935c1b48dSChao Hao #define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21))
600df4fabeSYong Wu
610df4fabeSYong Wu #define REG_MMU_CTRL_REG 0x110
62acb3c92aSYong Wu #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4)
630df4fabeSYong Wu #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4)
64acb3c92aSYong Wu #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5)
650df4fabeSYong Wu
660df4fabeSYong Wu #define REG_MMU_IVRP_PADDR 0x114
6770ca608bSYong Wu
6830e2fccfSYong Wu #define REG_MMU_VLD_PA_RNG 0x118
6930e2fccfSYong Wu #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA))
700df4fabeSYong Wu
710df4fabeSYong Wu #define REG_MMU_INT_CONTROL0 0x120
720df4fabeSYong Wu #define F_L2_MULIT_HIT_EN BIT(0)
730df4fabeSYong Wu #define F_TABLE_WALK_FAULT_INT_EN BIT(1)
740df4fabeSYong Wu #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2)
750df4fabeSYong Wu #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3)
760df4fabeSYong Wu #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5)
770df4fabeSYong Wu #define F_MISS_FIFO_ERR_INT_EN BIT(6)
780df4fabeSYong Wu #define F_INT_CLR_BIT BIT(12)
790df4fabeSYong Wu
800df4fabeSYong Wu #define REG_MMU_INT_MAIN_CONTROL 0x124
8115a01f4cSYong Wu /* mmu0 | mmu1 */
8215a01f4cSYong Wu #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7))
8315a01f4cSYong Wu #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8))
8415a01f4cSYong Wu #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9))
8515a01f4cSYong Wu #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10))
8615a01f4cSYong Wu #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11))
8715a01f4cSYong Wu #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12))
8815a01f4cSYong Wu #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13))
890df4fabeSYong Wu
900df4fabeSYong Wu #define REG_MMU_CPE_DONE 0x12C
910df4fabeSYong Wu
920df4fabeSYong Wu #define REG_MMU_FAULT_ST1 0x134
9315a01f4cSYong Wu #define F_REG_MMU0_FAULT_MASK GENMASK(6, 0)
9415a01f4cSYong Wu #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7)
950df4fabeSYong Wu
9615a01f4cSYong Wu #define REG_MMU0_FAULT_VA 0x13c
97ef0f0986SYong Wu #define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12)
98ef0f0986SYong Wu #define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9)
99ef0f0986SYong Wu #define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6)
1000df4fabeSYong Wu #define F_MMU_FAULT_VA_WRITE_BIT BIT(1)
1010df4fabeSYong Wu #define F_MMU_FAULT_VA_LAYER_BIT BIT(0)
1020df4fabeSYong Wu
10315a01f4cSYong Wu #define REG_MMU0_INVLD_PA 0x140
10415a01f4cSYong Wu #define REG_MMU1_FAULT_VA 0x144
10515a01f4cSYong Wu #define REG_MMU1_INVLD_PA 0x148
10615a01f4cSYong Wu #define REG_MMU0_INT_ID 0x150
10715a01f4cSYong Wu #define REG_MMU1_INT_ID 0x154
10837276e00SChao Hao #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7)
10937276e00SChao Hao #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3)
1109ec30c09SYong Wu #define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7)
1119ec30c09SYong Wu #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7)
11265df7d82SFabien Parent /* Macro for 5 bits length port ID field (default) */
11315a01f4cSYong Wu #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
11415a01f4cSYong Wu #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
11565df7d82SFabien Parent /* Macro for 6 bits length port ID field */
11665df7d82SFabien Parent #define F_MMU_INT_ID_LARB_ID_WID_6(a) (((a) >> 8) & 0x7)
11765df7d82SFabien Parent #define F_MMU_INT_ID_PORT_ID_WID_6(a) (((a) >> 2) & 0x3f)
1180df4fabeSYong Wu
119829316b3SChao Hao #define MTK_PROTECT_PA_ALIGN 256
12042d57fc5SYong Wu #define MTK_IOMMU_BANK_SZ 0x1000
1210df4fabeSYong Wu
122f9b8c9b2SYong Wu #define PERICFG_IOMMU_1 0x714
123f9b8c9b2SYong Wu
1246b717796SChao Hao #define HAS_4GB_MODE BIT(0)
1256b717796SChao Hao /* HW will use the EMI clock if there isn't the "bclk". */
1266b717796SChao Hao #define HAS_BCLK BIT(1)
1276b717796SChao Hao #define HAS_VLD_PA_RNG BIT(2)
1286b717796SChao Hao #define RESET_AXI BIT(3)
1294bb2bf4cSChao Hao #define OUT_ORDER_WR_EN BIT(4)
1309ec30c09SYong Wu #define HAS_SUB_COMM_2BITS BIT(5)
1319ec30c09SYong Wu #define HAS_SUB_COMM_3BITS BIT(6)
1329ec30c09SYong Wu #define WR_THROT_EN BIT(7)
1339ec30c09SYong Wu #define HAS_LEGACY_IVRP_PADDR BIT(8)
1349ec30c09SYong Wu #define IOVA_34_EN BIT(9)
1359ec30c09SYong Wu #define SHARE_PGTABLE BIT(10) /* 2 HW share pgtable */
1369ec30c09SYong Wu #define DCM_DISABLE BIT(11)
1379ec30c09SYong Wu #define STD_AXI_MODE BIT(12) /* For non MM iommu */
1388cd1e619SYong Wu /* 2 bits: iommu type */
1398cd1e619SYong Wu #define MTK_IOMMU_TYPE_MM (0x0 << 13)
1408cd1e619SYong Wu #define MTK_IOMMU_TYPE_INFRA (0x1 << 13)
1418cd1e619SYong Wu #define MTK_IOMMU_TYPE_MASK (0x3 << 13)
1426077c7e5SYong Wu /* PM and clock always on. e.g. infra iommu */
1436077c7e5SYong Wu #define PM_CLK_AO BIT(15)
144e7629070SYong Wu #define IFA_IOMMU_PCIE_SUPPORT BIT(16)
145301c3ca1SYunfei Wang #define PGTABLE_PA_35_EN BIT(17)
14686580ec9SAngeloGioacchino Del Regno #define TF_PORT_TO_ADDR_MT8173 BIT(18)
14765df7d82SFabien Parent #define INT_ID_PORT_WIDTH_6 BIT(19)
148946e719cSChengci.Xu #define CFG_IFA_MASTER_IN_ATF BIT(20)
1496b717796SChao Hao
1508cd1e619SYong Wu #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \
1518cd1e619SYong Wu ((((pdata)->flags) & (mask)) == (_x))
1528cd1e619SYong Wu
1538cd1e619SYong Wu #define MTK_IOMMU_HAS_FLAG(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, _x)
1548cd1e619SYong Wu #define MTK_IOMMU_IS_TYPE(pdata, _x) MTK_IOMMU_HAS_FLAG_MASK(pdata, _x,\
1558cd1e619SYong Wu MTK_IOMMU_TYPE_MASK)
1566b717796SChao Hao
157d2e9a110SYong Wu #define MTK_INVALID_LARBID MTK_LARB_NR_MAX
158d2e9a110SYong Wu
1599485a04aSYong Wu #define MTK_LARB_COM_MAX 8
1609485a04aSYong Wu #define MTK_LARB_SUBCOM_MAX 8
1619485a04aSYong Wu
1629485a04aSYong Wu #define MTK_IOMMU_GROUP_MAX 8
16399ca0228SYong Wu #define MTK_IOMMU_BANK_MAX 5
1649485a04aSYong Wu
1659485a04aSYong Wu enum mtk_iommu_plat {
1669485a04aSYong Wu M4U_MT2712,
1679485a04aSYong Wu M4U_MT6779,
168717ec15eSAngeloGioacchino Del Regno M4U_MT6795,
1699485a04aSYong Wu M4U_MT8167,
1709485a04aSYong Wu M4U_MT8173,
1719485a04aSYong Wu M4U_MT8183,
172e8d7ccaaSYong Wu M4U_MT8186,
173a09e8403SChengci.Xu M4U_MT8188,
1749485a04aSYong Wu M4U_MT8192,
1759485a04aSYong Wu M4U_MT8195,
1763cd0e4a3SFabien Parent M4U_MT8365,
1779485a04aSYong Wu };
1789485a04aSYong Wu
1799485a04aSYong Wu struct mtk_iommu_iova_region {
1809485a04aSYong Wu dma_addr_t iova_base;
1819485a04aSYong Wu unsigned long long size;
1829485a04aSYong Wu };
1839485a04aSYong Wu
1846a513de3SYong Wu struct mtk_iommu_suspend_reg {
1856a513de3SYong Wu u32 misc_ctrl;
1866a513de3SYong Wu u32 dcm_dis;
1876a513de3SYong Wu u32 ctrl_reg;
1886a513de3SYong Wu u32 vld_pa_rng;
1896a513de3SYong Wu u32 wr_len_ctrl;
190d7127de1SYong Wu
191d7127de1SYong Wu u32 int_control[MTK_IOMMU_BANK_MAX];
192d7127de1SYong Wu u32 int_main_control[MTK_IOMMU_BANK_MAX];
193d7127de1SYong Wu u32 ivrp_paddr[MTK_IOMMU_BANK_MAX];
1946a513de3SYong Wu };
1956a513de3SYong Wu
1969485a04aSYong Wu struct mtk_iommu_plat_data {
1979485a04aSYong Wu enum mtk_iommu_plat m4u_plat;
1989485a04aSYong Wu u32 flags;
1999485a04aSYong Wu u32 inv_sel_reg;
2009485a04aSYong Wu
2019485a04aSYong Wu char *pericfg_comp_str;
2029485a04aSYong Wu struct list_head *hw_list;
203ae669345SYong Wu
204ae669345SYong Wu /*
205ae669345SYong Wu * The IOMMU HW may support 16GB iova. In order to balance the IOVA ranges,
206ae669345SYong Wu * different masters will be put in different iova ranges, for example vcodec
207ae669345SYong Wu * is in 4G-8G and cam is in 8G-12G. Meanwhile, some masters may have the
208ae669345SYong Wu * special IOVA range requirement, like CCU can only support the address
209ae669345SYong Wu * 0x40000000-0x44000000.
210ae669345SYong Wu * Here list the iova ranges this SoC supports and which larbs/ports are in
211ae669345SYong Wu * which region.
212ae669345SYong Wu *
213ae669345SYong Wu * 16GB iova all use one pgtable, but each a region is a iommu group.
214ae669345SYong Wu */
215ae669345SYong Wu struct {
2169485a04aSYong Wu unsigned int iova_region_nr;
2179485a04aSYong Wu const struct mtk_iommu_iova_region *iova_region;
218b2a6876dSYong Wu /*
219b2a6876dSYong Wu * Indicate the correspondance between larbs, ports and regions.
220b2a6876dSYong Wu *
221b2a6876dSYong Wu * The index is the same as iova_region and larb port numbers are
222b2a6876dSYong Wu * described as bit positions.
223b2a6876dSYong Wu * For example, storing BIT(0) at index 2,1 means "larb 1, port0 is in region 2".
224b2a6876dSYong Wu * [2] = { [1] = BIT(0) }
225b2a6876dSYong Wu */
226b2a6876dSYong Wu const u32 (*iova_region_larb_msk)[MTK_LARB_NR_MAX];
227ae669345SYong Wu };
22899ca0228SYong Wu
229ae669345SYong Wu /*
230ae669345SYong Wu * The IOMMU HW may have 5 banks. Each bank has a independent pgtable.
231ae669345SYong Wu * Here list how many banks this SoC supports/enables and which ports are in which bank.
232ae669345SYong Wu */
233ae669345SYong Wu struct {
23499ca0228SYong Wu u8 banks_num;
23599ca0228SYong Wu bool banks_enable[MTK_IOMMU_BANK_MAX];
23657fb481fSYong Wu unsigned int banks_portmsk[MTK_IOMMU_BANK_MAX];
237ae669345SYong Wu };
238ae669345SYong Wu
2399485a04aSYong Wu unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
2409485a04aSYong Wu };
2419485a04aSYong Wu
24299ca0228SYong Wu struct mtk_iommu_bank_data {
2439485a04aSYong Wu void __iomem *base;
2449485a04aSYong Wu int irq;
24599ca0228SYong Wu u8 id;
24699ca0228SYong Wu struct device *parent_dev;
24799ca0228SYong Wu struct mtk_iommu_data *parent_data;
24899ca0228SYong Wu spinlock_t tlb_lock; /* lock for tlb range flush */
24999ca0228SYong Wu struct mtk_iommu_domain *m4u_dom; /* Each bank has a domain */
25099ca0228SYong Wu };
25199ca0228SYong Wu
25299ca0228SYong Wu struct mtk_iommu_data {
2539485a04aSYong Wu struct device *dev;
2549485a04aSYong Wu struct clk *bclk;
2559485a04aSYong Wu phys_addr_t protect_base; /* protect memory base */
2569485a04aSYong Wu struct mtk_iommu_suspend_reg reg;
2579485a04aSYong Wu struct iommu_group *m4u_group[MTK_IOMMU_GROUP_MAX];
2589485a04aSYong Wu bool enable_4GB;
2599485a04aSYong Wu
2609485a04aSYong Wu struct iommu_device iommu;
2619485a04aSYong Wu const struct mtk_iommu_plat_data *plat_data;
2629485a04aSYong Wu struct device *smicomm_dev;
2639485a04aSYong Wu
26499ca0228SYong Wu struct mtk_iommu_bank_data *bank;
265b07eba71SYong Wu struct mtk_iommu_domain *share_dom;
266cf69ef46SChengci.Xu
2679485a04aSYong Wu struct regmap *pericfg;
2689485a04aSYong Wu struct mutex mutex; /* Protect m4u_group/m4u_dom above */
2699485a04aSYong Wu
2709485a04aSYong Wu /*
2719485a04aSYong Wu * In the sharing pgtable case, list data->list to the global list like m4ulist.
2729485a04aSYong Wu * In the non-sharing pgtable case, list data->list to the itself hw_list_head.
2739485a04aSYong Wu */
2749485a04aSYong Wu struct list_head *hw_list;
2759485a04aSYong Wu struct list_head hw_list_head;
2769485a04aSYong Wu struct list_head list;
2779485a04aSYong Wu struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
2789485a04aSYong Wu };
2799485a04aSYong Wu
2800df4fabeSYong Wu struct mtk_iommu_domain {
2810df4fabeSYong Wu struct io_pgtable_cfg cfg;
2820df4fabeSYong Wu struct io_pgtable_ops *iop;
2830df4fabeSYong Wu
28499ca0228SYong Wu struct mtk_iommu_bank_data *bank;
2850df4fabeSYong Wu struct iommu_domain domain;
286ddf67a87SYong Wu
287ddf67a87SYong Wu struct mutex mutex; /* Protect "data" in this structure */
2880df4fabeSYong Wu };
2890df4fabeSYong Wu
mtk_iommu_bind(struct device * dev)2909485a04aSYong Wu static int mtk_iommu_bind(struct device *dev)
2919485a04aSYong Wu {
2929485a04aSYong Wu struct mtk_iommu_data *data = dev_get_drvdata(dev);
2939485a04aSYong Wu
2949485a04aSYong Wu return component_bind_all(dev, &data->larb_imu);
2959485a04aSYong Wu }
2969485a04aSYong Wu
mtk_iommu_unbind(struct device * dev)2979485a04aSYong Wu static void mtk_iommu_unbind(struct device *dev)
2989485a04aSYong Wu {
2999485a04aSYong Wu struct mtk_iommu_data *data = dev_get_drvdata(dev);
3009485a04aSYong Wu
3019485a04aSYong Wu component_unbind_all(dev, &data->larb_imu);
3029485a04aSYong Wu }
3039485a04aSYong Wu
304b65f5016SArvind Yadav static const struct iommu_ops mtk_iommu_ops;
3050df4fabeSYong Wu
306e24453e1SYong Wu static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid);
3077f37a91dSYong Wu
308bfed8731SYong Wu #define MTK_IOMMU_TLB_ADDR(iova) ({ \
309bfed8731SYong Wu dma_addr_t _addr = iova; \
310bfed8731SYong Wu ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\
311bfed8731SYong Wu })
312bfed8731SYong Wu
31376ce6546SYong Wu /*
31476ce6546SYong Wu * In M4U 4GB mode, the physical address is remapped as below:
31576ce6546SYong Wu *
31676ce6546SYong Wu * CPU Physical address:
31776ce6546SYong Wu * ====================
31876ce6546SYong Wu *
31976ce6546SYong Wu * 0 1G 2G 3G 4G 5G
32076ce6546SYong Wu * |---A---|---B---|---C---|---D---|---E---|
32176ce6546SYong Wu * +--I/O--+------------Memory-------------+
32276ce6546SYong Wu *
32376ce6546SYong Wu * IOMMU output physical address:
32476ce6546SYong Wu * =============================
32576ce6546SYong Wu *
32676ce6546SYong Wu * 4G 5G 6G 7G 8G
32776ce6546SYong Wu * |---E---|---B---|---C---|---D---|
32876ce6546SYong Wu * +------------Memory-------------+
32976ce6546SYong Wu *
33076ce6546SYong Wu * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the
33176ce6546SYong Wu * bit32 of the CPU physical address always is needed to set, and for Region
33276ce6546SYong Wu * 'E', the CPU physical address keep as is.
33376ce6546SYong Wu * Additionally, The iommu consumers always use the CPU phyiscal address.
33476ce6546SYong Wu */
335b4dad40eSYong Wu #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL
33676ce6546SYong Wu
3377c3a2ec0SYong Wu static LIST_HEAD(m4ulist); /* List all the M4U HWs */
3387c3a2ec0SYong Wu
3399e3a2a64SYong Wu #define for_each_m4u(data, head) list_for_each_entry(data, head, list)
3407c3a2ec0SYong Wu
3413df9bdd4SYong Wu #define MTK_IOMMU_IOVA_SZ_4G (SZ_4G - SZ_8M) /* 8M as gap */
3423df9bdd4SYong Wu
343585e58f4SYong Wu static const struct mtk_iommu_iova_region single_domain[] = {
3443df9bdd4SYong Wu {.iova_base = 0, .size = MTK_IOMMU_IOVA_SZ_4G},
345585e58f4SYong Wu };
346585e58f4SYong Wu
3476b1317f9SYong Wu #define MT8192_MULTI_REGION_NR_MAX 6
3486b1317f9SYong Wu
3496b1317f9SYong Wu #define MT8192_MULTI_REGION_NR (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) ? \
3506b1317f9SYong Wu MT8192_MULTI_REGION_NR_MAX : 1)
3516b1317f9SYong Wu
3526b1317f9SYong Wu static const struct mtk_iommu_iova_region mt8192_multi_dom[MT8192_MULTI_REGION_NR] = {
3533df9bdd4SYong Wu { .iova_base = 0x0, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 0 ~ 4G, */
3549e3489e0SYong Wu #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)
3553df9bdd4SYong Wu { .iova_base = SZ_4G, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 4G ~ 8G */
3563df9bdd4SYong Wu { .iova_base = SZ_4G * 2, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 8G ~ 12G */
3573df9bdd4SYong Wu { .iova_base = SZ_4G * 3, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 12G ~ 16G */
358129a3b88SYong Wu
3599e3489e0SYong Wu { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */
3609e3489e0SYong Wu { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */
3619e3489e0SYong Wu #endif
3629e3489e0SYong Wu };
3639e3489e0SYong Wu
3649e3a2a64SYong Wu /* If 2 M4U share a domain(use the same hwlist), Put the corresponding info in first data.*/
mtk_iommu_get_frst_data(struct list_head * hwlist)3659e3a2a64SYong Wu static struct mtk_iommu_data *mtk_iommu_get_frst_data(struct list_head *hwlist)
3667c3a2ec0SYong Wu {
3679e3a2a64SYong Wu return list_first_entry(hwlist, struct mtk_iommu_data, list);
3687c3a2ec0SYong Wu }
3697c3a2ec0SYong Wu
to_mtk_domain(struct iommu_domain * dom)3700df4fabeSYong Wu static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
3710df4fabeSYong Wu {
3720df4fabeSYong Wu return container_of(dom, struct mtk_iommu_domain, domain);
3730df4fabeSYong Wu }
3740df4fabeSYong Wu
mtk_iommu_tlb_flush_all(struct mtk_iommu_data * data)3750954d61aSYong Wu static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
3760df4fabeSYong Wu {
37799ca0228SYong Wu /* Tlb flush all always is in bank0. */
37899ca0228SYong Wu struct mtk_iommu_bank_data *bank = &data->bank[0];
37999ca0228SYong Wu void __iomem *base = bank->base;
38015672b6dSYong Wu unsigned long flags;
381c0b57581SYong Wu
38299ca0228SYong Wu spin_lock_irqsave(&bank->tlb_lock, flags);
383887cf6a7SYong Wu writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg);
384887cf6a7SYong Wu writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE);
3850df4fabeSYong Wu wmb(); /* Make sure the tlb flush all done */
38699ca0228SYong Wu spin_unlock_irqrestore(&bank->tlb_lock, flags);
3877c3a2ec0SYong Wu }
3880df4fabeSYong Wu
mtk_iommu_tlb_flush_range_sync(unsigned long iova,size_t size,struct mtk_iommu_bank_data * bank)3891f4fd624SYong Wu static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
39099ca0228SYong Wu struct mtk_iommu_bank_data *bank)
3910df4fabeSYong Wu {
39299ca0228SYong Wu struct list_head *head = bank->parent_data->hw_list;
39399ca0228SYong Wu struct mtk_iommu_bank_data *curbank;
39499ca0228SYong Wu struct mtk_iommu_data *data;
3956077c7e5SYong Wu bool check_pm_status;
3961f4fd624SYong Wu unsigned long flags;
397887cf6a7SYong Wu void __iomem *base;
3981f4fd624SYong Wu int ret;
3991f4fd624SYong Wu u32 tmp;
4000df4fabeSYong Wu
4019e3a2a64SYong Wu for_each_m4u(data, head) {
4026077c7e5SYong Wu /*
4036077c7e5SYong Wu * To avoid resume the iommu device frequently when the iommu device
4046077c7e5SYong Wu * is not active, it doesn't always call pm_runtime_get here, then tlb
4056077c7e5SYong Wu * flush depends on the tlb flush all in the runtime resume.
4066077c7e5SYong Wu *
4076077c7e5SYong Wu * There are 2 special cases:
4086077c7e5SYong Wu *
4096077c7e5SYong Wu * Case1: The iommu dev doesn't have power domain but has bclk. This case
4106077c7e5SYong Wu * should also avoid the tlb flush while the dev is not active to mute
4116077c7e5SYong Wu * the tlb timeout log. like mt8173.
4126077c7e5SYong Wu *
4136077c7e5SYong Wu * Case2: The power/clock of infra iommu is always on, and it doesn't
4146077c7e5SYong Wu * have the device link with the master devices. This case should avoid
4156077c7e5SYong Wu * the PM status check.
4166077c7e5SYong Wu */
4176077c7e5SYong Wu check_pm_status = !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO);
4186077c7e5SYong Wu
4196077c7e5SYong Wu if (check_pm_status) {
420c0b57581SYong Wu if (pm_runtime_get_if_in_use(data->dev) <= 0)
421c0b57581SYong Wu continue;
4226077c7e5SYong Wu }
423c0b57581SYong Wu
42499ca0228SYong Wu curbank = &data->bank[bank->id];
42599ca0228SYong Wu base = curbank->base;
426887cf6a7SYong Wu
42799ca0228SYong Wu spin_lock_irqsave(&curbank->tlb_lock, flags);
4287c3a2ec0SYong Wu writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
429887cf6a7SYong Wu base + data->plat_data->inv_sel_reg);
4300df4fabeSYong Wu
431887cf6a7SYong Wu writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A);
432bfed8731SYong Wu writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1),
433887cf6a7SYong Wu base + REG_MMU_INVLD_END_A);
434887cf6a7SYong Wu writel_relaxed(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE);
4350df4fabeSYong Wu
4361f4fd624SYong Wu /* tlb sync */
437887cf6a7SYong Wu ret = readl_poll_timeout_atomic(base + REG_MMU_CPE_DONE,
438c90ae4a6SYong Wu tmp, tmp != 0, 10, 1000);
43915672b6dSYong Wu
44015672b6dSYong Wu /* Clear the CPE status */
441887cf6a7SYong Wu writel_relaxed(0, base + REG_MMU_CPE_DONE);
44299ca0228SYong Wu spin_unlock_irqrestore(&curbank->tlb_lock, flags);
44315672b6dSYong Wu
4440df4fabeSYong Wu if (ret) {
4450df4fabeSYong Wu dev_warn(data->dev,
4460df4fabeSYong Wu "Partial TLB flush timed out, falling back to full flush\n");
4470954d61aSYong Wu mtk_iommu_tlb_flush_all(data);
4480df4fabeSYong Wu }
449c0b57581SYong Wu
4506077c7e5SYong Wu if (check_pm_status)
451c0b57581SYong Wu pm_runtime_put(data->dev);
4520df4fabeSYong Wu }
4537c3a2ec0SYong Wu }
4540df4fabeSYong Wu
mtk_iommu_isr(int irq,void * dev_id)4550df4fabeSYong Wu static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
4560df4fabeSYong Wu {
45799ca0228SYong Wu struct mtk_iommu_bank_data *bank = dev_id;
45899ca0228SYong Wu struct mtk_iommu_data *data = bank->parent_data;
45999ca0228SYong Wu struct mtk_iommu_domain *dom = bank->m4u_dom;
460d2e9a110SYong Wu unsigned int fault_larb = MTK_INVALID_LARBID, fault_port = 0, sub_comm = 0;
461ef0f0986SYong Wu u32 int_state, regval, va34_32, pa34_32;
462887cf6a7SYong Wu const struct mtk_iommu_plat_data *plat_data = data->plat_data;
46399ca0228SYong Wu void __iomem *base = bank->base;
464ef0f0986SYong Wu u64 fault_iova, fault_pa;
4650df4fabeSYong Wu bool layer, write;
4660df4fabeSYong Wu
4670df4fabeSYong Wu /* Read error info from registers */
468887cf6a7SYong Wu int_state = readl_relaxed(base + REG_MMU_FAULT_ST1);
46915a01f4cSYong Wu if (int_state & F_REG_MMU0_FAULT_MASK) {
470887cf6a7SYong Wu regval = readl_relaxed(base + REG_MMU0_INT_ID);
471887cf6a7SYong Wu fault_iova = readl_relaxed(base + REG_MMU0_FAULT_VA);
472887cf6a7SYong Wu fault_pa = readl_relaxed(base + REG_MMU0_INVLD_PA);
47315a01f4cSYong Wu } else {
474887cf6a7SYong Wu regval = readl_relaxed(base + REG_MMU1_INT_ID);
475887cf6a7SYong Wu fault_iova = readl_relaxed(base + REG_MMU1_FAULT_VA);
476887cf6a7SYong Wu fault_pa = readl_relaxed(base + REG_MMU1_INVLD_PA);
47715a01f4cSYong Wu }
4780df4fabeSYong Wu layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
4790df4fabeSYong Wu write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
480887cf6a7SYong Wu if (MTK_IOMMU_HAS_FLAG(plat_data, IOVA_34_EN)) {
481ef0f0986SYong Wu va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova);
482ef0f0986SYong Wu fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK;
483ef0f0986SYong Wu fault_iova |= (u64)va34_32 << 32;
484ef0f0986SYong Wu }
48582e51771SYong Wu pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova);
48682e51771SYong Wu fault_pa |= (u64)pa34_32 << 32;
487ef0f0986SYong Wu
488887cf6a7SYong Wu if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) {
489887cf6a7SYong Wu if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) {
49037276e00SChao Hao fault_larb = F_MMU_INT_ID_COMM_ID(regval);
49137276e00SChao Hao sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
49265df7d82SFabien Parent fault_port = F_MMU_INT_ID_PORT_ID(regval);
493887cf6a7SYong Wu } else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) {
4949ec30c09SYong Wu fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);
4959ec30c09SYong Wu sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);
49665df7d82SFabien Parent fault_port = F_MMU_INT_ID_PORT_ID(regval);
49765df7d82SFabien Parent } else if (MTK_IOMMU_HAS_FLAG(plat_data, INT_ID_PORT_WIDTH_6)) {
49865df7d82SFabien Parent fault_port = F_MMU_INT_ID_PORT_ID_WID_6(regval);
49965df7d82SFabien Parent fault_larb = F_MMU_INT_ID_LARB_ID_WID_6(regval);
50037276e00SChao Hao } else {
50165df7d82SFabien Parent fault_port = F_MMU_INT_ID_PORT_ID(regval);
50237276e00SChao Hao fault_larb = F_MMU_INT_ID_LARB_ID(regval);
50337276e00SChao Hao }
50437276e00SChao Hao fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
505d2e9a110SYong Wu }
506b3e5eee7SYong Wu
50700ef8885SRicardo Ribalda if (!dom || report_iommu_fault(&dom->domain, bank->parent_dev, fault_iova,
5080df4fabeSYong Wu write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
5090df4fabeSYong Wu dev_err_ratelimited(
51099ca0228SYong Wu bank->parent_dev,
511f9b8c9b2SYong Wu "fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n",
512f9b8c9b2SYong Wu int_state, fault_iova, fault_pa, regval, fault_larb, fault_port,
5130df4fabeSYong Wu layer, write ? "write" : "read");
5140df4fabeSYong Wu }
5150df4fabeSYong Wu
5160df4fabeSYong Wu /* Interrupt clear */
517887cf6a7SYong Wu regval = readl_relaxed(base + REG_MMU_INT_CONTROL0);
5180df4fabeSYong Wu regval |= F_INT_CLR_BIT;
519887cf6a7SYong Wu writel_relaxed(regval, base + REG_MMU_INT_CONTROL0);
5200df4fabeSYong Wu
5210df4fabeSYong Wu mtk_iommu_tlb_flush_all(data);
5220df4fabeSYong Wu
5230df4fabeSYong Wu return IRQ_HANDLED;
5240df4fabeSYong Wu }
5250df4fabeSYong Wu
mtk_iommu_get_bank_id(struct device * dev,const struct mtk_iommu_plat_data * plat_data)52657fb481fSYong Wu static unsigned int mtk_iommu_get_bank_id(struct device *dev,
52757fb481fSYong Wu const struct mtk_iommu_plat_data *plat_data)
52857fb481fSYong Wu {
52957fb481fSYong Wu struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
53057fb481fSYong Wu unsigned int i, portmsk = 0, bankid = 0;
53157fb481fSYong Wu
53257fb481fSYong Wu if (plat_data->banks_num == 1)
53357fb481fSYong Wu return bankid;
53457fb481fSYong Wu
53557fb481fSYong Wu for (i = 0; i < fwspec->num_ids; i++)
53657fb481fSYong Wu portmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i]));
53757fb481fSYong Wu
53857fb481fSYong Wu for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) {
53957fb481fSYong Wu if (!plat_data->banks_enable[i])
54057fb481fSYong Wu continue;
54157fb481fSYong Wu
54257fb481fSYong Wu if (portmsk & plat_data->banks_portmsk[i]) {
54357fb481fSYong Wu bankid = i;
54457fb481fSYong Wu break;
54557fb481fSYong Wu }
54657fb481fSYong Wu }
54757fb481fSYong Wu return bankid; /* default is 0 */
54857fb481fSYong Wu }
54957fb481fSYong Wu
mtk_iommu_get_iova_region_id(struct device * dev,const struct mtk_iommu_plat_data * plat_data)550d72e0ff5SYong Wu static int mtk_iommu_get_iova_region_id(struct device *dev,
551803cf9e5SYong Wu const struct mtk_iommu_plat_data *plat_data)
552803cf9e5SYong Wu {
553b2a6876dSYong Wu struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
554b2a6876dSYong Wu unsigned int portidmsk = 0, larbid;
555b2a6876dSYong Wu const u32 *rgn_larb_msk;
556b2a6876dSYong Wu int i;
557803cf9e5SYong Wu
558b2a6876dSYong Wu if (plat_data->iova_region_nr == 1)
559803cf9e5SYong Wu return 0;
560803cf9e5SYong Wu
561b2a6876dSYong Wu larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
562b2a6876dSYong Wu for (i = 0; i < fwspec->num_ids; i++)
563b2a6876dSYong Wu portidmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i]));
564b2a6876dSYong Wu
565b2a6876dSYong Wu for (i = 0; i < plat_data->iova_region_nr; i++) {
566b2a6876dSYong Wu rgn_larb_msk = plat_data->iova_region_larb_msk[i];
567b2a6876dSYong Wu if (!rgn_larb_msk)
568b2a6876dSYong Wu continue;
569b2a6876dSYong Wu
570b2a6876dSYong Wu if ((rgn_larb_msk[larbid] & portidmsk) == portidmsk)
571803cf9e5SYong Wu return i;
572803cf9e5SYong Wu }
573803cf9e5SYong Wu
574b2a6876dSYong Wu dev_err(dev, "Can NOT find the region for larb(%d-%x).\n",
575b2a6876dSYong Wu larbid, portidmsk);
576803cf9e5SYong Wu return -EINVAL;
577803cf9e5SYong Wu }
578803cf9e5SYong Wu
mtk_iommu_config(struct mtk_iommu_data * data,struct device * dev,bool enable,unsigned int regionid)579f9b8c9b2SYong Wu static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev,
580d72e0ff5SYong Wu bool enable, unsigned int regionid)
5810df4fabeSYong Wu {
5820df4fabeSYong Wu struct mtk_smi_larb_iommu *larb_mmu;
5830df4fabeSYong Wu unsigned int larbid, portid;
584a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
5858d2c749eSYong Wu const struct mtk_iommu_iova_region *region;
5869a890510SChengci.Xu unsigned long portid_msk = 0;
587946e719cSChengci.Xu struct arm_smccc_res res;
588f9b8c9b2SYong Wu int i, ret = 0;
5890df4fabeSYong Wu
59058f0d1d5SRobin Murphy for (i = 0; i < fwspec->num_ids; ++i) {
59158f0d1d5SRobin Murphy portid = MTK_M4U_TO_PORT(fwspec->ids[i]);
5929a890510SChengci.Xu portid_msk |= BIT(portid);
5939a890510SChengci.Xu }
5948d2c749eSYong Wu
595d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
5969a890510SChengci.Xu /* All ports should be in the same larb. just use 0 here */
5979a890510SChengci.Xu larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
5981ee9feb2SYong Wu larb_mmu = &data->larb_imu[larbid];
599d72e0ff5SYong Wu region = data->plat_data->iova_region + regionid;
6009a890510SChengci.Xu
6019a890510SChengci.Xu for_each_set_bit(portid, &portid_msk, 32)
6028d2c749eSYong Wu larb_mmu->bank[portid] = upper_32_bits(region->iova_base);
6038d2c749eSYong Wu
6049a890510SChengci.Xu dev_dbg(dev, "%s iommu for larb(%s) port 0x%lx region %d rgn-bank %d.\n",
6058d2c749eSYong Wu enable ? "enable" : "disable", dev_name(larb_mmu->dev),
6069a890510SChengci.Xu portid_msk, regionid, upper_32_bits(region->iova_base));
6070df4fabeSYong Wu
6080df4fabeSYong Wu if (enable)
6099a890510SChengci.Xu larb_mmu->mmu |= portid_msk;
6100df4fabeSYong Wu else
6119a890510SChengci.Xu larb_mmu->mmu &= ~portid_msk;
612f9b8c9b2SYong Wu } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {
613946e719cSChengci.Xu if (MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) {
614946e719cSChengci.Xu arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL,
615946e719cSChengci.Xu IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU,
616946e719cSChengci.Xu portid_msk, enable, 0, 0, 0, 0, &res);
617946e719cSChengci.Xu ret = res.a0;
618946e719cSChengci.Xu } else {
619e7629070SYong Wu /* PCI dev has only one output id, enable the next writing bit for PCIe */
6209a890510SChengci.Xu if (dev_is_pci(dev)) {
6219a890510SChengci.Xu if (fwspec->num_ids != 1) {
6229a890510SChengci.Xu dev_err(dev, "PCI dev can only have one port.\n");
6239a890510SChengci.Xu return -ENODEV;
6240df4fabeSYong Wu }
6259a890510SChengci.Xu portid_msk |= BIT(portid + 1);
6269a890510SChengci.Xu }
6279a890510SChengci.Xu
6289a890510SChengci.Xu ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1,
6299a890510SChengci.Xu (u32)portid_msk, enable ? (u32)portid_msk : 0);
630946e719cSChengci.Xu }
6319a890510SChengci.Xu if (ret)
6329a890510SChengci.Xu dev_err(dev, "%s iommu(%s) inframaster 0x%lx fail(%d).\n",
6339a890510SChengci.Xu enable ? "enable" : "disable",
6349a890510SChengci.Xu dev_name(data->dev), portid_msk, ret);
6350df4fabeSYong Wu }
636f9b8c9b2SYong Wu return ret;
637d2e9a110SYong Wu }
6380df4fabeSYong Wu
mtk_iommu_domain_finalise(struct mtk_iommu_domain * dom,struct mtk_iommu_data * data,unsigned int region_id)6394f956c97SYong Wu static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
640c3045f39SYong Wu struct mtk_iommu_data *data,
641d72e0ff5SYong Wu unsigned int region_id)
6420df4fabeSYong Wu {
643cf69ef46SChengci.Xu struct mtk_iommu_domain *share_dom = data->share_dom;
644c3045f39SYong Wu const struct mtk_iommu_iova_region *region;
645c3045f39SYong Wu
646b07eba71SYong Wu /* Share pgtable when 2 MM IOMMU share the pgtable or one IOMMU use multiple iova ranges */
647b07eba71SYong Wu if (share_dom) {
648cf69ef46SChengci.Xu dom->iop = share_dom->iop;
649cf69ef46SChengci.Xu dom->cfg = share_dom->cfg;
650cf69ef46SChengci.Xu dom->domain.pgsize_bitmap = share_dom->cfg.pgsize_bitmap;
651c3045f39SYong Wu goto update_iova_region;
652c3045f39SYong Wu }
653c3045f39SYong Wu
6540df4fabeSYong Wu dom->cfg = (struct io_pgtable_cfg) {
6550df4fabeSYong Wu .quirks = IO_PGTABLE_QUIRK_ARM_NS |
6560df4fabeSYong Wu IO_PGTABLE_QUIRK_NO_PERMS |
657b4dad40eSYong Wu IO_PGTABLE_QUIRK_ARM_MTK_EXT,
6580df4fabeSYong Wu .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
6592f317da4SYong Wu .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32,
6600df4fabeSYong Wu .iommu_dev = data->dev,
6610df4fabeSYong Wu };
6620df4fabeSYong Wu
663301c3ca1SYunfei Wang if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))
664301c3ca1SYunfei Wang dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT;
665301c3ca1SYunfei Wang
6669bdfe4c1SYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
6679bdfe4c1SYong Wu dom->cfg.oas = data->enable_4GB ? 33 : 32;
6689bdfe4c1SYong Wu else
6699bdfe4c1SYong Wu dom->cfg.oas = 35;
6709bdfe4c1SYong Wu
6710df4fabeSYong Wu dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data);
6720df4fabeSYong Wu if (!dom->iop) {
6730df4fabeSYong Wu dev_err(data->dev, "Failed to alloc io pgtable\n");
674bd7ebb77SNicolin Chen return -ENOMEM;
6750df4fabeSYong Wu }
6760df4fabeSYong Wu
6770df4fabeSYong Wu /* Update our support page sizes bitmap */
678d16e0faaSRobin Murphy dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap;
679b7875eb9SYong Wu
680cf69ef46SChengci.Xu data->share_dom = dom;
681cf69ef46SChengci.Xu
682c3045f39SYong Wu update_iova_region:
683c3045f39SYong Wu /* Update the iova region for this domain */
684d72e0ff5SYong Wu region = data->plat_data->iova_region + region_id;
685c3045f39SYong Wu dom->domain.geometry.aperture_start = region->iova_base;
686c3045f39SYong Wu dom->domain.geometry.aperture_end = region->iova_base + region->size - 1;
687b7875eb9SYong Wu dom->domain.geometry.force_aperture = true;
6880df4fabeSYong Wu return 0;
6890df4fabeSYong Wu }
6900df4fabeSYong Wu
mtk_iommu_domain_alloc_paging(struct device * dev)6913529375eSJason Gunthorpe static struct iommu_domain *mtk_iommu_domain_alloc_paging(struct device *dev)
6920df4fabeSYong Wu {
6930df4fabeSYong Wu struct mtk_iommu_domain *dom;
6940df4fabeSYong Wu
6950df4fabeSYong Wu dom = kzalloc(sizeof(*dom), GFP_KERNEL);
6960df4fabeSYong Wu if (!dom)
6970df4fabeSYong Wu return NULL;
698ddf67a87SYong Wu mutex_init(&dom->mutex);
6990df4fabeSYong Wu
7004f956c97SYong Wu return &dom->domain;
7014f956c97SYong Wu }
7024f956c97SYong Wu
mtk_iommu_domain_free(struct iommu_domain * domain)7030df4fabeSYong Wu static void mtk_iommu_domain_free(struct iommu_domain *domain)
7040df4fabeSYong Wu {
7050df4fabeSYong Wu kfree(to_mtk_domain(domain));
7060df4fabeSYong Wu }
7070df4fabeSYong Wu
mtk_iommu_attach_device(struct iommu_domain * domain,struct device * dev)7080df4fabeSYong Wu static int mtk_iommu_attach_device(struct iommu_domain *domain,
7090df4fabeSYong Wu struct device *dev)
7100df4fabeSYong Wu {
711645b87c1SYong Wu struct mtk_iommu_data *data = dev_iommu_priv_get(dev), *frstdata;
7120df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain);
7139e3a2a64SYong Wu struct list_head *hw_list = data->hw_list;
714c0b57581SYong Wu struct device *m4udev = data->dev;
71599ca0228SYong Wu struct mtk_iommu_bank_data *bank;
71657fb481fSYong Wu unsigned int bankid;
717d72e0ff5SYong Wu int ret, region_id;
7180df4fabeSYong Wu
719d72e0ff5SYong Wu region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data);
720d72e0ff5SYong Wu if (region_id < 0)
721d72e0ff5SYong Wu return region_id;
722803cf9e5SYong Wu
72357fb481fSYong Wu bankid = mtk_iommu_get_bank_id(dev, data->plat_data);
724ddf67a87SYong Wu mutex_lock(&dom->mutex);
72599ca0228SYong Wu if (!dom->bank) {
726645b87c1SYong Wu /* Data is in the frstdata in sharing pgtable case. */
7279e3a2a64SYong Wu frstdata = mtk_iommu_get_frst_data(hw_list);
728645b87c1SYong Wu
729cf69ef46SChengci.Xu mutex_lock(&frstdata->mutex);
730d72e0ff5SYong Wu ret = mtk_iommu_domain_finalise(dom, frstdata, region_id);
731cf69ef46SChengci.Xu mutex_unlock(&frstdata->mutex);
732ddf67a87SYong Wu if (ret) {
733ddf67a87SYong Wu mutex_unlock(&dom->mutex);
73404cee82eSNicolin Chen return ret;
735ddf67a87SYong Wu }
73699ca0228SYong Wu dom->bank = &data->bank[bankid];
7374f956c97SYong Wu }
738ddf67a87SYong Wu mutex_unlock(&dom->mutex);
7394f956c97SYong Wu
7400e5a3f2eSYong Wu mutex_lock(&data->mutex);
74199ca0228SYong Wu bank = &data->bank[bankid];
742e24453e1SYong Wu if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */
743c0b57581SYong Wu ret = pm_runtime_resume_and_get(m4udev);
744e24453e1SYong Wu if (ret < 0) {
745e24453e1SYong Wu dev_err(m4udev, "pm get fail(%d) in attach.\n", ret);
7460e5a3f2eSYong Wu goto err_unlock;
747e24453e1SYong Wu }
748c0b57581SYong Wu
749e24453e1SYong Wu ret = mtk_iommu_hw_init(data, bankid);
750c0b57581SYong Wu if (ret) {
751c0b57581SYong Wu pm_runtime_put(m4udev);
7520e5a3f2eSYong Wu goto err_unlock;
753c0b57581SYong Wu }
75499ca0228SYong Wu bank->m4u_dom = dom;
755301c3ca1SYunfei Wang writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR);
756c0b57581SYong Wu
757c0b57581SYong Wu pm_runtime_put(m4udev);
7580df4fabeSYong Wu }
7590e5a3f2eSYong Wu mutex_unlock(&data->mutex);
7600df4fabeSYong Wu
761f7da2da8SYong Wu if (region_id > 0) {
762f7da2da8SYong Wu ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34));
763f7da2da8SYong Wu if (ret) {
764f7da2da8SYong Wu dev_err(m4udev, "Failed to set dma_mask for %s(%d).\n", dev_name(dev), ret);
765f7da2da8SYong Wu return ret;
766f7da2da8SYong Wu }
767f7da2da8SYong Wu }
768f7da2da8SYong Wu
769d72e0ff5SYong Wu return mtk_iommu_config(data, dev, true, region_id);
7700e5a3f2eSYong Wu
7710e5a3f2eSYong Wu err_unlock:
7720e5a3f2eSYong Wu mutex_unlock(&data->mutex);
7730e5a3f2eSYong Wu return ret;
7740df4fabeSYong Wu }
7750df4fabeSYong Wu
mtk_iommu_identity_attach(struct iommu_domain * identity_domain,struct device * dev)776b01b1257SJason Gunthorpe static int mtk_iommu_identity_attach(struct iommu_domain *identity_domain,
777b01b1257SJason Gunthorpe struct device *dev)
778b01b1257SJason Gunthorpe {
779b01b1257SJason Gunthorpe struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
780b01b1257SJason Gunthorpe struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
781b01b1257SJason Gunthorpe
782b01b1257SJason Gunthorpe if (domain == identity_domain || !domain)
783b01b1257SJason Gunthorpe return 0;
784b01b1257SJason Gunthorpe
785b01b1257SJason Gunthorpe mtk_iommu_config(data, dev, false, 0);
786b01b1257SJason Gunthorpe return 0;
787b01b1257SJason Gunthorpe }
788b01b1257SJason Gunthorpe
789b01b1257SJason Gunthorpe static struct iommu_domain_ops mtk_iommu_identity_ops = {
790b01b1257SJason Gunthorpe .attach_dev = mtk_iommu_identity_attach,
791b01b1257SJason Gunthorpe };
792b01b1257SJason Gunthorpe
793b01b1257SJason Gunthorpe static struct iommu_domain mtk_iommu_identity_domain = {
794b01b1257SJason Gunthorpe .type = IOMMU_DOMAIN_IDENTITY,
795b01b1257SJason Gunthorpe .ops = &mtk_iommu_identity_ops,
796b01b1257SJason Gunthorpe };
797b01b1257SJason Gunthorpe
mtk_iommu_map(struct iommu_domain * domain,unsigned long iova,phys_addr_t paddr,size_t pgsize,size_t pgcount,int prot,gfp_t gfp,size_t * mapped)7980df4fabeSYong Wu static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
79985637380SRobin Murphy phys_addr_t paddr, size_t pgsize, size_t pgcount,
80085637380SRobin Murphy int prot, gfp_t gfp, size_t *mapped)
8010df4fabeSYong Wu {
8020df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain);
8030df4fabeSYong Wu
804b4dad40eSYong Wu /* The "4GB mode" M4U physically can not use the lower remap of Dram. */
80599ca0228SYong Wu if (dom->bank->parent_data->enable_4GB)
806b4dad40eSYong Wu paddr |= BIT_ULL(32);
807b4dad40eSYong Wu
80860829b4dSYong Wu /* Synchronize with the tlb_lock */
80985637380SRobin Murphy return dom->iop->map_pages(dom->iop, iova, paddr, pgsize, pgcount, prot, gfp, mapped);
8100df4fabeSYong Wu }
8110df4fabeSYong Wu
mtk_iommu_unmap(struct iommu_domain * domain,unsigned long iova,size_t pgsize,size_t pgcount,struct iommu_iotlb_gather * gather)8120df4fabeSYong Wu static size_t mtk_iommu_unmap(struct iommu_domain *domain,
81385637380SRobin Murphy unsigned long iova, size_t pgsize, size_t pgcount,
81456f8af5eSWill Deacon struct iommu_iotlb_gather *gather)
8150df4fabeSYong Wu {
8160df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain);
8170df4fabeSYong Wu
81885637380SRobin Murphy iommu_iotlb_gather_add_range(gather, iova, pgsize * pgcount);
81985637380SRobin Murphy return dom->iop->unmap_pages(dom->iop, iova, pgsize, pgcount, gather);
8200df4fabeSYong Wu }
8210df4fabeSYong Wu
mtk_iommu_flush_iotlb_all(struct iommu_domain * domain)82256f8af5eSWill Deacon static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain)
82356f8af5eSWill Deacon {
82408500c43SYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain);
82508500c43SYong Wu
826b3fc9570SChen-Yu Tsai if (dom->bank)
82799ca0228SYong Wu mtk_iommu_tlb_flush_all(dom->bank->parent_data);
82856f8af5eSWill Deacon }
82956f8af5eSWill Deacon
mtk_iommu_iotlb_sync(struct iommu_domain * domain,struct iommu_iotlb_gather * gather)83056f8af5eSWill Deacon static void mtk_iommu_iotlb_sync(struct iommu_domain *domain,
83156f8af5eSWill Deacon struct iommu_iotlb_gather *gather)
8324d689b61SRobin Murphy {
83308500c43SYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain);
834862c3715SYong Wu size_t length = gather->end - gather->start + 1;
835da3cc91bSYong Wu
83699ca0228SYong Wu mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->bank);
8374d689b61SRobin Murphy }
8384d689b61SRobin Murphy
mtk_iommu_sync_map(struct iommu_domain * domain,unsigned long iova,size_t size)839fa4c4507SNiklas Schnelle static int mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova,
84020143451SYong Wu size_t size)
84120143451SYong Wu {
84208500c43SYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain);
84320143451SYong Wu
84499ca0228SYong Wu mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank);
845fa4c4507SNiklas Schnelle return 0;
84620143451SYong Wu }
84720143451SYong Wu
mtk_iommu_iova_to_phys(struct iommu_domain * domain,dma_addr_t iova)8480df4fabeSYong Wu static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
8490df4fabeSYong Wu dma_addr_t iova)
8500df4fabeSYong Wu {
8510df4fabeSYong Wu struct mtk_iommu_domain *dom = to_mtk_domain(domain);
8520df4fabeSYong Wu phys_addr_t pa;
8530df4fabeSYong Wu
8540df4fabeSYong Wu pa = dom->iop->iova_to_phys(dom->iop, iova);
855f13efafcSArnd Bergmann if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
85699ca0228SYong Wu dom->bank->parent_data->enable_4GB &&
857f13efafcSArnd Bergmann pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE)
858b4dad40eSYong Wu pa &= ~BIT_ULL(32);
85930e2fccfSYong Wu
8600df4fabeSYong Wu return pa;
8610df4fabeSYong Wu }
8620df4fabeSYong Wu
mtk_iommu_probe_device(struct device * dev)86380e4592aSJoerg Roedel static struct iommu_device *mtk_iommu_probe_device(struct device *dev)
8640df4fabeSYong Wu {
865a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
866e7080665SRobin Murphy struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
867635319a4SYong Wu struct device_link *link;
868635319a4SYong Wu struct device *larbdev;
869635319a4SYong Wu unsigned int larbid, larbidx, i;
8700df4fabeSYong Wu
871d2e9a110SYong Wu if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM))
872d2e9a110SYong Wu return &data->iommu;
873d2e9a110SYong Wu
874635319a4SYong Wu /*
875635319a4SYong Wu * Link the consumer device with the smi-larb device(supplier).
876635319a4SYong Wu * The device that connects with each a larb is a independent HW.
877635319a4SYong Wu * All the ports in each a device should be in the same larbs.
878635319a4SYong Wu */
879635319a4SYong Wu larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
880de78657eSMiles Chen if (larbid >= MTK_LARB_NR_MAX)
881de78657eSMiles Chen return ERR_PTR(-EINVAL);
882de78657eSMiles Chen
883635319a4SYong Wu for (i = 1; i < fwspec->num_ids; i++) {
884635319a4SYong Wu larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]);
885635319a4SYong Wu if (larbid != larbidx) {
886635319a4SYong Wu dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n",
887635319a4SYong Wu larbid, larbidx);
888635319a4SYong Wu return ERR_PTR(-EINVAL);
889635319a4SYong Wu }
890635319a4SYong Wu }
891635319a4SYong Wu larbdev = data->larb_imu[larbid].dev;
892de78657eSMiles Chen if (!larbdev)
893de78657eSMiles Chen return ERR_PTR(-EINVAL);
894de78657eSMiles Chen
895635319a4SYong Wu link = device_link_add(dev, larbdev,
896635319a4SYong Wu DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
897635319a4SYong Wu if (!link)
898635319a4SYong Wu dev_err(dev, "Unable to link %s\n", dev_name(larbdev));
89980e4592aSJoerg Roedel return &data->iommu;
9000df4fabeSYong Wu }
9010df4fabeSYong Wu
mtk_iommu_release_device(struct device * dev)90280e4592aSJoerg Roedel static void mtk_iommu_release_device(struct device *dev)
9030df4fabeSYong Wu {
904a9bf2eecSJoerg Roedel struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
905635319a4SYong Wu struct mtk_iommu_data *data;
906635319a4SYong Wu struct device *larbdev;
907635319a4SYong Wu unsigned int larbid;
908b16c0170SJoerg Roedel
909635319a4SYong Wu data = dev_iommu_priv_get(dev);
910d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
911635319a4SYong Wu larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
912635319a4SYong Wu larbdev = data->larb_imu[larbid].dev;
913635319a4SYong Wu device_link_remove(dev, larbdev);
914d2e9a110SYong Wu }
9150df4fabeSYong Wu }
9160df4fabeSYong Wu
mtk_iommu_get_group_id(struct device * dev,const struct mtk_iommu_plat_data * plat_data)91757fb481fSYong Wu static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data)
91857fb481fSYong Wu {
91957fb481fSYong Wu unsigned int bankid;
92057fb481fSYong Wu
92157fb481fSYong Wu /*
92257fb481fSYong Wu * If the bank function is enabled, each bank is a iommu group/domain.
92357fb481fSYong Wu * Otherwise, each iova region is a iommu group/domain.
92457fb481fSYong Wu */
92557fb481fSYong Wu bankid = mtk_iommu_get_bank_id(dev, plat_data);
92657fb481fSYong Wu if (bankid)
92757fb481fSYong Wu return bankid;
92857fb481fSYong Wu
92957fb481fSYong Wu return mtk_iommu_get_iova_region_id(dev, plat_data);
93057fb481fSYong Wu }
93157fb481fSYong Wu
mtk_iommu_device_group(struct device * dev)9320df4fabeSYong Wu static struct iommu_group *mtk_iommu_device_group(struct device *dev)
9330df4fabeSYong Wu {
9349e3a2a64SYong Wu struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data;
9359e3a2a64SYong Wu struct list_head *hw_list = c_data->hw_list;
936c3045f39SYong Wu struct iommu_group *group;
93757fb481fSYong Wu int groupid;
9380df4fabeSYong Wu
9399e3a2a64SYong Wu data = mtk_iommu_get_frst_data(hw_list);
94058f0d1d5SRobin Murphy if (!data)
9410df4fabeSYong Wu return ERR_PTR(-ENODEV);
9420df4fabeSYong Wu
94357fb481fSYong Wu groupid = mtk_iommu_get_group_id(dev, data->plat_data);
94457fb481fSYong Wu if (groupid < 0)
94557fb481fSYong Wu return ERR_PTR(groupid);
946803cf9e5SYong Wu
9470e5a3f2eSYong Wu mutex_lock(&data->mutex);
94857fb481fSYong Wu group = data->m4u_group[groupid];
949c3045f39SYong Wu if (!group) {
950c3045f39SYong Wu group = iommu_group_alloc();
951c3045f39SYong Wu if (!IS_ERR(group))
95257fb481fSYong Wu data->m4u_group[groupid] = group;
9533a8d40b6SRobin Murphy } else {
954c3045f39SYong Wu iommu_group_ref_get(group);
9550df4fabeSYong Wu }
9560e5a3f2eSYong Wu mutex_unlock(&data->mutex);
957c3045f39SYong Wu return group;
9580df4fabeSYong Wu }
9590df4fabeSYong Wu
mtk_iommu_of_xlate(struct device * dev,const struct of_phandle_args * args)960b42a905bSKrzysztof Kozlowski static int mtk_iommu_of_xlate(struct device *dev,
961b42a905bSKrzysztof Kozlowski const struct of_phandle_args *args)
9620df4fabeSYong Wu {
9630df4fabeSYong Wu struct platform_device *m4updev;
9640df4fabeSYong Wu
9650df4fabeSYong Wu if (args->args_count != 1) {
9660df4fabeSYong Wu dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
9670df4fabeSYong Wu args->args_count);
9680df4fabeSYong Wu return -EINVAL;
9690df4fabeSYong Wu }
9700df4fabeSYong Wu
9713524b559SJoerg Roedel if (!dev_iommu_priv_get(dev)) {
9720df4fabeSYong Wu /* Get the m4u device */
9730df4fabeSYong Wu m4updev = of_find_device_by_node(args->np);
9740df4fabeSYong Wu if (WARN_ON(!m4updev))
9750df4fabeSYong Wu return -EINVAL;
9760df4fabeSYong Wu
9773524b559SJoerg Roedel dev_iommu_priv_set(dev, platform_get_drvdata(m4updev));
9780df4fabeSYong Wu }
9790df4fabeSYong Wu
98058f0d1d5SRobin Murphy return iommu_fwspec_add_ids(dev, args->args, 1);
9810df4fabeSYong Wu }
9820df4fabeSYong Wu
mtk_iommu_get_resv_regions(struct device * dev,struct list_head * head)983ab1d5281SYong Wu static void mtk_iommu_get_resv_regions(struct device *dev,
984ab1d5281SYong Wu struct list_head *head)
985ab1d5281SYong Wu {
986ab1d5281SYong Wu struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
987d72e0ff5SYong Wu unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i;
988ab1d5281SYong Wu const struct mtk_iommu_iova_region *resv, *curdom;
989ab1d5281SYong Wu struct iommu_resv_region *region;
990ab1d5281SYong Wu int prot = IOMMU_WRITE | IOMMU_READ;
991ab1d5281SYong Wu
992d72e0ff5SYong Wu if ((int)regionid < 0)
993ab1d5281SYong Wu return;
994d72e0ff5SYong Wu curdom = data->plat_data->iova_region + regionid;
995ab1d5281SYong Wu for (i = 0; i < data->plat_data->iova_region_nr; i++) {
996ab1d5281SYong Wu resv = data->plat_data->iova_region + i;
997ab1d5281SYong Wu
998ab1d5281SYong Wu /* Only reserve when the region is inside the current domain */
999ab1d5281SYong Wu if (resv->iova_base <= curdom->iova_base ||
1000ab1d5281SYong Wu resv->iova_base + resv->size >= curdom->iova_base + curdom->size)
1001ab1d5281SYong Wu continue;
1002ab1d5281SYong Wu
1003ab1d5281SYong Wu region = iommu_alloc_resv_region(resv->iova_base, resv->size,
10040251d010SLu Baolu prot, IOMMU_RESV_RESERVED,
10050251d010SLu Baolu GFP_KERNEL);
1006ab1d5281SYong Wu if (!region)
1007ab1d5281SYong Wu return;
1008ab1d5281SYong Wu
1009ab1d5281SYong Wu list_add_tail(®ion->list, head);
1010ab1d5281SYong Wu }
1011ab1d5281SYong Wu }
1012ab1d5281SYong Wu
1013b65f5016SArvind Yadav static const struct iommu_ops mtk_iommu_ops = {
1014b01b1257SJason Gunthorpe .identity_domain = &mtk_iommu_identity_domain,
10153529375eSJason Gunthorpe .domain_alloc_paging = mtk_iommu_domain_alloc_paging,
101680e4592aSJoerg Roedel .probe_device = mtk_iommu_probe_device,
101780e4592aSJoerg Roedel .release_device = mtk_iommu_release_device,
10180df4fabeSYong Wu .device_group = mtk_iommu_device_group,
10190df4fabeSYong Wu .of_xlate = mtk_iommu_of_xlate,
1020ab1d5281SYong Wu .get_resv_regions = mtk_iommu_get_resv_regions,
10210df4fabeSYong Wu .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
102218d8c74eSYong Wu .owner = THIS_MODULE,
10239a630a4bSLu Baolu .default_domain_ops = &(const struct iommu_domain_ops) {
10249a630a4bSLu Baolu .attach_dev = mtk_iommu_attach_device,
102585637380SRobin Murphy .map_pages = mtk_iommu_map,
102685637380SRobin Murphy .unmap_pages = mtk_iommu_unmap,
10279a630a4bSLu Baolu .flush_iotlb_all = mtk_iommu_flush_iotlb_all,
10289a630a4bSLu Baolu .iotlb_sync = mtk_iommu_iotlb_sync,
10299a630a4bSLu Baolu .iotlb_sync_map = mtk_iommu_sync_map,
10309a630a4bSLu Baolu .iova_to_phys = mtk_iommu_iova_to_phys,
10319a630a4bSLu Baolu .free = mtk_iommu_domain_free,
10329a630a4bSLu Baolu }
10330df4fabeSYong Wu };
10340df4fabeSYong Wu
mtk_iommu_hw_init(const struct mtk_iommu_data * data,unsigned int bankid)1035e24453e1SYong Wu static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid)
10360df4fabeSYong Wu {
1037e24453e1SYong Wu const struct mtk_iommu_bank_data *bankx = &data->bank[bankid];
103899ca0228SYong Wu const struct mtk_iommu_bank_data *bank0 = &data->bank[0];
10390df4fabeSYong Wu u32 regval;
10400df4fabeSYong Wu
1041e24453e1SYong Wu /*
1042e24453e1SYong Wu * Global control settings are in bank0. May re-init these global registers
1043e24453e1SYong Wu * since no sure if there is bank0 consumers.
1044e24453e1SYong Wu */
104586580ec9SAngeloGioacchino Del Regno if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) {
1046acb3c92aSYong Wu regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
1047acb3c92aSYong Wu F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
104886444413SChao Hao } else {
104999ca0228SYong Wu regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG);
105086444413SChao Hao regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
105186444413SChao Hao }
105299ca0228SYong Wu writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG);
10530df4fabeSYong Wu
10546b717796SChao Hao if (data->enable_4GB &&
10556b717796SChao Hao MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) {
105630e2fccfSYong Wu /*
105730e2fccfSYong Wu * If 4GB mode is enabled, the validate PA range is from
105830e2fccfSYong Wu * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
105930e2fccfSYong Wu */
106030e2fccfSYong Wu regval = F_MMU_VLD_PA_RNG(7, 4);
106199ca0228SYong Wu writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG);
106230e2fccfSYong Wu }
10639a87005eSYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE))
106499ca0228SYong Wu writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS);
10659a87005eSYong Wu else
106699ca0228SYong Wu writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS);
10679a87005eSYong Wu
106835c1b48dSChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) {
106935c1b48dSChao Hao /* write command throttling mode */
107099ca0228SYong Wu regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL);
107135c1b48dSChao Hao regval &= ~F_MMU_WR_THROT_DIS_MASK;
107299ca0228SYong Wu writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL);
107335c1b48dSChao Hao }
1074e6dec923SYong Wu
10756b717796SChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
107675eed350SChao Hao /* The register is called STANDARD_AXI_MODE in this case */
10774bb2bf4cSChao Hao regval = 0;
10784bb2bf4cSChao Hao } else {
107999ca0228SYong Wu regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL);
1080d265a4adSYong Wu if (!MTK_IOMMU_HAS_FLAG(data->plat_data, STD_AXI_MODE))
10814bb2bf4cSChao Hao regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
10824bb2bf4cSChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
10834bb2bf4cSChao Hao regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
108475eed350SChao Hao }
108599ca0228SYong Wu writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL);
10860df4fabeSYong Wu
1087e24453e1SYong Wu /* Independent settings for each bank */
1088634f57dfSYong Wu regval = F_L2_MULIT_HIT_EN |
1089634f57dfSYong Wu F_TABLE_WALK_FAULT_INT_EN |
1090634f57dfSYong Wu F_PREETCH_FIFO_OVERFLOW_INT_EN |
1091634f57dfSYong Wu F_MISS_FIFO_OVERFLOW_INT_EN |
1092634f57dfSYong Wu F_PREFETCH_FIFO_ERR_INT_EN |
1093634f57dfSYong Wu F_MISS_FIFO_ERR_INT_EN;
1094e24453e1SYong Wu writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0);
1095634f57dfSYong Wu
1096634f57dfSYong Wu regval = F_INT_TRANSLATION_FAULT |
1097634f57dfSYong Wu F_INT_MAIN_MULTI_HIT_FAULT |
1098634f57dfSYong Wu F_INT_INVALID_PA_FAULT |
1099634f57dfSYong Wu F_INT_ENTRY_REPLACEMENT_FAULT |
1100634f57dfSYong Wu F_INT_TLB_MISS_FAULT |
1101634f57dfSYong Wu F_INT_MISS_TRANSACTION_FIFO_FAULT |
1102634f57dfSYong Wu F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
1103e24453e1SYong Wu writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL);
1104634f57dfSYong Wu
1105634f57dfSYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
1106634f57dfSYong Wu regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
1107634f57dfSYong Wu else
1108634f57dfSYong Wu regval = lower_32_bits(data->protect_base) |
1109634f57dfSYong Wu upper_32_bits(data->protect_base);
1110e24453e1SYong Wu writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR);
1111634f57dfSYong Wu
1112e24453e1SYong Wu if (devm_request_irq(bankx->parent_dev, bankx->irq, mtk_iommu_isr, 0,
1113e24453e1SYong Wu dev_name(bankx->parent_dev), (void *)bankx)) {
1114e24453e1SYong Wu writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR);
1115e24453e1SYong Wu dev_err(bankx->parent_dev, "Failed @ IRQ-%d Request\n", bankx->irq);
11160df4fabeSYong Wu return -ENODEV;
11170df4fabeSYong Wu }
11180df4fabeSYong Wu
11190df4fabeSYong Wu return 0;
11200df4fabeSYong Wu }
11210df4fabeSYong Wu
11220df4fabeSYong Wu static const struct component_master_ops mtk_iommu_com_ops = {
11230df4fabeSYong Wu .bind = mtk_iommu_bind,
11240df4fabeSYong Wu .unbind = mtk_iommu_unbind,
11250df4fabeSYong Wu };
11260df4fabeSYong Wu
mtk_iommu_mm_dts_parse(struct device * dev,struct component_match ** match,struct mtk_iommu_data * data)1127d2e9a110SYong Wu static int mtk_iommu_mm_dts_parse(struct device *dev, struct component_match **match,
1128d2e9a110SYong Wu struct mtk_iommu_data *data)
1129d2e9a110SYong Wu {
11306cde583dSYong Wu struct device_node *larbnode, *frst_avail_smicomm_node = NULL;
1131dcb40e9fSYong Wu struct platform_device *plarbdev, *pcommdev;
1132d2e9a110SYong Wu struct device_link *link;
1133d2e9a110SYong Wu int i, larb_nr, ret;
1134d2e9a110SYong Wu
1135d2e9a110SYong Wu larb_nr = of_count_phandle_with_args(dev->of_node, "mediatek,larbs", NULL);
1136d2e9a110SYong Wu if (larb_nr < 0)
1137d2e9a110SYong Wu return larb_nr;
1138ef693a84SGuenter Roeck if (larb_nr == 0 || larb_nr > MTK_LARB_NR_MAX)
1139ef693a84SGuenter Roeck return -EINVAL;
1140d2e9a110SYong Wu
1141d2e9a110SYong Wu for (i = 0; i < larb_nr; i++) {
11426cde583dSYong Wu struct device_node *smicomm_node, *smi_subcomm_node;
1143d2e9a110SYong Wu u32 id;
1144d2e9a110SYong Wu
1145d2e9a110SYong Wu larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
114626593928SYong Wu if (!larbnode) {
114726593928SYong Wu ret = -EINVAL;
114826593928SYong Wu goto err_larbdev_put;
114926593928SYong Wu }
1150d2e9a110SYong Wu
1151d2e9a110SYong Wu if (!of_device_is_available(larbnode)) {
1152d2e9a110SYong Wu of_node_put(larbnode);
1153d2e9a110SYong Wu continue;
1154d2e9a110SYong Wu }
1155d2e9a110SYong Wu
1156d2e9a110SYong Wu ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id);
1157d2e9a110SYong Wu if (ret)/* The id is consecutive if there is no this property */
1158d2e9a110SYong Wu id = i;
1159ef693a84SGuenter Roeck if (id >= MTK_LARB_NR_MAX) {
1160ef693a84SGuenter Roeck of_node_put(larbnode);
1161ef693a84SGuenter Roeck ret = -EINVAL;
1162ef693a84SGuenter Roeck goto err_larbdev_put;
1163ef693a84SGuenter Roeck }
1164d2e9a110SYong Wu
1165d2e9a110SYong Wu plarbdev = of_find_device_by_node(larbnode);
1166d2e9a110SYong Wu of_node_put(larbnode);
1167d2e9a110SYong Wu if (!plarbdev) {
116826593928SYong Wu ret = -ENODEV;
116926593928SYong Wu goto err_larbdev_put;
1170d2e9a110SYong Wu }
1171ef693a84SGuenter Roeck if (data->larb_imu[id].dev) {
1172ef693a84SGuenter Roeck platform_device_put(plarbdev);
1173ef693a84SGuenter Roeck ret = -EEXIST;
1174ef693a84SGuenter Roeck goto err_larbdev_put;
1175d2e9a110SYong Wu }
1176d2e9a110SYong Wu data->larb_imu[id].dev = &plarbdev->dev;
1177d2e9a110SYong Wu
117826593928SYong Wu if (!plarbdev->dev.driver) {
117926593928SYong Wu ret = -EPROBE_DEFER;
118026593928SYong Wu goto err_larbdev_put;
1181d2e9a110SYong Wu }
1182d2e9a110SYong Wu
1183f7b71d0dSYong Wu /* Get smi-(sub)-common dev from the last larb. */
1184f7b71d0dSYong Wu smi_subcomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0);
11856cde583dSYong Wu if (!smi_subcomm_node) {
11866cde583dSYong Wu ret = -EINVAL;
11876cde583dSYong Wu goto err_larbdev_put;
11886cde583dSYong Wu }
1189d2e9a110SYong Wu
1190f7b71d0dSYong Wu /*
1191f7b71d0dSYong Wu * It may have two level smi-common. the node is smi-sub-common if it
1192f7b71d0dSYong Wu * has a new mediatek,smi property. otherwise it is smi-commmon.
1193f7b71d0dSYong Wu */
1194f7b71d0dSYong Wu smicomm_node = of_parse_phandle(smi_subcomm_node, "mediatek,smi", 0);
1195f7b71d0dSYong Wu if (smicomm_node)
1196f7b71d0dSYong Wu of_node_put(smi_subcomm_node);
1197f7b71d0dSYong Wu else
1198f7b71d0dSYong Wu smicomm_node = smi_subcomm_node;
1199f7b71d0dSYong Wu
12006cde583dSYong Wu /*
12016cde583dSYong Wu * All the larbs that connect to one IOMMU must connect with the same
12026cde583dSYong Wu * smi-common.
12036cde583dSYong Wu */
12046cde583dSYong Wu if (!frst_avail_smicomm_node) {
12056cde583dSYong Wu frst_avail_smicomm_node = smicomm_node;
12066cde583dSYong Wu } else if (frst_avail_smicomm_node != smicomm_node) {
12076cde583dSYong Wu dev_err(dev, "mediatek,smi property is not right @larb%d.", id);
1208d2e9a110SYong Wu of_node_put(smicomm_node);
12096cde583dSYong Wu ret = -EINVAL;
12106cde583dSYong Wu goto err_larbdev_put;
12116cde583dSYong Wu } else {
12126cde583dSYong Wu of_node_put(smicomm_node);
12136cde583dSYong Wu }
12146cde583dSYong Wu
12156cde583dSYong Wu component_match_add(dev, match, component_compare_dev, &plarbdev->dev);
12166cde583dSYong Wu platform_device_put(plarbdev);
12176cde583dSYong Wu }
12186cde583dSYong Wu
12196cde583dSYong Wu if (!frst_avail_smicomm_node)
12206cde583dSYong Wu return -EINVAL;
12216cde583dSYong Wu
12226cde583dSYong Wu pcommdev = of_find_device_by_node(frst_avail_smicomm_node);
12236cde583dSYong Wu of_node_put(frst_avail_smicomm_node);
1224dcb40e9fSYong Wu if (!pcommdev)
1225dcb40e9fSYong Wu return -ENODEV;
1226dcb40e9fSYong Wu data->smicomm_dev = &pcommdev->dev;
1227d2e9a110SYong Wu
1228d2e9a110SYong Wu link = device_link_add(data->smicomm_dev, dev,
1229d2e9a110SYong Wu DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
1230dcb40e9fSYong Wu platform_device_put(pcommdev);
1231d2e9a110SYong Wu if (!link) {
1232d2e9a110SYong Wu dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev));
1233d2e9a110SYong Wu return -EINVAL;
1234d2e9a110SYong Wu }
1235d2e9a110SYong Wu return 0;
123626593928SYong Wu
123726593928SYong Wu err_larbdev_put:
1238462e768bSDan Carpenter for (i = MTK_LARB_NR_MAX - 1; i >= 0; i--) {
123926593928SYong Wu if (!data->larb_imu[i].dev)
124026593928SYong Wu continue;
124126593928SYong Wu put_device(data->larb_imu[i].dev);
124226593928SYong Wu }
124326593928SYong Wu return ret;
1244d2e9a110SYong Wu }
1245d2e9a110SYong Wu
mtk_iommu_probe(struct platform_device * pdev)12460df4fabeSYong Wu static int mtk_iommu_probe(struct platform_device *pdev)
12470df4fabeSYong Wu {
12480df4fabeSYong Wu struct mtk_iommu_data *data;
12490df4fabeSYong Wu struct device *dev = &pdev->dev;
12500df4fabeSYong Wu struct resource *res;
1251b16c0170SJoerg Roedel resource_size_t ioaddr;
12520df4fabeSYong Wu struct component_match *match = NULL;
1253c2c59456SMiles Chen struct regmap *infracfg;
12540df4fabeSYong Wu void *protect;
125542d57fc5SYong Wu int ret, banks_num, i = 0;
1256c2c59456SMiles Chen u32 val;
1257c2c59456SMiles Chen char *p;
125899ca0228SYong Wu struct mtk_iommu_bank_data *bank;
125999ca0228SYong Wu void __iomem *base;
12600df4fabeSYong Wu
12610df4fabeSYong Wu data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
12620df4fabeSYong Wu if (!data)
12630df4fabeSYong Wu return -ENOMEM;
12640df4fabeSYong Wu data->dev = dev;
1265cecdce9dSYong Wu data->plat_data = of_device_get_match_data(dev);
12660df4fabeSYong Wu
12670df4fabeSYong Wu /* Protect memory. HW will access here while translation fault.*/
1268b07cd3b7SErick Archer protect = devm_kcalloc(dev, 2, MTK_PROTECT_PA_ALIGN, GFP_KERNEL);
12690df4fabeSYong Wu if (!protect)
12700df4fabeSYong Wu return -ENOMEM;
12710df4fabeSYong Wu data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
12720df4fabeSYong Wu
1273c2c59456SMiles Chen if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) {
12747d748ffdSAngeloGioacchino Del Regno infracfg = syscon_regmap_lookup_by_phandle(dev->of_node, "mediatek,infracfg");
12757d748ffdSAngeloGioacchino Del Regno if (IS_ERR(infracfg)) {
12767d748ffdSAngeloGioacchino Del Regno /*
12777d748ffdSAngeloGioacchino Del Regno * Legacy devicetrees will not specify a phandle to
12787d748ffdSAngeloGioacchino Del Regno * mediatek,infracfg: in that case, we use the older
12797d748ffdSAngeloGioacchino Del Regno * way to retrieve a syscon to infra.
12807d748ffdSAngeloGioacchino Del Regno *
12817d748ffdSAngeloGioacchino Del Regno * This is for retrocompatibility purposes only, hence
12827d748ffdSAngeloGioacchino Del Regno * no more compatibles shall be added to this.
12837d748ffdSAngeloGioacchino Del Regno */
1284c2c59456SMiles Chen switch (data->plat_data->m4u_plat) {
1285c2c59456SMiles Chen case M4U_MT2712:
1286c2c59456SMiles Chen p = "mediatek,mt2712-infracfg";
1287c2c59456SMiles Chen break;
1288c2c59456SMiles Chen case M4U_MT8173:
1289c2c59456SMiles Chen p = "mediatek,mt8173-infracfg";
1290c2c59456SMiles Chen break;
1291c2c59456SMiles Chen default:
1292c2c59456SMiles Chen p = NULL;
1293c2c59456SMiles Chen }
1294c2c59456SMiles Chen
1295c2c59456SMiles Chen infracfg = syscon_regmap_lookup_by_compatible(p);
1296c2c59456SMiles Chen if (IS_ERR(infracfg))
1297c2c59456SMiles Chen return PTR_ERR(infracfg);
12987d748ffdSAngeloGioacchino Del Regno }
1299c2c59456SMiles Chen
1300c2c59456SMiles Chen ret = regmap_read(infracfg, REG_INFRA_MISC, &val);
1301c2c59456SMiles Chen if (ret)
1302c2c59456SMiles Chen return ret;
1303c2c59456SMiles Chen data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN);
1304c2c59456SMiles Chen }
130501e23c93SYong Wu
130642d57fc5SYong Wu banks_num = data->plat_data->banks_num;
13070df4fabeSYong Wu res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
130873b6924cSYang Yingliang if (!res)
130973b6924cSYang Yingliang return -EINVAL;
131042d57fc5SYong Wu if (resource_size(res) < banks_num * MTK_IOMMU_BANK_SZ) {
131142d57fc5SYong Wu dev_err(dev, "banknr %d. res %pR is not enough.\n", banks_num, res);
131242d57fc5SYong Wu return -EINVAL;
131342d57fc5SYong Wu }
131499ca0228SYong Wu base = devm_ioremap_resource(dev, res);
131599ca0228SYong Wu if (IS_ERR(base))
131699ca0228SYong Wu return PTR_ERR(base);
1317b16c0170SJoerg Roedel ioaddr = res->start;
13180df4fabeSYong Wu
131999ca0228SYong Wu data->bank = devm_kmalloc(dev, banks_num * sizeof(*data->bank), GFP_KERNEL);
132099ca0228SYong Wu if (!data->bank)
132199ca0228SYong Wu return -ENOMEM;
132299ca0228SYong Wu
132342d57fc5SYong Wu do {
132442d57fc5SYong Wu if (!data->plat_data->banks_enable[i])
132542d57fc5SYong Wu continue;
132642d57fc5SYong Wu bank = &data->bank[i];
132742d57fc5SYong Wu bank->id = i;
132842d57fc5SYong Wu bank->base = base + i * MTK_IOMMU_BANK_SZ;
132999ca0228SYong Wu bank->m4u_dom = NULL;
133042d57fc5SYong Wu
133142d57fc5SYong Wu bank->irq = platform_get_irq(pdev, i);
133299ca0228SYong Wu if (bank->irq < 0)
133399ca0228SYong Wu return bank->irq;
133499ca0228SYong Wu bank->parent_dev = dev;
133599ca0228SYong Wu bank->parent_data = data;
133699ca0228SYong Wu spin_lock_init(&bank->tlb_lock);
133742d57fc5SYong Wu } while (++i < banks_num);
13380df4fabeSYong Wu
13396b717796SChao Hao if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) {
13400df4fabeSYong Wu data->bclk = devm_clk_get(dev, "bclk");
13410df4fabeSYong Wu if (IS_ERR(data->bclk))
13420df4fabeSYong Wu return PTR_ERR(data->bclk);
13432aa4c259SYong Wu }
13440df4fabeSYong Wu
1345f045e9dfSYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN)) {
1346f045e9dfSYong Wu ret = dma_set_mask(dev, DMA_BIT_MASK(35));
1347f045e9dfSYong Wu if (ret) {
1348f045e9dfSYong Wu dev_err(dev, "Failed to set dma_mask 35.\n");
1349f045e9dfSYong Wu return ret;
1350f045e9dfSYong Wu }
1351f045e9dfSYong Wu }
1352f045e9dfSYong Wu
1353c0b57581SYong Wu pm_runtime_enable(dev);
1354c0b57581SYong Wu
1355d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1356d2e9a110SYong Wu ret = mtk_iommu_mm_dts_parse(dev, &match, data);
1357d2e9a110SYong Wu if (ret) {
13583168010dSNícolas F. R. A. Prado dev_err_probe(dev, ret, "mm dts parse fail\n");
1359c0b57581SYong Wu goto out_runtime_disable;
1360baf94e6eSYong Wu }
1361946e719cSChengci.Xu } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) &&
1362946e719cSChengci.Xu !MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) {
136321fd9be4SAngeloGioacchino Del Regno p = data->plat_data->pericfg_comp_str;
136421fd9be4SAngeloGioacchino Del Regno data->pericfg = syscon_regmap_lookup_by_compatible(p);
136521fd9be4SAngeloGioacchino Del Regno if (IS_ERR(data->pericfg)) {
136621fd9be4SAngeloGioacchino Del Regno ret = PTR_ERR(data->pericfg);
1367f9b8c9b2SYong Wu goto out_runtime_disable;
1368f9b8c9b2SYong Wu }
1369d2e9a110SYong Wu }
1370baf94e6eSYong Wu
13710df4fabeSYong Wu platform_set_drvdata(pdev, data);
13720e5a3f2eSYong Wu mutex_init(&data->mutex);
13730df4fabeSYong Wu
1374b16c0170SJoerg Roedel ret = iommu_device_sysfs_add(&data->iommu, dev, NULL,
1375b16c0170SJoerg Roedel "mtk-iommu.%pa", &ioaddr);
1376b16c0170SJoerg Roedel if (ret)
1377baf94e6eSYong Wu goto out_link_remove;
1378b16c0170SJoerg Roedel
13792d471b20SRobin Murphy ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev);
1380b16c0170SJoerg Roedel if (ret)
1381986d9ec5SYong Wu goto out_sysfs_remove;
1382b16c0170SJoerg Roedel
13839e3a2a64SYong Wu if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) {
13849e3a2a64SYong Wu list_add_tail(&data->list, data->plat_data->hw_list);
13859e3a2a64SYong Wu data->hw_list = data->plat_data->hw_list;
13869e3a2a64SYong Wu } else {
13879e3a2a64SYong Wu INIT_LIST_HEAD(&data->hw_list_head);
13889e3a2a64SYong Wu list_add_tail(&data->list, &data->hw_list_head);
13899e3a2a64SYong Wu data->hw_list = &data->hw_list_head;
13909e3a2a64SYong Wu }
13917c3a2ec0SYong Wu
1392d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1393986d9ec5SYong Wu ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
1394986d9ec5SYong Wu if (ret)
1395e7629070SYong Wu goto out_list_del;
1396e7629070SYong Wu }
1397986d9ec5SYong Wu return ret;
1398986d9ec5SYong Wu
1399986d9ec5SYong Wu out_list_del:
1400986d9ec5SYong Wu list_del(&data->list);
1401986d9ec5SYong Wu iommu_device_unregister(&data->iommu);
1402986d9ec5SYong Wu out_sysfs_remove:
1403986d9ec5SYong Wu iommu_device_sysfs_remove(&data->iommu);
1404baf94e6eSYong Wu out_link_remove:
1405d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM))
1406baf94e6eSYong Wu device_link_remove(data->smicomm_dev, dev);
1407c0b57581SYong Wu out_runtime_disable:
1408c0b57581SYong Wu pm_runtime_disable(dev);
1409986d9ec5SYong Wu return ret;
14100df4fabeSYong Wu }
14110df4fabeSYong Wu
mtk_iommu_remove(struct platform_device * pdev)1412d8149d39SUwe Kleine-König static void mtk_iommu_remove(struct platform_device *pdev)
14130df4fabeSYong Wu {
14140df4fabeSYong Wu struct mtk_iommu_data *data = platform_get_drvdata(pdev);
141542d57fc5SYong Wu struct mtk_iommu_bank_data *bank;
141642d57fc5SYong Wu int i;
14170df4fabeSYong Wu
1418b16c0170SJoerg Roedel iommu_device_sysfs_remove(&data->iommu);
1419b16c0170SJoerg Roedel iommu_device_unregister(&data->iommu);
1420b16c0170SJoerg Roedel
1421ee55f75eSYong Wu list_del(&data->list);
14220df4fabeSYong Wu
1423d2e9a110SYong Wu if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1424baf94e6eSYong Wu device_link_remove(data->smicomm_dev, &pdev->dev);
1425d2e9a110SYong Wu component_master_del(&pdev->dev, &mtk_iommu_com_ops);
1426d2e9a110SYong Wu }
1427c0b57581SYong Wu pm_runtime_disable(&pdev->dev);
142842d57fc5SYong Wu for (i = 0; i < data->plat_data->banks_num; i++) {
142942d57fc5SYong Wu bank = &data->bank[i];
143042d57fc5SYong Wu if (!bank->m4u_dom)
143142d57fc5SYong Wu continue;
143299ca0228SYong Wu devm_free_irq(&pdev->dev, bank->irq, bank);
143342d57fc5SYong Wu }
14340df4fabeSYong Wu }
14350df4fabeSYong Wu
mtk_iommu_runtime_suspend(struct device * dev)143634665c79SYong Wu static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev)
14370df4fabeSYong Wu {
14380df4fabeSYong Wu struct mtk_iommu_data *data = dev_get_drvdata(dev);
14390df4fabeSYong Wu struct mtk_iommu_suspend_reg *reg = &data->reg;
1440d7127de1SYong Wu void __iomem *base;
1441d7127de1SYong Wu int i = 0;
14420df4fabeSYong Wu
1443d7127de1SYong Wu base = data->bank[i].base;
144435c1b48dSChao Hao reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL);
144575eed350SChao Hao reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);
14460df4fabeSYong Wu reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
14470df4fabeSYong Wu reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
1448b9475b34SYong Wu reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG);
1449d7127de1SYong Wu do {
1450d7127de1SYong Wu if (!data->plat_data->banks_enable[i])
1451d7127de1SYong Wu continue;
1452d7127de1SYong Wu base = data->bank[i].base;
1453d7127de1SYong Wu reg->int_control[i] = readl_relaxed(base + REG_MMU_INT_CONTROL0);
1454d7127de1SYong Wu reg->int_main_control[i] = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
1455d7127de1SYong Wu reg->ivrp_paddr[i] = readl_relaxed(base + REG_MMU_IVRP_PADDR);
1456d7127de1SYong Wu } while (++i < data->plat_data->banks_num);
14576254b64fSYong Wu clk_disable_unprepare(data->bclk);
14580df4fabeSYong Wu return 0;
14590df4fabeSYong Wu }
14600df4fabeSYong Wu
mtk_iommu_runtime_resume(struct device * dev)146134665c79SYong Wu static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
14620df4fabeSYong Wu {
14630df4fabeSYong Wu struct mtk_iommu_data *data = dev_get_drvdata(dev);
14640df4fabeSYong Wu struct mtk_iommu_suspend_reg *reg = &data->reg;
1465d7127de1SYong Wu struct mtk_iommu_domain *m4u_dom;
1466d7127de1SYong Wu void __iomem *base;
1467d7127de1SYong Wu int ret, i = 0;
14680df4fabeSYong Wu
14696254b64fSYong Wu ret = clk_prepare_enable(data->bclk);
14706254b64fSYong Wu if (ret) {
14716254b64fSYong Wu dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
14726254b64fSYong Wu return ret;
14736254b64fSYong Wu }
1474b34ea31fSDafna Hirschfeld
1475b34ea31fSDafna Hirschfeld /*
1476b34ea31fSDafna Hirschfeld * Uppon first resume, only enable the clk and return, since the values of the
1477b34ea31fSDafna Hirschfeld * registers are not yet set.
1478b34ea31fSDafna Hirschfeld */
1479d7127de1SYong Wu if (!reg->wr_len_ctrl)
1480b34ea31fSDafna Hirschfeld return 0;
1481b34ea31fSDafna Hirschfeld
1482d7127de1SYong Wu base = data->bank[i].base;
148335c1b48dSChao Hao writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL);
148475eed350SChao Hao writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
14850df4fabeSYong Wu writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
14860df4fabeSYong Wu writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
1487b9475b34SYong Wu writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
1488d7127de1SYong Wu do {
1489d7127de1SYong Wu m4u_dom = data->bank[i].m4u_dom;
1490d7127de1SYong Wu if (!data->plat_data->banks_enable[i] || !m4u_dom)
1491d7127de1SYong Wu continue;
1492d7127de1SYong Wu base = data->bank[i].base;
1493d7127de1SYong Wu writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0);
1494d7127de1SYong Wu writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL);
1495d7127de1SYong Wu writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR);
1496301c3ca1SYunfei Wang writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR);
1497d7127de1SYong Wu } while (++i < data->plat_data->banks_num);
14984f23f6d4SYong Wu
14994f23f6d4SYong Wu /*
15004f23f6d4SYong Wu * Users may allocate dma buffer before they call pm_runtime_get,
15014f23f6d4SYong Wu * in which case it will lack the necessary tlb flush.
15024f23f6d4SYong Wu * Thus, make sure to update the tlb after each PM resume.
15034f23f6d4SYong Wu */
15044f23f6d4SYong Wu mtk_iommu_tlb_flush_all(data);
15050df4fabeSYong Wu return 0;
15060df4fabeSYong Wu }
15070df4fabeSYong Wu
1508e6dec923SYong Wu static const struct dev_pm_ops mtk_iommu_pm_ops = {
150934665c79SYong Wu SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL)
151034665c79SYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
151134665c79SYong Wu pm_runtime_force_resume)
15120df4fabeSYong Wu };
15130df4fabeSYong Wu
1514cecdce9dSYong Wu static const struct mtk_iommu_plat_data mt2712_data = {
1515cecdce9dSYong Wu .m4u_plat = M4U_MT2712,
1516d2e9a110SYong Wu .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE |
1517d2e9a110SYong Wu MTK_IOMMU_TYPE_MM,
15189e3a2a64SYong Wu .hw_list = &m4ulist,
1519b053bc71SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
1520585e58f4SYong Wu .iova_region = single_domain,
152199ca0228SYong Wu .banks_num = 1,
152299ca0228SYong Wu .banks_enable = {true},
1523585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain),
152437276e00SChao Hao .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
1525cecdce9dSYong Wu };
1526cecdce9dSYong Wu
1527068c86e9SChao Hao static const struct mtk_iommu_plat_data mt6779_data = {
1528068c86e9SChao Hao .m4u_plat = M4U_MT6779,
1529d2e9a110SYong Wu .flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN |
1530301c3ca1SYunfei Wang MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN,
1531068c86e9SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
153299ca0228SYong Wu .banks_num = 1,
153399ca0228SYong Wu .banks_enable = {true},
1534585e58f4SYong Wu .iova_region = single_domain,
1535585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain),
1536068c86e9SChao Hao .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
1537cecdce9dSYong Wu };
1538cecdce9dSYong Wu
1539717ec15eSAngeloGioacchino Del Regno static const struct mtk_iommu_plat_data mt6795_data = {
1540717ec15eSAngeloGioacchino Del Regno .m4u_plat = M4U_MT6795,
1541717ec15eSAngeloGioacchino Del Regno .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
1542717ec15eSAngeloGioacchino Del Regno HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM |
1543717ec15eSAngeloGioacchino Del Regno TF_PORT_TO_ADDR_MT8173,
1544717ec15eSAngeloGioacchino Del Regno .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
1545717ec15eSAngeloGioacchino Del Regno .banks_num = 1,
1546717ec15eSAngeloGioacchino Del Regno .banks_enable = {true},
1547717ec15eSAngeloGioacchino Del Regno .iova_region = single_domain,
1548717ec15eSAngeloGioacchino Del Regno .iova_region_nr = ARRAY_SIZE(single_domain),
1549717ec15eSAngeloGioacchino Del Regno .larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. */
1550717ec15eSAngeloGioacchino Del Regno };
1551717ec15eSAngeloGioacchino Del Regno
15523c213562SFabien Parent static const struct mtk_iommu_plat_data mt8167_data = {
15533c213562SFabien Parent .m4u_plat = M4U_MT8167,
1554d2e9a110SYong Wu .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM,
15553c213562SFabien Parent .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
155699ca0228SYong Wu .banks_num = 1,
155799ca0228SYong Wu .banks_enable = {true},
1558585e58f4SYong Wu .iova_region = single_domain,
1559585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain),
15603c213562SFabien Parent .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
15613c213562SFabien Parent };
15623c213562SFabien Parent
1563cecdce9dSYong Wu static const struct mtk_iommu_plat_data mt8173_data = {
1564cecdce9dSYong Wu .m4u_plat = M4U_MT8173,
1565d1b5ef00SFabien Parent .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
156686580ec9SAngeloGioacchino Del Regno HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM |
156786580ec9SAngeloGioacchino Del Regno TF_PORT_TO_ADDR_MT8173,
1568b053bc71SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
156999ca0228SYong Wu .banks_num = 1,
157099ca0228SYong Wu .banks_enable = {true},
1571585e58f4SYong Wu .iova_region = single_domain,
1572585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain),
157337276e00SChao Hao .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
1574cecdce9dSYong Wu };
1575cecdce9dSYong Wu
1576907ba6a1SYong Wu static const struct mtk_iommu_plat_data mt8183_data = {
1577907ba6a1SYong Wu .m4u_plat = M4U_MT8183,
1578d2e9a110SYong Wu .flags = RESET_AXI | MTK_IOMMU_TYPE_MM,
1579b053bc71SChao Hao .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
158099ca0228SYong Wu .banks_num = 1,
158199ca0228SYong Wu .banks_enable = {true},
1582585e58f4SYong Wu .iova_region = single_domain,
1583585e58f4SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain),
158437276e00SChao Hao .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
1585907ba6a1SYong Wu };
1586907ba6a1SYong Wu
1587f5d4233aSYong Wu static const unsigned int mt8186_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
1588f5d4233aSYong Wu [0] = {~0, ~0, ~0}, /* Region0: all ports for larb0/1/2 */
1589f5d4233aSYong Wu [1] = {0, 0, 0, 0, ~0, 0, 0, ~0}, /* Region1: larb4/7 */
1590f5d4233aSYong Wu [2] = {0, 0, 0, 0, 0, 0, 0, 0, /* Region2: larb8/9/11/13/16/17/19/20 */
1591f5d4233aSYong Wu ~0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), 0, 0,
1592f5d4233aSYong Wu /* larb13: the other ports except port9/10 */
1593f5d4233aSYong Wu ~0, ~0, 0, ~0, ~0},
1594f5d4233aSYong Wu [3] = {0},
1595f5d4233aSYong Wu [4] = {[13] = BIT(9) | BIT(10)}, /* larb13 port9/10 */
1596f5d4233aSYong Wu [5] = {[14] = ~0}, /* larb14 */
1597f5d4233aSYong Wu };
1598f5d4233aSYong Wu
1599e8d7ccaaSYong Wu static const struct mtk_iommu_plat_data mt8186_data_mm = {
1600e8d7ccaaSYong Wu .m4u_plat = M4U_MT8186,
1601e8d7ccaaSYong Wu .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1602e8d7ccaaSYong Wu WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM,
1603e8d7ccaaSYong Wu .larbid_remap = {{0}, {1, MTK_INVALID_LARBID, 8}, {4}, {7}, {2}, {9, 11, 19, 20},
1604e8d7ccaaSYong Wu {MTK_INVALID_LARBID, 14, 16},
1605e8d7ccaaSYong Wu {MTK_INVALID_LARBID, 13, MTK_INVALID_LARBID, 17}},
1606e8d7ccaaSYong Wu .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
1607e8d7ccaaSYong Wu .banks_num = 1,
1608e8d7ccaaSYong Wu .banks_enable = {true},
1609e8d7ccaaSYong Wu .iova_region = mt8192_multi_dom,
1610e8d7ccaaSYong Wu .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1611f5d4233aSYong Wu .iova_region_larb_msk = mt8186_larb_region_msk,
1612e8d7ccaaSYong Wu };
1613e8d7ccaaSYong Wu
1614a09e8403SChengci.Xu static const struct mtk_iommu_plat_data mt8188_data_infra = {
1615a09e8403SChengci.Xu .m4u_plat = M4U_MT8188,
1616a09e8403SChengci.Xu .flags = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO |
1617a09e8403SChengci.Xu MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT |
1618a09e8403SChengci.Xu PGTABLE_PA_35_EN | CFG_IFA_MASTER_IN_ATF,
1619a09e8403SChengci.Xu .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
1620a09e8403SChengci.Xu .banks_num = 1,
1621a09e8403SChengci.Xu .banks_enable = {true},
1622a09e8403SChengci.Xu .iova_region = single_domain,
1623a09e8403SChengci.Xu .iova_region_nr = ARRAY_SIZE(single_domain),
1624a09e8403SChengci.Xu };
1625a09e8403SChengci.Xu
16261e8a4639SYong Wu static const u32 mt8188_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
16271e8a4639SYong Wu [0] = {~0, ~0, ~0, ~0}, /* Region0: all ports for larb0/1/2/3 */
16281e8a4639SYong Wu [1] = {0, 0, 0, 0, 0, 0, 0, 0,
16291e8a4639SYong Wu 0, 0, 0, 0, 0, 0, 0, 0,
16301e8a4639SYong Wu 0, 0, 0, 0, 0, ~0, ~0, ~0}, /* Region1: larb19(21)/21(22)/23 */
16311e8a4639SYong Wu [2] = {0, 0, 0, 0, ~0, ~0, ~0, ~0, /* Region2: the other larbs. */
16321e8a4639SYong Wu ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0,
16331e8a4639SYong Wu ~0, ~0, ~0, ~0, ~0, 0, 0, 0,
16341e8a4639SYong Wu 0, ~0},
16351e8a4639SYong Wu [3] = {0},
16361e8a4639SYong Wu [4] = {[24] = BIT(0) | BIT(1)}, /* Only larb27(24) port0/1 */
16371e8a4639SYong Wu [5] = {[24] = BIT(2) | BIT(3)}, /* Only larb27(24) port2/3 */
16381e8a4639SYong Wu };
16391e8a4639SYong Wu
1640a09e8403SChengci.Xu static const struct mtk_iommu_plat_data mt8188_data_vdo = {
1641a09e8403SChengci.Xu .m4u_plat = M4U_MT8188,
1642a09e8403SChengci.Xu .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
1643a09e8403SChengci.Xu WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE |
1644a09e8403SChengci.Xu PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM,
1645a09e8403SChengci.Xu .hw_list = &m4ulist,
1646a09e8403SChengci.Xu .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
1647a09e8403SChengci.Xu .banks_num = 1,
1648a09e8403SChengci.Xu .banks_enable = {true},
1649a09e8403SChengci.Xu .iova_region = mt8192_multi_dom,
1650a09e8403SChengci.Xu .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
16511e8a4639SYong Wu .iova_region_larb_msk = mt8188_larb_region_msk,
1652a09e8403SChengci.Xu .larbid_remap = {{2}, {0}, {21}, {0}, {19}, {9, 10,
1653a09e8403SChengci.Xu 11 /* 11a */, 25 /* 11c */},
1654a09e8403SChengci.Xu {13, 0, 29 /* 16b */, 30 /* 17b */, 0}, {5}},
1655a09e8403SChengci.Xu };
1656a09e8403SChengci.Xu
1657a09e8403SChengci.Xu static const struct mtk_iommu_plat_data mt8188_data_vpp = {
1658a09e8403SChengci.Xu .m4u_plat = M4U_MT8188,
1659a09e8403SChengci.Xu .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
1660a09e8403SChengci.Xu WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE |
1661a09e8403SChengci.Xu PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM,
1662a09e8403SChengci.Xu .hw_list = &m4ulist,
1663a09e8403SChengci.Xu .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
1664a09e8403SChengci.Xu .banks_num = 1,
1665a09e8403SChengci.Xu .banks_enable = {true},
1666a09e8403SChengci.Xu .iova_region = mt8192_multi_dom,
1667a09e8403SChengci.Xu .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
16681e8a4639SYong Wu .iova_region_larb_msk = mt8188_larb_region_msk,
1669a09e8403SChengci.Xu .larbid_remap = {{1}, {3}, {23}, {7}, {MTK_INVALID_LARBID},
1670a09e8403SChengci.Xu {12, 15, 24 /* 11b */}, {14, MTK_INVALID_LARBID,
1671a09e8403SChengci.Xu 16 /* 16a */, 17 /* 17a */, MTK_INVALID_LARBID,
1672a09e8403SChengci.Xu 27, 28 /* ccu0 */, MTK_INVALID_LARBID}, {4, 6}},
1673a09e8403SChengci.Xu };
1674a09e8403SChengci.Xu
16756b1317f9SYong Wu static const unsigned int mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
16766b1317f9SYong Wu [0] = {~0, ~0}, /* Region0: larb0/1 */
16776b1317f9SYong Wu [1] = {0, 0, 0, 0, ~0, ~0, 0, ~0}, /* Region1: larb4/5/7 */
16786b1317f9SYong Wu [2] = {0, 0, ~0, 0, 0, 0, 0, 0, /* Region2: larb2/9/11/13/14/16/17/18/19/20 */
16796b1317f9SYong Wu 0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), ~(u32)(BIT(4) | BIT(5)), 0,
16806b1317f9SYong Wu ~0, ~0, ~0, ~0, ~0},
16816b1317f9SYong Wu [3] = {0},
16826b1317f9SYong Wu [4] = {[13] = BIT(9) | BIT(10)}, /* larb13 port9/10 */
16836b1317f9SYong Wu [5] = {[14] = BIT(4) | BIT(5)}, /* larb14 port4/5 */
16840df4fabeSYong Wu };
16850df4fabeSYong Wu
16869e3489e0SYong Wu static const struct mtk_iommu_plat_data mt8192_data = {
16879e3489e0SYong Wu .m4u_plat = M4U_MT8192,
16889ec30c09SYong Wu .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1689d2e9a110SYong Wu WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM,
16909e3489e0SYong Wu .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
169199ca0228SYong Wu .banks_num = 1,
169299ca0228SYong Wu .banks_enable = {true},
16939e3489e0SYong Wu .iova_region = mt8192_multi_dom,
16949e3489e0SYong Wu .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
16956b1317f9SYong Wu .iova_region_larb_msk = mt8192_larb_region_msk,
16969e3489e0SYong Wu .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
16979e3489e0SYong Wu {0, 14, 16}, {0, 13, 18, 17}},
16989e3489e0SYong Wu };
16999e3489e0SYong Wu
1700ef68a193SYong Wu static const struct mtk_iommu_plat_data mt8195_data_infra = {
1701ef68a193SYong Wu .m4u_plat = M4U_MT8195,
1702ef68a193SYong Wu .flags = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO |
1703ef68a193SYong Wu MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT,
1704ef68a193SYong Wu .pericfg_comp_str = "mediatek,mt8195-pericfg_ao",
1705ef68a193SYong Wu .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
17067597e3c5SYong Wu .banks_num = 5,
17077597e3c5SYong Wu .banks_enable = {true, false, false, false, true},
17087597e3c5SYong Wu .banks_portmsk = {[0] = GENMASK(19, 16), /* PCIe */
17097597e3c5SYong Wu [4] = GENMASK(31, 20), /* USB */
17107597e3c5SYong Wu },
1711ef68a193SYong Wu .iova_region = single_domain,
1712ef68a193SYong Wu .iova_region_nr = ARRAY_SIZE(single_domain),
1713ef68a193SYong Wu };
1714ef68a193SYong Wu
1715a43e767dSYong Wu static const unsigned int mt8195_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
1716a43e767dSYong Wu [0] = {~0, ~0, ~0, ~0}, /* Region0: all ports for larb0/1/2/3 */
1717a43e767dSYong Wu [1] = {0, 0, 0, 0, 0, 0, 0, 0,
1718a43e767dSYong Wu 0, 0, 0, 0, 0, 0, 0, 0,
1719a43e767dSYong Wu 0, 0, 0, ~0, ~0, ~0, ~0, ~0, /* Region1: larb19/20/21/22/23/24 */
1720a43e767dSYong Wu ~0},
1721a43e767dSYong Wu [2] = {0, 0, 0, 0, ~0, ~0, ~0, ~0, /* Region2: the other larbs. */
1722a43e767dSYong Wu ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0,
1723a43e767dSYong Wu ~0, ~0, 0, 0, 0, 0, 0, 0,
1724a43e767dSYong Wu 0, ~0, ~0, ~0, ~0},
1725a43e767dSYong Wu [3] = {0},
1726a43e767dSYong Wu [4] = {[18] = BIT(0) | BIT(1)}, /* Only larb18 port0/1 */
1727a43e767dSYong Wu [5] = {[18] = BIT(2) | BIT(3)}, /* Only larb18 port2/3 */
1728a43e767dSYong Wu };
1729a43e767dSYong Wu
1730ef68a193SYong Wu static const struct mtk_iommu_plat_data mt8195_data_vdo = {
1731ef68a193SYong Wu .m4u_plat = M4U_MT8195,
1732ef68a193SYong Wu .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1733ef68a193SYong Wu WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
1734ef68a193SYong Wu .hw_list = &m4ulist,
1735ef68a193SYong Wu .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
173699ca0228SYong Wu .banks_num = 1,
173799ca0228SYong Wu .banks_enable = {true},
1738ef68a193SYong Wu .iova_region = mt8192_multi_dom,
1739ef68a193SYong Wu .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1740a43e767dSYong Wu .iova_region_larb_msk = mt8195_larb_region_msk,
1741ef68a193SYong Wu .larbid_remap = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11},
1742ef68a193SYong Wu {13, 17, 15/* 17b */, 25}, {5}},
1743ef68a193SYong Wu };
1744ef68a193SYong Wu
1745ef68a193SYong Wu static const struct mtk_iommu_plat_data mt8195_data_vpp = {
1746ef68a193SYong Wu .m4u_plat = M4U_MT8195,
1747ef68a193SYong Wu .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
1748ef68a193SYong Wu WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
1749ef68a193SYong Wu .hw_list = &m4ulist,
1750ef68a193SYong Wu .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
175199ca0228SYong Wu .banks_num = 1,
175299ca0228SYong Wu .banks_enable = {true},
1753ef68a193SYong Wu .iova_region = mt8192_multi_dom,
1754ef68a193SYong Wu .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1755a43e767dSYong Wu .iova_region_larb_msk = mt8195_larb_region_msk,
1756ef68a193SYong Wu .larbid_remap = {{1}, {3},
1757ef68a193SYong Wu {22, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 23},
1758ef68a193SYong Wu {8}, {20}, {12},
1759ef68a193SYong Wu /* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */
1760ef68a193SYong Wu {14, 16, 29, 26, 30, 31, 18},
1761ef68a193SYong Wu {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}},
1762ef68a193SYong Wu };
1763ef68a193SYong Wu
17643cd0e4a3SFabien Parent static const struct mtk_iommu_plat_data mt8365_data = {
17653cd0e4a3SFabien Parent .m4u_plat = M4U_MT8365,
17663cd0e4a3SFabien Parent .flags = RESET_AXI | INT_ID_PORT_WIDTH_6,
17673cd0e4a3SFabien Parent .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
17683cd0e4a3SFabien Parent .banks_num = 1,
17693cd0e4a3SFabien Parent .banks_enable = {true},
17703cd0e4a3SFabien Parent .iova_region = single_domain,
17713cd0e4a3SFabien Parent .iova_region_nr = ARRAY_SIZE(single_domain),
17723cd0e4a3SFabien Parent .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
17733cd0e4a3SFabien Parent };
17743cd0e4a3SFabien Parent
17750df4fabeSYong Wu static const struct of_device_id mtk_iommu_of_ids[] = {
1776cecdce9dSYong Wu { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
1777068c86e9SChao Hao { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
1778717ec15eSAngeloGioacchino Del Regno { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data},
17793c213562SFabien Parent { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data},
1780cecdce9dSYong Wu { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
1781907ba6a1SYong Wu { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
1782e8d7ccaaSYong Wu { .compatible = "mediatek,mt8186-iommu-mm", .data = &mt8186_data_mm}, /* mm: m4u */
1783a09e8403SChengci.Xu { .compatible = "mediatek,mt8188-iommu-infra", .data = &mt8188_data_infra},
1784a09e8403SChengci.Xu { .compatible = "mediatek,mt8188-iommu-vdo", .data = &mt8188_data_vdo},
1785a09e8403SChengci.Xu { .compatible = "mediatek,mt8188-iommu-vpp", .data = &mt8188_data_vpp},
17869e3489e0SYong Wu { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
1787ef68a193SYong Wu { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra},
1788ef68a193SYong Wu { .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo},
1789ef68a193SYong Wu { .compatible = "mediatek,mt8195-iommu-vpp", .data = &mt8195_data_vpp},
17903cd0e4a3SFabien Parent { .compatible = "mediatek,mt8365-m4u", .data = &mt8365_data},
17910df4fabeSYong Wu {}
17920df4fabeSYong Wu };
1793*7537e31dSKrzysztof Kozlowski MODULE_DEVICE_TABLE(of, mtk_iommu_of_ids);
17940df4fabeSYong Wu
17950df4fabeSYong Wu static struct platform_driver mtk_iommu_driver = {
17960df4fabeSYong Wu .probe = mtk_iommu_probe,
1797d8149d39SUwe Kleine-König .remove_new = mtk_iommu_remove,
17980df4fabeSYong Wu .driver = {
17990df4fabeSYong Wu .name = "mtk-iommu",
1800f53dd978SKrzysztof Kozlowski .of_match_table = mtk_iommu_of_ids,
18010df4fabeSYong Wu .pm = &mtk_iommu_pm_ops,
18020df4fabeSYong Wu }
18030df4fabeSYong Wu };
180418d8c74eSYong Wu module_platform_driver(mtk_iommu_driver);
18050df4fabeSYong Wu
180618d8c74eSYong Wu MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations");
180718d8c74eSYong Wu MODULE_LICENSE("GPL v2");
1808