1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2a439fe51SSam Ravnborg /* iommu.h: Definitions for the sun4m IOMMU.
3a439fe51SSam Ravnborg *
4a439fe51SSam Ravnborg * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5a439fe51SSam Ravnborg */
6a439fe51SSam Ravnborg #ifndef _SPARC_IOMMU_H
7a439fe51SSam Ravnborg #define _SPARC_IOMMU_H
8a439fe51SSam Ravnborg
9a439fe51SSam Ravnborg #include <asm/page.h>
10a439fe51SSam Ravnborg #include <asm/bitext.h>
11a439fe51SSam Ravnborg
12a439fe51SSam Ravnborg /* The iommu handles all virtual to physical address translations
13a439fe51SSam Ravnborg * that occur between the SBUS and physical memory. Access by
14a439fe51SSam Ravnborg * the cpu to IO registers and similar go over the mbus so are
15a439fe51SSam Ravnborg * translated by the on chip SRMMU. The iommu and the srmmu do
16a439fe51SSam Ravnborg * not need to have the same translations at all, in fact most
17a439fe51SSam Ravnborg * of the time the translations they handle are a disjunct set.
18a439fe51SSam Ravnborg * Basically the iommu handles all dvma sbus activity.
19a439fe51SSam Ravnborg */
20a439fe51SSam Ravnborg
21a439fe51SSam Ravnborg /* The IOMMU registers occupy three pages in IO space. */
22a439fe51SSam Ravnborg struct iommu_regs {
23a439fe51SSam Ravnborg /* First page */
24a439fe51SSam Ravnborg volatile unsigned long control; /* IOMMU control */
25a439fe51SSam Ravnborg volatile unsigned long base; /* Physical base of iopte page table */
26a439fe51SSam Ravnborg volatile unsigned long _unused1[3];
27a439fe51SSam Ravnborg volatile unsigned long tlbflush; /* write only */
28a439fe51SSam Ravnborg volatile unsigned long pageflush; /* write only */
29a439fe51SSam Ravnborg volatile unsigned long _unused2[1017];
30a439fe51SSam Ravnborg /* Second page */
31a439fe51SSam Ravnborg volatile unsigned long afsr; /* Async-fault status register */
32a439fe51SSam Ravnborg volatile unsigned long afar; /* Async-fault physical address */
33a439fe51SSam Ravnborg volatile unsigned long _unused3[2];
34a439fe51SSam Ravnborg volatile unsigned long sbuscfg0; /* SBUS configuration registers, per-slot */
35a439fe51SSam Ravnborg volatile unsigned long sbuscfg1;
36a439fe51SSam Ravnborg volatile unsigned long sbuscfg2;
37a439fe51SSam Ravnborg volatile unsigned long sbuscfg3;
38a439fe51SSam Ravnborg volatile unsigned long mfsr; /* Memory-fault status register */
39a439fe51SSam Ravnborg volatile unsigned long mfar; /* Memory-fault physical address */
40a439fe51SSam Ravnborg volatile unsigned long _unused4[1014];
41a439fe51SSam Ravnborg /* Third page */
42a439fe51SSam Ravnborg volatile unsigned long mid; /* IOMMU module-id */
43a439fe51SSam Ravnborg };
44a439fe51SSam Ravnborg
45a439fe51SSam Ravnborg #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
46a439fe51SSam Ravnborg #define IOMMU_CTRL_VERS 0x0f000000 /* Version */
47a439fe51SSam Ravnborg #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
48a439fe51SSam Ravnborg #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
49a439fe51SSam Ravnborg #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
50a439fe51SSam Ravnborg #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
51a439fe51SSam Ravnborg #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
52a439fe51SSam Ravnborg #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
53a439fe51SSam Ravnborg #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
54a439fe51SSam Ravnborg #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
55a439fe51SSam Ravnborg #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
56a439fe51SSam Ravnborg #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
57a439fe51SSam Ravnborg
58a439fe51SSam Ravnborg #define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
59a439fe51SSam Ravnborg #define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */
60a439fe51SSam Ravnborg #define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */
61a439fe51SSam Ravnborg #define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */
62a439fe51SSam Ravnborg #define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
63a439fe51SSam Ravnborg #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
64a439fe51SSam Ravnborg #define IOMMU_AFSR_RESV 0x00f00000 /* Reserver, forced to 0x8 by hardware */
65a439fe51SSam Ravnborg #define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
66a439fe51SSam Ravnborg #define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
67a439fe51SSam Ravnborg #define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
68a439fe51SSam Ravnborg
69a439fe51SSam Ravnborg #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
70a439fe51SSam Ravnborg #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
71a439fe51SSam Ravnborg #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
72a439fe51SSam Ravnborg #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
73a439fe51SSam Ravnborg produced by this device as pure
74a439fe51SSam Ravnborg physical. */
75a439fe51SSam Ravnborg
76a439fe51SSam Ravnborg #define IOMMU_MFSR_ERR 0x80000000 /* One or more of PERR1 or PERR0 */
77a439fe51SSam Ravnborg #define IOMMU_MFSR_S 0x01000000 /* Sparc was in supervisor mode */
78a439fe51SSam Ravnborg #define IOMMU_MFSR_CPU 0x00800000 /* CPU transaction caused parity error */
79a439fe51SSam Ravnborg #define IOMMU_MFSR_ME 0x00080000 /* Multiple parity errors occurred */
80a439fe51SSam Ravnborg #define IOMMU_MFSR_PERR 0x00006000 /* high bit indicates parity error occurred
81a439fe51SSam Ravnborg on the even word of the access, low bit
82a439fe51SSam Ravnborg indicated odd word caused the parity error */
83a439fe51SSam Ravnborg #define IOMMU_MFSR_BM 0x00001000 /* Error occurred while in boot mode */
84a439fe51SSam Ravnborg #define IOMMU_MFSR_C 0x00000800 /* Address causing error was marked cacheable */
85a439fe51SSam Ravnborg #define IOMMU_MFSR_RTYP 0x000000f0 /* Memory request transaction type */
86a439fe51SSam Ravnborg
87a439fe51SSam Ravnborg #define IOMMU_MID_SBAE 0x001f0000 /* SBus arbitration enable */
88a439fe51SSam Ravnborg #define IOMMU_MID_SE 0x00100000 /* Enables SCSI/ETHERNET arbitration */
89a439fe51SSam Ravnborg #define IOMMU_MID_SB3 0x00080000 /* Enable SBUS device 3 arbitration */
90a439fe51SSam Ravnborg #define IOMMU_MID_SB2 0x00040000 /* Enable SBUS device 2 arbitration */
91a439fe51SSam Ravnborg #define IOMMU_MID_SB1 0x00020000 /* Enable SBUS device 1 arbitration */
92a439fe51SSam Ravnborg #define IOMMU_MID_SB0 0x00010000 /* Enable SBUS device 0 arbitration */
93a439fe51SSam Ravnborg #define IOMMU_MID_MID 0x0000000f /* Module-id, hardcoded to 0x8 */
94a439fe51SSam Ravnborg
95a439fe51SSam Ravnborg /* The format of an iopte in the page tables */
96a439fe51SSam Ravnborg #define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
97a439fe51SSam Ravnborg #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
98a439fe51SSam Ravnborg #define IOPTE_WRITE 0x00000004 /* Writeable */
99a439fe51SSam Ravnborg #define IOPTE_VALID 0x00000002 /* IOPTE is valid */
100a439fe51SSam Ravnborg #define IOPTE_WAZ 0x00000001 /* Write as zeros */
101a439fe51SSam Ravnborg
102a439fe51SSam Ravnborg struct iommu_struct {
103f977ea49SSam Ravnborg struct iommu_regs __iomem *regs;
104a439fe51SSam Ravnborg iopte_t *page_table;
105a439fe51SSam Ravnborg /* For convenience */
106a439fe51SSam Ravnborg unsigned long start; /* First managed virtual address */
107a439fe51SSam Ravnborg unsigned long end; /* Last managed virtual address */
108a439fe51SSam Ravnborg
109a439fe51SSam Ravnborg struct bit_map usemap;
110a439fe51SSam Ravnborg };
111a439fe51SSam Ravnborg
iommu_invalidate(struct iommu_regs __iomem * regs)112f977ea49SSam Ravnborg static inline void iommu_invalidate(struct iommu_regs __iomem *regs)
113a439fe51SSam Ravnborg {
114f977ea49SSam Ravnborg sbus_writel(0, ®s->tlbflush);
115a439fe51SSam Ravnborg }
116a439fe51SSam Ravnborg
iommu_invalidate_page(struct iommu_regs __iomem * regs,unsigned long ba)117f977ea49SSam Ravnborg static inline void iommu_invalidate_page(struct iommu_regs __iomem *regs, unsigned long ba)
118a439fe51SSam Ravnborg {
119f977ea49SSam Ravnborg sbus_writel(ba & PAGE_MASK, ®s->pageflush);
120a439fe51SSam Ravnborg }
121a439fe51SSam Ravnborg
122a439fe51SSam Ravnborg #endif /* !(_SPARC_IOMMU_H) */
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