| /linux/drivers/pci/controller/dwc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare-based PCIe controllers"
39 required only for DT-based platforms. ACPI platforms with the
50 DesignWare IP and therefore the driver re-uses the DesignWare
61 and therefore the driver re-uses the DesignWare core functions to
68 bool "Axis ARTPEC-6 PCIe controller (host mode)"
74 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
78 bool "Axis ARTPEC-6 PCIe controller (endpoint mode)"
84 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
88 tristate "Baikal-T1 PCIe controller"
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| H A D | pcie-artpec6.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Axis ARTPEC-6 SoC
23 #include "pcie-designware.h"
25 #define to_artpec6_pcie(x) dev_get_drvdata((x)->dev)
34 struct regmap *regmap; /* DT axis,syscon-pcie */
47 /* ARTPEC-6 specific registers */
56 #define PCIECFG_PCLK_ENABLE BIT(8)
61 /* ARTPEC-7 specific fields */
66 /* ARTPEC-7 specific fields */
88 regmap_read(artpec6_pcie->regmap, offset, &val); in artpec6_pcie_readl()
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | axis,artpec8-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Axis ARTPEC-8 SoC clock controller
10 - Jesper Nilsson <jesper.nilsson@axis.com>
13 ARTPEC-8 clock controller is comprised of several CMU (Clock Management Unit)
17 This external clock must be defined as a fixed-rate clock in dts.
19 CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
26 'include/dt-bindings/clock/axis,artpec8-clk.h' header.
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| /linux/include/dt-bindings/clock/ |
| H A D | axis,artpec6-clkctrl.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * ARTPEC-6 clock controller indexes
19 #define ARTPEC6_CLK_SD_IMCLK 8
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| H A D | axis,artpec8-clk.h | 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
8 * Device Tree binding constants for ARTPEC-8 clock controller.
22 #define CLK_DOUT_SHARED1_DIV4 8
73 #define CLK_DOUT_CPUCL_CLUSTER_ATCLK 8
91 #define CLK_DOUT_FSYS_PCIE_PHY_REFCLK_SYSPLL 8
147 #define CLK_DOUT_PERI_UART2 8
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | axis,artpec6-pinctrl.txt | 1 Axis ARTPEC-6 Pin Controller
4 - compatible: "axis,artpec6-pinctrl".
5 - reg: Should contain the register physical address and length for the pin
15 Required subnode-properties:
16 - function: Function to mux.
17 - groups: Name of the pin group to use for the function above.
49 Optional subnode-properties (see pinctrl-bindings.txt):
50 - drive-strength: 4, 6, 8, 9 mA. For SD and NAND pins, this is for 3.3V VCCQ3.
51 - bias-pull-up
52 - bias-disable
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| /linux/drivers/crypto/axis/ |
| H A D | artpec6_crypto.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for ARTPEC-6 crypto block using the kernel asynchronous crypto api.
5 * Copyright (C) 2014-2017 Axis Communications AB
13 #include <linux/dma-mapping.h>
14 #include <linux/fault-inject.h>
35 /* Max length of a line in all cache levels for Artpec SoCs. */
118 #define A7_CRY_MD_OPER GENMASK(11, 8)
186 #define MODULE_NAME "Artpec-6 CA"
198 /* The PDMA is a DMA-engine tightly coupled with a ciphering engine.
203 * a 4-byte metadata that is inserted at the beginning of each dma packet.
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| /linux/drivers/clk/axis/ |
| H A D | clk-artpec6.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARTPEC-6 clock initialization
5 * Copyright 2015-2016 Axis Communications AB.
8 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
46 i = of_property_match_string(np, "clock-names", "sys_refclk"); in of_artpec6_clkctrl_setup()
56 clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
59 clks[i] = ERR_PTR(-EPROBE_DEFER); in of_artpec6_clkctrl_setup()
61 clkdata->syscon_base = of_iomap(np, 0); in of_artpec6_clkctrl_setup()
62 BUG_ON(clkdata->syscon_base == NULL); in of_artpec6_clkctrl_setup()
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | snps,dwc-qos-ethernet.txt | 13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
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| /linux/drivers/clk/samsung/ |
| H A D | clk-artpec8.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Common Clock Framework support for ARTPEC-8 SoC.
11 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/axis,artpec8-clk.h>
16 #include "clk-exynos-arm64.h"
244 FFACTOR(CLK_DOUT_CMU_OTP, "dout_clkcmu_otp", "fin_pll", 1, 8, 0),
681 "mout_clk_pll_fsys", CLK_CON_DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL, 0, 8),
842 CLK_OF_DECLARE(artpec8_clk_cmu_imem, "axis,artpec8-cmu-imem", artpec8_clk_cmu_imem_init);
992 * artpec8_cmu_probe - Probe function for ARTPEC platform clocks
995 * Configure clock hierarchy for clock domains of ARTPEC platform
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| /linux/drivers/pinctrl/ |
| H A D | pinctrl-artpec6.c | 2 * Driver for the Axis ARTPEC-6 pin controller
18 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
50 #define ARTPEC6_DRIVE_8mA 8
90 PINCTRL_PIN(8, "GPIO8"),
186 static const unsigned int i2s0_pins0[] = { 8, 9, 10, 11 };
294 .num_pins = ARRAY_SIZE(uart0_pins1) - 2,
360 .num_pins = ARRAY_SIZE(uart5_pins0) - 1,
401 { 0, 35, 0x0 }, /* 0x0 - 0x8c */
402 { 36, 52, 0x100 }, /* 0x100 - 0x140 */
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| /linux/arch/arm/boot/dts/axis/ |
| H A D | artpec6.dtsi | 2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
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| /linux/arch/arm/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
162 The ARM series is a line of low-power-consumption RISC chip designs
164 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
165 manufactured, but legacy ARM-based PC hardware remains popular in
173 relocations. The combined range is -/+ 256 MiB, which is usually
186 default 8
266 Patch phys-to-virt and virt-to-phys translation functions at
270 This can only be used with non-XIP MMU kernels where the base
316 bool "MMU-based Paged Memory Management Support"
319 Select if you want MMU-based virtualised addressing space
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| /linux/drivers/tty/serial/ |
| H A D | samsung_tty.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
21 * BJD, 04-Nov-2004
28 #include <linux/dma-mapping.h>
165 #define portaddr(port, reg) ((port)->membase + (reg))
167 ((unsigned long *)(unsigned long)((port)->membase + (reg)))
171 switch (port->iotype) { in rd_reg()
186 switch (port->iotype) { in wr_reg()
200 /* Byte-order aware bit setting/clearing functions. */
237 return to_platform_device(port->dev)->name; in s3c24xx_serial_portname()
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| /linux/ |
| H A D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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