Lines Matching +full:artpec +full:- +full:8
1 // SPDX-License-Identifier: GPL-2.0-only
8 * Common Clock Framework support for ARTPEC-8 SoC.
11 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/axis,artpec8-clk.h>
16 #include "clk-exynos-arm64.h"
244 FFACTOR(CLK_DOUT_CMU_OTP, "dout_clkcmu_otp", "fin_pll", 1, 8, 0),
681 "mout_clk_pll_fsys", CLK_CON_DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL, 0, 8),
842 CLK_OF_DECLARE(artpec8_clk_cmu_imem, "axis,artpec8-cmu-imem", artpec8_clk_cmu_imem_init);
992 * artpec8_cmu_probe - Probe function for ARTPEC platform clocks
995 * Configure clock hierarchy for clock domains of ARTPEC platform
1000 struct device *dev = &pdev->dev; in artpec8_cmu_probe()
1003 exynos_arm64_register_cmu(dev, dev->of_node, info); in artpec8_cmu_probe()
1010 .compatible = "axis,artpec8-cmu-cmu",
1013 .compatible = "axis,artpec8-cmu-bus",
1016 .compatible = "axis,artpec8-cmu-core",
1019 .compatible = "axis,artpec8-cmu-cpucl",
1022 .compatible = "axis,artpec8-cmu-fsys",
1025 .compatible = "axis,artpec8-cmu-peri",
1033 .name = "artpec8-cmu",