1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2025 Samsung Electronics Co., Ltd.
4 * https://www.samsung.com
5 * Copyright (c) 2025 Axis Communications AB.
6 * https://www.axis.com
7 *
8 * Common Clock Framework support for ARTPEC-8 SoC.
9 */
10
11 #include <linux/clk-provider.h>
12 #include <linux/platform_device.h>
13 #include <dt-bindings/clock/axis,artpec8-clk.h>
14
15 #include "clk.h"
16 #include "clk-exynos-arm64.h"
17
18 /* NOTE: Must be equal to the last clock ID increased by one */
19 #define CMU_CMU_NR_CLK (CLK_DOUT_CMU_VPP_CORE + 1)
20 #define CMU_BUS_NR_CLK (CLK_DOUT_BUS_PCLK + 1)
21 #define CMU_CORE_NR_CLK (CLK_DOUT_CORE_PCLK + 1)
22 #define CMU_CPUCL_NR_CLK (CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK + 1)
23 #define CMU_FSYS_NR_CLK (CLK_GOUT_FSYS_QSPI_IPCLKPORT_SSI_CLK + 1)
24 #define CMU_IMEM_NR_CLK (CLK_GOUT_IMEM_PCLK_TMU0_APBIF + 1)
25 #define CMU_PERI_NR_CLK (CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK + 1)
26
27 /* Register Offset definitions for CMU_CMU (0x12400000) */
28 #define PLL_LOCKTIME_PLL_AUDIO 0x0000
29 #define PLL_LOCKTIME_PLL_SHARED0 0x0004
30 #define PLL_LOCKTIME_PLL_SHARED1 0x0008
31 #define PLL_CON0_PLL_AUDIO 0x0100
32 #define PLL_CON0_PLL_SHARED0 0x0120
33 #define PLL_CON0_PLL_SHARED1 0x0140
34 #define CLK_CON_MUX_CLKCMU_2D 0x1000
35 #define CLK_CON_MUX_CLKCMU_3D 0x1004
36 #define CLK_CON_MUX_CLKCMU_BUS 0x1008
37 #define CLK_CON_MUX_CLKCMU_BUS_DLP 0x100c
38 #define CLK_CON_MUX_CLKCMU_CDC_CORE 0x1010
39 #define CLK_CON_MUX_CLKCMU_FSYS_SCAN0 0x1014
40 #define CLK_CON_MUX_CLKCMU_FSYS_SCAN1 0x1018
41 #define CLK_CON_MUX_CLKCMU_IMEM_JPEG 0x101c
42 #define CLK_CON_MUX_CLKCMU_PERI_DISP 0x1020
43 #define CLK_CON_MUX_CLKCMU_CORE_BUS 0x1024
44 #define CLK_CON_MUX_CLKCMU_CORE_DLP 0x1028
45 #define CLK_CON_MUX_CLKCMU_CPUCL_SWITCH 0x1030
46 #define CLK_CON_MUX_CLKCMU_DLP_CORE 0x1034
47 #define CLK_CON_MUX_CLKCMU_FSYS_BUS 0x1038
48 #define CLK_CON_MUX_CLKCMU_FSYS_IP 0x103c
49 #define CLK_CON_MUX_CLKCMU_IMEM_ACLK 0x1054
50 #define CLK_CON_MUX_CLKCMU_MIF_BUSP 0x1080
51 #define CLK_CON_MUX_CLKCMU_MIF_SWITCH 0x1084
52 #define CLK_CON_MUX_CLKCMU_PERI_IP 0x1088
53 #define CLK_CON_MUX_CLKCMU_RSP_CORE 0x108c
54 #define CLK_CON_MUX_CLKCMU_TRFM_CORE 0x1090
55 #define CLK_CON_MUX_CLKCMU_VCA_ACE 0x1094
56 #define CLK_CON_MUX_CLKCMU_VCA_OD 0x1098
57 #define CLK_CON_MUX_CLKCMU_VIO_CORE 0x109c
58 #define CLK_CON_MUX_CLKCMU_VIP0_CORE 0x10a0
59 #define CLK_CON_MUX_CLKCMU_VIP1_CORE 0x10a4
60 #define CLK_CON_MUX_CLKCMU_VPP_CORE 0x10a8
61
62 #define CLK_CON_DIV_CLKCMU_BUS 0x1800
63 #define CLK_CON_DIV_CLKCMU_BUS_DLP 0x1804
64 #define CLK_CON_DIV_CLKCMU_CDC_CORE 0x1808
65 #define CLK_CON_DIV_CLKCMU_FSYS_SCAN0 0x180c
66 #define CLK_CON_DIV_CLKCMU_FSYS_SCAN1 0x1810
67 #define CLK_CON_DIV_CLKCMU_IMEM_JPEG 0x1814
68 #define CLK_CON_DIV_CLKCMU_MIF_SWITCH 0x1818
69 #define CLK_CON_DIV_CLKCMU_CORE_DLP 0x181c
70 #define CLK_CON_DIV_CLKCMU_CORE_MAIN 0x1820
71 #define CLK_CON_DIV_CLKCMU_PERI_DISP 0x1824
72 #define CLK_CON_DIV_CLKCMU_CPUCL_SWITCH 0x1828
73 #define CLK_CON_DIV_CLKCMU_DLP_CORE 0x182c
74 #define CLK_CON_DIV_CLKCMU_FSYS_BUS 0x1830
75 #define CLK_CON_DIV_CLKCMU_FSYS_IP 0x1834
76 #define CLK_CON_DIV_CLKCMU_VIO_AUDIO 0x1838
77 #define CLK_CON_DIV_CLKCMU_GPU_2D 0x1848
78 #define CLK_CON_DIV_CLKCMU_GPU_3D 0x184c
79 #define CLK_CON_DIV_CLKCMU_IMEM_ACLK 0x1854
80 #define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x1884
81 #define CLK_CON_DIV_CLKCMU_PERI_AUDIO 0x1890
82 #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1894
83 #define CLK_CON_DIV_CLKCMU_RSP_CORE 0x1898
84 #define CLK_CON_DIV_CLKCMU_TRFM_CORE 0x189c
85 #define CLK_CON_DIV_CLKCMU_VCA_ACE 0x18a0
86 #define CLK_CON_DIV_CLKCMU_VCA_OD 0x18a4
87 #define CLK_CON_DIV_CLKCMU_VIO_CORE 0x18ac
88 #define CLK_CON_DIV_CLKCMU_VIP0_CORE 0x18b0
89 #define CLK_CON_DIV_CLKCMU_VIP1_CORE 0x18b4
90 #define CLK_CON_DIV_CLKCMU_VPP_CORE 0x18b8
91 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18bc
92 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18c0
93 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18c4
94 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18c8
95 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18cc
96 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18d0
97
98 static const unsigned long cmu_cmu_clk_regs[] __initconst = {
99 PLL_LOCKTIME_PLL_AUDIO,
100 PLL_LOCKTIME_PLL_SHARED0,
101 PLL_LOCKTIME_PLL_SHARED1,
102 PLL_CON0_PLL_AUDIO,
103 PLL_CON0_PLL_SHARED0,
104 PLL_CON0_PLL_SHARED1,
105 CLK_CON_MUX_CLKCMU_2D,
106 CLK_CON_MUX_CLKCMU_3D,
107 CLK_CON_MUX_CLKCMU_BUS,
108 CLK_CON_MUX_CLKCMU_BUS_DLP,
109 CLK_CON_MUX_CLKCMU_CDC_CORE,
110 CLK_CON_MUX_CLKCMU_FSYS_SCAN0,
111 CLK_CON_MUX_CLKCMU_FSYS_SCAN1,
112 CLK_CON_MUX_CLKCMU_IMEM_JPEG,
113 CLK_CON_MUX_CLKCMU_PERI_DISP,
114 CLK_CON_MUX_CLKCMU_CORE_BUS,
115 CLK_CON_MUX_CLKCMU_CORE_DLP,
116 CLK_CON_MUX_CLKCMU_CPUCL_SWITCH,
117 CLK_CON_MUX_CLKCMU_DLP_CORE,
118 CLK_CON_MUX_CLKCMU_FSYS_BUS,
119 CLK_CON_MUX_CLKCMU_FSYS_IP,
120 CLK_CON_MUX_CLKCMU_IMEM_ACLK,
121 CLK_CON_MUX_CLKCMU_MIF_BUSP,
122 CLK_CON_MUX_CLKCMU_MIF_SWITCH,
123 CLK_CON_MUX_CLKCMU_PERI_IP,
124 CLK_CON_MUX_CLKCMU_RSP_CORE,
125 CLK_CON_MUX_CLKCMU_TRFM_CORE,
126 CLK_CON_MUX_CLKCMU_VCA_ACE,
127 CLK_CON_MUX_CLKCMU_VCA_OD,
128 CLK_CON_MUX_CLKCMU_VIO_CORE,
129 CLK_CON_MUX_CLKCMU_VIP0_CORE,
130 CLK_CON_MUX_CLKCMU_VIP1_CORE,
131 CLK_CON_MUX_CLKCMU_VPP_CORE,
132 CLK_CON_DIV_CLKCMU_BUS,
133 CLK_CON_DIV_CLKCMU_BUS_DLP,
134 CLK_CON_DIV_CLKCMU_CDC_CORE,
135 CLK_CON_DIV_CLKCMU_FSYS_SCAN0,
136 CLK_CON_DIV_CLKCMU_FSYS_SCAN1,
137 CLK_CON_DIV_CLKCMU_IMEM_JPEG,
138 CLK_CON_DIV_CLKCMU_MIF_SWITCH,
139 CLK_CON_DIV_CLKCMU_CORE_DLP,
140 CLK_CON_DIV_CLKCMU_CORE_MAIN,
141 CLK_CON_DIV_CLKCMU_PERI_DISP,
142 CLK_CON_DIV_CLKCMU_CPUCL_SWITCH,
143 CLK_CON_DIV_CLKCMU_DLP_CORE,
144 CLK_CON_DIV_CLKCMU_FSYS_BUS,
145 CLK_CON_DIV_CLKCMU_FSYS_IP,
146 CLK_CON_DIV_CLKCMU_VIO_AUDIO,
147 CLK_CON_DIV_CLKCMU_GPU_2D,
148 CLK_CON_DIV_CLKCMU_GPU_3D,
149 CLK_CON_DIV_CLKCMU_IMEM_ACLK,
150 CLK_CON_DIV_CLKCMU_MIF_BUSP,
151 CLK_CON_DIV_CLKCMU_PERI_AUDIO,
152 CLK_CON_DIV_CLKCMU_PERI_IP,
153 CLK_CON_DIV_CLKCMU_RSP_CORE,
154 CLK_CON_DIV_CLKCMU_TRFM_CORE,
155 CLK_CON_DIV_CLKCMU_VCA_ACE,
156 CLK_CON_DIV_CLKCMU_VCA_OD,
157 CLK_CON_DIV_CLKCMU_VIO_CORE,
158 CLK_CON_DIV_CLKCMU_VIP0_CORE,
159 CLK_CON_DIV_CLKCMU_VIP1_CORE,
160 CLK_CON_DIV_CLKCMU_VPP_CORE,
161 CLK_CON_DIV_PLL_SHARED0_DIV2,
162 CLK_CON_DIV_PLL_SHARED0_DIV3,
163 CLK_CON_DIV_PLL_SHARED0_DIV4,
164 CLK_CON_DIV_PLL_SHARED1_DIV2,
165 CLK_CON_DIV_PLL_SHARED1_DIV3,
166 CLK_CON_DIV_PLL_SHARED1_DIV4,
167 };
168
169 static const struct samsung_pll_rate_table artpec8_pll_audio_rates[] __initconst = {
170 PLL_36XX_RATE(25 * MHZ, 589823913U, 47, 1, 1, 12184),
171 PLL_36XX_RATE(25 * MHZ, 393215942U, 47, 3, 0, 12184),
172 PLL_36XX_RATE(25 * MHZ, 294911956U, 47, 1, 2, 12184),
173 PLL_36XX_RATE(25 * MHZ, 100000000U, 32, 2, 2, 0),
174 PLL_36XX_RATE(25 * MHZ, 98303985U, 47, 3, 2, 12184),
175 PLL_36XX_RATE(25 * MHZ, 49151992U, 47, 3, 3, 12184),
176 };
177
178 static const struct samsung_pll_clock cmu_cmu_pll_clks[] __initconst = {
179 PLL(pll_1017x, CLK_FOUT_SHARED0_PLL, "fout_pll_shared0", "fin_pll",
180 PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, NULL),
181 PLL(pll_1017x, CLK_FOUT_SHARED1_PLL, "fout_pll_shared1", "fin_pll",
182 PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1, NULL),
183 PLL(pll_1031x, CLK_FOUT_AUDIO_PLL, "fout_pll_audio", "fin_pll",
184 PLL_LOCKTIME_PLL_AUDIO, PLL_CON0_PLL_AUDIO, artpec8_pll_audio_rates),
185 };
186
187 PNAME(mout_clkcmu_bus_bus_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
188 "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
189 PNAME(mout_clkcmu_bus_dlp_p) = { "dout_pll_shared0_div2", "dout_pll_shared0_div4",
190 "dout_pll_shared1_div2", "dout_pll_shared1_div4" };
191 PNAME(mout_clkcmu_core_bus_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
192 "dout_pll_shared0_div4", "dout_pll_shared1_div3" };
193 PNAME(mout_clkcmu_core_dlp_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
194 "dout_pll_shared0_div3", "dout_pll_shared1_div3" };
195 PNAME(mout_clkcmu_cpucl_switch_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
196 "dout_pll_shared0_div3", "dout_pll_shared1_div3" };
197 PNAME(mout_clkcmu_fsys_bus_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div2",
198 "dout_pll_shared1_div4", "dout_pll_shared1_div3" };
199 PNAME(mout_clkcmu_fsys_ip_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div3",
200 "dout_pll_shared1_div2", "dout_pll_shared0_div3" };
201 PNAME(mout_clkcmu_fsys_scan0_p) = { "dout_pll_shared0_div4", "dout_pll_shared1_div4" };
202 PNAME(mout_clkcmu_fsys_scan1_p) = { "dout_pll_shared0_div4", "dout_pll_shared1_div4" };
203 PNAME(mout_clkcmu_imem_imem_p) = { "dout_pll_shared1_div4", "dout_pll_shared0_div3",
204 "dout_pll_shared1_div3", "dout_pll_shared1_div2" };
205 PNAME(mout_clkcmu_imem_jpeg_p) = { "dout_pll_shared0_div2", "dout_pll_shared0_div3",
206 "dout_pll_shared1_div2", "dout_pll_shared1_div3" };
207 PNAME(mout_clkcmu_cdc_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
208 "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
209 PNAME(mout_clkcmu_dlp_core_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
210 "dout_pll_shared0_div3", "dout_pll_shared1_div3" };
211 PNAME(mout_clkcmu_3d_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
212 "dout_pll_shared0_div3", "dout_pll_shared1_div3" };
213 PNAME(mout_clkcmu_2d_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
214 "dout_pll_shared0_div3", "dout_pll_shared1_div3" };
215 PNAME(mout_clkcmu_mif_switch_p) = { "dout_pll_shared0", "dout_pll_shared1",
216 "dout_pll_shared0_div2", "dout_pll_shared0_div3" };
217 PNAME(mout_clkcmu_mif_busp_p) = { "dout_pll_shared0_div3", "dout_pll_shared1_div4",
218 "dout_pll_shared0_div4", "dout_pll_shared0_div2" };
219 PNAME(mout_clkcmu_peri_disp_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div2",
220 "dout_pll_shared1_div4", "dout_pll_shared1_div3" };
221 PNAME(mout_clkcmu_peri_ip_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div4",
222 "dout_pll_shared1_div4", "dout_pll_shared0_div2" };
223 PNAME(mout_clkcmu_rsp_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
224 "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
225 PNAME(mout_clkcmu_trfm_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
226 "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
227 PNAME(mout_clkcmu_vca_ace_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
228 "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
229 PNAME(mout_clkcmu_vca_od_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
230 "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
231 PNAME(mout_clkcmu_vio_core_p) = { "dout_pll_shared0_div3", "dout_pll_shared0_div2",
232 "dout_pll_shared1_div2", "dout_pll_shared1_div3" };
233 PNAME(mout_clkcmu_vip0_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
234 "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
235 PNAME(mout_clkcmu_vip1_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
236 "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
237 PNAME(mout_clkcmu_vpp_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
238 "dout_pll_shared1_div3", "dout_pll_shared1_div4" };
239 PNAME(mout_clkcmu_pll_shared0_p) = { "fin_pll", "fout_pll_shared0" };
240 PNAME(mout_clkcmu_pll_shared1_p) = { "fin_pll", "fout_pll_shared1" };
241 PNAME(mout_clkcmu_pll_audio_p) = { "fin_pll", "fout_pll_audio" };
242
243 static const struct samsung_fixed_factor_clock cmu_fixed_factor_clks[] __initconst = {
244 FFACTOR(CLK_DOUT_CMU_OTP, "dout_clkcmu_otp", "fin_pll", 1, 8, 0),
245 };
246
247 static const struct samsung_mux_clock cmu_cmu_mux_clks[] __initconst = {
248 MUX(0, "mout_clkcmu_pll_shared0", mout_clkcmu_pll_shared0_p, PLL_CON0_PLL_SHARED0, 4, 1),
249 MUX(0, "mout_clkcmu_pll_shared1", mout_clkcmu_pll_shared1_p, PLL_CON0_PLL_SHARED1, 4, 1),
250 MUX(0, "mout_clkcmu_pll_audio", mout_clkcmu_pll_audio_p, PLL_CON0_PLL_AUDIO, 4, 1),
251 MUX(0, "mout_clkcmu_bus_bus", mout_clkcmu_bus_bus_p, CLK_CON_MUX_CLKCMU_BUS, 0, 2),
252 MUX(0, "mout_clkcmu_bus_dlp", mout_clkcmu_bus_dlp_p, CLK_CON_MUX_CLKCMU_BUS_DLP, 0, 2),
253 MUX(0, "mout_clkcmu_core_bus", mout_clkcmu_core_bus_p, CLK_CON_MUX_CLKCMU_CORE_BUS, 0, 2),
254 MUX(0, "mout_clkcmu_core_dlp", mout_clkcmu_core_dlp_p, CLK_CON_MUX_CLKCMU_CORE_DLP, 0, 2),
255 MUX(0, "mout_clkcmu_cpucl_switch", mout_clkcmu_cpucl_switch_p,
256 CLK_CON_MUX_CLKCMU_CPUCL_SWITCH, 0, 3),
257 MUX(0, "mout_clkcmu_fsys_bus", mout_clkcmu_fsys_bus_p, CLK_CON_MUX_CLKCMU_FSYS_BUS, 0, 2),
258 MUX(0, "mout_clkcmu_fsys_ip", mout_clkcmu_fsys_ip_p, CLK_CON_MUX_CLKCMU_FSYS_IP, 0, 2),
259 MUX(0, "mout_clkcmu_fsys_scan0", mout_clkcmu_fsys_scan0_p,
260 CLK_CON_MUX_CLKCMU_FSYS_SCAN0, 0, 1),
261 MUX(0, "mout_clkcmu_fsys_scan1", mout_clkcmu_fsys_scan1_p,
262 CLK_CON_MUX_CLKCMU_FSYS_SCAN1, 0, 1),
263 MUX(0, "mout_clkcmu_imem_imem", mout_clkcmu_imem_imem_p,
264 CLK_CON_MUX_CLKCMU_IMEM_ACLK, 0, 2),
265 MUX(0, "mout_clkcmu_imem_jpeg", mout_clkcmu_imem_jpeg_p,
266 CLK_CON_MUX_CLKCMU_IMEM_JPEG, 0, 2),
267 nMUX(0, "mout_clkcmu_cdc_core", mout_clkcmu_cdc_core_p, CLK_CON_MUX_CLKCMU_CDC_CORE, 0, 2),
268 nMUX(0, "mout_clkcmu_dlp_core", mout_clkcmu_dlp_core_p, CLK_CON_MUX_CLKCMU_DLP_CORE, 0, 2),
269 MUX(0, "mout_clkcmu_3d", mout_clkcmu_3d_p, CLK_CON_MUX_CLKCMU_3D, 0, 2),
270 MUX(0, "mout_clkcmu_2d", mout_clkcmu_2d_p, CLK_CON_MUX_CLKCMU_2D, 0, 2),
271 MUX(0, "mout_clkcmu_mif_switch", mout_clkcmu_mif_switch_p,
272 CLK_CON_MUX_CLKCMU_MIF_SWITCH, 0, 2),
273 MUX(0, "mout_clkcmu_mif_busp", mout_clkcmu_mif_busp_p, CLK_CON_MUX_CLKCMU_MIF_BUSP, 0, 2),
274 MUX(0, "mout_clkcmu_peri_disp", mout_clkcmu_peri_disp_p,
275 CLK_CON_MUX_CLKCMU_PERI_DISP, 0, 2),
276 MUX(0, "mout_clkcmu_peri_ip", mout_clkcmu_peri_ip_p, CLK_CON_MUX_CLKCMU_PERI_IP, 0, 2),
277 MUX(0, "mout_clkcmu_rsp_core", mout_clkcmu_rsp_core_p, CLK_CON_MUX_CLKCMU_RSP_CORE, 0, 2),
278 nMUX(0, "mout_clkcmu_trfm_core", mout_clkcmu_trfm_core_p,
279 CLK_CON_MUX_CLKCMU_TRFM_CORE, 0, 2),
280 MUX(0, "mout_clkcmu_vca_ace", mout_clkcmu_vca_ace_p, CLK_CON_MUX_CLKCMU_VCA_ACE, 0, 2),
281 MUX(0, "mout_clkcmu_vca_od", mout_clkcmu_vca_od_p, CLK_CON_MUX_CLKCMU_VCA_OD, 0, 2),
282 MUX(0, "mout_clkcmu_vio_core", mout_clkcmu_vio_core_p, CLK_CON_MUX_CLKCMU_VIO_CORE, 0, 2),
283 nMUX(0, "mout_clkcmu_vip0_core", mout_clkcmu_vip0_core_p,
284 CLK_CON_MUX_CLKCMU_VIP0_CORE, 0, 2),
285 nMUX(0, "mout_clkcmu_vip1_core", mout_clkcmu_vip1_core_p,
286 CLK_CON_MUX_CLKCMU_VIP1_CORE, 0, 2),
287 nMUX(0, "mout_clkcmu_vpp_core", mout_clkcmu_vpp_core_p, CLK_CON_MUX_CLKCMU_VPP_CORE, 0, 2),
288 };
289
290 static const struct samsung_div_clock cmu_cmu_div_clks[] __initconst = {
291 DIV(CLK_DOUT_SHARED0_DIV2, "dout_pll_shared0_div2",
292 "mout_clkcmu_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
293 DIV(CLK_DOUT_SHARED0_DIV3, "dout_pll_shared0_div3",
294 "mout_clkcmu_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
295 DIV(CLK_DOUT_SHARED0_DIV4, "dout_pll_shared0_div4",
296 "dout_pll_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
297 DIV(CLK_DOUT_SHARED1_DIV2, "dout_pll_shared1_div2",
298 "mout_clkcmu_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
299 DIV(CLK_DOUT_SHARED1_DIV3, "dout_pll_shared1_div3",
300 "mout_clkcmu_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
301 DIV(CLK_DOUT_SHARED1_DIV4, "dout_pll_shared1_div4",
302 "dout_pll_shared1_div2", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
303 DIV(CLK_DOUT_CMU_BUS, "dout_clkcmu_bus",
304 "mout_clkcmu_bus_bus", CLK_CON_DIV_CLKCMU_BUS, 0, 4),
305 DIV(CLK_DOUT_CMU_BUS_DLP, "dout_clkcmu_bus_dlp",
306 "mout_clkcmu_bus_dlp", CLK_CON_DIV_CLKCMU_BUS_DLP, 0, 4),
307 DIV(CLK_DOUT_CMU_CORE_MAIN, "dout_clkcmu_core_main",
308 "mout_clkcmu_core_bus", CLK_CON_DIV_CLKCMU_CORE_MAIN, 0, 4),
309 DIV(CLK_DOUT_CMU_CORE_DLP, "dout_clkcmu_core_dlp",
310 "mout_clkcmu_core_dlp", CLK_CON_DIV_CLKCMU_CORE_DLP, 0, 4),
311 DIV(CLK_DOUT_CMU_CPUCL_SWITCH, "dout_clkcmu_cpucl_switch",
312 "mout_clkcmu_cpucl_switch", CLK_CON_DIV_CLKCMU_CPUCL_SWITCH, 0, 3),
313 DIV(CLK_DOUT_CMU_FSYS_BUS, "dout_clkcmu_fsys_bus",
314 "mout_clkcmu_fsys_bus", CLK_CON_DIV_CLKCMU_FSYS_BUS, 0, 4),
315 DIV(CLK_DOUT_CMU_FSYS_IP, "dout_clkcmu_fsys_ip",
316 "mout_clkcmu_fsys_ip", CLK_CON_DIV_CLKCMU_FSYS_IP, 0, 9),
317 DIV(CLK_DOUT_CMU_FSYS_SCAN0, "dout_clkcmu_fsys_scan0",
318 "mout_clkcmu_fsys_scan0", CLK_CON_DIV_CLKCMU_FSYS_SCAN0, 0, 4),
319 DIV(CLK_DOUT_CMU_FSYS_SCAN1, "dout_clkcmu_fsys_scan1",
320 "mout_clkcmu_fsys_scan1", CLK_CON_DIV_CLKCMU_FSYS_SCAN1, 0, 4),
321 DIV(CLK_DOUT_CMU_IMEM_ACLK, "dout_clkcmu_imem_aclk",
322 "mout_clkcmu_imem_imem", CLK_CON_DIV_CLKCMU_IMEM_ACLK, 0, 4),
323 DIV(CLK_DOUT_CMU_IMEM_JPEG, "dout_clkcmu_imem_jpeg",
324 "mout_clkcmu_imem_jpeg", CLK_CON_DIV_CLKCMU_IMEM_JPEG, 0, 4),
325 DIV_F(CLK_DOUT_CMU_CDC_CORE, "dout_clkcmu_cdc_core",
326 "mout_clkcmu_cdc_core", CLK_CON_DIV_CLKCMU_CDC_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
327 DIV_F(CLK_DOUT_CMU_DLP_CORE, "dout_clkcmu_dlp_core",
328 "mout_clkcmu_dlp_core", CLK_CON_DIV_CLKCMU_DLP_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
329 DIV(CLK_DOUT_CMU_GPU_3D, "dout_clkcmu_gpu_3d",
330 "mout_clkcmu_3d", CLK_CON_DIV_CLKCMU_GPU_3D, 0, 3),
331 DIV(CLK_DOUT_CMU_GPU_2D, "dout_clkcmu_gpu_2d",
332 "mout_clkcmu_2d", CLK_CON_DIV_CLKCMU_GPU_2D, 0, 4),
333 DIV(CLK_DOUT_CMU_MIF_SWITCH, "dout_clkcmu_mif_switch",
334 "mout_clkcmu_mif_switch", CLK_CON_DIV_CLKCMU_MIF_SWITCH, 0, 4),
335 DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_clkcmu_mif_busp",
336 "mout_clkcmu_mif_busp", CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 3),
337 DIV(CLK_DOUT_CMU_PERI_DISP, "dout_clkcmu_peri_disp",
338 "mout_clkcmu_peri_disp", CLK_CON_DIV_CLKCMU_PERI_DISP, 0, 4),
339 DIV(CLK_DOUT_CMU_PERI_IP, "dout_clkcmu_peri_ip",
340 "mout_clkcmu_peri_ip", CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
341 DIV(CLK_DOUT_CMU_PERI_AUDIO, "dout_clkcmu_peri_audio",
342 "mout_clkcmu_pll_audio", CLK_CON_DIV_CLKCMU_PERI_AUDIO, 0, 4),
343 DIV(CLK_DOUT_CMU_RSP_CORE, "dout_clkcmu_rsp_core",
344 "mout_clkcmu_rsp_core", CLK_CON_DIV_CLKCMU_RSP_CORE, 0, 4),
345 DIV_F(CLK_DOUT_CMU_TRFM_CORE, "dout_clkcmu_trfm_core",
346 "mout_clkcmu_trfm_core", CLK_CON_DIV_CLKCMU_TRFM_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
347 DIV(CLK_DOUT_CMU_VCA_ACE, "dout_clkcmu_vca_ace",
348 "mout_clkcmu_vca_ace", CLK_CON_DIV_CLKCMU_VCA_ACE, 0, 4),
349 DIV(CLK_DOUT_CMU_VCA_OD, "dout_clkcmu_vca_od",
350 "mout_clkcmu_vca_od", CLK_CON_DIV_CLKCMU_VCA_OD, 0, 4),
351 DIV(CLK_DOUT_CMU_VIO_CORE, "dout_clkcmu_vio_core",
352 "mout_clkcmu_vio_core", CLK_CON_DIV_CLKCMU_VIO_CORE, 0, 4),
353 DIV(CLK_DOUT_CMU_VIO_AUDIO, "dout_clkcmu_vio_audio",
354 "mout_clkcmu_pll_audio", CLK_CON_DIV_CLKCMU_VIO_AUDIO, 0, 4),
355 DIV_F(CLK_DOUT_CMU_VIP0_CORE, "dout_clkcmu_vip0_core",
356 "mout_clkcmu_vip0_core", CLK_CON_DIV_CLKCMU_VIP0_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
357 DIV_F(CLK_DOUT_CMU_VIP1_CORE, "dout_clkcmu_vip1_core",
358 "mout_clkcmu_vip1_core", CLK_CON_DIV_CLKCMU_VIP1_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
359 DIV_F(CLK_DOUT_CMU_VPP_CORE, "dout_clkcmu_vpp_core",
360 "mout_clkcmu_vpp_core", CLK_CON_DIV_CLKCMU_VPP_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
361 };
362
363 static const struct samsung_cmu_info cmu_cmu_info __initconst = {
364 .pll_clks = cmu_cmu_pll_clks,
365 .nr_pll_clks = ARRAY_SIZE(cmu_cmu_pll_clks),
366 .fixed_factor_clks = cmu_fixed_factor_clks,
367 .nr_fixed_factor_clks = ARRAY_SIZE(cmu_fixed_factor_clks),
368 .mux_clks = cmu_cmu_mux_clks,
369 .nr_mux_clks = ARRAY_SIZE(cmu_cmu_mux_clks),
370 .div_clks = cmu_cmu_div_clks,
371 .nr_div_clks = ARRAY_SIZE(cmu_cmu_div_clks),
372 .nr_clk_ids = CMU_CMU_NR_CLK,
373 .clk_regs = cmu_cmu_clk_regs,
374 .nr_clk_regs = ARRAY_SIZE(cmu_cmu_clk_regs),
375 };
376
377 /* Register Offset definitions for CMU_BUS (0x12c10000) */
378 #define PLL_CON0_MUX_CLK_BUS_ACLK_USER 0x0100
379 #define PLL_CON0_MUX_CLK_BUS_DLP_USER 0x0120
380 #define CLK_CON_DIV_CLK_BUS_PCLK 0x1800
381
382 static const unsigned long cmu_bus_clk_regs[] __initconst = {
383 PLL_CON0_MUX_CLK_BUS_ACLK_USER,
384 PLL_CON0_MUX_CLK_BUS_DLP_USER,
385 CLK_CON_DIV_CLK_BUS_PCLK,
386 };
387
388 PNAME(mout_clk_bus_aclk_user_p) = { "fin_pll", "dout_clkcmu_bus" };
389 PNAME(mout_clk_bus_dlp_user_p) = { "fin_pll", "dout_clkcmu_bus_dlp" };
390
391 static const struct samsung_mux_clock cmu_bus_mux_clks[] __initconst = {
392 MUX(CLK_MOUT_BUS_ACLK_USER, "mout_clk_bus_aclk_user",
393 mout_clk_bus_aclk_user_p, PLL_CON0_MUX_CLK_BUS_ACLK_USER, 4, 1),
394 MUX(CLK_MOUT_BUS_DLP_USER, "mout_clk_bus_dlp_user",
395 mout_clk_bus_dlp_user_p, PLL_CON0_MUX_CLK_BUS_DLP_USER, 4, 1),
396 };
397
398 static const struct samsung_div_clock cmu_bus_div_clks[] __initconst = {
399 DIV(CLK_DOUT_BUS_PCLK, "dout_clk_bus_pclk", "mout_clk_bus_aclk_user",
400 CLK_CON_DIV_CLK_BUS_PCLK, 0, 4),
401 };
402
403 static const struct samsung_cmu_info cmu_bus_info __initconst = {
404 .mux_clks = cmu_bus_mux_clks,
405 .nr_mux_clks = ARRAY_SIZE(cmu_bus_mux_clks),
406 .div_clks = cmu_bus_div_clks,
407 .nr_div_clks = ARRAY_SIZE(cmu_bus_div_clks),
408 .nr_clk_ids = CMU_BUS_NR_CLK,
409 .clk_regs = cmu_bus_clk_regs,
410 .nr_clk_regs = ARRAY_SIZE(cmu_bus_clk_regs),
411 };
412
413 /* Register Offset definitions for CMU_CORE (0x12410000) */
414 #define PLL_CON0_MUX_CLK_CORE_ACLK_USER 0x0100
415 #define PLL_CON0_MUX_CLK_CORE_DLP_USER 0x0120
416 #define CLK_CON_DIV_CLK_CORE_PCLK 0x1800
417
418 static const unsigned long cmu_core_clk_regs[] __initconst = {
419 PLL_CON0_MUX_CLK_CORE_ACLK_USER,
420 PLL_CON0_MUX_CLK_CORE_DLP_USER,
421 CLK_CON_DIV_CLK_CORE_PCLK,
422 };
423
424 PNAME(mout_clk_core_aclk_user_p) = { "fin_pll", "dout_clkcmu_core_main" };
425 PNAME(mout_clk_core_dlp_user_p) = { "fin_pll", "dout_clkcmu_core_dlp" };
426
427 static const struct samsung_mux_clock cmu_core_mux_clks[] __initconst = {
428 MUX(CLK_MOUT_CORE_ACLK_USER, "mout_clk_core_aclk_user",
429 mout_clk_core_aclk_user_p, PLL_CON0_MUX_CLK_CORE_ACLK_USER, 4, 1),
430 MUX(CLK_MOUT_CORE_DLP_USER, "mout_clk_core_dlp_user",
431 mout_clk_core_dlp_user_p, PLL_CON0_MUX_CLK_CORE_DLP_USER, 4, 1),
432 };
433
434 static const struct samsung_div_clock cmu_core_div_clks[] __initconst = {
435 DIV(CLK_DOUT_CORE_PCLK, "dout_clk_core_pclk",
436 "mout_clk_core_aclk_user", CLK_CON_DIV_CLK_CORE_PCLK, 0, 4),
437 };
438
439 static const struct samsung_cmu_info cmu_core_info __initconst = {
440 .mux_clks = cmu_core_mux_clks,
441 .nr_mux_clks = ARRAY_SIZE(cmu_core_mux_clks),
442 .div_clks = cmu_core_div_clks,
443 .nr_div_clks = ARRAY_SIZE(cmu_core_div_clks),
444 .nr_clk_ids = CMU_CORE_NR_CLK,
445 .clk_regs = cmu_core_clk_regs,
446 .nr_clk_regs = ARRAY_SIZE(cmu_core_clk_regs),
447 };
448
449 /* Register Offset definitions for CMU_CPUCL (0x11410000) */
450 #define PLL_LOCKTIME_PLL_CPUCL 0x0000
451 #define PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER 0x0120
452 #define PLL_CON0_PLL_CPUCL 0x0140
453 #define CLK_CON_MUX_CLK_CPUCL_PLL 0x1000
454 #define CLK_CON_DIV_CLK_CLUSTER_ACLK 0x1800
455 #define CLK_CON_DIV_CLK_CLUSTER_CNTCLK 0x1804
456 #define CLK_CON_DIV_CLK_CLUSTER_PCLKDBG 0x1808
457 #define CLK_CON_DIV_CLK_CPUCL_CMUREF 0x180c
458 #define CLK_CON_DIV_CLK_CPUCL_PCLK 0x1814
459 #define CLK_CON_DIV_CLK_CLUSTER_ATCLK 0x1818
460 #define CLK_CON_DIV_CLK_CPUCL_DBG 0x181c
461 #define CLK_CON_DIV_CLK_CPUCL_PCLKDBG 0x1820
462 #define CLK_CON_GAT_CLK_CLUSTER_CPU 0x2008
463 #define CLK_CON_GAT_CLK_CPUCL_SHORTSTOP 0x200c
464 #define CLK_CON_DMYQCH_CON_CSSYS_QCH 0x3008
465
466 static const unsigned long cmu_cpucl_clk_regs[] __initconst = {
467 PLL_LOCKTIME_PLL_CPUCL,
468 PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER,
469 PLL_CON0_PLL_CPUCL,
470 CLK_CON_MUX_CLK_CPUCL_PLL,
471 CLK_CON_DIV_CLK_CLUSTER_ACLK,
472 CLK_CON_DIV_CLK_CLUSTER_CNTCLK,
473 CLK_CON_DIV_CLK_CLUSTER_PCLKDBG,
474 CLK_CON_DIV_CLK_CPUCL_CMUREF,
475 CLK_CON_DIV_CLK_CPUCL_PCLK,
476 CLK_CON_DIV_CLK_CLUSTER_ATCLK,
477 CLK_CON_DIV_CLK_CPUCL_DBG,
478 CLK_CON_DIV_CLK_CPUCL_PCLKDBG,
479 CLK_CON_GAT_CLK_CLUSTER_CPU,
480 CLK_CON_GAT_CLK_CPUCL_SHORTSTOP,
481 CLK_CON_DMYQCH_CON_CSSYS_QCH,
482 };
483
484 static const struct samsung_pll_clock cmu_cpucl_pll_clks[] __initconst = {
485 PLL(pll_1017x, CLK_FOUT_CPUCL_PLL, "fout_pll_cpucl", "fin_pll",
486 PLL_LOCKTIME_PLL_CPUCL, PLL_CON0_PLL_CPUCL, NULL),
487 };
488
489 PNAME(mout_clkcmu_cpucl_switch_user_p) = { "fin_pll", "dout_clkcmu_cpucl_switch" };
490 PNAME(mout_pll_cpucl_p) = { "fin_pll", "fout_pll_cpucl" };
491 PNAME(mout_clk_cpucl_pll_p) = { "mout_pll_cpucl", "mout_clkcmu_cpucl_switch_user" };
492
493 static const struct samsung_mux_clock cmu_cpucl_mux_clks[] __initconst = {
494 MUX_F(0, "mout_pll_cpucl", mout_pll_cpucl_p, PLL_CON0_PLL_CPUCL, 4, 1,
495 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
496 MUX(CLK_MOUT_CPUCL_SWITCH_USER, "mout_clkcmu_cpucl_switch_user",
497 mout_clkcmu_cpucl_switch_user_p, PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER, 4, 1),
498 MUX_F(CLK_MOUT_CPUCL_PLL, "mout_clk_cpucl_pll", mout_clk_cpucl_pll_p,
499 CLK_CON_MUX_CLK_CPUCL_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
500 };
501
502 static const struct samsung_fixed_factor_clock cpucl_ffactor_clks[] __initconst = {
503 FFACTOR(CLK_DOUT_CPUCL_CPU, "dout_clk_cpucl_cpu",
504 "mout_clk_cpucl_pll", 1, 1, CLK_SET_RATE_PARENT),
505 };
506
507 static const struct samsung_div_clock cmu_cpucl_div_clks[] __initconst = {
508 DIV(CLK_DOUT_CPUCL_CLUSTER_ACLK, "dout_clk_cluster_aclk",
509 "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CLUSTER_ACLK, 0, 4),
510 DIV(CLK_DOUT_CPUCL_CLUSTER_PCLKDBG, "dout_clk_cluster_pclkdbg",
511 "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CLUSTER_PCLKDBG, 0, 4),
512 DIV(CLK_DOUT_CPUCL_CLUSTER_CNTCLK, "dout_clk_cluster_cntclk",
513 "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CLUSTER_CNTCLK, 0, 4),
514 DIV(CLK_DOUT_CPUCL_CLUSTER_ATCLK, "dout_clk_cluster_atclk",
515 "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CLUSTER_ATCLK, 0, 4),
516 DIV(CLK_DOUT_CPUCL_PCLK, "dout_clk_cpucl_pclk",
517 "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CPUCL_PCLK, 0, 4),
518 DIV(CLK_DOUT_CPUCL_CMUREF, "dout_clk_cpucl_cmuref",
519 "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CPUCL_CMUREF, 0, 3),
520 DIV(CLK_DOUT_CPUCL_DBG, "dout_clk_cpucl_dbg",
521 "dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CPUCL_DBG, 0, 4),
522 DIV(CLK_DOUT_CPUCL_PCLKDBG, "dout_clk_cpucl_pclkdbg",
523 "dout_clk_cpucl_dbg", CLK_CON_DIV_CLK_CPUCL_PCLKDBG, 0, 4),
524 };
525
526 static const struct samsung_gate_clock cmu_cpucl_gate_clks[] __initconst = {
527 GATE(CLK_GOUT_CPUCL_CLUSTER_CPU, "clk_con_gat_clk_cluster_cpu",
528 "clk_con_gat_clk_cpucl_shortstop", CLK_CON_GAT_CLK_CLUSTER_CPU, 21,
529 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
530 GATE(CLK_GOUT_CPUCL_SHORTSTOP, "clk_con_gat_clk_cpucl_shortstop",
531 "dout_clk_cpucl_cpu", CLK_CON_GAT_CLK_CPUCL_SHORTSTOP, 21,
532 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
533 GATE(CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG, "cssys_ipclkport_pclkdbg",
534 "dout_clk_cpucl_pclkdbg", CLK_CON_DMYQCH_CON_CSSYS_QCH, 1,
535 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
536 GATE(CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK, "cssys_ipclkport_atclk",
537 "dout_clk_cpucl_dbg", CLK_CON_DMYQCH_CON_CSSYS_QCH, 1,
538 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
539 };
540
541 static const struct samsung_cmu_info cmu_cpucl_info __initconst = {
542 .pll_clks = cmu_cpucl_pll_clks,
543 .nr_pll_clks = ARRAY_SIZE(cmu_cpucl_pll_clks),
544 .fixed_factor_clks = cpucl_ffactor_clks,
545 .nr_fixed_factor_clks = ARRAY_SIZE(cpucl_ffactor_clks),
546 .mux_clks = cmu_cpucl_mux_clks,
547 .nr_mux_clks = ARRAY_SIZE(cmu_cpucl_mux_clks),
548 .div_clks = cmu_cpucl_div_clks,
549 .nr_div_clks = ARRAY_SIZE(cmu_cpucl_div_clks),
550 .gate_clks = cmu_cpucl_gate_clks,
551 .nr_gate_clks = ARRAY_SIZE(cmu_cpucl_gate_clks),
552 .nr_clk_ids = CMU_CPUCL_NR_CLK,
553 .clk_regs = cmu_cpucl_clk_regs,
554 .nr_clk_regs = ARRAY_SIZE(cmu_cpucl_clk_regs),
555 };
556
557 /* Register Offset definitions for CMU_FSYS (0x16c10000) */
558 #define PLL_LOCKTIME_PLL_FSYS 0x0004
559 #define PLL_CON0_MUX_CLK_FSYS_BUS_USER 0x0120
560 #define PLL_CON0_MUX_CLK_FSYS_MMC_USER 0x0140
561 #define PLL_CON0_MUX_CLK_FSYS_SCAN0_USER 0x0160
562 #define PLL_CON0_MUX_CLK_FSYS_SCAN1_USER 0x0180
563 #define PLL_CON0_PLL_FSYS 0x01c0
564 #define CLK_CON_DIV_CLK_FSYS_ADC 0x1804
565 #define CLK_CON_DIV_CLK_FSYS_BUS300 0x1808
566 #define CLK_CON_DIV_CLK_FSYS_BUS_QSPI 0x180c
567 #define CLK_CON_DIV_CLK_FSYS_EQOS_25 0x1810
568 #define CLK_CON_DIV_CLK_FSYS_EQOS_2P5 0x1814
569 #define CLK_CON_DIV_CLK_FSYS_EQOS_500 0x1818
570 #define CLK_CON_DIV_CLK_FSYS_EQOS_INT125 0x181c
571 #define CLK_CON_DIV_CLK_FSYS_MMC_CARD0 0x1820
572 #define CLK_CON_DIV_CLK_FSYS_MMC_CARD1 0x1824
573 #define CLK_CON_DIV_CLK_FSYS_OTP_MEM 0x1828
574 #define CLK_CON_DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL 0x182c
575 #define CLK_CON_DIV_CLK_FSYS_QSPI 0x1830
576 #define CLK_CON_DIV_CLK_FSYS_SCLK_UART 0x1834
577 #define CLK_CON_DIV_CLK_FSYS_SFMC_NAND 0x1838
578 #define CLK_CON_DIV_SCAN_CLK_FSYS_125 0x183c
579 #define CLK_CON_DIV_SCAN_CLK_FSYS_MMC 0x1840
580 #define CLK_CON_DIV_SCAN_CLK_FSYS_PCIE_PIPE 0x1844
581 #define CLK_CON_FSYS_I2C0_IPCLKPORT_I_PCLK 0x2044
582 #define CLK_CON_FSYS_I2C1_IPCLKPORT_I_PCLK 0x2048
583 #define CLK_CON_FSYS_UART0_IPCLKPORT_I_PCLK 0x204c
584 #define CLK_CON_FSYS_UART0_IPCLKPORT_I_SCLK_UART 0x2050
585 #define CLK_CON_MMC0_IPCLKPORT_I_ACLK 0x2070
586 #define CLK_CON_MMC1_IPCLKPORT_I_ACLK 0x2078
587 #define CLK_CON_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x208c
588 #define CLK_CON_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2090
589 #define CLK_CON_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2094
590 #define CLK_CON_PWM_IPCLKPORT_I_PCLK_S0 0x20a0
591 #define CLK_CON_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20 0x20bc
592 #define CLK_CON_USB20DRD_IPCLKPORT_BUS_CLK_EARLY 0x20c0
593 #define CLK_CON_XHB_AHBBR_IPCLKPORT_CLK 0x20c4
594 #define CLK_CON_XHB_USB_IPCLKPORT_CLK 0x20cc
595 #define CLK_CON_BUS_P_FSYS_IPCLKPORT_QSPICLK 0x201c
596 #define CLK_CON_DMYQCH_CON_EQOS_TOP_QCH 0x3008
597 #define CLK_CON_DMYQCH_CON_MMC0_QCH 0x300c
598 #define CLK_CON_DMYQCH_CON_MMC1_QCH 0x3010
599 #define CLK_CON_DMYQCH_CON_PCIE_TOP_QCH 0x3018
600 #define CLK_CON_DMYQCH_CON_PCIE_TOP_QCH_REF 0x301c
601 #define CLK_CON_DMYQCH_CON_QSPI_QCH 0x3020
602 #define CLK_CON_DMYQCH_CON_SFMC_QCH 0x3024
603
604 static const unsigned long cmu_fsys_clk_regs[] __initconst = {
605 PLL_LOCKTIME_PLL_FSYS,
606 PLL_CON0_MUX_CLK_FSYS_BUS_USER,
607 PLL_CON0_MUX_CLK_FSYS_MMC_USER,
608 PLL_CON0_MUX_CLK_FSYS_SCAN0_USER,
609 PLL_CON0_MUX_CLK_FSYS_SCAN1_USER,
610 PLL_CON0_PLL_FSYS,
611 CLK_CON_DIV_CLK_FSYS_ADC,
612 CLK_CON_DIV_CLK_FSYS_BUS300,
613 CLK_CON_DIV_CLK_FSYS_BUS_QSPI,
614 CLK_CON_DIV_CLK_FSYS_EQOS_25,
615 CLK_CON_DIV_CLK_FSYS_EQOS_2P5,
616 CLK_CON_DIV_CLK_FSYS_EQOS_500,
617 CLK_CON_DIV_CLK_FSYS_EQOS_INT125,
618 CLK_CON_DIV_CLK_FSYS_MMC_CARD0,
619 CLK_CON_DIV_CLK_FSYS_MMC_CARD1,
620 CLK_CON_DIV_CLK_FSYS_OTP_MEM,
621 CLK_CON_DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL,
622 CLK_CON_DIV_CLK_FSYS_QSPI,
623 CLK_CON_DIV_CLK_FSYS_SCLK_UART,
624 CLK_CON_DIV_CLK_FSYS_SFMC_NAND,
625 CLK_CON_DIV_SCAN_CLK_FSYS_125,
626 CLK_CON_DIV_SCAN_CLK_FSYS_MMC,
627 CLK_CON_DIV_SCAN_CLK_FSYS_PCIE_PIPE,
628 CLK_CON_FSYS_I2C0_IPCLKPORT_I_PCLK,
629 CLK_CON_FSYS_I2C1_IPCLKPORT_I_PCLK,
630 CLK_CON_FSYS_UART0_IPCLKPORT_I_PCLK,
631 CLK_CON_FSYS_UART0_IPCLKPORT_I_SCLK_UART,
632 CLK_CON_MMC0_IPCLKPORT_I_ACLK,
633 CLK_CON_MMC1_IPCLKPORT_I_ACLK,
634 CLK_CON_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
635 CLK_CON_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
636 CLK_CON_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
637 CLK_CON_PWM_IPCLKPORT_I_PCLK_S0,
638 CLK_CON_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20,
639 CLK_CON_USB20DRD_IPCLKPORT_BUS_CLK_EARLY,
640 CLK_CON_XHB_AHBBR_IPCLKPORT_CLK,
641 CLK_CON_XHB_USB_IPCLKPORT_CLK,
642 CLK_CON_BUS_P_FSYS_IPCLKPORT_QSPICLK,
643 CLK_CON_DMYQCH_CON_EQOS_TOP_QCH,
644 CLK_CON_DMYQCH_CON_MMC0_QCH,
645 CLK_CON_DMYQCH_CON_MMC1_QCH,
646 CLK_CON_DMYQCH_CON_PCIE_TOP_QCH,
647 CLK_CON_DMYQCH_CON_PCIE_TOP_QCH_REF,
648 CLK_CON_DMYQCH_CON_QSPI_QCH,
649 CLK_CON_DMYQCH_CON_SFMC_QCH,
650 };
651
652 static const struct samsung_pll_clock cmu_fsys_pll_clks[] __initconst = {
653 PLL(pll_1017x, CLK_FOUT_FSYS_PLL, "fout_pll_fsys", "fin_pll",
654 PLL_LOCKTIME_PLL_FSYS, PLL_CON0_PLL_FSYS, NULL),
655 };
656
657 PNAME(mout_fsys_scan0_user_p) = { "fin_pll", "dout_clkcmu_fsys_scan0" };
658 PNAME(mout_fsys_scan1_user_p) = { "fin_pll", "dout_clkcmu_fsys_scan1" };
659 PNAME(mout_fsys_bus_user_p) = { "fin_pll", "dout_clkcmu_fsys_bus" };
660 PNAME(mout_fsys_mmc_user_p) = { "fin_pll", "dout_clkcmu_fsys_ip" };
661 PNAME(mout_fsys_pll_fsys_p) = { "fin_pll", "fout_pll_fsys" };
662
663 static const struct samsung_mux_clock cmu_fsys_mux_clks[] __initconst = {
664 MUX(0, "mout_clk_pll_fsys", mout_fsys_pll_fsys_p, PLL_CON0_PLL_FSYS, 4, 1),
665 MUX(CLK_MOUT_FSYS_SCAN0_USER, "mout_fsys_scan0_user",
666 mout_fsys_scan0_user_p, PLL_CON0_MUX_CLK_FSYS_SCAN0_USER, 4, 1),
667 MUX(CLK_MOUT_FSYS_SCAN1_USER, "mout_fsys_scan1_user",
668 mout_fsys_scan1_user_p, PLL_CON0_MUX_CLK_FSYS_SCAN1_USER, 4, 1),
669 MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user",
670 mout_fsys_bus_user_p, PLL_CON0_MUX_CLK_FSYS_BUS_USER, 4, 1),
671 MUX(CLK_MOUT_FSYS_MMC_USER, "mout_fsys_mmc_user",
672 mout_fsys_mmc_user_p, PLL_CON0_MUX_CLK_FSYS_MMC_USER, 4, 1),
673 };
674
675 static const struct samsung_div_clock cmu_fsys_div_clks[] __initconst = {
676 DIV(CLK_DOUT_FSYS_PCIE_PIPE, "dout_fsys_pcie_pipe", "mout_clk_pll_fsys",
677 CLK_CON_DIV_SCAN_CLK_FSYS_PCIE_PIPE, 0, 4),
678 DIV(CLK_DOUT_FSYS_ADC, "dout_fsys_adc", "mout_clk_pll_fsys",
679 CLK_CON_DIV_CLK_FSYS_ADC, 0, 7),
680 DIV(CLK_DOUT_FSYS_PCIE_PHY_REFCLK_SYSPLL, "dout_fsys_pcie_phy_refclk_syspll",
681 "mout_clk_pll_fsys", CLK_CON_DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL, 0, 8),
682 DIV(CLK_DOUT_FSYS_QSPI, "dout_fsys_qspi", "mout_fsys_mmc_user",
683 CLK_CON_DIV_CLK_FSYS_QSPI, 0, 4),
684 DIV(CLK_DOUT_FSYS_EQOS_INT125, "dout_fsys_eqos_int125", "mout_clk_pll_fsys",
685 CLK_CON_DIV_CLK_FSYS_EQOS_INT125, 0, 4),
686 DIV(CLK_DOUT_FSYS_OTP_MEM, "dout_fsys_otp_mem", "fin_pll",
687 CLK_CON_DIV_CLK_FSYS_OTP_MEM, 0, 9),
688 DIV(CLK_DOUT_FSYS_SCLK_UART, "dout_fsys_sclk_uart", "mout_clk_pll_fsys",
689 CLK_CON_DIV_CLK_FSYS_SCLK_UART, 0, 10),
690 DIV(CLK_DOUT_FSYS_SFMC_NAND, "dout_fsys_sfmc_nand", "mout_fsys_mmc_user",
691 CLK_CON_DIV_CLK_FSYS_SFMC_NAND, 0, 4),
692 DIV(CLK_DOUT_SCAN_CLK_FSYS_125, "dout_scan_clk_fsys_125", "mout_clk_pll_fsys",
693 CLK_CON_DIV_SCAN_CLK_FSYS_125, 0, 4),
694 DIV(CLK_DOUT_FSYS_SCAN_CLK_MMC, "dout_scan_clk_fsys_mmc", "fout_pll_fsys",
695 CLK_CON_DIV_SCAN_CLK_FSYS_MMC, 0, 4),
696 DIV(CLK_DOUT_FSYS_EQOS_25, "dout_fsys_eqos_25", "dout_fsys_eqos_int125",
697 CLK_CON_DIV_CLK_FSYS_EQOS_25, 0, 4),
698 DIV_F(CLK_DOUT_FSYS_EQOS_2p5, "dout_fsys_eqos_2p5", "dout_fsys_eqos_25",
699 CLK_CON_DIV_CLK_FSYS_EQOS_2P5, 0, 4, CLK_SET_RATE_PARENT, 0),
700 DIV(0, "dout_fsys_eqos_500", "mout_clk_pll_fsys",
701 CLK_CON_DIV_CLK_FSYS_EQOS_500, 0, 4),
702 DIV(CLK_DOUT_FSYS_BUS300, "dout_fsys_bus300", "mout_fsys_bus_user",
703 CLK_CON_DIV_CLK_FSYS_BUS300, 0, 4),
704 DIV(CLK_DOUT_FSYS_BUS_QSPI, "dout_fsys_bus_qspi", "mout_fsys_mmc_user",
705 CLK_CON_DIV_CLK_FSYS_BUS_QSPI, 0, 4),
706 DIV(CLK_DOUT_FSYS_MMC_CARD0, "dout_fsys_mmc_card0", "mout_fsys_mmc_user",
707 CLK_CON_DIV_CLK_FSYS_MMC_CARD0, 0, 10),
708 DIV(CLK_DOUT_FSYS_MMC_CARD1, "dout_fsys_mmc_card1", "mout_fsys_mmc_user",
709 CLK_CON_DIV_CLK_FSYS_MMC_CARD1, 0, 10),
710 };
711
712 static const struct samsung_gate_clock cmu_fsys_gate_clks[] __initconst = {
713 GATE(CLK_GOUT_FSYS_PCIE_PHY_REFCLK_IN, "pcie_sub_ctrl_inst_0_phy_refclk_in",
714 "dout_fsys_pcie_phy_refclk_syspll", CLK_CON_DMYQCH_CON_PCIE_TOP_QCH_REF, 1,
715 CLK_SET_RATE_PARENT, 0),
716 GATE(CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_I_RGMII_TXCLK_2P5,
717 "eqos_top_ipclkport_i_rgmii_txclk_2p5",
718 "dout_fsys_eqos_2p5", CLK_CON_DMYQCH_CON_EQOS_TOP_QCH, 1, CLK_SET_RATE_PARENT, 0),
719 GATE(CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_ACLK_I, "eqos_top_ipclkport_aclk_i",
720 "dout_fsys_bus300", CLK_CON_DMYQCH_CON_EQOS_TOP_QCH, 1, CLK_SET_RATE_PARENT, 0),
721 GATE(CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_CLK_CSR_I, "eqos_top_ipclkport_clk_csr_i",
722 "dout_fsys_bus300", CLK_CON_DMYQCH_CON_EQOS_TOP_QCH, 1, CLK_SET_RATE_PARENT, 0),
723 GATE(CLK_GOUT_FSYS_PIPE_PAL_INST_0_I_APB_PCLK, "pipe_pal_inst_0_i_apb_pclk",
724 "dout_fsys_bus300", CLK_CON_DMYQCH_CON_PCIE_TOP_QCH, 1, CLK_SET_RATE_PARENT, 0),
725 GATE(CLK_GOUT_FSYS_QSPI_IPCLKPORT_HCLK, "qspi_ipclkport_hclk",
726 "dout_fsys_bus_qspi", CLK_CON_DMYQCH_CON_QSPI_QCH, 1, CLK_SET_RATE_PARENT, 0),
727 GATE(CLK_GOUT_FSYS_QSPI_IPCLKPORT_SSI_CLK, "qspi_ipclkport_ssi_clk",
728 "dout_fsys_qspi", CLK_CON_DMYQCH_CON_QSPI_QCH, 1, CLK_SET_RATE_PARENT, 0),
729 GATE(CLK_GOUT_FSYS_MMC0_IPCLKPORT_SDCLKIN, "mmc0_ipclkport_sdclkin",
730 "dout_fsys_mmc_card0", CLK_CON_DMYQCH_CON_MMC0_QCH, 1, CLK_SET_RATE_PARENT, 0),
731 GATE(CLK_GOUT_FSYS_MMC1_IPCLKPORT_SDCLKIN, "mmc1_ipclkport_sdclkin",
732 "dout_fsys_mmc_card1", CLK_CON_DMYQCH_CON_MMC1_QCH, 1, CLK_SET_RATE_PARENT, 0),
733 GATE(CLK_GOUT_FSYS_SFMC_IPCLKPORT_I_ACLK_NAND, "sfmc_ipclkport_i_aclk_nand",
734 "dout_fsys_sfmc_nand", CLK_CON_DMYQCH_CON_SFMC_QCH, 1, CLK_SET_RATE_PARENT, 0),
735 GATE(CLK_GOUT_FSYS_UART0_SCLK_UART, "uart0_sclk", "dout_fsys_sclk_uart",
736 CLK_CON_FSYS_UART0_IPCLKPORT_I_SCLK_UART, 21,
737 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
738 GATE(CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, "dwc_pcie_ctl_inst_0_mstr_aclk_ug",
739 "mout_fsys_bus_user", CLK_CON_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, 21,
740 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
741 GATE(CLK_GOUT_FSYS_DWC_PCIE_CTL_INXT_0_SLV_ACLK_UG, "dwc_pcie_ctl_inst_0_slv_aclk_ug",
742 "mout_fsys_bus_user", CLK_CON_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, 21,
743 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
744 GATE(CLK_GOUT_FSYS_I2C0_IPCLKPORT_I_PCLK, "fsys_i2c0_ipclkport_i_pclk", "dout_fsys_bus300",
745 CLK_CON_FSYS_I2C0_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
746 GATE(CLK_GOUT_FSYS_I2C1_IPCLKPORT_I_PCLK, "fsys_i2c1_ipclkport_i_pclk", "dout_fsys_bus300",
747 CLK_CON_FSYS_I2C1_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
748 GATE(CLK_GOUT_FSYS_UART0_PCLK, "uart0_pclk", "dout_fsys_bus300",
749 CLK_CON_FSYS_UART0_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
750 GATE(CLK_GOUT_FSYS_MMC0_IPCLKPORT_I_ACLK, "mmc0_ipclkport_i_aclk", "dout_fsys_bus300",
751 CLK_CON_MMC0_IPCLKPORT_I_ACLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
752 GATE(CLK_GOUT_FSYS_MMC1_IPCLKPORT_I_ACLK, "mmc1_ipclkport_i_aclk", "dout_fsys_bus300",
753 CLK_CON_MMC1_IPCLKPORT_I_ACLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
754 GATE(CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, "dwc_pcie_ctl_inst_0_dbi_aclk_ug",
755 "dout_fsys_bus300", CLK_CON_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, 21,
756 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
757 GATE(CLK_GOUT_FSYS_PWM_IPCLKPORT_I_PCLK_S0, "pwm_ipclkport_i_pclk_s0", "dout_fsys_bus300",
758 CLK_CON_PWM_IPCLKPORT_I_PCLK_S0, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
759 GATE(CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20, "usb20drd_ipclkport_aclk_phyctrl_20",
760 "dout_fsys_bus300", CLK_CON_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20, 21,
761 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
762 GATE(CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_BUS_CLK_EARLY, "usb20drd_ipclkport_bus_clk_early",
763 "dout_fsys_bus300", CLK_CON_USB20DRD_IPCLKPORT_BUS_CLK_EARLY, 21,
764 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
765 GATE(CLK_GOUT_FSYS_XHB_AHBBR_IPCLKPORT_CLK, "xhb_ahbbr_ipclkport_clk", "dout_fsys_bus300",
766 CLK_CON_XHB_AHBBR_IPCLKPORT_CLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
767 GATE(CLK_GOUT_FSYS_XHB_USB_IPCLKPORT_CLK, "xhb_usb_ipclkport_clk", "dout_fsys_bus300",
768 CLK_CON_XHB_USB_IPCLKPORT_CLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
769 GATE(CLK_GOUT_FSYS_BUS_QSPI, "bus_p_fsys_ipclkport_qspiclk", "dout_fsys_bus_qspi",
770 CLK_CON_BUS_P_FSYS_IPCLKPORT_QSPICLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
771 };
772
773 static const struct samsung_cmu_info cmu_fsys_info __initconst = {
774 .pll_clks = cmu_fsys_pll_clks,
775 .nr_pll_clks = ARRAY_SIZE(cmu_fsys_pll_clks),
776 .mux_clks = cmu_fsys_mux_clks,
777 .nr_mux_clks = ARRAY_SIZE(cmu_fsys_mux_clks),
778 .div_clks = cmu_fsys_div_clks,
779 .nr_div_clks = ARRAY_SIZE(cmu_fsys_div_clks),
780 .gate_clks = cmu_fsys_gate_clks,
781 .nr_gate_clks = ARRAY_SIZE(cmu_fsys_gate_clks),
782 .nr_clk_ids = CMU_FSYS_NR_CLK,
783 .clk_regs = cmu_fsys_clk_regs,
784 .nr_clk_regs = ARRAY_SIZE(cmu_fsys_clk_regs),
785 };
786
787 /* Register Offset definitions for CMU_IMEM (0x10010000) */
788 #define PLL_CON0_MUX_CLK_IMEM_ACLK_USER 0x0100
789 #define PLL_CON0_MUX_CLK_IMEM_JPEG_USER 0x0120
790 #define CLK_CON_MUX_CLK_IMEM_GIC_CA53 0x1000
791 #define CLK_CON_MUX_CLK_IMEM_GIC_CA5 0x1008
792 #define CLK_CON_MCT_IPCLKPORT_PCLK 0x2038
793 #define CLK_CON_SFRIF_TMU_IMEM_IPCLKPORT_PCLK 0x2044
794
795 static const unsigned long cmu_imem_clk_regs[] __initconst = {
796 PLL_CON0_MUX_CLK_IMEM_ACLK_USER,
797 PLL_CON0_MUX_CLK_IMEM_JPEG_USER,
798 CLK_CON_MUX_CLK_IMEM_GIC_CA53,
799 CLK_CON_MUX_CLK_IMEM_GIC_CA5,
800 CLK_CON_MCT_IPCLKPORT_PCLK,
801 CLK_CON_SFRIF_TMU_IMEM_IPCLKPORT_PCLK,
802 };
803
804 PNAME(mout_imem_aclk_user_p) = { "fin_pll", "dout_clkcmu_imem_aclk" };
805 PNAME(mout_imem_gic_ca53_p) = { "mout_imem_aclk_user", "fin_pll" };
806 PNAME(mout_imem_gic_ca5_p) = { "mout_imem_aclk_user", "fin_pll" };
807 PNAME(mout_imem_jpeg_user_p) = { "fin_pll", "dout_clkcmu_imem_jpeg" };
808
809 static const struct samsung_mux_clock cmu_imem_mux_clks[] __initconst = {
810 MUX(CLK_MOUT_IMEM_ACLK_USER, "mout_imem_aclk_user",
811 mout_imem_aclk_user_p, PLL_CON0_MUX_CLK_IMEM_ACLK_USER, 4, 1),
812 MUX(CLK_MOUT_IMEM_GIC_CA53, "mout_imem_gic_ca53",
813 mout_imem_gic_ca53_p, CLK_CON_MUX_CLK_IMEM_GIC_CA53, 0, 1),
814 MUX(CLK_MOUT_IMEM_GIC_CA5, "mout_imem_gic_ca5",
815 mout_imem_gic_ca5_p, CLK_CON_MUX_CLK_IMEM_GIC_CA5, 0, 1),
816 MUX(CLK_MOUT_IMEM_JPEG_USER, "mout_imem_jpeg_user",
817 mout_imem_jpeg_user_p, PLL_CON0_MUX_CLK_IMEM_JPEG_USER, 4, 1),
818 };
819
820 static const struct samsung_gate_clock cmu_imem_gate_clks[] __initconst = {
821 GATE(CLK_GOUT_IMEM_MCT_PCLK, "mct_pclk", "mout_imem_aclk_user",
822 CLK_CON_MCT_IPCLKPORT_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
823 GATE(CLK_GOUT_IMEM_PCLK_TMU0_APBIF, "sfrif_tmu_imem_ipclkport_pclk", "mout_imem_aclk_user",
824 CLK_CON_SFRIF_TMU_IMEM_IPCLKPORT_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
825 };
826
827 static const struct samsung_cmu_info cmu_imem_info __initconst = {
828 .mux_clks = cmu_imem_mux_clks,
829 .nr_mux_clks = ARRAY_SIZE(cmu_imem_mux_clks),
830 .gate_clks = cmu_imem_gate_clks,
831 .nr_gate_clks = ARRAY_SIZE(cmu_imem_gate_clks),
832 .nr_clk_ids = CMU_IMEM_NR_CLK,
833 .clk_regs = cmu_imem_clk_regs,
834 .nr_clk_regs = ARRAY_SIZE(cmu_imem_clk_regs),
835 };
836
artpec8_clk_cmu_imem_init(struct device_node * np)837 static void __init artpec8_clk_cmu_imem_init(struct device_node *np)
838 {
839 samsung_cmu_register_one(np, &cmu_imem_info);
840 }
841
842 CLK_OF_DECLARE(artpec8_clk_cmu_imem, "axis,artpec8-cmu-imem", artpec8_clk_cmu_imem_init);
843
844 /* Register Offset definitions for CMU_PERI (0x16410000) */
845 #define PLL_CON0_MUX_CLK_PERI_AUDIO_USER 0x0100
846 #define PLL_CON0_MUX_CLK_PERI_DISP_USER 0x0120
847 #define PLL_CON0_MUX_CLK_PERI_IP_USER 0x0140
848 #define CLK_CON_MUX_CLK_PERI_I2S0 0x1000
849 #define CLK_CON_MUX_CLK_PERI_I2S1 0x1004
850 #define CLK_CON_DIV_CLK_PERI_DSIM 0x1800
851 #define CLK_CON_DIV_CLK_PERI_I2S0 0x1804
852 #define CLK_CON_DIV_CLK_PERI_I2S1 0x1808
853 #define CLK_CON_DIV_CLK_PERI_PCLK 0x180c
854 #define CLK_CON_DIV_CLK_PERI_SPI 0x1810
855 #define CLK_CON_DIV_CLK_PERI_UART1 0x1814
856 #define CLK_CON_DIV_CLK_PERI_UART2 0x1818
857 #define CLK_CON_APB_ASYNC_DSIM_IPCLKPORT_PCLKS 0x2004
858 #define CLK_CON_PERI_I2C2_IPCLKPORT_I_PCLK 0x2030
859 #define CLK_CON_PERI_I2C3_IPCLKPORT_I_PCLK 0x2034
860 #define CLK_CON_PERI_SPI0_IPCLKPORT_I_PCLK 0x2048
861 #define CLK_CON_PERI_SPI0_IPCLKPORT_I_SCLK_SPI 0x204c
862 #define CLK_CON_PERI_UART1_IPCLKPORT_I_PCLK 0x2050
863 #define CLK_CON_PERI_UART1_IPCLKPORT_I_SCLK_UART 0x2054
864 #define CLK_CON_PERI_UART2_IPCLKPORT_I_PCLK 0x2058
865 #define CLK_CON_PERI_UART2_IPCLKPORT_I_SCLK_UART 0x205c
866 #define CLK_CON_DMYQCH_CON_AUDIO_OUT_QCH 0x3000
867 #define CLK_CON_DMYQCH_CON_DMA4DSIM_QCH 0x3004
868 #define CLK_CON_DMYQCH_CON_PERI_I2SSC0_QCH 0x3008
869 #define CLK_CON_DMYQCH_CON_PERI_I2SSC1_QCH 0x300c
870
871 static const unsigned long cmu_peri_clk_regs[] __initconst = {
872 PLL_CON0_MUX_CLK_PERI_AUDIO_USER,
873 PLL_CON0_MUX_CLK_PERI_DISP_USER,
874 PLL_CON0_MUX_CLK_PERI_IP_USER,
875 CLK_CON_MUX_CLK_PERI_I2S0,
876 CLK_CON_MUX_CLK_PERI_I2S1,
877 CLK_CON_DIV_CLK_PERI_DSIM,
878 CLK_CON_DIV_CLK_PERI_I2S0,
879 CLK_CON_DIV_CLK_PERI_I2S1,
880 CLK_CON_DIV_CLK_PERI_PCLK,
881 CLK_CON_DIV_CLK_PERI_SPI,
882 CLK_CON_DIV_CLK_PERI_UART1,
883 CLK_CON_DIV_CLK_PERI_UART2,
884 CLK_CON_APB_ASYNC_DSIM_IPCLKPORT_PCLKS,
885 CLK_CON_PERI_I2C2_IPCLKPORT_I_PCLK,
886 CLK_CON_PERI_I2C3_IPCLKPORT_I_PCLK,
887 CLK_CON_PERI_SPI0_IPCLKPORT_I_PCLK,
888 CLK_CON_PERI_SPI0_IPCLKPORT_I_SCLK_SPI,
889 CLK_CON_PERI_UART1_IPCLKPORT_I_PCLK,
890 CLK_CON_PERI_UART1_IPCLKPORT_I_SCLK_UART,
891 CLK_CON_PERI_UART2_IPCLKPORT_I_PCLK,
892 CLK_CON_PERI_UART2_IPCLKPORT_I_SCLK_UART,
893 CLK_CON_DMYQCH_CON_AUDIO_OUT_QCH,
894 CLK_CON_DMYQCH_CON_DMA4DSIM_QCH,
895 CLK_CON_DMYQCH_CON_PERI_I2SSC0_QCH,
896 CLK_CON_DMYQCH_CON_PERI_I2SSC1_QCH,
897 };
898
899 static const struct samsung_fixed_rate_clock peri_fixed_clks[] __initconst = {
900 FRATE(0, "clk_peri_audio", NULL, 0, 100000000),
901 };
902
903 PNAME(mout_peri_ip_user_p) = { "fin_pll", "dout_clkcmu_peri_ip" };
904 PNAME(mout_peri_audio_user_p) = { "fin_pll", "dout_clkcmu_peri_audio" };
905 PNAME(mout_peri_disp_user_p) = { "fin_pll", "dout_clkcmu_peri_disp" };
906 PNAME(mout_peri_i2s0_p) = { "dout_peri_i2s0", "clk_peri_audio" };
907 PNAME(mout_peri_i2s1_p) = { "dout_peri_i2s1", "clk_peri_audio" };
908
909 static const struct samsung_mux_clock cmu_peri_mux_clks[] __initconst = {
910 MUX(CLK_MOUT_PERI_IP_USER, "mout_peri_ip_user", mout_peri_ip_user_p,
911 PLL_CON0_MUX_CLK_PERI_IP_USER, 4, 1),
912 MUX(CLK_MOUT_PERI_AUDIO_USER, "mout_peri_audio_user",
913 mout_peri_audio_user_p, PLL_CON0_MUX_CLK_PERI_AUDIO_USER, 4, 1),
914 MUX(CLK_MOUT_PERI_DISP_USER, "mout_peri_disp_user", mout_peri_disp_user_p,
915 PLL_CON0_MUX_CLK_PERI_DISP_USER, 4, 1),
916 MUX(CLK_MOUT_PERI_I2S0, "mout_peri_i2s0", mout_peri_i2s0_p,
917 CLK_CON_MUX_CLK_PERI_I2S0, 0, 1),
918 MUX(CLK_MOUT_PERI_I2S1, "mout_peri_i2s1", mout_peri_i2s1_p,
919 CLK_CON_MUX_CLK_PERI_I2S1, 0, 1),
920 };
921
922 static const struct samsung_div_clock cmu_peri_div_clks[] __initconst = {
923 DIV(CLK_DOUT_PERI_SPI, "dout_peri_spi", "mout_peri_ip_user",
924 CLK_CON_DIV_CLK_PERI_SPI, 0, 10),
925 DIV(CLK_DOUT_PERI_UART1, "dout_peri_uart1", "mout_peri_ip_user",
926 CLK_CON_DIV_CLK_PERI_UART1, 0, 10),
927 DIV(CLK_DOUT_PERI_UART2, "dout_peri_uart2", "mout_peri_ip_user",
928 CLK_CON_DIV_CLK_PERI_UART2, 0, 10),
929 DIV(CLK_DOUT_PERI_PCLK, "dout_peri_pclk", "mout_peri_ip_user",
930 CLK_CON_DIV_CLK_PERI_PCLK, 0, 4),
931 DIV(CLK_DOUT_PERI_I2S0, "dout_peri_i2s0", "mout_peri_audio_user",
932 CLK_CON_DIV_CLK_PERI_I2S0, 0, 4),
933 DIV(CLK_DOUT_PERI_I2S1, "dout_peri_i2s1", "mout_peri_audio_user",
934 CLK_CON_DIV_CLK_PERI_I2S1, 0, 4),
935 DIV(CLK_DOUT_PERI_DSIM, "dout_peri_dsim", "mout_peri_disp_user",
936 CLK_CON_DIV_CLK_PERI_DSIM, 0, 4),
937 };
938
939 static const struct samsung_gate_clock cmu_peri_gate_clks[] __initconst = {
940 GATE(CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK, "dma4dsim_ipclkport_clk_apb_clk",
941 "dout_peri_pclk", CLK_CON_DMYQCH_CON_DMA4DSIM_QCH, 1, CLK_SET_RATE_PARENT, 0),
942 GATE(CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK_HST, "i2ssc0_ipclkport_clk_hst", "dout_peri_pclk",
943 CLK_CON_DMYQCH_CON_PERI_I2SSC0_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
944 GATE(CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK_HST, "i2ssc1_ipclkport_clk_hst", "dout_peri_pclk",
945 CLK_CON_DMYQCH_CON_PERI_I2SSC1_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
946 GATE(CLK_GOUT_PERI_AUDIO_OUT_IPCLKPORT_CLK, "audio_out_ipclkport_clk",
947 "mout_peri_audio_user", CLK_CON_DMYQCH_CON_AUDIO_OUT_QCH, 1, CLK_SET_RATE_PARENT, 0),
948 GATE(CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK, "peri_i2ssc0_ipclkport_clk", "mout_peri_i2s0",
949 CLK_CON_DMYQCH_CON_PERI_I2SSC0_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
950 GATE(CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK, "peri_i2ssc1_ipclkport_clk", "mout_peri_i2s1",
951 CLK_CON_DMYQCH_CON_PERI_I2SSC1_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
952 GATE(CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK, "dma4dsim_ipclkport_clk_axi_clk",
953 "mout_peri_disp_user", CLK_CON_DMYQCH_CON_DMA4DSIM_QCH, 1, CLK_SET_RATE_PARENT, 0),
954 GATE(CLK_GOUT_PERI_SPI0_SCLK_SPI, "peri_spi0_ipclkport_i_sclk_spi", "dout_peri_spi",
955 CLK_CON_PERI_SPI0_IPCLKPORT_I_SCLK_SPI, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
956 GATE(CLK_GOUT_PERI_UART1_SCLK_UART, "uart1_sclk", "dout_peri_uart1",
957 CLK_CON_PERI_UART1_IPCLKPORT_I_SCLK_UART, 21,
958 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
959 GATE(CLK_GOUT_PERI_UART2_SCLK_UART, "uart2_sclk", "dout_peri_uart2",
960 CLK_CON_PERI_UART2_IPCLKPORT_I_SCLK_UART, 21,
961 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
962 GATE(CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS, "apb_async_dsim_ipclkport_pclks",
963 "dout_peri_pclk", CLK_CON_APB_ASYNC_DSIM_IPCLKPORT_PCLKS, 21,
964 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
965 GATE(CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK, "peri_i2c2_ipclkport_i_pclk", "dout_peri_pclk",
966 CLK_CON_PERI_I2C2_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
967 GATE(CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK, "peri_i2c3_ipclkport_i_pclk", "dout_peri_pclk",
968 CLK_CON_PERI_I2C3_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
969 GATE(CLK_GOUT_PERI_SPI0_PCLK, "peri_spi0_ipclkport_i_pclk", "dout_peri_pclk",
970 CLK_CON_PERI_SPI0_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
971 GATE(CLK_GOUT_PERI_UART1_PCLK, "uart1_pclk", "dout_peri_pclk",
972 CLK_CON_PERI_UART1_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
973 GATE(CLK_GOUT_PERI_UART2_PCLK, "uart2_pclk", "dout_peri_pclk",
974 CLK_CON_PERI_UART2_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
975 };
976
977 static const struct samsung_cmu_info cmu_peri_info __initconst = {
978 .mux_clks = cmu_peri_mux_clks,
979 .nr_mux_clks = ARRAY_SIZE(cmu_peri_mux_clks),
980 .div_clks = cmu_peri_div_clks,
981 .nr_div_clks = ARRAY_SIZE(cmu_peri_div_clks),
982 .gate_clks = cmu_peri_gate_clks,
983 .nr_gate_clks = ARRAY_SIZE(cmu_peri_gate_clks),
984 .fixed_clks = peri_fixed_clks,
985 .nr_fixed_clks = ARRAY_SIZE(peri_fixed_clks),
986 .nr_clk_ids = CMU_PERI_NR_CLK,
987 .clk_regs = cmu_peri_clk_regs,
988 .nr_clk_regs = ARRAY_SIZE(cmu_peri_clk_regs),
989 };
990
991 /**
992 * artpec8_cmu_probe - Probe function for ARTPEC platform clocks
993 * @pdev: Pointer to platform device
994 *
995 * Configure clock hierarchy for clock domains of ARTPEC platform
996 */
artpec8_cmu_probe(struct platform_device * pdev)997 static int __init artpec8_cmu_probe(struct platform_device *pdev)
998 {
999 const struct samsung_cmu_info *info;
1000 struct device *dev = &pdev->dev;
1001
1002 info = of_device_get_match_data(dev);
1003 exynos_arm64_register_cmu(dev, dev->of_node, info);
1004
1005 return 0;
1006 }
1007
1008 static const struct of_device_id artpec8_cmu_of_match[] = {
1009 {
1010 .compatible = "axis,artpec8-cmu-cmu",
1011 .data = &cmu_cmu_info,
1012 }, {
1013 .compatible = "axis,artpec8-cmu-bus",
1014 .data = &cmu_bus_info,
1015 }, {
1016 .compatible = "axis,artpec8-cmu-core",
1017 .data = &cmu_core_info,
1018 }, {
1019 .compatible = "axis,artpec8-cmu-cpucl",
1020 .data = &cmu_cpucl_info,
1021 }, {
1022 .compatible = "axis,artpec8-cmu-fsys",
1023 .data = &cmu_fsys_info,
1024 }, {
1025 .compatible = "axis,artpec8-cmu-peri",
1026 .data = &cmu_peri_info,
1027 }, {
1028 },
1029 };
1030
1031 static struct platform_driver artpec8_cmu_driver __refdata = {
1032 .driver = {
1033 .name = "artpec8-cmu",
1034 .of_match_table = artpec8_cmu_of_match,
1035 .suppress_bind_attrs = true,
1036 },
1037 .probe = artpec8_cmu_probe,
1038 };
1039
artpec8_cmu_init(void)1040 static int __init artpec8_cmu_init(void)
1041 {
1042 return platform_driver_register(&artpec8_cmu_driver);
1043 }
1044 core_initcall(artpec8_cmu_init);
1045