1*91f98de4SHakyeong Kim# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*91f98de4SHakyeong Kim%YAML 1.2 3*91f98de4SHakyeong Kim--- 4*91f98de4SHakyeong Kim$id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml# 5*91f98de4SHakyeong Kim$schema: http://devicetree.org/meta-schemas/core.yaml# 6*91f98de4SHakyeong Kim 7*91f98de4SHakyeong Kimtitle: Axis ARTPEC-8 SoC clock controller 8*91f98de4SHakyeong Kim 9*91f98de4SHakyeong Kimmaintainers: 10*91f98de4SHakyeong Kim - Jesper Nilsson <jesper.nilsson@axis.com> 11*91f98de4SHakyeong Kim 12*91f98de4SHakyeong Kimdescription: | 13*91f98de4SHakyeong Kim ARTPEC-8 clock controller is comprised of several CMU (Clock Management Unit) 14*91f98de4SHakyeong Kim units, generating clocks for different domains. Those CMU units are modeled 15*91f98de4SHakyeong Kim as separate device tree nodes, and might depend on each other. 16*91f98de4SHakyeong Kim The root clock in that root tree is an external clock: OSCCLK (25 MHz). 17*91f98de4SHakyeong Kim This external clock must be defined as a fixed-rate clock in dts. 18*91f98de4SHakyeong Kim 19*91f98de4SHakyeong Kim CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and 20*91f98de4SHakyeong Kim dividers; all other clocks of function blocks (other CMUs) are usually 21*91f98de4SHakyeong Kim derived from CMU_CMU. 22*91f98de4SHakyeong Kim 23*91f98de4SHakyeong Kim Each clock is assigned an identifier and client nodes can use this identifier 24*91f98de4SHakyeong Kim to specify the clock which they consume. All clocks available for usage 25*91f98de4SHakyeong Kim in clock consumer nodes are defined as preprocessor macros in 26*91f98de4SHakyeong Kim 'include/dt-bindings/clock/axis,artpec8-clk.h' header. 27*91f98de4SHakyeong Kim 28*91f98de4SHakyeong Kimproperties: 29*91f98de4SHakyeong Kim compatible: 30*91f98de4SHakyeong Kim enum: 31*91f98de4SHakyeong Kim - axis,artpec8-cmu-cmu 32*91f98de4SHakyeong Kim - axis,artpec8-cmu-bus 33*91f98de4SHakyeong Kim - axis,artpec8-cmu-core 34*91f98de4SHakyeong Kim - axis,artpec8-cmu-cpucl 35*91f98de4SHakyeong Kim - axis,artpec8-cmu-fsys 36*91f98de4SHakyeong Kim - axis,artpec8-cmu-imem 37*91f98de4SHakyeong Kim - axis,artpec8-cmu-peri 38*91f98de4SHakyeong Kim 39*91f98de4SHakyeong Kim reg: 40*91f98de4SHakyeong Kim maxItems: 1 41*91f98de4SHakyeong Kim 42*91f98de4SHakyeong Kim clocks: 43*91f98de4SHakyeong Kim minItems: 1 44*91f98de4SHakyeong Kim maxItems: 5 45*91f98de4SHakyeong Kim 46*91f98de4SHakyeong Kim clock-names: 47*91f98de4SHakyeong Kim minItems: 1 48*91f98de4SHakyeong Kim maxItems: 5 49*91f98de4SHakyeong Kim 50*91f98de4SHakyeong Kim "#clock-cells": 51*91f98de4SHakyeong Kim const: 1 52*91f98de4SHakyeong Kim 53*91f98de4SHakyeong Kimrequired: 54*91f98de4SHakyeong Kim - compatible 55*91f98de4SHakyeong Kim - reg 56*91f98de4SHakyeong Kim - clocks 57*91f98de4SHakyeong Kim - clock-names 58*91f98de4SHakyeong Kim - "#clock-cells" 59*91f98de4SHakyeong Kim 60*91f98de4SHakyeong KimallOf: 61*91f98de4SHakyeong Kim - if: 62*91f98de4SHakyeong Kim properties: 63*91f98de4SHakyeong Kim compatible: 64*91f98de4SHakyeong Kim const: axis,artpec8-cmu-cmu 65*91f98de4SHakyeong Kim 66*91f98de4SHakyeong Kim then: 67*91f98de4SHakyeong Kim properties: 68*91f98de4SHakyeong Kim clocks: 69*91f98de4SHakyeong Kim items: 70*91f98de4SHakyeong Kim - description: External reference clock (25 MHz) 71*91f98de4SHakyeong Kim 72*91f98de4SHakyeong Kim clock-names: 73*91f98de4SHakyeong Kim items: 74*91f98de4SHakyeong Kim - const: fin_pll 75*91f98de4SHakyeong Kim 76*91f98de4SHakyeong Kim - if: 77*91f98de4SHakyeong Kim properties: 78*91f98de4SHakyeong Kim compatible: 79*91f98de4SHakyeong Kim const: axis,artpec8-cmu-bus 80*91f98de4SHakyeong Kim 81*91f98de4SHakyeong Kim then: 82*91f98de4SHakyeong Kim properties: 83*91f98de4SHakyeong Kim clocks: 84*91f98de4SHakyeong Kim items: 85*91f98de4SHakyeong Kim - description: External reference clock (25 MHz) 86*91f98de4SHakyeong Kim - description: CMU_BUS BUS clock (from CMU_CMU) 87*91f98de4SHakyeong Kim - description: CMU_BUS DLP clock (from CMU_CMU) 88*91f98de4SHakyeong Kim 89*91f98de4SHakyeong Kim clock-names: 90*91f98de4SHakyeong Kim items: 91*91f98de4SHakyeong Kim - const: fin_pll 92*91f98de4SHakyeong Kim - const: bus 93*91f98de4SHakyeong Kim - const: dlp 94*91f98de4SHakyeong Kim 95*91f98de4SHakyeong Kim - if: 96*91f98de4SHakyeong Kim properties: 97*91f98de4SHakyeong Kim compatible: 98*91f98de4SHakyeong Kim const: axis,artpec8-cmu-core 99*91f98de4SHakyeong Kim 100*91f98de4SHakyeong Kim then: 101*91f98de4SHakyeong Kim properties: 102*91f98de4SHakyeong Kim clocks: 103*91f98de4SHakyeong Kim items: 104*91f98de4SHakyeong Kim - description: External reference clock (25 MHz) 105*91f98de4SHakyeong Kim - description: CMU_CORE main clock (from CMU_CMU) 106*91f98de4SHakyeong Kim - description: CMU_CORE DLP clock (from CMU_CMU) 107*91f98de4SHakyeong Kim 108*91f98de4SHakyeong Kim clock-names: 109*91f98de4SHakyeong Kim items: 110*91f98de4SHakyeong Kim - const: fin_pll 111*91f98de4SHakyeong Kim - const: main 112*91f98de4SHakyeong Kim - const: dlp 113*91f98de4SHakyeong Kim 114*91f98de4SHakyeong Kim - if: 115*91f98de4SHakyeong Kim properties: 116*91f98de4SHakyeong Kim compatible: 117*91f98de4SHakyeong Kim const: axis,artpec8-cmu-cpucl 118*91f98de4SHakyeong Kim 119*91f98de4SHakyeong Kim then: 120*91f98de4SHakyeong Kim properties: 121*91f98de4SHakyeong Kim clocks: 122*91f98de4SHakyeong Kim items: 123*91f98de4SHakyeong Kim - description: External reference clock (25 MHz) 124*91f98de4SHakyeong Kim - description: CMU_CPUCL switch clock (from CMU_CMU) 125*91f98de4SHakyeong Kim 126*91f98de4SHakyeong Kim clock-names: 127*91f98de4SHakyeong Kim items: 128*91f98de4SHakyeong Kim - const: fin_pll 129*91f98de4SHakyeong Kim - const: switch 130*91f98de4SHakyeong Kim 131*91f98de4SHakyeong Kim - if: 132*91f98de4SHakyeong Kim properties: 133*91f98de4SHakyeong Kim compatible: 134*91f98de4SHakyeong Kim const: axis,artpec8-cmu-fsys 135*91f98de4SHakyeong Kim 136*91f98de4SHakyeong Kim then: 137*91f98de4SHakyeong Kim properties: 138*91f98de4SHakyeong Kim clocks: 139*91f98de4SHakyeong Kim items: 140*91f98de4SHakyeong Kim - description: External reference clock (25 MHz) 141*91f98de4SHakyeong Kim - description: CMU_FSYS SCAN0 clock (from CMU_CMU) 142*91f98de4SHakyeong Kim - description: CMU_FSYS SCAN1 clock (from CMU_CMU) 143*91f98de4SHakyeong Kim - description: CMU_FSYS BUS clock (from CMU_CMU) 144*91f98de4SHakyeong Kim - description: CMU_FSYS IP clock (from CMU_CMU) 145*91f98de4SHakyeong Kim 146*91f98de4SHakyeong Kim clock-names: 147*91f98de4SHakyeong Kim items: 148*91f98de4SHakyeong Kim - const: fin_pll 149*91f98de4SHakyeong Kim - const: scan0 150*91f98de4SHakyeong Kim - const: scan1 151*91f98de4SHakyeong Kim - const: bus 152*91f98de4SHakyeong Kim - const: ip 153*91f98de4SHakyeong Kim 154*91f98de4SHakyeong Kim - if: 155*91f98de4SHakyeong Kim properties: 156*91f98de4SHakyeong Kim compatible: 157*91f98de4SHakyeong Kim const: axis,artpec8-cmu-imem 158*91f98de4SHakyeong Kim 159*91f98de4SHakyeong Kim then: 160*91f98de4SHakyeong Kim properties: 161*91f98de4SHakyeong Kim clocks: 162*91f98de4SHakyeong Kim items: 163*91f98de4SHakyeong Kim - description: External reference clock (25 MHz) 164*91f98de4SHakyeong Kim - description: CMU_IMEM ACLK clock (from CMU_CMU) 165*91f98de4SHakyeong Kim - description: CMU_IMEM JPEG clock (from CMU_CMU) 166*91f98de4SHakyeong Kim 167*91f98de4SHakyeong Kim clock-names: 168*91f98de4SHakyeong Kim items: 169*91f98de4SHakyeong Kim - const: fin_pll 170*91f98de4SHakyeong Kim - const: aclk 171*91f98de4SHakyeong Kim - const: jpeg 172*91f98de4SHakyeong Kim 173*91f98de4SHakyeong Kim - if: 174*91f98de4SHakyeong Kim properties: 175*91f98de4SHakyeong Kim compatible: 176*91f98de4SHakyeong Kim const: axis,artpec8-cmu-peri 177*91f98de4SHakyeong Kim 178*91f98de4SHakyeong Kim then: 179*91f98de4SHakyeong Kim properties: 180*91f98de4SHakyeong Kim clocks: 181*91f98de4SHakyeong Kim items: 182*91f98de4SHakyeong Kim - description: External reference clock (25 MHz) 183*91f98de4SHakyeong Kim - description: CMU_PERI IP clock (from CMU_CMU) 184*91f98de4SHakyeong Kim - description: CMU_PERI AUDIO clock (from CMU_CMU) 185*91f98de4SHakyeong Kim - description: CMU_PERI DISP clock (from CMU_CMU) 186*91f98de4SHakyeong Kim 187*91f98de4SHakyeong Kim clock-names: 188*91f98de4SHakyeong Kim items: 189*91f98de4SHakyeong Kim - const: fin_pll 190*91f98de4SHakyeong Kim - const: ip 191*91f98de4SHakyeong Kim - const: audio 192*91f98de4SHakyeong Kim - const: disp 193*91f98de4SHakyeong Kim 194*91f98de4SHakyeong KimadditionalProperties: false 195*91f98de4SHakyeong Kim 196*91f98de4SHakyeong Kimexamples: 197*91f98de4SHakyeong Kim # Clock controller node for CMU_FSYS 198*91f98de4SHakyeong Kim - | 199*91f98de4SHakyeong Kim #include <dt-bindings/clock/axis,artpec8-clk.h> 200*91f98de4SHakyeong Kim 201*91f98de4SHakyeong Kim cmu_fsys: clock-controller@16c10000 { 202*91f98de4SHakyeong Kim compatible = "axis,artpec8-cmu-fsys"; 203*91f98de4SHakyeong Kim reg = <0x16c10000 0x4000>; 204*91f98de4SHakyeong Kim #clock-cells = <1>; 205*91f98de4SHakyeong Kim clocks = <&fin_pll>, 206*91f98de4SHakyeong Kim <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>, 207*91f98de4SHakyeong Kim <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>, 208*91f98de4SHakyeong Kim <&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>, 209*91f98de4SHakyeong Kim <&cmu_cmu CLK_DOUT_CMU_FSYS_IP>; 210*91f98de4SHakyeong Kim clock-names = "fin_pll", "scan0", "scan1", "bus", "ip"; 211*91f98de4SHakyeong Kim }; 212*91f98de4SHakyeong Kim 213*91f98de4SHakyeong Kim... 214