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/freebsd/sys/dev/dpaa2/
H A Ddpaa2_ni_dpkg.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause AND BSD-2-Clause
4 * Copyright © 2013-2015 Freescale Semiconductor, Inc.
17 * 3. Neither the name of the copyright holder nor the names of its
41 * Copyright © 2021-2022 Dmitry Salychev
68 #define BIT(x) (1ul << (x)) macro
71 * DPKG_NUM_OF_MASKS - Number of masks per key extraction
76 * DPKG_MAX_NUM_OF_EXTRACTS - Number of extractions per key profile
81 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
93 * enum dpkg_extract_type - Enumeration for selecting extraction type
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/freebsd/contrib/wpa/src/common/
H A Dieee802_11_defs.h3 * Copyright (c) 2002-2019, Jouni Malinen <j@w1.fi>
4 * Copyright (c) 2007-2008 Intel Corporation
39 #define WLAN_GET_SEQ_FRAG(seq) ((seq) & (BIT(3) | BIT(2) | BIT(1) | BIT(0)))
41 (((seq) & (~(BIT(3) | BIT(2) | BIT(1) | BIT(0)))) >> 4)
46 #define WLAN_FC_TYPE_EXT 3
52 #define WLAN_FC_STYPE_REASSOC_RESP 3
75 #define WLAN_FC_STYPE_DATA_CFACKPOLL 3
96 #define WLAN_AUTH_SAE 3
105 #define WLAN_CAPABILITY_ESS BIT(0)
106 #define WLAN_CAPABILITY_IBSS BIT(1)
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/freebsd/sys/dev/qat/qat_hw/qat_dh895xcc/
H A Dadf_dh895xcc_hw_data.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
31 #define ADF_DH895XCC_ENABLE_AE_ECC_ERR BIT(28)
32 #define ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
35 #define ADF_DH895XCC_ERRSSMSH_EN BIT(3)
38 /* BIT(2) enables the logging of push/pull data errors. */
39 #define ADF_DH895XCC_PPERR_EN (BIT(2))
50 #define ADF_DH895XCC_ERRMSK0_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0))
51 #define ADF_DH895XCC_ERRMSK1_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0))
52 #define ADF_DH895XCC_ERRMSK3_CERR (BIT(7))
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/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Drs.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2022, 2024 Intel Corporation
12 * enum iwl_tlc_mng_cfg_flags - options for TLC config flags
27 IWL_TLC_MNG_CFG_FLAGS_STBC_MSK = BIT(
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmc13xxx.txt4 - compatible : Should be "fsl,mc13783" or "fsl,mc13892"
7 - fsl,mc13xxx-uses-adc : Indicate the ADC is being used
8 - fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used
9 - fsl,mc13xxx-uses-rtc : Indicate the RTC is being used
10 - fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used
12 Sub-nodes:
13 - codec: Contain the Audio Codec node.
14 - adc-port: Contain PMIC SSI port number used for ADC.
15 - dac-port: Contain PMIC SSI port number used for DAC.
16 - leds : Contain the led nodes and initial register values in property
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/freebsd/sys/dev/qat/qat_hw/qat_200xx/
H A Dadf_200xx_hw_data.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
11 #define ADF_200XX_MAX_ACCELERATORS 3
22 #define ADF_200XX_POWERGATE_PKE BIT(24)
23 #define ADF_200XX_POWERGATE_CY BIT(23)
30 #define ADF_200XX_ENABLE_AE_ECC_ERR BIT(28)
31 #define ADF_200XX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
34 #define ADF_200XX_ERRSSMSH_EN BIT(3)
38 /* BIT(2) enables the logging of push/pull data errors. */
39 #define ADF_200XX_PPERR_EN (BIT(2))
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/freebsd/sys/dev/qat/qat_hw/qat_c3xxx/
H A Dadf_c3xxx_hw_data.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
11 #define ADF_C3XXX_MAX_ACCELERATORS 3
22 #define ADF_C3XXX_POWERGATE_PKE BIT(24)
23 #define ADF_C3XXX_POWERGATE_CY BIT(23)
28 #define ADF_C3XXX_ENABLE_AE_ECC_ERR BIT(28)
29 #define ADF_C3XXX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
32 #define ADF_C3XXX_ERRSSMSH_EN BIT(3)
36 /* BIT(2) enables the logging of push/pull data errors. */
37 #define ADF_C3XXX_PPERR_EN (BIT(2))
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/freebsd/sys/contrib/dev/rtw89/
H A Dpci.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
13 #define MDIO_PG1_G2 3
18 #define BAC_OOBS_SEL BIT(4)
20 #define B_BAC_EQ_SEL BIT(5)
22 #define B_PCIE_BIT_PSAVE BIT(1
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H A Dtxrx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
12 #define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0)
18 #define DATA_RATE_VHT_HE_IDX_MASK GENMASK(3, 0)
27 if (rtwdev->chip->chip_ge in rtw89_get_data_rate_mode()
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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Davxvnniint8intrin.h1 /*===-------- avxvnniint8intrin.h - AVXVNNIINT8 intrinsics -----------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
25 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in \a __A with
26 /// corresponding signed 8-bit integers in \a __B, producing 4 intermediate
27 /// signed 16-bit results. Sum these 4 results with the corresponding
28 /// 32-bit integer in \a __W, and store the packed 32-bit results in \a dst.
39 /// A 128-bit vector of [16 x char].
41 /// A 128-bit vector of [16 x char].
43 /// A 128-bit vector of [4 x int].
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/freebsd/sys/dev/ice/
H A Dice_adminq_cmd.h1 /* SPDX-License-Identifier: BSD-3-Clause */
15 * 3. Neither the name of the Intel Corporation nor the names of its
87 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
106 #define ICE_AQC_RES_ID_CHNG_LOCK 3
203 /* Manage MAC address, read command - indirect (0x0107)
208 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(
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/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_hw_data.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
32 #define ADF_C4XXX_FUSE_PROD_SKU_MASK BIT(31)
34 #define ADF_C4XXX_LEGFUSE_BASE_SKU_MASK (BIT(2) | BIT(3))
36 #define ADF_C4XXX_FUSE_DISABLE_INLINE_INGRESS BIT(12)
37 #define ADF_C4XXX_FUSE_DISABLE_INLINE_EGRESS BIT(13)
61 #define ADF_C4XXX_ENABLE_AE_ECC_ERR BIT(28)
62 #define ADF_C4XXX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
64 #define ADF_C4XXX_UERRSSMSH_INTS_CLEAR_MASK (~BIT(0) ^ BIT(16))
66 #define ADF_C4XXX_CERRSSMSH_INTS_CLEAR_MASK (~BIT(0))
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H A Dadf_c4xxx_inline.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
19 #define ADF_C4XXX_SADB_SIZE_BIT BIT(24)
21 ((accel_dev)->aram_info->sadb_region_size / 32)
24 /* SADB CTRL register bit offsets */
39 #define ADF_C4XXX_STATS_REQUEST_ENABLED BIT(16)
40 #define ADF_C4XXX_STATS_REQUEST_DISABLED ~BIT(16)
45 #define ADF_C4XXX_MAC_STATS_READY BIT(0)
48 #define ADF_C4XXX_MAC_ERROR_TX_UNDERRUN BIT(6)
49 #define ADF_C4XXX_MAC_ERROR_TX_FCS BIT(7)
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/freebsd/sys/contrib/dev/athk/ath10k/
H A Drx_desc.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
13 RX_ATTENTION_FLAGS_FIRST_MPDU = BIT(0),
14 RX_ATTENTION_FLAGS_LAST_MPDU = BIT(1),
15 RX_ATTENTION_FLAGS_MCAST_BCAST = BIT(2),
16 RX_ATTENTION_FLAGS_PEER_IDX_INVALID = BIT(3),
17 RX_ATTENTION_FLAGS_PEER_IDX_TIMEOUT = BIT(4),
18 RX_ATTENTION_FLAGS_POWER_MGMT = BIT(5),
19 RX_ATTENTION_FLAGS_NON_QOS = BIT(6),
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/freebsd/sys/contrib/dev/rtw88/
H A Drtw8821c.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -3
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H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
9 #define BIT_FEN_EN_25_1 BIT(13)
10 #define BIT_FEN_ELDR BIT(12)
11 #define BIT_FEN_CPUEN BIT(
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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td1 //===- IntrinsicsAMDGPU.td - Defines AMDGPU intrinsics -----*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines all of the R600-specific intrinsics.
11 //===----------------------------------------------------------------------===//
15 // The amdgpu-no-* attributes (ex amdgpu-no-workitem-id-z) typically inferred
16 // by the backend cause whole-program undefined behavior when violated, such as
18 // values. In non-entry-point functions, attempting to call a function that needs
20 // of the calling convention and also program-level UB. Outside of such IR-level UB,
21 // these preloaded registers are always set to a well-defined value and are thus `noundef`.
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H A DIntrinsicsRISCVXsf.td1 //===- IntrinsicsRISCVXsf.td - SiFive intrinsics -----------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines all of the SiFive vendor intrinsics for RISC-V.
11 //===----------------------------------------------------------------------===//
22 // Input: (bit<27-26>, bit<24-20>, scalar_in, vl) or
23 class RISCVSFCustomVC_X<bit HasSE, bit ImmScalar>
26 … !listconcat([IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>], // bit<27-26> and bit<24-20>
32 let VLOperand = 3;
35 // Input: (bit<27-26>, bit<24-20>, bit<11-7>, scalar_in, sew, log2lmul, vl)
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/freebsd/sys/dev/sfxge/common/
H A Defx_regs_pci.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
41 * PC_VEND_ID_REG(16bit):
52 * PC_DEV_ID_REG(16bit):
63 * PC_CMD_REG(16bit):
84 #define PCRF_AZ_SPEC_CYC_LBN 3
94 * PC_STAT_REG(16bit):
121 #define PCRF_AZ_INTX_STAT_LBN 3
125 * PC_REV_ID_REG(8bit):
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/freebsd/sys/dev/msk/
H A Dif_mskreg.h17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
62 * 3. All advertising materials mentioning features or use of this software
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
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/freebsd/share/man/man3/
H A Dqmath.331 .Nd fixed-point math library based on the
39 data types and APIs support fixed-point math based on the
79 None of the operations is affected by the floating-point environment.
86 .Bl -column "isgreaterequal" "bessel function of the second kind of the order 0"
91 .Xr Q_INI 3 initialise a Q number
95 .Xr Q_QADDQ 3 addition
96 .Xr Q_QDIVQ 3 division
97 .Xr Q_QMULQ 3 multiplication
98 .Xr Q_QSUBQ 3 subtraction
99 .Xr Q_NORMPREC 3 normalisation
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/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
38 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
40 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
54 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
55 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
56 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
57 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
78 …Bit 0 - For ending "endless completion". 0 - When receiving a completion timeout while receiving a…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 … // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo push overflow…
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/freebsd/sys/contrib/dev/athk/ath12k/
H A Ddp.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
81 #define DP_LINK_DESC_SHIFT 3
188 #define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; })
235 /* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */
238 /* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */
255 #define DP_INVALID_BANK_ID -1
332 * - reo_cmd_list
333 * - reo_cmd_cache_flush_list
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrFormats.td1 //===- ARCInstrFormats.td - ARC Instruction Formats --------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
21 "\n return isUInt<"#BSz#">(N->getSExtValue());"> {
27 "\n return isInt<"#BSz#">(N->getSExtValue());"> {
31 // e.g. s3 field may encode the signed integers values -1 .. 6
34 "\n return isInt<"#BSz#">(N->getSExtValue());"> {
64 class ExtMode<bit mode, string instSfx, string asmSfx> {
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/freebsd/sys/dev/flash/flexspi/
H A Dflex_spi.h1 /*-
29 #define BIT(x) (1 << (x)) macro
35 #define FSPI_MCR0_LEARN_EN BIT(15)
36 #define FSPI_MCR0_SCRFRUN_EN BIT(14)
37 #define FSPI_MCR0_OCTCOMB_EN BIT(13)
38 #define FSPI_MCR0_DOZE_EN BIT(12)
39 #define FSPI_MCR0_HSEN BIT(11)
40 #define FSPI_MCR0_SERCLKDIV BIT(8)
41 #define FSPI_MCR0_ATDF_EN BIT(7)
42 #define FSPI_MCR0_ARDF_EN BIT(6)
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