Lines Matching +full:3 +full:- +full:bit
2 * Copyright (c) 2017-2018 Cavium, Inc.
38 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
40 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
54 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
55 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
56 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
57 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
78 …Bit 0 - For ending "endless completion". 0 - When receiving a completion timeout while receiving a…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 … // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo push overflow…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
83 …he value will not be loaded, EEPROM load will stop, and the FastLinkEnable bit will be set in the …
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
102 …aster enable. If the PF or any of its VFs try to master the bus when this bit is not set, the req…
104 … (0x1<<3) // Special cycle en…
105 …CIEIP_REG_PCIEEP_CMD_SCSE_E5_SHIFT 3
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
147 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
151 …_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_K2 (0x1<<3) // Special Cycle En…
152 …CIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_K2_SHIFT 3
185 …2 (0x1<<30) // Fatal or Non-Fatal Error Message s…
189 …20 // This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)
190 … (0x1<<0) // This bit indicates that the …
192 … (0x1<<1) // This bit controls the enabli…
194 … (0x1<<2) // This bit controls the enabli…
196 …CIAL_CYCLES_BB (0x1<<3) // Does not apply t…
197 …CIEIP_REG_STATUS_COMMAND_SPECIAL_CYCLES_BB_SHIFT 3
202 …6) // This bit enables the write to the Master data parity error status bit. If this bit is cleare…
206 …bit enables the non fatal and fatal errors detected by the function to be reported to the Root Com…
210 …bit is set, function is not permitted to generate IntX interrupt messages (de-asserted) regardless…
216 … (0x1<<19) // This bit indicates the inter…
218 … (0x1<<20) // This bit is tied high to ind…
226 …bit is set by a requester if the parity error enable bit is set in its command register and either…
230 …BB (0x1<<27) // This bit is set when a funct…
232 …BB (0x1<<28) // This bit is set when a reque…
234 …_BB (0x1<<29) // This bit is set when a reque…
236 … (0x1<<30) // This bit is set when a function sends an ERR_FATAL or ERR_NONFATAL messag…
238 … (0x1<<31) // When this bit is set, it indicate…
250 …n Revision ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
252 …ing Interface. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
254 …t Device Type. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
256 …t Device Type. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
261 … (0xffffff<<8) // The 24-bit Class Code register…
270 …vice. The multi function device bit is writable through PEM()_CFG_WR. The application must not wr…
281 …multifunction. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
290 … (0xff<<16) // The 8-bit Header Type register identifies both the layout of byt…
292 … (0xff<<24) // The 8-bit BIST register is used to initiate and report the results o…
297 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. Th…
299 … (0x1<<3) // Prefetchable. Th…
300 …CIEIP_REG_PCIEEP_BAR0L_PF_E5_SHIFT 3
303 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
304 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
306 … (0x3<<1) // BAR0 32-bit or 64-bit. Note: The access attributes of this field a…
308 … (0x1<<3) // BAR0 Prefetchable. Note: The access attributes of this fi…
309 …CIEIP_REG_BAR0_REG_BAR0_PREFETCH_K2_SHIFT 3
310 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
312 …-bit BAR_1 register programs the base address for the memory space mapped by the card onto the PCI…
313 … (0x1<<0) // This bit indicates that BAR_…
315 …ate that BAR_1 may be programmed to map this adapter to anywhere in the 64-bit address space. Path…
317 … (0x1<<3) // This bit indicates that the area mapped by BAR_1 may be pre-fetched or cached…
318 …CIEIP_REG_BAR_1_PREFETCH_BB_SHIFT 3
319 …s within a 32-bit address space that will be card will respond in. These bits may be combined with…
322 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
323 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
325 … (0x3<<1) // BAR1 32-bit or 64-bit. Note: The access attributes of this field a…
327 … (0x1<<3) // BAR1 Prefetchable. Note: The access attributes of this fi…
328 …CIEIP_REG_BAR1_REG_BAR1_PREFETCH_K2_SHIFT 3
329 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
331 … 0x000014UL //Access:RW DataWidth:0x20 // The 32-bit BAR_2 register prog…
335 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. Th…
337 … (0x1<<3) // Prefetchable. Th…
338 …CIEIP_REG_PCIEEP_BAR2L_PF_E5_SHIFT 3
341 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
342 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
344 … (0x3<<1) // BAR2 32-bit or 64-bit. Note: The access attributes of this field a…
346 … (0x1<<3) // BAR2 Prefetchable. Note: The access attributes of this fi…
347 …CIEIP_REG_BAR2_REG_BAR2_PREFETCH_K2_SHIFT 3
348 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
350 …-bit BAR_3 register programs the 2nd base address for the memory space mapped by the card onto the…
351 … (0x1<<0) // This bit indicates that BAR_…
353 …ate that BAR_2 may be programmed to map this adapter to anywhere in the 64-bit address space. Path…
355 … (0x1<<3) // This bit indicates that the area mapped by BAR_2 …
356 …CIEIP_REG_BAR_3_PREFETCH_BB_SHIFT 3
357 …s within a 32-bit address space that will be card will respond in. These bits may be combined with…
360 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
361 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
363 … (0x3<<1) // BAR3 32-bit or 64-bit. Note: The access attributes of this field a…
365 … (0x1<<3) // BAR3 Prefetchable. Note: The access attributes of this fi…
366 …CIEIP_REG_BAR3_REG_BAR3_PREFETCH_K2_SHIFT 3
367 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
369 … 0x00001cUL //Access:RW DataWidth:0x20 // The 32-bit BAR_4 register prog…
373 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. Th…
375 … (0x1<<3) // Prefetchable. Th…
376 …CIEIP_REG_PCIEEP_BAR4L_PF_E5_SHIFT 3
379 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
380 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
382 … (0x3<<1) // BAR4 32-bit or 64-bit. Note: The access attributes of this field a…
384 … (0x1<<3) // BAR4 Prefetchable. Note: The access attributes of this fi…
385 …CIEIP_REG_BAR4_REG_BAR4_PREFETCH_K2_SHIFT 3
386 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
388 …-bit BAR_5 register programs the 3rd base address for the memory space mapped by the card onto the…
389 … (0x1<<0) // This bit indicates that BAR_…
391 …ate that BAR_3 may be programmed to map this adapter to anywhere in the 64-bit address space. Path…
393 … (0x1<<3) // This bit indicates that the area mapped by BAR_3 …
394 …CIEIP_REG_BAR_5_PREFETCH_BB_SHIFT 3
395 …s within a 32-bit address space that will be card will respond in. These bits may be combined with…
398 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
399 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
401 … (0x3<<1) // BAR5 32-bit or 64-bit. Note: The access attributes of this field a…
403 … (0x1<<3) // BAR5 Prefetchable. Note: The access attributes of this fi…
404 …CIEIP_REG_BAR5_REG_BAR5_PREFETCH_K2_SHIFT 3
405 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
407 …x000024UL //Access:RW DataWidth:0x20 // The 32-bit BAR_4 register programs the upper half of t…
412 … (0xffff<<0) // Subsystem vendor ID. Assigned by PCI-SIG, writable through…
414 … (0xffff<<16) // Subsystem ID. Assigned by PCI-SIG, writable through…
417 …tem Vendor ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
419 …tem Device ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
422 …NDOR_ID_BB (0xffff<<0) // The 16-bit Subsystem Vendor ID…
424 …BB (0xffff<<16) // The 16-bit Subsystem ID regist…
431 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
432 …<<0) // Expansion ROM Enable. Note: The access attributes of this field are as follows: - Dbi: R
434 …Expansion ROM Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W
436 … 0x000030UL //Access:RW DataWidth:0x20 // The 32-bit Expansion ROM BAR r…
437 …bit indicates that the Expansion ROM BAR is valid when set to one. If it is zero, the expansion BA…
449 …ity Structure. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
452 …-bit Capabilities Pointer register specifies an offset in the PCI address space of a linked list o…
466 …egister Field. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
469 …NT_LINE_BB (0xff<<0) // The 8-bit Interrupt Line regi…
471 …NT_PIN_BB (0xff<<8) // The 8-bit Interrupt Pin regis…
494 …bit indicates that the device (or function) is not capable of generating PME messages while in tha…
499 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
501 … Spec Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
505 … Return to D0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
507 …0x1<<21) // Device Specific Initialization Bit. Note: The access attributes of this field are as…
509 … Requirements. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
511 …State Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
513 …State Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
515 …tion parameter. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
520 …E5 (0x1<<3) // No soft reset, w…
521 …CIEIP_REG_PCIEEP_PM_CTL_NSR_E5_SHIFT 3
537 …owever, the read-back value is the actual power state, not the write value. Note: The access attr…
539 … (0x1<<3) // No soft Reset. Note: The access attributes of this fiel…
540 …CIEIP_REG_CON_STATUS_REG_NO_SOFT_RST_K2_SHIFT 3
556 … (0xff<<0) // The 8-bit Power Management Ca…
558 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
560 …ies with revision 1.2 of the PCI Power Management Interface Specification. Bit is programmable thr…
564 …bit indicates that the device relies on the presence of the PCI clock for PME# operation. This chi…
568 …bit indicates that the device requires a specific initialization (DSI) sequence following a transi…
572 …(0x1<<25) // This bit indicates whether the device supports the D1 power management state. This bi…
574 …(0x1<<26) // This bit indicates whether the device supports the D2 power management state. This bi…
576 … // This bit indicates whether the device supports transmiting PME message from the D0 power state…
578 … // This bit indicates whether the device supports transmiting PME message from the D1 power state…
580 … // This bit indicates whether the device supports transmiting PME message from the D2 power state…
582 … This bit indicates whether the device supports transmiting PME message from the D3hot power state…
584 …bit indicates whether the device supports transmiting PME message from the D3cold power state. Thi…
587 …e as the PM_STATE bits. When written from the PCI bus, only values of 0 and 3 will be accepted. Th…
591 … (0x1<<3) // When device transitions from D3 to D0, device does not perform a…
592 …CIEIP_REG_PM_CSR_NO_SOFT_RESET_BB_SHIFT 3
595 … (0x1<<8) // This bit enables the device to transmit PME messages. On HARD reset, this b…
601 …bit is set when a PME is asserted from the MAC or RX Parser blocks, regardless of the state of the…
610 … Next Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
614 …ssage Capable. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
618 … (0x1<<23) // MSI 64-bit Address Capable. Note: The access attributes of this fiel…
623 … (0xff<<0) // The 8-bit VPD Capability ID is set to 3 to i…
625 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
629 …// This value is the 32-bit word address of the VPD value being accessed in the vpd_data register.…
631 …bit is used to control passing of data between the vpd_data register and Non-Volatile memory. To r…
634 …essage Lower Address Field. Note: The access attributes of this field are as follows: - Dbi: R/W
636 … This is the VPD data transfer register. See the instructions for the FLAG bit above for usage of …
637 …58UL //Access:RW DataWidth:0x20 // For a 32 bit MSI Message, this register contains Data. For …
638 …-bit MSI Message, this field contains Data. For 64-bit it contains lower 16 bits of the Upper Addr…
640 …bit MSI Message, this is reserved. For 64-bit it contains upper 16 bits of the Upper Address. Not…
643 … (0xff<<0) // The 8-bit MSI Capability ID i…
645 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
647 …16) // When this bit is set, the chip will generate MSI cycles to indicate interrupts instead of a…
649 …g. This value comes from the Path = i_cfg_func.i_cfg_private MULTI_MSG_CAP bit in the register spa…
653 … (0x1<<23) // This bit indicates that the chip is capable of generatin…
655 … (0x1<<24) // This bit indicates if the function supports per vector masking. This value come…
657 …5cUL //Access:RW DataWidth:0x20 // For a 64 bit MSI Message, this register contains Data. For …
658 …-bit MSI Message, this field contains Data. For 32-bit, it contains the lower Mask Bits if PVM is …
660 …-bit MSI Message, this field contains Data. For 32-bit, it contains the upper Mask Bits if PVM is …
667 …x20 // Used for MSI when Vector Masking Capable. For 32 bit contains Pending Bits. For 64 bit, c…
669 … 0x000064UL //Access:R DataWidth:0x20 // Used for MSI 64 bit messaging when Vect…
676 … (0xff<<8) // Next capability pointer. Points to the MSI-X Capabilities by def…
682 …This bit is writable through PEM()_CFG_WR. However, it must be 0 for an endpoint device. Therefore…
689 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
695 …emented Valid. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
697 …essage Number. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
704 …_E5 (0x3<<3) // Phantom function…
705 …CIEIP_REG_PCIEEP_DEV_CAP_PFS_E5_SHIFT 3
706 … (0x1<<5) // Extended tag field supported. This bit is writable through…
712 … (0x1<<15) // Role-based error reporting…
718 … (0x1<<28) // Function level reset capability. Set to 1 for SR-IOV core.
721 …ize Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
723 … (0x3<<3) // Phantom Functions Supported. Note: The access attributes of th…
724 …CIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_K2_SHIFT 3
725 …eld Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
727 …table latency. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
729 …table latency. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
731 … (0x1<<15) // Role-based Error Reporting Implemented. Note: The access attributes of th…
737 …dpoints only). Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
746 …EN_E5 (0x1<<3) // Unsupported requ…
747 …CIEIP_REG_PCIEEP_DEV_CTL_UR_EN_E5_SHIFT 3
752 … (0x1<<8) // Extended tag field enable. Set this bit to enable extended …
754 … (0x1<<9) // Phantom function enable. This bit should never be set…
764 …if we receive any of the errors in PCIEEP_COR_ERR_STAT, for example a replay-timer timeout. Also,…
770 …ests are nonfatal errors, so [UR_D] should cause [NFE_D]. Receiving a vendor-defined message shoul…
779 …S_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2 (0x1<<1) // Non-fatal Error Reporting…
783 …ICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_K2 (0x1<<3) // Unsupported Requ…
784 …CIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_K2_SHIFT 3
789 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
791 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
793 …K2 (0x1<<10) // Aux Power PM Enable. This bit is derived by sampl…
795 …(0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R
803 …_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2 (0x1<<17) // Non-Fatal Error Detected …
809 … (0x1<<20) // Aux Power Detected Status. This bit is derived by sampl…
837 …In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. Note: The …
839 …In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. Note: The …
841 …ment) Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
843 …bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) deter…
845 …bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) deter…
847 …er Management. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
855 …ty Compliance. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
857 …/ Port Number. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
862 …B_E5 (0x1<<3) // Read completion …
863 …CIEIP_REG_PCIEEP_LINK_CTL_RCB_E5_SHIFT 3
876 … (0x1<<10) // Link bandwidth management interrupt enable. This bit is not applicable a…
878 … (0x1<<11) // Link autonomous bandwidth interrupt enable. This bit is not applicable a…
882 …bit location in the supported link speeds vector (in the link capabilities 2 register) that corres…
899 … (0x1<<3) // Read Completion Boundary (RCB). Note: The access attributes of t…
900 …CIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_K2_SHIFT 3
901 …_LINK_CTRL_OFF. Note: The access attributes of this field are as follows: - Dbi: CX_CROSSLINK_EN…
903 …e Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description
909 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
911 …e Autonomous Width Disable. Note: The access attributes of this field are as follows: - Dbi: R/W
913 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
915 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
923 …figuration or Recovery State. Note: The access attributes of this field are as follows: - Dbi: R
925 …Configuration. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
929 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
931 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
942 … (0x1<<7) // 32-bit AtomicOp supported.…
944 … (0x1<<8) // 64-bit AtomicOp supported.…
946 … (0x1<<9) // 128-bit AtomicOp supported.…
948 … (0x1<<10) // No RO-enabled PR-PR passing. (This bit appl…
956 …PP_E5 (0x1<<16) // 10-bit tag completer suppo…
958 …PP_E5 (0x1<<17) // 10-bit tag requestor suppo…
964 … (0x1<<21) // End-end TLP prefix suppor…
966 … (0x3<<22) // Max end-end TLP prefixes. 0x1 = 1. 0x2 = 2. 0x3 =…
977 …E_CAP_32_ATOMIC_CPL_SUPP_K2 (0x1<<7) // 32 Bit AtomicOp Completer …
979 …E_CAP_64_ATOMIC_CPL_SUPP_K2 (0x1<<8) // 64 Bit AtomicOp Completer …
981 …_CAP_128_CAS_CPL_SUPP_K2 (0x1<<9) // 128 Bit CAS Completer Suppo…
983 …R2PR_PAR_K2 (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
987 …P_TPH_CMPLT_SUPPORT_0_K2 (0x1<<12) // TPH Completer Supported Bit 0.
989 …P_TPH_CMPLT_SUPPORT_1_K2 (0x1<<13) // TPH Completer Supported Bit 1.
1010 …_E5 (0x1<<12) // 10-bit tag requester enabl…
1014 … (0x1<<15) // End-end TLP prefix blocki…
1017 …/ Completion Timeout Value. Note: The access attributes of this field are as follows: - Dbi: R/W
1036 …bit, a value of 1 b indicates that the corresponding link speed is supported; otherwise, the link …
1049 …DRS Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1052 …e target compliance mode speed when software is using the enter compliance bit to force a link int…
1054 …mode at the speed indicated in the target link speed field by setting this bit to one in both comp…
1056 …he application must disable hardware from changing the link speed for device-specific reasons othe…
1060 …-deemphasized voltage level at the transmitter pins: 0x0 = 800-1200 mV for full swing 400-600 mV …
1062 … (0x1<<10) // Enter modified compliance. When this bit is set to one, the …
1064 …mpliance patterns. When the link is operating at 2.5 GT/s, the setting of this bit has no effect.
1066 …bit sets the deemphasis level in Polling.Compliance state if the entry occurred due to the TX comp…
1068 … operating at 5 GT/s speed, this bit reflects the level of deemphasis. 0 = -6 dB. 1 = -3.5 dB. …
1076 … (0x1<<20) // Equalization phase 3 successful.
1091 …K_SPEED_K2 (0xf<<0) // Target Link Speed. In M-PCIe mode, the conten…
1095 …Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
1097 …EMPHASIS_K2 (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. …
1101 …ed Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
1103 … transmission. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1105 … // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The access attributes of thi…
1107 … (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is alwa…
1115 … (0x1<<20) // Equalization 8.0GT/s Phase 3 Successful. Note: …
1126 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
1128 …f<<16) // System sw reads this field to determine the MSI-X table size N, which is encoded as N-1 …
1132 …ssociated with the function are masked regardless of their per vector Mask bit. Path = i_cfg_func.…
1134 … (0x1<<31) // If 1, and the MSI enable bit in the MSI message …
1137 … (0x7<<0) // Indicates which one of functions BAR is used to map MSI-X table into memory s…
1139 …FSET_BB (0x1fffffff<<3) // Path = i_cfg_fun…
1140 …CIEIP_REG_MSIX_TBL_OFF_BIR_TABLE_OFFSET_BB_SHIFT 3
1142 … (0x7<<0) // Indicates which one of functions BAR is used to map MSI-X PBA into memory spa…
1144 …ET_BB (0x1fffffff<<3) // Path = i_cfg_fun…
1145 …CIEIP_REG_MSIX_PBA_BIR_OFF_PBA_OFFSET_BB_SHIFT 3
1157 …-X vector is used for the interrupt message generated in association with any of the status bits o…
1160 …MSIXCID_E5 (0xff<<0) // MSI-X capability ID.
1164 … (0x7ff<<16) // MSI-X table size encoded as (table size - 1)…
1166 …ask bit determines whether the vector is masked or not. 1 = All vectors associated with the funct…
1168 … (0x1<<31) // MSI-X enable. If MSI-X is enabled,…
1170 … 0x0000b0UL //Access:RW DataWidth:0x20 // MSI-X Capability ID, Next…
1171 …TRL_REG_PCI_MSIX_CAP_ID_K2 (0xff<<0) // MSI-X Capability ID.
1173 … (0xff<<8) // MSI-X Next Capability Pointer. Note: The access attributes of this f…
1175 …-X Table Size. SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PC…
1177 …(0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W
1179 … (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are…
1184 …EVICE_CAPABILITY_UNUSED0_BB (0x3<<3) //
1185 …CIEIP_REG_DEVICE_CAPABILITY_UNUSED0_BB_SHIFT 3
1186 … (0x1<<5) // Extended Tag Field Support. This bit is programmable thr…
1202 … (0x1<<28) // FLR capability is advertized when flr_supported bit in private device_c…
1205 … (0x7<<0) // MSI-X table BAR indicator register (BIR). Indicates which BAR is u…
1207 … (0x1fffffff<<3) // MSI-X table offset register. Base address of …
1208 …CIEIP_REG_PCIEEP_MSIX_TABLE_MSIXTOFFS_E5_SHIFT 3
1209 … 0x0000b4UL //Access:RW DataWidth:0x20 // MSI-X Table Offset and BI…
1210 … (0x7<<0) // MSI-X Table Bar Indicator Register Field. Note: The access attributes of …
1212 … (0x1fffffff<<3) // MSI-X Table Offset. Note: The access attributes of this fi…
1213 …CIEIP_REG_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_K2_SHIFT 3
1217 …L_ERR_REPORT_EN_BB (0x1<<1) // Non-Fatal Error Reporting…
1221 …ROL_U_REQ_REPORT_EN_BB (0x1<<3) // Unsupported Requ…
1222 …CIEIP_REG_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN_BB_SHIFT 3
1231 …M_ENA_BB (0x1<<10) // This bit when set enables de…
1233 … (0x1<<11) // Enable No Snoop. When this bit is set to 1, PCIE initiates a read request with the …
1237 …bit is writeable only if flr_supported bit in private device_capability register is set. A write o…
1241 …TAL_ERR_DET_BB (0x1<<17) // Non-Fatal Error Detected.…
1247 …ET_BB (0x1<<20) // This bit is the current stat…
1249 … (0x1<<21) // This is bit is read back a 1, whenever a non-pos…
1252 … (0x7<<0) // MSI-X PBA BAR indicator register (BIR). Indicates which BAR is used to …
1254 … (0x1fffffff<<3) // MSI-X table offset register. Base address of …
1255 …CIEIP_REG_PCIEEP_MSIX_PBA_MSIXPOFFS_E5_SHIFT 3
1256 … 0x0000b8UL //Access:RW DataWidth:0x20 // MSI-X PBA Offset and BIR …
1257 … (0x7<<0) // MSI-X PBA BIR. Note: The access attributes of this field are…
1259 … (0x1fffffff<<3) // MSI-X PBA Offset. Note: The access attributes of this fie…
1260 …CIEIP_REG_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_K2_SHIFT 3
1264 … (0x3f<<4) // Maximum Link Width. These are programmable through reg space.Bit 9 is always 0 and i…
1274 … (0x1<<19) // Surprise Down Error Reporting Capable: RC: this bit must be set if the …
1276 … (0x1<<20) // Data Link Layer Link Active Reporting Capable: RC: this bit must be hardwired t…
1285 …<0) // ASPM Control. Value used by logic is dependent on the value of this bit for each enabled fu…
1289 …L_RCB_BB (0x1<<3) // Read Completion …
1290 …CIEIP_REG_LINK_STATUS_CONTROL_RCB_BB_SHIFT 3
1291 …4) // Requesting PHY to disable the link. This bit is only applicable to RC. So for EP it is read …
1293 …5) // Requesting PHY to retrain the link. This bit is only applicable to RC. So for EP it is read …
1295 …d by logic is resolved to 1 only if all functions (when enabled) have this bit set. For ARI device…
1297 …bit when set forces the transmission of 4096 FTS ordered sets in the L0s state followed by a singl…
1299 …/ Enable Clock Power Management: RC: N/A and hardwired to 0. EP: When this bit is set, the device …
1301 … (0x1<<9) // Hardware Autonomous Width Disable: When Set, this bit disables hardware f…
1303 …pt Enable: when Set, this bit enables the generation of an interrupt to indicate that the Link Ban…
1305 …pt Enable: When Set, this bit enables the generation of an interrupt to indicate that the Link Aut…
1315 …B (0x1<<27) // EP: This bit is N/A and is hardw…
1317 … (0x1<<28) // Slot Clock configuration. This bit is read-only by host, bu…
1355 …xt Capability. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1357 …0x7fff<<16) // VPD Address. Note: The access attributes of this field are as follows: - Dbi: R/W
1359 … (0x1<<31) // VPD Flag. Note: The access attributes of this field are as follows: - Dbi: R/W
1368 …pported, Programmable through register space. This field will read 1, when bit 5 of ext_cap_ena fi…
1385 … (0x1<<6) // Atomic requester Enable. When this bit is set, function an…
1389 …ble, This field is writeable, when bit ido_supported bit of private device_capability_2 register i…
1391 …ble, This field is writeable, when bit ido_supported bit of private device_capability_2 register i…
1393 …ism Enable, This field is writeable, when bit 5 of ext_cap_ena field in private register space is …
1397 …ing method. This field is writeable, when bit 5 of ext_cap_ena field in private register space is …
1404 …pliance with PCIE spec 1.1. To enable this register, reset comply_pcie_1_1 bit in the register spa…
1411 … bit selects the level of de-emphasis. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap Value used by l…
1425 … (0x1<<17) // Equalization Complete - when set, this indic…
1427 … (0x1<<18) // Equalization Phase 1 Successful - when set, this indic…
1429 … (0x1<<19) // Equalization Phase 2 Successful - when set, this indic…
1431 … (0x1<<20) // Equalization Phase 3 Successful - when set, this indicates that Pha…
1433 …EQ_REQUEST_BB (0x1<<21) // This bit is set by hardware …
1451 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1453 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1455 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1518 …al Error Status. The core sets this bit when your application asserts app_err_bus[9]. It does n…
1597 …sk (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1603 …sk (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1605 … Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1686 …ty (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1692 …ty (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1694 … Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1751 …ATAL_ERR_STATUS_K2 (0x1<<13) // Advisory Non-Fatal Error Status.
1802 …ERR_MASK_K2 (0x1<<13) // Advisory Non-Fatal Error Mask. N…
1858 … (0x1f<<0) // First Error Pointer - These bits correspond to the bit posi…
1870 … (0xff<<0) // Byte 0 of Header log register of First 32 bit Data Word. Note: …
1872 … (0xff<<8) // Byte 1 of Header log register of First 32 bit Data Word. Note: …
1874 … (0xff<<16) // Byte 2 of Header log register of First 32 bit Data Word. Note: …
1876 … (0xff<<24) // Byte 3 of Header log register of First 32 bit D…
1881 … (0xff<<0) // Byte 0 of Header log register of Second 32 bit Data Word. Note: …
1883 … (0xff<<8) // Byte 1 of Header log register of Second 32 bit Data Word. Note: …
1885 … (0xff<<16) // Byte 2 of Header log register of Second 32 bit Data Word. Note: …
1887 … (0xff<<24) // Byte 3 of Header log register of Second 32 bit …
1892 … (0xff<<0) // Byte 0 of Header log register of Third 32 bit Data Word. Note: …
1894 … (0xff<<8) // Byte 1 of Header log register of Third 32 bit Data Word. Note: …
1896 … (0xff<<16) // Byte 2 of Header log register of Third 32 bit Data Word. Note: …
1898 … (0xff<<24) // Byte 3 of Header log register of Third 32 bit D…
1902 … 0x000128UL //Access:R DataWidth:0x20 // Header Log Register 3.
1903 … (0xff<<0) // Byte 0 of Header log register of Fourth 32 bit Data Word. Note: …
1905 … (0xff<<8) // Byte 1 of Header log register of Fourth 32 bit Data Word. Note: …
1907 … (0xff<<16) // Byte 2 of Header log register of Fourth 32 bit Data Word. Note: …
1909 … (0xff<<24) // Byte 3 of Header log register of Fourth 32 bit …
1923 …X_LOG_1_FOURTH_BYTE_K2 (0xff<<24) // Byte 3 of Error TLP Prefix …
1933 …X_LOG_2_FOURTH_BYTE_K2 (0xff<<24) // Byte 3 Error TLP Prefix Log…
1943 … 0x000140UL //Access:R DataWidth:0x20 // TLP Prefix Log Register 3.
1944 … (0xff<<0) // Byte 0 Error TLP Prefix Log 3. Note: This regist…
1946 … (0xff<<8) // Byte 1 Error TLP Prefix Log 3. Note: This regist…
1948 … (0xff<<16) // Byte 2 Error TLP Prefix Log 3. Note: This regist…
1950 …TH_BYTE_K2 (0xff<<24) // Byte 3 Error TLP Prefix Log 3. Note: …
1961 …X_LOG_4_FOURTH_BYTE_K2 (0xff<<24) // Byte 3 Error TLP Prefix Log…
1972 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1974 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1976 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1982 …nded VC Count. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1990 …on Capability. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1999 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
2021 …// Reject Snoop Transactions. Note: The access attributes of this field are as follows: - Dbi: R
2023 … (0x3f<<16) // Maximum Time Slots-1 supported. Note: The access attributes of this field ar…
2044 …C_MAP_VC0_K2 (0x1<<0) // Bit 0 of TC to VC Mappi…
2057 …bit when set indicates that the power budget for the device is included within the system power bu…
2077 … 0x000160UL //Access:R DataWidth:0x20 // The read-back value of this re…
2096 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2098 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2100 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2124 … 0x000174UL //Access:RW DataWidth:0x20 // The read-back value of this re…
2125 … (0x1<<0) // This bit is hardwired to one…
2127 … are mapped to the VC resource. This field is valid for all devices. Note: Bit 0 of this field is …
2131 … (0x1<<31) // Enables virtual channel. This bit is hardwired to 1 f…
2141 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2143 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2145 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2176 …taWidth:0x20 // The read-only value of this register is controlled by setting bit 0 of the EXT_C…
2201 … Allocated PB. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2203 …taWidth:0x20 // The read-only value of this register is controlled by setting bit 0 of the EXT_C…
2204 … (0xffff<<0) // VSEC ID. This field is a vendor-defined ID number tha…
2206 … (0xf<<16) // VSEC Rev. This field is a vendor-defined version numbe…
2208 …uding the PCI Express Enhanced Capability header, the Vendor-Specific header, and the Vendor-Speci…
2219 … (0xf<<16) // Lane 3 downstream port tran…
2221 … (0x7<<20) // Lane 3 downstream port rece…
2223 … (0xf<<24) // Lane 3 upstream port transm…
2225 … (0x7<<28) // Lane 3 upstream port receiv…
2228 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2230 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2232 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2234 … 0x000188UL //Access:RW DataWidth:0x20 // If bit 0 of the EXT_CAP_ENA for EP or bit 0 …
2235 …ment of the BAR0 for each VF. This field may only have 1 bit set.This field is ignored when bit 31…
2237 … (0x1<<31) // Enable VF Bar0 Stride. When this bit bit is clear, computa…
2288 …ment of the BAR2 for each VF. This field may only have 1 bit set.This field is ignored when bit 31…
2290 … (0x1<<31) // Enable VF Bar2 Stride. When this bit bit is clear, computa…
2328 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2330 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2332 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2335 …ment of the BAR4 for each VF. This field may only have 1 bit set.This field is ignored when bit 31…
2337 … (0x1<<31) // Enable VF Bar4 Stride. When this bit bit is clear, computa…
2356 … 0x00019cUL //Access:R DataWidth:0x20 // Link Control 3 Register.
2357 …0) // Perform Equalization. Note: The access attributes of this field are as follows: - Dbi: R/W
2359 …n Request Interrupt Enable. Note: The access attributes of this field are as follows: - Dbi: R/W
2382 …tter Preset 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2384 …Preset Hint 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2386 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2388 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2390 …tter Preset 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2392 …Preset Hint 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2394 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2396 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2405 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2406 …itter Preset2. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2408 … Preset Hint2. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2410 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2412 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2414 …itter Preset3. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2416 … Preset Hint3. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2418 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2420 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2423 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2424 …itter Preset4. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2426 … Preset Hint4. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2428 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2430 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2432 …itter Preset5. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2434 … Preset Hint5. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2436 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2438 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2441 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2442 …itter Preset6. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2444 … Preset Hint6. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2446 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2448 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2450 …itter Preset7. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2452 … Preset Hint7. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2454 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2456 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2458 …-only value of this register is controlled by setting bit 5 of the EXT_CAP_ENA for EP, By default,…
2468 … (0x1<<1) // Equalization 16.0 GT/s phase 3 successful.
2470 … (0x1<<2) // Equalization 16.0 GT/s phase 3 successful.
2472 … (0x1<<3) // Equalization 16.0 GT/s phase 3 suc…
2473 …CIEIP_REG_PCIEEP_PL16G_STATUS_EQ_CPL_P3_E5_SHIFT 3
2476 …DataWidth:0x20 // The RW value of this register is controlled by setting bit 5 of the EXT_CAP_EN…
2477 …g with Max snoop latency scale field, this register specifies the maximum no-snoop latency that a …
2483 …ith Max No snoop latency scale field, this register specifies the maximum no-snoop latency that a …
2490 … 0x0001b8UL //Access:RW DataWidth:0x20 // SR-IOV Capability Header…
2491 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2493 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2495 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2497 …1b8UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by sett…
2507 … 0x0001bcUL //Access:RW DataWidth:0x20 // SR-IOV Capability Regist…
2510 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2514 …DataWidth:0x20 // The RW value of this register is controlled by setting bit 6 of the EXT_CAP_EN…
2528 … 0x0001c0UL //Access:RW DataWidth:0x20 // SR-IOV Control and Statu…
2535 …_SRIOV_VF_MSE_K2 (0x1<<3) // VF Memory Space …
2536 …CIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MSE_K2_SHIFT 3
2537 …access attributes of this field are as follows: - Dbi: R/W but read-value is not always same as w…
2539 …1c0UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by sett…
2547 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
2549 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2571 … (0xf<<24) // Downstream port 16.0 GT/s transmitter preset 3.
2573 … (0xf<<28) // Upstream port 16.0 GT/s transmitter preset 3.
2575 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
2576 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: STATUS_CONTROL_…
2585 …_BB (0x1<<2) // This bit has no effect in IP…
2587 …SE_BB (0x1<<3) // When set, memory…
2588 …CIEIP_REG_SRIOV_CONTROL_VF_MSE_BB_SHIFT 3
2613 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register" det…
2615 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register". de…
2640 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2692 …-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derive…
2693 …bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualizatio…
2695 …3) // VF BAR0 Prefetchable. For a description of this standard PCIe register field, see the Single…
2696 …CIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_PREFETCH_K2_SHIFT 3
2697 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2703 …L_STAT0_MT_E5 (0x7<<3) // Margin type for …
2704 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT0_MT_E5_SHIFT 3
2717 …-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derive…
2718 …bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualizatio…
2720 …3) // VF BAR1 Prefetchable. For a description of this standard PCIe register field, see the Single…
2721 …CIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_PREFETCH_K2_SHIFT 3
2722 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2728 …L_STAT1_MT_E5 (0x7<<3) // Margin type for …
2729 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_MT_E5_SHIFT 3
2742 …-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derive…
2743 …bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualizatio…
2745 …3) // VF BAR2 Prefetchable. For a description of this standard PCIe register field, see the Single…
2746 …CIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_PREFETCH_K2_SHIFT 3
2747 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2749 …-bit VF_BAR0 register programs the base address for the memory space mapped by the VFs belonging t…
2750 … (0x1<<0) // This bit indicates that VF_B…
2752 …_BAR0 may be programmed to map this adapter to anywhere in the 64-bit address space. Bit can be pr…
2754 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR0 may be pre-fetched or cache…
2755 …CIEIP_REG_VF_BAR0_VF_PREFETCH_BB_SHIFT 3
2758 …ess within a 32-bit address space that device will respond in. These bits may be combined with the…
2763 …L_STAT2_MT_E5 (0x7<<3) // Margin type for …
2764 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT2_MT_E5_SHIFT 3
2777 …-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derive…
2778 …bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualizatio…
2780 …3) // VF BAR3 Prefetchable. For a description of this standard PCIe register field, see the Single…
2781 …CIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_PREFETCH_K2_SHIFT 3
2782 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2784 … 0x0001e8UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR1 register pr…
2788 …L_STAT3_MT_E5 (0x7<<3) // Margin type for …
2789 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_MT_E5_SHIFT 3
2802 …-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derive…
2803 …bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualizatio…
2805 …3) // VF BAR4 Prefetchable. For a description of this standard PCIe register field, see the Single…
2806 …CIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_PREFETCH_K2_SHIFT 3
2807 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2809 …-bit VF_BAR2 register programs the base address for the memory space mapped by the VFs belonging t…
2810 … (0x1<<0) // This bit indicates that VF_B…
2812 …e that VF_BAR2 may be programmed to map this adapter to anywhere in the 64-bit address space(reg 0…
2814 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR2 may be pre-fetched or cache…
2815 …CIEIP_REG_VF_BAR2_VF_PREFETCH_BB_SHIFT 3
2818 …ess within a 32-bit address space that device will respond in. These bits may be combined with the…
2823 …L_STAT4_MT_E5 (0x7<<3) // Margin type for …
2824 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT4_MT_E5_SHIFT 3
2837 …-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derive…
2838 …bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualizatio…
2840 …3) // VF BAR5 Prefetchable. For a description of this standard PCIe register field, see the Single…
2841 …CIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_PREFETCH_K2_SHIFT 3
2842 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2844 … 0x0001f0UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR3 register pr…
2848 …L_STAT5_MT_E5 (0x7<<3) // Margin type for …
2849 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT5_MT_E5_SHIFT 3
2865 …REG_SRIOV_VF_MIGRATION_STATE_OFFSET_K2 (0x1fffffff<<3) // VF Migration Sta…
2866 …CIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_SRIOV_VF_MIGRATION_STATE_OFFSET_K2_SHIFT 3
2867 …-bit VF_BAR4 register programs the base address for the memory space mapped by the VFs belonging t…
2868 … (0x1<<0) // This bit indicates that VF_B…
2870 …e that VF_BAR4 may be programmed to map this adapter to anywhere in the 64-bit address space(reg 0…
2872 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR4 may be pre-fetched or cache…
2873 …CIEIP_REG_VF_BAR4_VF_PREFETCH_BB_SHIFT 3
2876 …ess within a 32-bit address space that device will respond in. These bits may be combined with the…
2881 …L_STAT6_MT_E5 (0x7<<3) // Margin type for …
2882 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT6_MT_E5_SHIFT 3
2896 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2898 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2900 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2902 … 0x0001f8UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR5 register pr…
2906 …L_STAT7_MT_E5 (0x7<<3) // Margin type for …
2907 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT7_MT_E5_SHIFT 3
2920 …orm a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
2923 …ode Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2925 …ode Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2927 …ter Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2929 … (0x1<<9) // ST Table Location Bit 0. Note: The access attributes of this field are a…
2931 … (0x1<<10) // ST Table Location Bit 1. Note: The access attributes of this field are a…
2933 …ST Table Size. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2938 …L_STAT8_MT_E5 (0x7<<3) // Margin type for …
2939 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT8_MT_E5_SHIFT 3
2953 …(0x7<<0) // ST Mode Select. Note: The access attributes of this field are as follows: - Dbi: R/W
2955 …H_REQ_CTRL_REQ_EN_K2 (0x3<<8) // TPH Requester Enable Bit.
2957 …-only value of this register is controlled by setting bit 0 of the EXT3_CAP_ENA for EP, The capabi…
2967 …L_STAT9_MT_E5 (0x7<<3) // Margin type for …
2968 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT9_MT_E5_SHIFT 3
2982 … 0 Lower Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
2984 … 0 Upper Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
2986 …DataWidth:0x20 // The RW value of this register is controlled by setting bit 0 of the EXT3_CAP_E…
2992 …L_STAT10_MT_E5 (0x7<<3) // Margin type for …
2993 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_MT_E5_SHIFT 3
3006 …DataWidth:0x20 // The RW value of this register is controlled by setting bit 0 of the EXT3_CAP_E…
3018 …L_STAT11_MT_E5 (0x7<<3) // Margin type for …
3019 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT11_MT_E5_SHIFT 3
3035 …L_STAT12_MT_E5 (0x7<<3) // Margin type for …
3036 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_MT_E5_SHIFT 3
3049 …210UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by sett…
3059 …L_STAT13_MT_E5 (0x7<<3) // Margin type for …
3060 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_MT_E5_SHIFT 3
3076 …EQ_BB (0x1<<5) // This bit when set indicates …
3089 …L_STAT14_MT_E5 (0x7<<3) // Margin type for …
3090 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT14_MT_E5_SHIFT 3
3106 …L_STAT15_MT_E5 (0x7<<3) // Margin type for …
3107 …CIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT15_MT_E5_SHIFT 3
3127 …220UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by sett…
3139 … (0x1<<2) // VF 10-bit tag requester suppo…
3146 …l operate with Bar sized to 1M. Value reflected here is from corresponding bit in private register.
3148 …l operate with Bar sized to 2M. Value reflected here is from corresponding bit in private register.
3150 …l operate with Bar sized to 4M. Value reflected here is from corresponding bit in private register.
3152 …l operate with Bar sized to 8M. Value reflected here is from corresponding bit in private register.
3154 … operate with Bar sized to 16M. Value reflected here is from corresponding bit in private register.
3156 … operate with Bar sized to 32M. Value reflected here is from corresponding bit in private register.
3158 … operate with Bar sized to 64M. Value reflected here is from corresponding bit in private register.
3160 …operate with Bar sized to 128M. Value reflected here is from corresponding bit in private register.
3162 …operate with Bar sized to 256M. Value reflected here is from corresponding bit in private register.
3164 …operate with Bar sized to 512M. Value reflected here is from corresponding bit in private register.
3166 …l operate with Bar sized to 1G. Value reflected here is from corresponding bit in private register.
3177 …RIOV_CTL_MSE_E5 (0x1<<3) // VF MSE.
3178 …CIEIP_REG_PCIEEP_SRIOV_CTL_MSE_E5_SHIFT 3
3179 … (0x1<<4) // ARI capable hierarchy. 0 = All PFs have non-ARI capable hierarchy…
3181 … (0x1<<5) // VF 10-bit Tag Requester Enabl…
3188 …RL_RSVD_BB (0x3<<3) // Unused
3189 …CIEIP_REG_RBAR_CTRL_RSVD_BB_SHIFT 3
3197 … (0xffff<<16) // Total VFs. Read-only copy of PCIEEP_S…
3204 …-only value of this register is controlled by setting bit 0 of the EXT2_CAP_ENA for EP, By default…
3212 …-ARI capable hierarchies. The PCIEEP_SRIOV_CTL[ACH] determines which one is being used for SR-IOV…
3214 …-ARI: 0x1. There are two VF stride registers; one for each ARI capable and non-ARI capable…
3216 …DataWidth:0x20 // The RW value of this register is controlled by setting bit 0 of the EXT2_CAP_E…
3223 …H_REQ_CAPABILITY_UNUSED0_BB (0x1f<<3) //
3224 …CIEIP_REG_TPH_REQ_CAPABILITY_UNUSED0_BB_SHIFT 3
3231 …ware reads this field to determine the STTable Size N, whihc is encoded as N-1. So a returned valu…
3236 …DataWidth:0x20 // The RW value of this register is controlled by setting bit 0 of the EXT2_CAP_E…
3239 …H_REQ_CONTROL_UNUSED0_BB (0x1f<<3) //
3240 …CIEIP_REG_TPH_REQ_CONTROL_UNUSED0_BB_SHIFT 3
3245 …-only value of this register is controlled by setting bit 2 of the EXT2_CAP_ENA for EP, By default…
3255 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR.
3257 …AR0L_PF_E5 (0x1<<3) // Prefetchable.
3258 …CIEIP_REG_PCIEEP_SRIOV_BAR0L_PF_E5_SHIFT 3
3268 …SPM_L1_1_SUPP_BB (0x1<<3) // Advertize L1_1 c…
3269 …CIEIP_REG_PML1_SUB_CAP_REG_ASPM_L1_1_SUPP_BB_SHIFT 3
3274 … (0xff<<8) // Time in us that device advertizes that it requires to re-establish common mode.
3292 …ASPM_L1_1_ENABLE_BB (0x1<<3) // When set, ASPM L…
3293 …CIEIP_REG_PML1_SUB_CONTROL1_ASPM_L1_1_ENABLE_BB_SHIFT 3
3307 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR.
3309 …AR2L_PF_E5 (0x1<<3) // Prefetchable.
3310 …CIEIP_REG_PCIEEP_SRIOV_BAR2L_PF_E5_SHIFT 3
3318 …_POWER_ON_VALUE_BB (0x1f<<3) // This field along…
3319 …CIEIP_REG_PML1_SUB_CONTROL2_T_POWER_ON_VALUE_BB_SHIFT 3
3324 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR.
3326 …AR4L_PF_E5 (0x1<<3) // Prefetchable.
3327 …CIEIP_REG_PCIEEP_SRIOV_BAR4L_PF_E5_SHIFT 3
3334 … (0x1fffffff<<3) // VF migration sta…
3335 …CIEIP_REG_PCIEEP_SRIOV_MS_MSO_E5_SHIFT 3
3352 … (0x1<<9) // Steering tag table bit 0.
3354 … (0x1<<10) // Steering tag table bit 1.
3356 … (0x7ff<<16) // ST table size (limited by MSI-X table size).
3369 …d Capacity ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3371 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3373 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3375 … 0x000288UL //Access:RW DataWidth:0x20 // LTR Max Snoop and No-Snoop Latency Registe…
3380 …T_K2 (0x3ff<<16) // Max No-Snoop Latency Value.
3382 …LAT_SCALE_K2 (0x7<<26) // Max No-Snoop Latency Scale.
3384 … 0x00028cUL //Access:RW DataWidth:0x20 // Vendor-Specific Extended Cap…
3385 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3387 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3389 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3391 … 0x000290UL //Access:R DataWidth:0x20 // Vendor-Specific Header.
3398 …- Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register det…
3399 …ear' code. The read value is always '0'. - 00: no change - 01: per clear - 10: no change - 11:…
3401 …ays '0'. - 000: no change - 001: per event off - 010: no change - 011: per event on - 100: no…
3403 …alue of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT…
3405 …a returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - ..…
3407 …- 27-24: Group number(4-bit: 0..0x7) - 23-16: Event number(8-bit: 0..0x13) within the Group For e…
3409 …s the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTRO…
3410 …idth:0x20 // Time-based Analysis Control. Used for controlling the measurement of RX/TX data thr…
3411 … (0x1<<0) // Timer Start. - 0: Start/Restart - 1: Stop This bit wi…
3413 …-based Duration Select. Selects the duration of time-based analysis. When "manual control" is sele…
3415 …-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_…
3417 …ataWidth:0x20 // Time-based Analysis Data. Contains the measurement results of RX/TX data throug…
3418 …bit in this register. The specific injection controls for each type of error are defined in the fo…
3425 …ROR_INJECTION3_ENABLE_K2 (0x1<<3) // Error Injection3…
3426 …CIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_K2_SHIFT 3
3431 …an set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = C…
3433 …- LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP; Data Link …
3434 …have been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE…
3436 …- 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b:…
3438 …- ((NEXT_TRANSMIT_SEQ -1) - AckNak_Seq_Num) mod 4096 > 2048 - (AckNak_Seq_Num - ACKD_SEQ) mod 409…
3439 …re being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION1_ENABLE …
3441 …nce number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - …
3443 …-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. …
3445 …- If "ACK/NAK DLLP's transmission block" is selected, replay timeout error will occur at the trans…
3446 … being inserted. - If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABL…
3448 … inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block …
3450 …3 (Symbol Error). When 8b/10b encoding is used, this register controls error insertion into the sp…
3451 …re being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE …
3453 …- Mask K symbol. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b: COM/PAD(TS2 Order set)…
3455 … - Posted TLP Header credit - Non-Posted TLP Header credit - Completion TLP Header credit - Po…
3456 …re being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION4_ENABLE …
3458 …-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Po…
3462 …-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is repr…
3464 …- For Duplicate TLP, the core initiates Data Link Retry by handling ACK DLLP as NAK DLLP. These TL…
3465 …re being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION5_ENABLE …
3467 …Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as N…
3471 …on Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP heade…
3472 … DataWidth:0x20 // Error Injection Control 6 (Compare Point Header DWORD #3). Program this regis…
3489 …_CR_E5 (0x1<<3) // ACS P2P completi…
3490 …CIEIP_REG_PCIEEP_ACS_CAP_CTL_CR_E5_SHIFT 3
3513 …on Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP heade…
3517 …L_VEC_UNUSED_E5 (0x1fffffff<<3) // Reserved.
3518 …CIEIP_REG_PCIEEP_ACS_EGR_CTL_VEC_UNUSED_E5_SHIFT 3
3519 … DataWidth:0x20 // Error Injection Control 6 (Compare Value Header DWORD #3). Program this regis…
3533 … (0x3ff<<16) // Max no-snoop latency value.
3535 … (0x7<<26) // Max no-snoop latency scale.
3545 …ion Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP heade…
3546 …-only value of this register is controlled by setting bit 1 of the EXT2_CAP_ENA for EP, The capabi…
3554 …PCIPM_SUP_E5 (0x1<<0) // PCI-PM L12 supported.
3556 …PCIPM_SUP_E5 (0x1<<1) // PCI-PM L11 supported.
3560 …1_1_ASPM_SUP_E5 (0x1<<3) // ASPM L11 support…
3561 …CIEIP_REG_PCIEEP_L1SUB_CAP_L1_1_ASPM_SUP_E5_SHIFT 3
3570 … DataWidth:0x20 // Error Injection Control 6 (Change Point Header DWORD #3). Program this regis…
3571 …DataWidth:0x20 // The RW value of this register is controlled by setting bit 1 of the EXT2_CAP_E…
3577 …1_2_PCIPM_EN_E5 (0x1<<0) // PCI-PM L12 enable.
3579 …1_1_PCIPM_EN_E5 (0x1<<1) // PCI-PM L11 enable.
3583 …_L1_1_ASPM_EN_E5 (0x1<<3) // ASPM L11 enable.
3584 …CIEIP_REG_PCIEEP_L1SUB_CTL1_L1_1_ASPM_EN_E5_SHIFT 3
3589 …s. 0x2 = 1024 ns. 0x3 = 32,768 ns. 0x4 = 1,048,575 ns. 0x5 = 33,554,432 ns. 0x6-7 = Reserved.
3593 …_BITS_BB (0xffff<<0) // Each bit indicates if corres…
3598 …_PWR_ON_VAL_E5 (0x1f<<3) // T power on value…
3599 …CIEIP_REG_PCIEEP_L1SUB_CTL2_T_PWR_ON_VAL_E5_SHIFT 3
3625 …ion Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP heade…
3656 … DataWidth:0x20 // Error Injection Control 6 (Change Value Header DWORD #3). Program this regis…
3681 …e following conditions are true. - Using 128b/130b encoding - Injecting errors into TLP Length f…
3682 …are been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION6_ENABLE …
3684 …- 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2…
3686 …e TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Pref…
3736 …ter data returned in the PCIEEP_RAS_EC_DATA[EV_CNTR_DATA]. 0x0-0x7 = Lane number. 0x8-0xF = Res…
3776 … (0x1<<0) // Timer start. 0x0 = Start/restart. 0x1 = Stop. This bit will be cleared aut…
3778 …-based duration select. Selects the duration of time-based analysis. 0x0 = Manual control. Ana…
3780 …EL_E5 (0xff<<24) // Time-based report select. …
3801 …uring LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. -…
3803 … (0x1<<16) // Force Detect Lane Enable. When this bit is set, the core ig…
3805 …-reset exit. The core selects the greater value between this register and the value defined by the…
3807 …m receiving EIOS to, RXELECIDLE assertion at the PHY. - 0x0: 40ns - 0x1: 160ns - 0x2: 320ns - …
3812 … When this bit is set to '1' in L0 or L0s, the LTSSM starts transitioning to Recovery State. This …
3814 … (0x1<<2) // Force LinkDown. When this bit is set and the core…
3816 … (0x1<<8) // Direct Recovery.Idle to Configuration. When this bit is set and the LTSS…
3818 … (0x1<<9) // Direct Polling.Compliance to Detect. When this bit is set and the LTSS…
3820 … (0x1<<10) // Detect Loopback Slave To Exit. When this bit is set and the LTSS…
3822 … (0x1<<16) // Framing Error Recovery Disable. This bit forces a transition…
3824 … // Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the…
3825 …er for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 …
3840 …- 01h: When non- STP/SDP/IDL Token was received and it was not in TLP/DLLP reception - 02h: When …
3848 …-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negoti…
3851 …- 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDL…
3853 …- 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 08h: L1 - 09h: L1_BLOCK_…
3855 …-send flag. When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host softwar…
3866 …_EINJ3_EN_E5 (0x1<<3) // Symbol datak mas…
3867 …CIEIP_REG_PCIEEP_RAS_EINJ_EN_EINJ3_EN_E5_SHIFT 3
3879 … (0x3<<24) // DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 1…
3888 …-FC DLLP. 0x3 = New TLP's ECRC error injection. 0x4 = TLP's FCRC error injection (128b/130b). 0…
3890 …LP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL…
3891 …ort-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data …
3893 …3) // Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_TL…
3894 …CIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_K2_SHIFT 3
3895 …iewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 d…
3897 …TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_D…
3899 …TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value …
3901 …YPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value …
3908 …-assigned sequence numbers. This value is represented by two's complement. 0x0FFF = +4095. 0x0…
3911 …- 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: T…
3923 …ng - Mask K symbol. 0x0 = Reserved. 0x1 = COM/PAD(TS1 Order Set). 0x2 = COM/PAD(TS2 Order Set)…
3928 …-FC type. Selects the credit type. 0x0 = Posted TLP header credit value control. 0x1 = Non-Pos…
3932 …-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. The value is rep…
3934 … fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ…
3935 …-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] view…
3937 …the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/…
3939 …al Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11:…
3951 … (0x3f<<0) // Force Local Transmitter Pre-cursor. Indicates th…
3955 … (0x3f<<12) // Force Local Transmitter Post-Cursor. Indicates th…
3961 …fficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CUR…
3968 … 0x000364UL //Access:RW DataWidth:0x20 // Silicon Debug EQ Control 3. This viewport regis…
3969 … (0x3f<<0) // Force Remote Transmitter Pre-Cursor. Indicates th…
3973 … (0x3f<<12) // Force Remote Transmitter Post-Cursor. Indicates th…
3975 …ficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CU…
3979 …ed unsuccessfully(EQ_CONVERGENCE_INFO=2). - EQ_RULEA_VIOLATION - EQ_RULEB_VIOLATION - EQ_RULEC_…
3982 … - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalizat…
3984 …ge method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cl…
3986 …ge method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cl…
3988 …ge method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cl…
3990 …/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cl…
3994 …_K2 (0x3f<<0) // EQ Local Pre-Cursor. Indicates Lo…
3998 …K2 (0x3f<<12) // EQ Local Post-Cursor. Indicates Lo…
4005 … 0x000374UL //Access:R DataWidth:0x20 // Silicon Debug EQ Status 3. This viewport regis…
4006 …_K2 (0x3f<<0) // EQ Remote Pre-Cursor. Indicates Re…
4010 …K2 (0x3f<<12) // EQ Remote Post-Cursor. Indicates Re…
4023 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4025 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4027 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4039 …r all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. N…
4045 …TRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_K2 (0x1<<3) // Error correction…
4046 …CIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_K2_SHIFT 3
4049 … (0x1<<5) // Error correction disable for layer 3 Tx path. Note: This…
4055 …letion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. N…
4063 … (0x1<<21) // Error correction disable for layer 3 Rx path. Note: This…
4068 … 0x000398UL //Access:RW DataWidth:0x20 // Corrected error (1-bit ECC) counter select…
4071 …) // Enable correctable errors counters. - 1: counters increment when the core detects a correcta…
4073 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4078 … 0x00039cUL //Access:R DataWidth:0x20 // Corrected error (1-bit ECC) counter data. …
4081 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4086 … 0x0003a0UL //Access:RW DataWidth:0x20 // Uncorrected error (2-bit ECC and parity) cou…
4089 … Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correct…
4091 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4098 …3] is used to replace bits specified by EINJ6_CHG_PT_H[0/1/2/3]. 0x1 = EINJ6_CHG_VAL_H[0/1/2/3] i…
4100 …ors into. 0x0 = TLP header. 0x1 = TLP prefix 1st 4-DWORDs. 0x2 = TLP prefix 2nd 4-DWORDs. 0x3…
4102 … 0x0003a4UL //Access:R DataWidth:0x20 // Uncorrected error (2-bit ECC and parity) cou…
4105 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4109 …he following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection mod…
4112 … (0x3<<4) // Error injection type: - 0: none - 1: 1-bit - 2: 2-bit
4114 … (0xff<<8) // Error injection count. - 0: errors are inserted in every TLP until you clear ERR…
4119 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4123 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4128 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4132 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4136 …_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are for…
4144 … (0x1<<16) // Force detect lane enable. When this bit is set, the core ig…
4146 …-reset exit. The core selects the greater value between this register and the value defined by the…
4148 …ing EIOS to, RXELECIDLE assertion at the PHY 0x0 = 40ns. 0x1 = 160ns. 0x2 = 320ns. 0x3 - 640ns.
4156 …his bit is set in L0 or L0s, the LTSSM starts transitioning to recovery state. This request does n…
4158 … (0x1<<2) // Force link down. When this bit is set and the core…
4160 … (0x1<<8) // Direct Recovery.Idle to configuration. When this bit is set and the LTSS…
4162 … (0x1<<9) // Direct Polling.Compliance to detect. When this bit is set and the LTSS…
4166 … (0x1<<16) // Framing error recovery disable. This bit disables a transiti…
4168 …L //Access:R DataWidth:0x20 // RAM Address where a corrected error (1-bit ECC) has been detec…
4169 … (0x7ffffff<<0) // RAM Address where a corrected error (1-bit ECC) has been detec…
4171 … (0xf<<28) // RAM index where a corrected error (1-bit ECC) has been detec…
4173 …/Access:R DataWidth:0x20 // RAM Address where an uncorrected error (2-bit ECC) has been detec…
4174 … (0x7ffffff<<0) // RAM Address where an uncorrected error (2-bit ECC) has been detec…
4176 … (0xf<<28) // RAM index where an uncorrected error (2-bit ECC) has been detec…
4179 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4181 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4183 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4186 … silicon debug status register of Layer1-PerLane. 0x0 = Lane0. 0x1 = Lane1. 0x2 = Lane2. 0x7 …
4201 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4203 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4205 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4207 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4210 …-STP/SDP/IDL token was received and it was not in TLP/DLLP reception. 0x02 = When current token w…
4218 …ualization_done_8GT_data_rate. 0x7 = equalization_done_16GT_data_rate. 0x8-0xF = idle_to_rlock_t…
4223 …s Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: HWINIT
4225 …s Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: HWINIT
4228 … 0x17 = L0S_BLOCK_TLP. 0x18 = WAIT_LAST_PMDLLP. 0x19 = WAIT_DSTATE_UPDATE. 0x20-0x1F = Reserved.
4230 …S_L23RDY_WAIT4ALIVE. 0x0F = S_L23RDY_WAIT4IDLE. 0x10 = S_WAIT_LAST_PMDLLP. 0x10-0x1F = Reserved.
4232 … sets PME_Status bit. If host software does not clear PME_Status bit for 100ms (+50%/-5%), the DUT…
4239 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4241 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4243 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4257 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4259 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4261 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4264 …CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields determi…
4266 …(0x1<<3) // Credit select (credit type). This field in conjunction with the [CREDIT_SEL_VC], [CRE…
4267 …CIEIP_REG_PCIEEP_RAS_SD_STATUSL3FC_CREDIT_SEL_CREDIT_TYPE_E5_SHIFT 3
4268 …] viewport-select fields determines that data that is returned by the [CREDIT_DATA0] and [CREDIT_D…
4270 …CREDIT_SEL_VC], [CREDIT_SEL_CREDIT_TYPE], and [CREDIT_SEL_TLP_TYPE] viewport-select fields determi…
4272 …CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields. RX = …
4274 …CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields. RX = …
4277 … (0x1<<0) // PTM Requester Auto Update Enabled - When enabled PTM Req…
4279 …) // PTM Requester Start Update - When set the PTM Requester will attempt a PTM Dialogue to update…
4281 …K2 (0x1<<2) // PTM Fast Timers - Debug mode for PTM T…
4283 … (0xff<<8) // PTM Requester Long Timer - Determines the perio…
4286 …bit in message TLP. 0x09 = Unexpected CRS status in completion TLP. 0x0A = Byte enable. 0x0B = …
4291 … (0x1<<0) // PTM Requester Context Valid - Indicate that the Ti…
4293 … (0x1<<1) // PTM Requester Manual Update Allowed - Indicates whether or…
4298 …-lane silicon debug EQ status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] view…
4300 …Q_LANE_SEL] determines the per-lane silicon debug EQ status data returned by the SD_EQ_CONTROL[2/3…
4302 …3 timeout. This field is used when the ltssm is in Recovery.EQ2/3. When this field is set, the v…
4330 … (0x3f<<0) // Force remote transmitter pre-cursor as selected by…
4343 …fully. 0x2 = Equalization finished unsuccessfully. 0x3 = Reserved. This bit is automatically cl…
4345 …for Transmitter Coefficients" in the PCI Express Base Specification. This bit is automatically cl…
4347 …for Transmitter Coefficients" in the PCI Express Base Specification. This bit is automatically cl…
4349 …for Transmitter Coefficients" in the PCI Express Base Specification. This bit is automatically cl…
4351 …Reject=1b during EQ master phase (DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cl…
4383 …bit enables the advertisement of bar_1 as a 32-bit address. The value of this bit maps directly to…
4385 …bit will force the PCI bus to re-try all cycles to the current Expansion ROM BAR area. When this b…
4387 …bit will force the PCI bus to re-try all cycles to the configuration space until it is cleared. Th…
4389 … (0x1<<7) // This bit will be set the fir…
4391 …en this value is non-zero, the Expansion ROM attention must be handled by an internal processor to…
4393 … (0x1<<16) // This bit when set is reflected in bit 3 of bar_1 and indicates tha…
4399 …t by HARD Reset such that it can be used to detect initial power up if a non-zero value is written…
4403 …bit to '1' forces the VF to drop any mem request that it receives. UR completion will be returned …
4407 … (0x1<<24) // Setting this bit to '1' forces the P…
4409 … (0x1<<25) // This bit indicates the current state of the PME_STATU…
4411 … (0x1<<26) // This is the current state of the PME_ENABLE bit in configuration sp…
4417 … (0x1<<30) // This bit indicates the input…
4419 …OWER This bit indicates the current state of power on the PCI bus. If this bit is '1', it indicate…
4429 …from the pm_data register when the DATA_SEL value in the PM_CSR register is 3. This is the power c…
4472 … (0xfff<<0) // PTM Requester TX Latency - Requester Transmit path latency (12 bit …
4481 …L_EP_DIS_DMA_WR_E5 (0x1<<3) // Error correction…
4482 …CIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_DMA_WR_E5_SHIFT 3
4485 … (0x1<<5) // Error correction disable for layer 3 TX path.
4499 … (0x1<<21) // Error correction disable for layer 3 RX path.
4504 … (0xfff<<0) // PTM Requester RX Latency - Requester Receive path latency (12 bit w…
4511 …3 RX path. 0x2 = Layer 2 RX path. 0x3 = DMA read engine inbound (not supported). 0x4 = AXI brid…
4516 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4518 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4520 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4525 …3 RX path. 0x2 = Layer 2 RX path. 0x3 = DMA inbound path (not supported). 0x4 = AXI bridge inbo…
4530 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4532 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4534 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4536 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4538 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4540 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4542 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4544 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4546 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4548 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4550 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4552 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4554 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4556 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4558 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4560 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4562 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4564 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4566 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4568 …BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4571 …bit will be set if there is a pending request for action by the firmware to handle a Vital Product…
4578 …3 RX path. 0x2 = Layer 2 RX path. 0x3 = DMA inbound path (not supported). 0x4 = AXI bridge inbo…
4587 …) // BAR Size. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4594 …bit indicates if the host is requesting a read or a write cycle. If this bit is set, then the host…
4599 …3 RX path. 0x2 = Layer 2 RX path. 0x3 = DMA inbound path (not supported). 0x4 = AXI bridge inbo…
4603 …bit is clear, this word should be written with the NVM data requested in the ADDRESS value to clea…
4607 … (0x3<<4) // Error injection type. 0x0 = None. 0x1 = 1-bit. 0x2 = 2-bit. 0x3 = Rese…
4609 … 0x0 = errors are injected in every TLP until [ERR_INJ_EN] is cleared. 0x1 - 0xFF = number of err…
4619 …3 RX path. 0x2 = Layer 2 RX path. 0x3 = DMA read engine (not supported). 0x4 = AXI bridge inbou…
4623 …3 RX path. 0x2 = Layer 2 RX path. 0x3 = DMA inbound path (not supported). 0x4 = AXI bridge inbo…
4633 …3 RX path. 0x2 = Layer 2 RX path. 0x3 = DMA inbound path (not supported). 0x4 = AXI bridge inbo…
4637 …3 RX path. 0x2 = Layer 2 RX path. 0x3 = DMA inbound path (not supported). 0x4 = AXI bridge inbo…
4642 …e read value of the class_code register of the configuration space. The 24-bit Class Code register…
4647 … (0x1<<0) // Set this bit to enable the core …
4649 …E5 (0x1<<1) // Set this bit to enable the core …
4652 …E capability is always enabled. Bit 0 enables the Power Management capability. Bit 1 enables the V…
4664 … (0x1<<15) // This bit indicates the programming of the MSI Enable bit in PCI configur…
4669 … (0x1<<0) // Set this bit to take the core ou…
4672 … (0x1<<0) // This bit indicates whether the device supports the D1 power management state. It i…
4674 … (0x1<<1) // This bit indicates whether the device supports the D2 power management state. It i…
4676 …<<2) // This bit indicates whether the device supports transmiting PME message from the D0 power s…
4678 … (0x1<<3) // This bit indicates whether the device supports transmiting PME message from the D1 po…
4679 …CIEIP_REG_REG_ID_VAL5_PME_IN_D1_BB_SHIFT 3
4680 …<<4) // This bit indicates whether the device supports transmiting PME message from the D2 power s…
4682 … // This bit indicates whether the device supports transmiting PME message from the D3hot power st…
4724 … (0x7fffff<<0) // Only bit 0 is currently defined - remote …
4730 …taWidth:0x20 // This register reflects the lower half of the MSI address bit[31:2] value in the …
4762 … 0x000468UL //Access:RW DataWidth:0x20 // Each pending bit that is set , the f…
4778 …the PTM Requester will attempt a PTM Dialogue to update it's context; This bit is self clearing. F…
4818 …orted resource sizes. PEM advertises the maximum allowable BAR size (512 GB - 0xF_FFFF) when the f…
4835 …ters located at 10h in configuration space is used to map the function's MSI-X table into memory s…
4837 …3) // This register controls the read value of the MSIX_TBL_OFF_BIR[31:3] register. This is used a…
4838 …CIEIP_REG_REG_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF_BB_SHIFT 3
4847 …ters located at 10h in configuration space is used to map the function's MSI-X PBA into memory spa…
4849 …3) // This register controls the read value of the MSIX_PBA_OFF_BIR[31:3] register. This is used a…
4850 …CIEIP_REG_REG_MSIX_PBA_OFF_BIR_MSIX_PBA_OFF_BB_SHIFT 3
4859 …-zero values indicate some software-defined post-firmware loaded state information or failure code…
4864 …E_1_1_BB (0x1<<5) // This bit when set, hides any…
4866 … (0x1<<6) // This bit when set, sets the ASPM optionality bit in the Link cap r…
4871 …EG_DEVICE_CAPABILITY_UNUSED0_BB (0x3<<3) //
4872 …CIEIP_REG_REG_DEVICE_CAPABILITY_UNUSED0_BB_SHIFT 3
4890 …also be cleared automatically after 55 ms if auto_clear bit in private reg space is set. This bit …
4894 …e VFs that belong to this PF should be flushed. Software should clear this bit within 1 second of …
4918 …bit enables the advertisement of bar_3 as a 32-bit address. The value of this bit maps directly to…
4920 … (0x1<<5) // This bit when set is reflected in bit 3 of bar_3 and indicates tha…
4925 … Timeout Ranges Supported. Controls value in same field in the config space 0xF- Ranges A,B,C and D
4931 … (0x1<<10) // This bit is valid only if IDO_Enabled is defined in version.v.…
4935 … this value to 2 or 3(also supported using Messages) This bit is valid only if PCIE_OBFF_SUPP is d…
4944 … (0x1<<0) // RC only. If set, indicates dl_active capability at bit 20 of link_capabili…
4951 … (0x1<<4) // This bit enables the advertisement of bar_5 as a 32-bit address. The value of …
4953 … (0x1<<5) // This bit when set is reflected in bit 3 of bar_5 and indicates tha…
4964 …2_CAP_ENA_BB (0x1f<<3) // If it is set, in…
4965 …CIEIP_REG_REG_ROOT_CAP_RC_EXT2_CAP_ENA_BB_SHIFT 3
4983 … (0x1<<0) // This value controls the corresponding bit in the ADV_ERR_CAP …
4985 … (0x1<<1) // This value controls the corresponding bit in the ADV_ERR_CAP …
5003 …_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 3. This value is stick…
5030 … register. The next set of capabilities are defined in etx2_cap_ena in bits 3:0 of this register. …
5046 …_L1_1_SUPP_BB (0x1<<3) // Advertize L1_1 c…
5047 …CIEIP_REG_REG_L1SUB_CAP_ASPM_L1_1_SUPP_BB_SHIFT 3
5052 … (0xff<<8) // Time in us that device advertizes that it requires to re-establish common mode.
5068 … (0x1<<0) // This bit controls the system alloc bit in t…
5084 … (0x1<<7) // Enable User Defined Mem area in RC mode. If this bit is set, then memory…
5096 … (0x1<<7) // Enable User Defined Mem area in RC mode. If this bit is set, then memory…
5116 … is not present, or a value of 2, which indicates ST table is located in MSI-X Table structure. Al…
5163 … (0x1<<4) // This bit enables the advertisement of VF BAR0 as a 64-bit address. The value of…
5165 … (0x1<<5) // This bit when set is reflected in bit 3 of VF BAR0 and indicates th…
5171 … (0x1<<12) // This bit enables the advertisement of VF BAR2 as a 64-bit address. The value of…
5173 … (0x1<<13) // This bit when set is reflected in bit 3 of VF BAR2 and indicates th…
5183 …and 4MB page sizes. This PF supports a page size of 2^n+12 if bit n is set. For eg, if bit 0 is se…
5185 …each enable combination is shown below. PCIE capability is always enabled. Bit 0 enables the MSIX …
5192 …bility structure of PF configuration space is used to map the function's MSI-X table into memory s…
5194 …3) // This register controls the read value of the MSIX_TBL_OFF_BIR[31:3] register in the VF cfg s…
5195 …CIEIP_REG_REG_VF_MSIX_TBL_BIR_OFF_VF_MSIX_TBL_BIR_OFF_BB_SHIFT 3
5197 …on space is used to map the VF's's MSI-X PBA into memory space. All the VF's that belong to the PF…
5199 …3) // This register controls the read value of the MSIX_PBA_OFF_BIR[31:3] registern the VF Cfg spa…
5200 …CIEIP_REG_REG_VF_MSIX_PBA_OFF_BIT_VF_MSIX_PBA_OFF_BB_SHIFT 3
5209 … (0x1<<4) // This bit enables the advertisement of VF BAR4 as a 64-bit address. The value of…
5211 … (0x1<<5) // This bit when set is reflected in bit 3 of VF BAR4 and indicates th…
5226 …ates the Untranslated Address always aligns to a 4K byte boundary. Setting this bit is recommended.
5235 … is not present, or a value of 2, which indicates ST table is located in MSI-X Table structure. Al…
5249 …3-7, 3-8, and 3-9 of the PCIe 3.0 specification. The limit must reflect the round trip latency fro…
5251 …3-4, 3-5, and 3-6 of the PCIe 3.0 specification. If there is a change in the payload size or link …
5262 …) // Link state. The link state that the PCI Express bus is forced to when bit 15 (force link) is …
5267 … (0xff<<0) // Link Number. Not used for endpoint. Not used for M-PCIe. Note: This reg…
5269 …The link command that the core is forced to transmit when you set FORCE_EN bit (Force Link). Link …
5271 …bit triggers the following actions: - Forces the LTSSM to the state specified by the Forced LTSSM…
5273 …tate. The LTSSM state that the core is forced to when you set the FORCE_EN bit (Force Link). LTSSM…
5275 …many clock cycles for the associated completion of a CfgWr to D-state register to go low-power. Th…
5284 …L0s entrance latency. Values correspond to: 0x0 = 1 ms. 0x1 = 2 ms. 0x2 = 3 ms. 0x3 = 4 ms. 0x…
5290 … 0x00070cUL //Access:RW DataWidth:0x20 // Ack Frequency and L0-L1 ASPM Control Regis…
5291 …- 0: Indicates that this Ack frequency control feature is turned off. The core schedules a low-pri…
5293 …-sets that a component can request is 255. The core does not support a value of zero; a value of z…
5295 …-sets that a component can request is 255. This field is only writable (sticky) when all of the fo…
5297 … - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us…
5299 … Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 …
5301 … (0x1<<30) // ASPM L1 Entry Control. - 1: Core enters ASPM L1 after a period in which it has …
5304 … (0x1<<0) // Other message request. When software writes a one to this bit, the PCI Express bu…
5306 … (0x1<<1) // Scramble disable. Setting this bit turns off data scra…
5308 …itiate loopback mode as a master. On a 0->1 transition, the PCIe core sends TS ordered sets with t…
5310 …_E5 (0x1<<3) // Reset assert. Tr…
5311 …CIEIP_REG_PCIEEP_PORT_CTL_RA_E5_SHIFT 3
5318 …EPROM load, the first word loaded is 0xFFFFFFFF, the EEPROM load is terminated and this bit is set.
5335 … a '1' to this bit, the core transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_…
5339 …-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during C…
5341 …_RESET_ASSERT_K2 (0x1<<3) // Reset Assert. Tr…
5342 …CIEIP_REG_PORT_LINK_CTRL_OFF_RESET_ASSERT_K2_SHIFT 3
5347 …-outs and to link up faster. The scaling factor is selected in FAST_LINK_SCALING_FACTOR(default : …
5351 …". - 000001: x1 - 000011: x2 - 000111: x4 - 001111: x8 - 011111: x16 - 111111: x32 (not supp…
5370 … (0xf<<27) // Set the implementation-specific number of la…
5372 … (0x1<<31) // Disable lane-to-lane deskew. Disables the internal lane-t…
5381 … (0x1<<31) // Disable Lane-to-Lane Deskew. Causes the core to disable the intern…
5384 … (0xff<<0) // Max number of functions supported. Used for SR-IOV.
5397 …-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in inc…
5403 …- 0: Scaling Factor is 1024 (1ms is 1us) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Scaling Fa…
5451 …- 0: For RADM RC filter to not allow CFG transaction being received - 1: For RADM RC filter to al…
5460 …_HANDLE_FLUSH_E5 (0x1<<3) // Mask core filter…
5461 …CIEIP_REG_PCIEEP_FILT_MSK2_M_HANDLE_FLUSH_E5_SHIFT 3
5466 …SK_TD_E5 (0x1<<6) // Disable unmask TD bit.
5492 … 0x000734UL //Access:R DataWidth:0x20 // Transmit Non-Posted FC Credit Stat…
5493 … (0xfff<<0) // Transmit Non-Posted Data FC Credits. The non-poste…
5495 … (0xff<<12) // Transmit Non-Posted Header FC Credits. The non-post…
5514 …S_RQOF_E5 (0x1<<3) // Receive credit q…
5515 …CIEIP_REG_PCIEEP_QUEUE_STATUS_RQOF_E5_SHIFT 3
5524 … (0x1<<31) // FC latency timer override enable. When this bit is set, the value i…
5535 … (0x1<<31) // FC Latency Timer Override Enable. When this bit is set, the value f…
5547 …xff<<0) // WRR Weight for VC0. Note: The access attributes of this field are as follows: - Dbi: R
5549 …xff<<8) // WRR Weight for VC1. Note: The access attributes of this field are as follows: - Dbi: R
5551 …ff<<16) // WRR Weight for VC2. Note: The access attributes of this field are as follows: - Dbi: R
5553 …ff<<24) // WRR Weight for VC3. Note: The access attributes of this field are as follows: - Dbi: R
5565 …xff<<0) // WRR Weight for VC4. Note: The access attributes of this field are as follows: - Dbi: R
5567 …xff<<8) // WRR Weight for VC5. Note: The access attributes of this field are as follows: - Dbi: R
5569 …ff<<16) // WRR Weight for VC6. Note: The access attributes of this field are as follows: - Dbi: R
5571 …ff<<24) // WRR Weight for VC7. Note: The access attributes of this field are as follows: - Dbi: R
5580 …-buffer configuration, writable through PEM()_CFG_WR. However, the application must not change thi…
5588 …he TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration,…
5590 …ines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration,…
5592 … 0x000748UL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Posted Rec…
5593 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5595 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5603 …ly in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ord…
5605 …eues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs …
5614 …-buffer configuration, writable through PEM()_CFG_WR. Only one bit can be set at a time: _ Bit 2…
5616 … (0x3<<24) // VC0 scale non-posted header credits.
5618 … (0x3<<26) // VC0 scale non-posted data credits.
5622 … 0x00074cUL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Non-Posted Receive…
5623 …-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in the segm…
5625 …-Posted Header Credits. The number of initial non-posted header credits for VC0, used only in the …
5640 …-buffer configuration, writable through PEM()_CFG_WR. Only one bit can be set at a time: _ Bit 2…
5648 … 0x000750UL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Completion…
5649 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5651 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5660 …uests it to prepare for leaving L0 before asserting tlp blocked. When this bit is set , if min cre…
5664 … (0x1<<2) // Target mem Rd should not be greater than 3 DW if set.
5666 …_1DW_CHK_BB (0x1<<3) // Target mem Wr sh…
5667 …CIEIP_REG_TL_CONTROL_0_MEMWR_1DW_CHK_BB_SHIFT 3
5668 … (0x1<<4) // Target Expansion ROM should not be greater than 3 DW if set.
5682 … (0x1<<12) // This bit if set will force D…
5700 … (0x1<<21) // When set, it enables WAKE generation in any L-state, when PME_EN bit is set an…
5706 … (0x1<<24) // When set, it prevents PM from re-entering L1 when programmed to non-D0 p…
5708 …BB (0x1<<25) // This bit is used by PCIE SER…
5714 …, when set, it enables pcie_scnd_rst_b to be asserted when Secondary reset bit in BridgeControl re…
5727 …_CHK_BB (0x1<<3) // Enable check to …
5728 …CIEIP_REG_TL_CONTROL_1_EN_BE_CHK_BB_SHIFT 3
5741 … (0x1<<10) // Enable Completion Timeout Check( This bit is no longer used, instead bit defi…
5743 … (0x1<<11) // This bit is used to disable function 1. Bit 17 of 800 can also b…
5745 … (0x1<<12) // This bit is used to disable …
5747 … (0x1<<13) // This bit is used to disable function 3.
5749 … (0x1<<14) // This bit is used to disable …
5751 … (0x1<<15) // This bit is used to disable …
5753 … (0x1<<16) // This bit is used to disable …
5755 … (0x1<<17) // This bit is used to disable …
5759 … and not wait for LTR message to be sent first even though device state may have changed to non-D0.
5767 …bit instructs h/w to send an LTR message with LTR values programmed in 'h848 whenever the h/w asse…
5769 …bit enables CRS status to be automatically cleared when internal timer is equal to either 1 second…
5771 … // This bit instructs h/w to send an LTR message with LTR values programmed in 'h84c whenever the…
5773 …d ASPM LTR message and wait for FC to be returned before entering L1. This bit is used only if LTR…
5775 …/ This bit instructs h/w to send an LTR message with LTR values programmed in 'h844 and 'h848 when…
5777 …bit instructs h/w to immediately send an LTR message with LTR values programmed in 'h840. This sta…
5786 …0_MASK_BB (0x1<<3) // Received UR Stat…
5787 …CIEIP_REG_TL_CONTROL_2_RX_UR0_MASK_BB_SHIFT 3
5845 …ive and L2.Idle. 0x1 = 1 lane. 0x2 = 2 lanes. 0x3 = 3 lanes. _ ... 0x10 = 16 lanes. 0x11-0x…
5847 …0 to physical lane 3. 0x3 = Connect logical Lane0 to physical lane 7. 0x4 = Connect logical …
5855 …Config TX compliance receive bit. When set to one, signals LTSSM to transmit TS ordered sets with …
5857 … (0x1<<20) // Set the deemphasis level for upstream ports. 0 = -6 dB. 1 = -3.5 dB.
5862 …his field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as…
5864 …- 0x01: 1 lane - 0x02: 2 lanes - 0x03: 3 lanes - .. When you have unused lanes in your system, …
5866 …- 3'b000: Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8…
5868 …his field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as…
5870 …- Write to LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device - Deas…
5872 …bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe. Not…
5874 …Bit. When set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit asse…
5876 …-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at…
5878 …core by just detecting the condition RxValid=0. - 0: Use RxElecIdle signal to infer Electrical Id…
5881 …e Completion retry upon completion timeout. (feature is not supported, but bit is defined for post…
5883 …x1<<1) // Enable Poisoned completions retry. (feature is not supported but bit is defined for post…
5885 …eleasing of Posted header credit. When this bit is set, PH credits are not released by IP if FIFO …
5887 … (0x1<<3) // Indicates no non-posted credit is available to us…
5888 …CIEIP_REG_TL_CONTROL_3_EN_HOLD_DMACRDT_BB_SHIFT 3
5897 … (0x1<<16) // This bit when set prevents DUT from entering L1 due to bei…
5899 … (0x7fff<<17) // Programmable delay to prevent link from re-entering L1, when lin…
5911 … (0x1<<0) // This bit is set when h/w det…
5913 … (0x1<<1) // This bit is set when h/w det…
5915 …BB (0x1<<2) // This bit is set when h/w det…
5917 …ABRT_BB (0x1<<3) // This bit is set when h/…
5918 …CIEIP_REG_TL_CTRLSTAT_5_ERR_MASTER_ABRT_BB_SHIFT 3
5919 … (0x1<<4) // This bit is set when h/w det…
5921 … (0x1<<5) // This bit is set when h/w det…
5923 … (0x1<<6) // This bit is set when h/w det…
5925 … (0x1<<7) // This bit is set when h/w det…
5927 … (0x1<<8) // This bit is set when h/w det…
5931 … (0x1<<10) // This bit is set when h/w det…
5933 … (0x1<<11) // This bit is set when h/w det…
5935 …BB (0x1<<12) // This bit is set when h/w det…
5939 … (0x1<<14) // This bit is set when h/w det…
5941 … (0x1<<15) // This bit is set when h/w det…
5943 … (0x1<<16) // This bit is set when h/w det…
5945 … (0x1<<17) // This bit is set when h/w det…
5947 … (0x1<<18) // This bit is set when h/w det…
5982 … (0x1<<0) // This bit is used to disable …
5984 … (0x1<<1) // This bit is used to disable …
5986 … (0x1<<2) // This bit is used to disable …
5988 …_BB (0x1<<3) // This bit is used to dis…
5989 …CIEIP_REG_TL_CONTROL_6_HIDE_FUNC_11_BB_SHIFT 3
5990 … (0x1<<4) // This bit is used to disable …
5992 … (0x1<<5) // This bit is used to disable …
5994 … (0x1<<6) // This bit is used to disable …
5996 … (0x1<<7) // This bit is used to disable …
6007 … (0x1<<15) // Requirement bit indicates if device…
6015 … (0x1<<31) // Requirement bit indicates if device…
6024 … (0x1<<15) // Requirement bit indicates if device…
6032 … (0x1<<31) // Requirement bit indicates if device…
6041 … (0x1<<15) // Requirement bit indicates if device…
6049 … (0x1<<31) // Requirement bit indicates if device…
6058 … (0x1<<15) // Requirement bit indicates if device…
6066 … (0x1<<31) // Requirement bit indicates if device…
6075 …_UR2_MASK_BB (0x1<<3) // Received UR Stat…
6076 …CIEIP_REG_TL_FUNC345_MASK_RX_UR2_MASK_BB_SHIFT 3
6132 …BB (0x1<<0) // This bit is set when h/w det…
6134 …B (0x1<<1) // This bit is set when h/w det…
6136 …T2_BB (0x1<<2) // This bit is set when h/w det…
6138 …R_ABRT2_BB (0x1<<3) // This bit is set when h/…
6139 …CIEIP_REG_TL_FUNC345_STAT_ERR_MASTER_ABRT2_BB_SHIFT 3
6140 …_BB (0x1<<4) // This bit is set when h/w det…
6142 …BB (0x1<<5) // This bit is set when h/w det…
6144 …BB (0x1<<6) // This bit is set when h/w det…
6146 … (0x1<<7) // This bit is set when h/w det…
6148 …BB (0x1<<8) // This bit is set when h/w det…
6152 … (0x1<<10) // This bit is set when h/w detects Poisoned Error Status in …
6154 … (0x1<<11) // This bit is set when h/w detects Flow Control Protocol Error Stat…
6156 … (0x1<<12) // This bit is set when h/w detects Completer Timeout Status in…
6158 … (0x1<<13) // This bit is set when h/w detects Receive UR Status in fu…
6160 … (0x1<<14) // This bit is set when h/w detects Unexpected Completion Status …
6162 … (0x1<<15) // This bit is set when h/w detects Receiver Overflow Status in…
6164 … (0x1<<16) // s bit is set when h/w detects Malformed TLP Status Status …
6166 … (0x1<<17) // This bit is set when h/w detects ECRC Error TLP Status in …
6168 …B (0x1<<18) // This bit is set when h/w det…
6172 …B (0x1<<20) // This bit is set when h/w det…
6174 … (0x1<<21) // This bit is set when h/w det…
6176 …4_BB (0x1<<22) // This bit is set when h/w det…
6178 …4_BB (0x1<<23) // This bit is set when h/w det…
6180 …BB (0x1<<24) // This bit is set when h/w det…
6182 …B (0x1<<25) // This bit is set when h/w det…
6184 …B (0x1<<26) // This bit is set when h/w det…
6186 … (0x1<<27) // This bit is set when h/w det…
6188 …B (0x1<<28) // This bit is set when h/w det…
6201 …_UR5_MASK_BB (0x1<<3) // Received UR Stat…
6202 …CIEIP_REG_TL_FUNC678_MASK_RX_UR5_MASK_BB_SHIFT 3
6264 …R_MASTER_ABRT5_BB (0x1<<3) // Receive UR Statu…
6265 …CIEIP_REG_TL_FUNC678_STAT_ERR_MASTER_ABRT5_BB_SHIFT 3
6323 …_INT_SEL_BB (0x7<<3) // Route the interr…
6324 …CIEIP_REG_FUNC_INT_SEL_FUNC1_INT_SEL_BB_SHIFT 3
6327 … (0x7<<9) // Route the interrupt pin for Function 3 to any of INTA to IN…
6342 …9_INT_SEL_BB (0x7<<3) // Route the interr…
6343 …CIEIP_REG_FUNC_INT_SEL2_FUNC9_INT_SEL_BB_SHIFT 3
6359 …_BB (0x1<<0) // This bit when cleared will k…
6361 …B (0x1<<1) // This bit when cleared will k…
6363 … (0x1<<2) // This bit when set will reset the Serdes register space, pro…
6365 … (0x1<<3) // Tthis bit when set will allow bit 2 value to propogate t…
6366 …CIEIP_REG_TL_RST_CTRL_SEL_SOFT_MDIO_RST_BB_SHIFT 3
6367 … (0x1<<4) // This bit when set will reset the micro, provided b…
6369 … (0x1<<5) // For gen3 serdes, this bit when set will allow bit 4 value to propogate to uc re…
6389 …r due to hide_func_1 pad being driven high or due to programming bit in TL reg This bit is tied to…
6391 …func2 is hidden either due to hide_func_2 pad being driven high or due to programming bit in TL reg
6393 …func3 is hidden either due to hide_func_3 pad being driven high or due to programming bit in TL reg
6395 … (0x1<<3) // Set if func4 is hidden either due to hide_func_4 pad being driven h…
6396 …CIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_4_HIDDEN_BB_SHIFT 3
6397 …func5 is hidden either due to hide_func_5 pad being driven high or due to programming bit in TL reg
6399 …func6 is hidden either due to hide_func_6 pad being driven high or due to programming bit in TL reg
6401 …func7 is hidden either due to hide_func_7 pad being driven high or due to programming bit in TL reg
6403 …func8 is hidden either due to hide_func_8 pad being driven high or due to programming bit in TL reg
6405 …func9 is hidden either due to hide_func_9 pad being driven high or due to programming bit in TL reg
6407 …nc10 is hidden either due to hide_func_10 pad being driven high or due to programming bit in TL reg
6409 …nc11 is hidden either due to hide_func_11 pad being driven high or due to programming bit in TL reg
6411 …nc12 is hidden either due to hide_func_12 pad being driven high or due to programming bit in TL reg
6413 …nc13 is hidden either due to hide_func_13 pad being driven high or due to programming bit in TL reg
6415 …nc14 is hidden either due to hide_func_14 pad being driven high or due to programming bit in TL reg
6417 …nc15 is hidden either due to hide_func_15 pad being driven high or due to programming bit in TL reg
6435 … (0x1<<0) // Direct reflection of Config PM PME enable bit for function 0.
6437 … (0x1<<1) // Direct reflection of config PM PME status bit for function 0.
6441 … (0x1<<3) // Direct reflection of Config PM PME enable…
6442 …CIEIP_REG_PM_STATUS_1_CFG_PME_ENABLE1_BB_SHIFT 3
6443 … (0x1<<4) // Direct reflection of config PM PME status bit for function 1.
6458 …RX_UR8_MASK_BB (0x1<<3) // Received UR Stat…
6459 …CIEIP_REG_TL_FUNC8TO10_MASK_RX_UR8_MASK_BB_SHIFT 3
6521 …ERR_MASTER_ABRT8_BB (0x1<<3) // Receive UR Statu…
6522 …CIEIP_REG_TL_FUNC8TO10_STAT_ERR_MASTER_ABRT8_BB_SHIFT 3
6584 …_RX_UR11_MASK_BB (0x1<<3) // Received UR Stat…
6585 …CIEIP_REG_TL_FUNC11TO13_MASK_RX_UR11_MASK_BB_SHIFT 3
6641 …gating feature when there is no receive traffic, receive queues and pre/post-queue pipelines are e…
6650 …_ERR_MASTER_ABRT11_BB (0x1<<3) // Receive UR Statu…
6651 …CIEIP_REG_TL_FUNC11TO13_STAT_ERR_MASTER_ABRT11_BB_SHIFT 3
6707 … (0x1<<0) // Gen3 receiver impedance ZRX-DC not compliant.
6711 … (0x1<<9) // Equalization phase 2 and phase 3 disable. This applie…
6727 …bit in DSP will not direct the controller to Recovery state to perform Gen4 equalization. Link sta…
6735 …-specific N_FTS field. The N_FTS field in the "Link Width and Speed Change Control Register" is us…
6736 …-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defin…
6740 …3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED, this register is shad…
6746 …bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding p…
6748 …- 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner. - 1: mac_phy_rxeq…
6765 …_RX_UR14_MASK_BB (0x1<<3) // Received UR Stat…
6766 …CIEIP_REG_TL_FUNC14TO15_MASK_RX_UR14_MASK_BB_SHIFT 3
6808 …_ERR_MASTER_ABRT14_BB (0x1<<3) // Receive UR Statu…
6809 …CIEIP_REG_TL_FUNC14TO15_STAT_ERR_MASTER_ABRT14_BB_SHIFT 3
6845 … with a data payload of 0xFFFFFFFF. When the MSB of a PF's HIDE_PFn is non-zero, the PF is consi…
6911 … (0xf<<0) // Feedback mode. 0 = Direction of change. 1 = Figure of merit. 2-15 = Reserved.
6913 …: * Equalization phase 3 successful status bit is not set in the link status register. * Equaliza…
6919 …Bit [15:0] = 0x0: No preset is requested and evaluated in the EQ master phase. Bit [i] = 1: Pres…
6925 … (0x1<<26) // Request core to send back-to-back EIEOS in Recove…
6927 …or Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP). M-PCIe doesn't have Con…
6928 … (0xf<<0) // Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserv…
6930 …- 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found then: …
6932 …Eval: - 0: abort the current evaluation, stop any attempt to modify the remote transmitter settin…
6934 …Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: "Preset=i"…
6936 …ter, when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include…
6940 …-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0:…
6945 …3 when determining if optimal coefficients have been found. When 0x0, EQ master is performed wit…
6947 … (0xf<<10) // Convergence window aperture for C-1. Precursor coeffici…
6951 …Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP), when you set …
6954 …3 when determining if optimal coefficients have been found. Allowed range: 0,1,2,..16 up to a maxi…
6956 …TA_K2 (0xf<<10) // Convergence Window Aperture for C-1. Pre-cursor coefficient…
6958 …K2 (0xf<<14) // Convergence Window Aperture for C+1. Post-cursor coefficients m…
6961 …-Posted passing posted ordering rule control. Determines if a NP can pass halted P queue. 0x0 = …
6963 …lted P queue. 0x0 = CPL can not pass P (recommended). 0x1 = CPL can pass P. 0x2-0xFF = Reserved.
6966 …<0) // Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue…
6968 … Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1…
6971 … (0xffff<<0) // Loopback rxvalid (lane enable - 1 bit per lane).
6984 … (0x1<<31) // PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This reg…
6987 … (0x1<<0) // Write to RO registers using DBI. When you set this bit, then some RO bits …
6989 …error reporting). A completion with UR status will be generated for non-posted requests. 0x1…
6991 …e suppresses error logging, error message generation, and CPL generation (for non-posted requests).
6993 …IMP_REPLAY_TIMER_E5 (0x1<<3) // Enables Simplifi…
6994 …CIEIP_REG_PCIEEP_MISC_CTL1_SIMP_REPLAY_TIMER_E5_SHIFT 3
6999 … 0x0008bcUL //Access:RW DataWidth:0x20 // DBI Read-Only Write Enable Reg…
7000 …he local application through the DBI. For more details, see "Writing to Read-Only Registers." Not…
7005 …bit is set. If PCIEEP_RAS_EINJ_CTL6PE[LTSSM_VAR] is set and PCIEEP_LINK_CTL2[HASD] is zero, the …
7009 … 0x0008c0UL //Access:RW DataWidth:0x20 // UpConfigure Multi-lane Control Register…
7010 …- 6'b000000: Core does not start upconfigure or autonomous width downsizing in the Configuration s…
7012 …bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DI…
7014 …n Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This reg…
7017 …ted condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. …
7021 … (0x1<<9) // L1 entry control bit. 0 = Core waits …
7023 … (0x1<<10) // L1 clock control bit. 0 = Controller …
7026 …Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. - [0]: Rx EIOS a…
7028 …bit. - 1: Core does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Co…
7033 …This is a one-shot bit. Writing a one triggers the deletion of the target completion LUT entry tha…
7035 …lication completions (on XALI0/1/2) corresponding to previously received non-posted requests from …
7038 …hot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is …
7096 … (0xff<<24) // Non-Posted Data credits available: bit[7:0…
7105 … (0xf<<28) // Non-Posted Data credits available: bit[11:…
7114 … (0xff<<24) // Non-Posted Data credits consumed: bit[7:0].
7123 … (0xf<<28) // Non-Posted Data credits consumed: bit[11:8…
7134 … (0x1<<16) // Available Non-posted credit for tar…
7137 …B (0xff<<0) // Non-Posted header credits…
7139 …B (0xff<<8) // Non-Posted data credits a…
7146 … (0xf<<0) // Target Non-Posted request State …
7175 …bit when set enables the DUT to assume that VFs are residing on a bus number that is different tha…
7177 …bit when set, prevents DUT from automatically setting VF offset to be greater than 256(when vf_nex…
7179 …T_BB (0x1<<2) // This bit when set, enables D…
7182 …non-posted data credits since the last request for immediate update that are needed to force an im…
7184 … (0xff<<12) // The number of accumulated non-posted header credits…
7186 …-posted credits are flagged for immediate update. When clear, the credits may or not be updated un…
7188 …the forced update if there are outstanding non-posted credits to update. The resolution on the tim…
7190 …-posted credit updates are forwarded to the DLL as immediate updates after a given number of micro…
7199 … update if there are outstanding posted credits to update. The resolution on the timer is +/- 1 us.
7201 …w) elapses since the last update. This is typically used with non-immediate (threshold-based) upda…
7204 …0_MASK_BB (0xf<<0) // Each bit, when set, indicate…
7206 …FN0_MASK_BB (0x3ff<<4) // Each bit, when set, indicate…
7208 …ENA_FN0_MASK_BB (0x3<<14) // Each bit, when set, indicate…
7210 …A_FN0_MASK_BB (0xf<<16) // Each bit, when set, indicate…
7212 …A_FN0_MASK_BB (0xf<<20) // Each bit, when set, indicate…
7216 …ENA_FN0_MASK_BB (0x1f<<26) // Each bit, when set, indicate…
7223 … (0x1<<16) // VDM is enabled when this bit is set. PCIe will pass VDM messgaes to user interface…
7226 … (0x1<<0) // This bit when set, forces hardware to generate a PTM Request message. Hardware…
7228 … field when set will prevent hardware from generating attention when PTM req- response handshake h…
7232 …is field when set inidcates that the PTM req-response handshake initiated by software has complete…
7234 …ld when set inidcates that the PTM req-response handshake completed successfully. This field is va…
7244 …bit to '1' enables the tx TLP statistics collection. Hardware will count various types of TLPs in …
7248 …he reg_ttx_tlp_stat_en bit to stop the operation. When it is set to a non-zero value, hardware aut…
7251 …0) // This register contains Enable bit and the TLP type that hardware can detect. Bit[7] is enabl…
7253 …8) // This register contains Enable bit and the TLP type that hardware can detect. Bit[15] is enab…
7255 …6) // This register contains Enable bit and the TLP type that hardware can detect. Bit[23] is enab…
7257 …4) // This register contains Enable bit and the TLP type that hardware can detect. Bit[31] is enab…
7260 …value is 0. If a bit is set to 1 then corresponding bit of reg_ttx_det_tlp_type_0 will be masked. …
7264 …value is 0. If a bit is set to 1 then corresponding bit of reg_ttx_det_tlp_type_1 will be masked. …
7268 …value is 0. If a bit is set to 1 then corresponding bit of reg_ttx_det_tlp_type_2 will be masked. …
7272 …value is 0. If a bit is set to 1 then corresponding bit of reg_ttx_det_tlp_type_3 will be masked. …
7277 …bit to '1' enables the rx TLP statistics collection. Hardware will count various types of TLPs pro…
7281 …he reg_trx_tlp_stat_en bit to stop the operation. When it is set to a non-zero value, hardware aut…
7284 …0) // This register contains Enable bit and the TLP type that hardware can detect. Bit[7] is enabl…
7286 …8) // This register contains Enable bit and the TLP type that hardware can detect. Bit[15] is enab…
7288 …6) // This register contains Enable bit and the TLP type that hardware can detect. Bit[23] is enab…
7290 …4) // This register contains Enable bit and the TLP type that hardware can detect. Bit[31] is enab…
7293 …value is 0. If a bit is set to 1 then corresponding bit of reg_trx_det_tlp_type_0 will be masked. …
7297 …value is 0. If a bit is set to 1 then corresponding bit of reg_trx_det_tlp_type_1 will be masked. …
7301 …value is 0. If a bit is set to 1 then corresponding bit of reg_trx_det_tlp_type_2 will be masked. …
7305 …value is 0. If a bit is set to 1 then corresponding bit of reg_trx_det_tlp_type_3 will be masked. …
7323 …<<0) // Snoop Latency Value. Note: The access attributes of this field are as follows: - Dbi: R/W
7325 …<10) // Snoop Latency Scale. Note: The access attributes of this field are as follows: - Dbi: R/W
7327 …/ Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W
7329 …) // No Snoop Latency Value. Note: The access attributes of this field are as follows: - Dbi: R/W
7331 …) // No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Dbi: R/W
7333 …o Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W
7336 … This value is used to provide a 1 us reference for counting time during low-power states with aux…
7339 …-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are…
7389 …RETRIG_CNT_BB (0xff<<0) // When non-zero, indicates the m…
7393 …ger location (where data corresponding to the trigger cycle is collected). Bit 17 is a wrap condit…
7403 …buffer is filled, the trig_addr field is used to determine the amount of pre-trigger data collected
7422 … (0x1ff<<23) // Current write address to the external FIFO. Bit 31 is a wrap condit…
7424 …- mask bits [319:0] for 0to1 trigger0 Register 10 :: IND_PCIE_DBG_TRIG0_1TO0_MASK - mask bits [319…
7455 …- no FIFO selected to read by user if 001 - PL/DL FIFO is selected to read by user if 010 - TLDA…
7457 …ER_TLPL_DBG_FIFO_CTL_UNUSED0_BB (0x1ff<<3) //
7458 …CIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_UNUSED0_BB_SHIFT 3
7459 … (0x7<<12) // 000 - generic lane is selected 001 - predefined lane 1 010 - predefine…
7490 …nterface. Note that there is a bug in earlier versions of the TLDA that make this a write-only bit.
7496 … (0x1<<14) // When set, indicates that the FIFO is operating in local mode - FIFO will be read fr…
7498 … (0x7f<<15) // The number of pre-trigger samples to ke…
7500 … (0x7f<<22) // The FIFO write address at the time of the trigger. Use bit 13 of this register…
7523 …-- First trigger configuration registers Register 0 :: IND_TLDA_TRIG0_0TO1_MASK0 -- Trigger 0 risi…
7525 … 0x000c50UL //Access:R DataWidth:0x20 // Bits [127:96] of the current half-data from the FIFO
7526 … 0x000c54UL //Access:R DataWidth:0x20 // Bits [95:64] of the current half-data from the FIFO
7527 … 0x000c58UL //Access:R DataWidth:0x20 // Bits [63:32] of the current half-data from the FIFO
7528 … 0x000c5cUL //Access:R DataWidth:0x20 // Bits [31:0] of the current half-data from the FIFO
7540 …nterface. Note that there is a bug in earlier versions of the TLDA that make this a write-only bit.
7546 … (0x1<<14) // When set, indicates that the FIFO is operating in local mode - FIFO will be read fr…
7548 … (0x7f<<15) // The number of pre-trigger samples to ke…
7550 … (0x7f<<22) // The FIFO write address at the time of the trigger. Use bit 13 of this register…
7573 …-- First trigger configuration registers Register 0 :: IND_TLDA_TRIG0_0TO1_MASK0 -- Trigger 0 risi…
7575 …000c70UL //Access:R DataWidth:0x20 // Bits [127:96] of the current half-data from the second …
7576 …x000c74UL //Access:R DataWidth:0x20 // Bits [95:64] of the current half-data from the second …
7577 …x000c78UL //Access:R DataWidth:0x20 // Bits [63:32] of the current half-data from the second …
7578 …0x000c7cUL //Access:R DataWidth:0x20 // Bits [31:0] of the current half-data from the second …
7582 … (0x1<<1) // PHY: Disable Inverse Polarity. Setting this bit to '1' disables the…
7586 …DL_CONTROL_0_RESERVED_3_BB (0x1<<3) //
7587 …CIEIP_REG_PDL_CONTROL_0_RESERVED_3_BB_SHIFT 3
7596 … (0x1<<10) // PHY: Disable Electrical Idle Retrain. Setting this bit to '1' prevents lin…
7598 … (0x1<<11) // DL: Disable Auto Credit Update. If this bit is set to '1', DL w…
7602 … (0x1<<13) // DL: Force L0 to L1. When this bit is set to '1', DL w…
7606 … (0x1<<23) // PHY: Force Receiver Detect All. When this bit is set to '1', inte…
7610 … (0x1<<27) // DL: Force L0 to L2. When this bit is set to '1', DL w…
7616 … (0x1<<31) // PHY: Direct Recovery to Configuration State. When this bit is set to '1', LTSS…
7621 … (0x1<<7) // When this bit is set, the softwar…
7625 … (0x1<<9) // When this bit is set, the software value will be used for UpdateFC L…
7627 …bit is set to '1', Replay Timer will not be reset if a NAK is received during a Replay operation. …
7629 … (0x1<<11) // PHY: Force to TX L0s. Setting this bit to '1' forces LTSSM…
7633 …x1<<14) // This initiates Link re-training by directing PHY LTSSM to recovery state. It is a pulse…
7641 … (0x1<<30) // Internal ASPM L1 Enable. When this bit is set to '1', hard…
7643 … (0x1<<31) // External ASPM L1 Enable. When this bit is set to '1', user…
7648 … (0x1<<2) // PHY: Disable SKP OS. When this bit is set to '1', peri…
7650 …LE_ACK_LAT_TIMER_BB (0x1<<3) // DL: If set, it w…
7651 …CIEIP_REG_PDL_CONTROL_2_ENABLE_ACK_LAT_TIMER_BB_SHIFT 3
7664 …1<<17) // DL: Enable Non-Posted Latency Timer. If this timer reaches MAX_ACK_LAT_TIMER value, DL w…
7678 … (0xfff<<0) // DL: Non-Posted Data for INITFC
7687 …BB (0x1<<8) // This bit is set to '1' if IP…
7700 … (0xffff<<16) // Reserved - always write 0
7703 …ay timeout in symbol time. It is selected if bit sw_replay_timer_sel is set to '1'; otherwise, the…
7705 …he replay timeout in symbol time. This delay is only applied to the hardware-calculated replay tim…
7707 …_BB (0x7ff<<21) // Reserved - always write 0
7712 …the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so t…
7717 …ay timeout in symbol time. It is selected if bit sw_replay_timer_sel is set to '1'; otherwise, the…
7719 …he replay timeout in symbol time. This delay is only applied to the hardware-calculated replay tim…
7728 … earlier, DL will nullify all subsequence memory write request whose pcie_cksum_err bit is not set.
7730 …WRITE_NULLIFY is set, regardless if they have bad or good checksum If this bit is clear and checks…
7734 …t from sending more Posted FC updates , potentially stall DMA requests, until the flag de-asserted.
7737 …ay timeout in symbol time. It is selected if bit sw_replay_timer_sel is set to '1'; otherwise, the…
7739 …he replay timeout in symbol time. This delay is only applied to the hardware-calculated replay tim…
7744 …the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so t…
7751 …the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so t…
7766 …(0x1<<31) // Enable GRC to control the driving of the debug bus. When this bit is set, it provides…
7775 …ADDRESS_PARITY_ERROR_BB (0x1<<3) // Set if Replay Ad…
7776 …CIEIP_REG_DLATTN_VEC_REPLAY_ADDRESS_PARITY_ERROR_BB_SHIFT 3
7779 …when Correctable Error counter reach max CORR_ERR_REG_MAX value defined at bit [27:18] of reg 0x10…
7781 … (0x1<<6) // Indicate un-decoded condition in de-framing l…
7791 … (0x1<<11) // Set if DL detects impossible condition to de-allocate entries in R…
7799 … (0x1<<15) // DL TX Underrun. This bit is set to '1' if un…
7801 … (0x1<<16) // Detect DLLP with mismatched CRC-16 on receiving side.
7837 …at DL has to send at least one UpdateFC DLLP for each FC credit type when Extended Sync bit is '0'.
7839 …at DL has to send at least one UpdateFC DLLP for each FC credit type when Extended Sync bit is '1'.
7844 …bit is set to '1' to enable the T2D FIFO threshold feature. Depending on TL, DL bus width and cloc…
7853 … (0x3ff<<0) // Replay FIFO Test Size. When bit replayfifo_testsize…
7855 … (0x3ff<<10) // D2T FIFO Test Size. When bit d2tfifo_testsize_se…
7859 … (0x1<<30) // Replay FIFO Test Size Select. When this bit is set to '1', the …
7861 … (0x1<<31) // D2T FIFO Test Size Select. When this bit is set to '1', the …
7874 … bit must be written as a '1' to initiate write cycle based ont the data in bits [15:0] and the md…
7879 …31) // This bit will read as '0' until a requested read of the PCIE serdes has completed, in which…
7881 …8-bit header information that is sent to TL logic to build a TLP. The header information is passed…
7888 … (0x1<<8) // ATE TLP Nullify. When this bit is set to '1', an i…
7897 …bit. When this bit is set to '1', the TX User Interface is bypassed and internal logic generates p…
7901 …bit. SW needs to read trx_reg_sb_op_done (bit[31]). If trx_reg_sb_op_done register value is 1, it …
7905 …oes not match with received TLP header. This bit can be cleared by writing '1' to reg_trx_clr_rx_t…
7907 …ta do not match with received TLP data. This bit can be cleared by writing '1' to reg_trx_clr_rx_t…
7911 … - offset 0x111c). trx_reg_err_tlp_num indicates the number of TLP that has error. This register i…
7915 …] of ate_tlp_cfg - offset 0x111c). This register value needs to be ignored until user writes '1' t…
7935 …This bit must be written as a '1' to initiate read cycle to the pmi_addr value. When the read has …
7937 …bit must be written as a '1' to initiate write cycle based on the data in bits [15:0] and the pmi_…
7944 …31) // This bit will read as '0' until a requested read of the PCIE serdes has completed, in which…
7967 … (0x1<<0) // Request a width change (ie -make the link wider, …
7969 … (0x1<<1) // Request a speed change (ie -make the link fast or…
7975 … (0x1<<6) // For multi-lane links on a 2.0 c…
7981 … (0x1<<9) // Consider loss of bit and symbol lock fro…
7997 … Modified Compliance Pattern in Polling.Compliance if the Enter Compliance bit of the Link Control…
8001 …ng.Compliance from Polling.Active. This also causes the Compliance Receive bit in the outgoing TS1…
8003 … (0x1<<21) // The value for the Selectable Deemphasis bit set in TS1s in Poll…
8005 …s to the PCIe Serdes via the TxDeemph signal. 0 == -6 dB, 1 == -3.5 dB (For Gen3, this is the low …
8007 … (0x1<<23) // The value for the Autonomous Change bit set in TS1s in the …
8015 … (0x1<<27) // Disable use of electrical idle in Recovery.Speed - only use inferred el…
8019 … (0x1<<29) // Disable the ability to compensate for lane reversal in multi-lane links.
8023 … (0x1<<31) // Enable gen2 features when in 1.1 compliance mode (register 0x4d0, bit 5 is set)
8026 … (0x1<<0) // Force the PIPE interface to be 16-bit, even in Gen 1 Soft…
8030 … (0x1<<2) // Enable the PIPE-style powerdown of unused lanes in a multi-…
8032 … (0x1<<3) // Enable the auxilliary powerdown of unused lanes …
8033 …CIEIP_REG_REG_PHY_CTL_1_REG_P2_POWERDOWN_ENA_NOSYNC_BB_SHIFT 3
8034 … (0x1<<4) // Initiate PL changes required for a far-end loopback
8052 …Skip Ordered Set (SOS) is received in any 128 us interval. See comments for bit 19 of this register
8054 …L0 if no UpdateFC is received in any 128 us interval. Can be combined with bit 18 of this register…
8068 … (0x1<<29) // Clear the LTSSM histogram. Not self-clearing
8070 … (0x1<<30) // Clear the Gen2 debug histogram. Not self-clearing
8072 … (0x1<<31) // Clear the recovery histogram. Not self-clearing
8081 …erved - only write 0. Spare flops for the PL - train_ctl_in[1:0]. [29] (PL_FIX_19) Enable Phase 3 …
8083 …es elastic buffers will be prevented from adjusting - generating dynamic clock compensation events…
8085 … (0x1<<31) // Reserved - only write 0. Spare flop for the PL - train_ctl…
8092 … (0x1<<14) // Enable the "pins" gloopback - assumes an external …
8127 …SPDUP_200MS_50MS_BB (0x1<<3) // For RC only. For…
8128 …CIEIP_REG_REG_PHY_CTL_4_REG_SPDUP_200MS_50MS_BB_SHIFT 3
8143 …nimum time to wait in Detect.Quiet (in 32 ns increments) if the state is entered at non-Gen1 speeds
8149 … (0x1<<16) // Enable exit from Compliance on 1.1-compliant systems on …
8162 … (0xf<<5) // High 4 bits of the 10 bit-counter of 25 MHz cl…
8168 …erdes device type to minimize the PLL lock time (when set, don't reuse the old value - start over).
8170 … (0x3<<22) // Selects the low-frequency clock used …
8172 … (0x3f<<24) // Low 6 bits of the 10 bit-counter of 25 MHz cl…
8174 … (0x1<<30) // Reserved - only write 0
8181 …B (0x3<<6) // Reserved - only write 0
8185 … (0x3<<14) // Reserved - only write 0
8189 … (0x1<<17) // Use any PhyStatus to indicate the P0->P2 transition. De…
8195 … (0xfff<<20) // Reserved - only write 0
8198 … (0xf<<0) // b0000: select pseudo-random value between …
8200 …<4) // b000 : prescale = 2**2 of clock periods (~16ns) b001 : prescale = 2**3 of clock periods b01…
8212 … (0x1fff<<18) // Reserved - always write 0
8223 …INK_IS_SKEW_BB (0x1<<3) // If set, the link…
8224 …CIEIP_REG_PHY_ERR_ATTN_VEC_LINK_IS_SKEW_BB_SHIFT 3
8233 …1_BB (0xf<<8) // Reserved - only write 0
8244 …MASK_LINK_IS_SKEW_BB (0x1<<3) // If set, masks LI…
8245 …CIEIP_REG_PHY_ERR_ATTN_MASK_MASK_LINK_IS_SKEW_BB_SHIFT 3
8254 …_1_BB (0xf<<8) // Reserved - only write 0
8265 …GEN3_DIS_BLOCK_ALIGN_ERR_BB (0x1<<3) // Disable error an…
8266 …CIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_BLOCK_ALIGN_ERR_BB_SHIFT 3
8269 … (0x1<<8) // *** Do not modify!! Enable 16-bit data for all rates.
8279 …rity reversal, and lane reversal information is saved, then restored. This bit disables the restor…
8287 … (0x3<<17) // Reserved - only write 0
8289 …) // Enable updated timeouts for Recovery.Equalization phases (now 12 ms for 0 and 1, 32 ms for 3).
8312 … (0x1<<20) // Enable a bad/misplaced End-of-Data-Stream token as a…
8343 … (0x1<<5) // Software sets if it can disable data traffic during re-equalization.
8371 …O_PRESET_BB (0x1<<22) // enable echo preset bit in Phase 3
8375 …or 2'b11 depending on whether Slave is an RC or EP respectively. When this bit is set to '1', Slav…
8383 …B (0x1<<28) // Reserved - only write 0
8406 … (0x1<<11) // Enable Gen3 redo deskew on framing/post-deskew alignment issu…
8428 … (0x1<<22) // (PL_FIX_05) Enable preset-coefficient lookup for EQ Phase 3
8447 …C_BB (0x1<<6) // SED read address auto-increment
8468 …ET_LUT_ENTRY_5_TO_0_BB (0x3f<<0) // Pre-cursor for the coeffi…
8472 …_LUT_ENTRY_17_TO_12_BB (0x3f<<12) // Post-cursor for the coeffi…
8478 …ET_SEL_BB (0x1<<23) // Conbtrol bit to select the defau…
8480 …y the EP to the Link partner-RC Transmitter in Phase2 EQ programmable preset value advertized by t…
8523 …eemphasis register control programming of coefficients for preset-0(-6dB) and preset-1(-3.5dB) in …
8525 …reset 0 and 1 0: points to the preset 0 coefficients(-6dB) 1: points to the preset 1 coefficients(…
8529 …0x1<<20) // Gen2 deemphasis register select control bit to change from Preset-1(-3.5dB) to preset-…
8531 … (0x1<<21) // Select control bit for the read status of the gen1/2 and gen2 lut en…
8544 … (0x1<<0) // AFE TX deemphasis register override enable control bit for prectrl[1:0] LS…
8546 … (0x3<<1) // AFE TX deemphasis register control two LSB bit value for prectrl[1…
8548 …BB (0x1<<3) // AFE TX deemphasis register override enable con…
8549 …CIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_MAIN_LSB_EN_BB_SHIFT 3
8550 … (0x3<<4) // AFE TX deemphasis register control two LSB bit value for main[1:0]
8552 … (0x1<<6) // AFE TX deemphasis register override enable control bit for postctrl[1:0] L…
8554 … (0x3<<7) // AFE TX deemphasis register control two LSB bit value for postctrl[…
8556 … (0x1<<9) // AFE TX deemphasis register override enable control bit for prectrl[4:2] up…
8558 … (0x7<<10) // AFE TX deemphasis register control upper three bit value for prectrl[4…
8560 … (0x1<<13) // AFE TX deemphasis register override enable control bit for main[4:2] upper…
8562 … (0x1f<<14) // AFE TX deemphasis register control upper five bit value for main[6:2]
8564 … (0x1<<19) // AFE TX deemphasis register override enable control bit for postctrl[5:2] u…
8566 … (0xf<<20) // AFE TX deemphasis register control upper four bit value for postctrl[…
8568 … (0x1<<24) // AFE TX deemphasis register override enable control bit for post2[3:0] four bits
8570 … (0xf<<25) // AFE TX deemphasis register control for four bit value for post2[3:0]
8576 … (0x1<<31) // RX reset EIEOS control bit for TS1(SYM6-Bit2) in Reco…
8579 …_BB (0x1<<0) // Enable bit to control the regi…
8581 … (0x3f<<1) // Registered programmed 6-bit FULL SWING value in…
8583 …_BB (0x1<<7) // Enable bit to control the regi…
8585 … (0x3f<<8) // Registered programmed 6-bit LOW FREQUENCY value…
8591 …BB (0x1<<16) // Enables EC0 echo use preset bit in EP mode
8593 …ET_BB (0x1<<17) // Enables EC2 echo use preset bit in RC mode
8599 …) // [DEBUG_BIT]: Disables Preset and coefficient rule check error in phase 3 of equalization in E…
8603 … (0x1<<22) // [DEBUG_BIT]: Ignores the phase 2 received usepreset bit when checking for p…
8605 … (0x1<<23) // RC Mode: Skips equalizationphas 2 and Phase 3.
8611 …<<26) // [DEBUG_BIT]: RC mode : Forces Gen3 equalization for every Speed change over from Gen1-Gen3
8613 … (0x1f<<27) // [DEBUG_BITS]: Equalization static debug 5-bit address control for…
8616 … (0x1<<0) // Enable Illegal Ordered Set After EDS Error. When this bit is set to '1', repo…
8618 … (0x1<<1) // Enable Ordered Set After SDS Error. When this bit is set to '1', repo…
8620 … (0x1<<2) // Enable Ordered Set with No EDS Error. When this bit is set to '1', repo…
8622 …B (0x1<<3) // Enable Bad Framing CRC Error. When this …
8623 …CIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_FCRC_ERR_BB_SHIFT 3
8624 … (0x1<<4) // Enable Bad Framing Parity Error. When this bit is set to '1', repo…
8626 … (0x1<<5) // Enable Bad EDB Error. When this bit is set to '1', repo…
8628 … (0x1<<6) // Enable Bad Framing Symbol Error. When this bit is set to '1', repo…
8630 … (0x1<<7) // Enable Data After EDS Error. When this bit is set to '1', repo…
8633 …bit to '1' enables the master loopback operation. Normally, if lpbk_master_len is set to '0', soft…
8635 … (0x1<<1) // Loopback Master Entry State. If this bit is set to '1', loop…
8637 …2) // Loopback Master Set Compliance Receive. If this bit is set to '1', the Compliance Receive bi…
8639 …(0x1<<3) // Loopback Master Automatically Set Compliance Receive. If this bit is set to '1', hardw…
8640 …CIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_AUTO_COMPL_RECV_BB_SHIFT 3
8641 …ter Force Setting. When loopback is entered from Recov.Idle state and this bit is set to '1', hard…
8643 …bit is set, SKP OS are periodically inserted to loopback data. If data is generated by PHY, MAC pr…
8645 …KIP ordered sets for each SKIP OS interval. For testing purpose, when this bit is set to '1', hard…
8653 …e lpbk_master_ena bit to stop the operation. When it is set to a non-zero value, hardware automati…
8656 …Master Entry Timeout. While in Loopback.Entry state, if Compliance Receive bit was not set in tran…
8661 …kwidth.Start and changed to a new speed. 2. Entered from Recovery.Idle and bit lpbk_master_frc_set…
8664 … (0xf<<3) // Loopback Master TS1 Transmitter Preset. This value is sen…
8665 …CIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_TXPRESET_BB_SHIFT 3
8668 …CURSOR_BB (0x3f<<8) // Loopback Master TS1 Pre-Cursor Coefficient. T…
8672 …URSOR_BB (0x3f<<20) // Loopback Master TS1 Post-cursor Coefficient. T…
8674 … (0x1<<26) // Loopback Master TS1 Selectable De-emphasis. This value …
8676 …kwidth.Start and changed to a new speed. 2. Entered from Recovery.Idle and bit lpbk_master_frc_set…
8679 … used when loopback is in Gen2 rate. Notes that for Gen1 the TX deemphasis is always set to -3.5db.
8682 … (0x1<<0) // Software LTSSM Enable. Setting this bit to '1' allows softw…
8684 … (0x1<<1) // Software LTSSM Delay Start. When this bit is set together wit…
8686 …bit updates the internal software LTSSM state with the state specified by sw_ltssm_topst and sw_lt…
8688 … (0x1<<3) // LTSSM Timeout Disable. When this bit …
8689 …CIEIP_REG_PL_SW_LTSSM_CTL_LTSSM_TMOUT_DIS_BB_SHIFT 3
8692 …-level State. This field specifies the state of the sub-level state machine that software wants LT…
8696 … (0x1ff<<20) // Software LTSSM Top-level State. This field specifies the state of th…
8700 … (0x1<<31) // Software LTSSM Internal Enable. This bit reflects the intern…
8703 …bit to '1' enables the PCIE statistic collection. Hardware will count various things such as the n…
8707 …ar the pcie_statis_ena bit to stop the operation. When it is set to a non-zero value, hardware aut…
8737 …bit to '1' enables the LTSSM statisic collection. When this bit is reset to '0', information is fr…
8739 … (0x1<<1) // LTSSM Statistic Auto Increment. When this bit is set to '1', hard…
8749 … (0xffff<<0) // Equalization Phase 3 Time. This field contains the time that LTSSM spent in Equ…
8775 … (0x7f<<8) // For lane 13 in a multi-lane system: The numb…
8777 … (0x1<<15) // For lane 13 in a multi-lane system: Set by t…
8783 … (0x7f<<24) // For lane 15 in a multi-lane system: The numb…
8785 … (0x1<<31) // For lane 15 in a multi-lane system: Set by t…
8792 … (0x7f<<8) // For lane 9 in a multi-lane system: The numb…
8794 … (0x1<<15) // For lane 9 in a multi-lane system: Set by t…
8800 … (0x7f<<24) // For lane 11 in a multi-lane system: The numb…
8802 … (0x1<<31) // For lane 11 in a multi-lane system: Set by t…
8809 … (0x7f<<8) // For lane 5 in a multi-lane system: The numb…
8811 … (0x1<<15) // For lane 5 in a multi-lane system: Set by t…
8817 … (0x7f<<24) // For lane 7 in a multi-lane system: The numb…
8819 … (0x1<<31) // For lane 7 in a multi-lane system: Set by t…
8826 … (0x7f<<8) // For lane 1 in a multi-lane system: The numb…
8828 … (0x1<<15) // For lane 1 in a multi-lane system: Set by t…
8834 … (0x7f<<24) // For lane 3 in a multi-lane system: Th…
8836 … (0x1<<31) // For lane 3 in a multi-lane system: Se…
8843 … (0x7f<<8) // For lane 13 in a multi-lane system: The numb…
8845 … (0x1<<15) // For lane 13 in a multi-lane system: Set by t…
8851 … (0x7f<<24) // For lane 15 in a multi-lane system: The numb…
8853 … (0x1<<31) // For lane 15 in a multi-lane system: Set by t…
8860 … (0x7f<<8) // For lane 9 in a multi-lane system: The numb…
8862 … (0x1<<15) // For lane 9 in a multi-lane system: Set by t…
8868 … (0x7f<<24) // For lane 11 in a multi-lane system: The numb…
8870 … (0x1<<31) // For lane 11 in a multi-lane system: Set by t…
8877 … (0x7f<<8) // For lane 5 in a multi-lane system: The numb…
8879 … (0x1<<15) // For lane 5 in a multi-lane system: Set by t…
8885 … (0x7f<<24) // For lane 7 in a multi-lane system: The numb…
8887 … (0x1<<31) // For lane 7 in a multi-lane system: Set by t…
8894 … (0x7f<<8) // For lane 1 in a multi-lane system: The numb…
8896 … (0x1<<15) // For lane 1 in a multi-lane system: Set by t…
8902 …B (0x7f<<24) // For lane 3 in a multi-lane system: Th…
8904 …BB (0x1<<31) // For lane 3 in a multi-lane system: Se…
8918 … (0xff<<24) // Count of recognized FTSOS 3 Rx_L0s ago
8939 … (0xff<<0) // Gen2 Debug History - current. Changes are…
8945 … (0xff<<24) // Gen2 Debug History 3 transitions ago (see…
8957 … (0xff<<0) // Recovery History - current. Changes are…
8963 … (0xff<<24) // Recovery History 3 transitions ago (see…
8999 … (0xff<<24) // LTSSM state 3 transitions in the p…
9015 …) // The current state of the ATE loopback SM tracker: b00011 : IDLE state - not active b00101 : …
9030 …_SET_GEN3_ERR_BAD_EDB_BB (0x1<<3) // Badly formed or …
9031 …CIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_EDB_BB_SHIFT 3
9062 …_ILLEGAL_EDSOS_BB (0x1<<19) // This bit is set to '1' when …
9066 … 0x001d38UL //Access:R DataWidth:0x20 // PHY Debug - Polling Compliance s…
9067 … 0x001d3cUL //Access:R DataWidth:0x20 // PHY Debug - Equalization signals
9158 …G_3_BB (0xff<<24) // SED Extended Configuration 3.
9188 … (0xf<<16) // The state of the clock PM state machine and perstb 3 transitions in the p…
9248 … (0x1<<0) // Instantaneous value of the top-level user_allow_gen3…
9253 … (0xffff<<0) // Vendor ID. For SR-IOV VFs always 0xFFFF.
9255 … (0xffff<<16) // Device ID. For SR-IOV VFs always 0xFFFF.
9258 …ENDOR_ID_K2 (0xffff<<0) // Vendor ID. PCI-SIG assigned Manufact…
9263 …E_E5 (0x1<<0) // VF read-only zero.
9265 …E_E5 (0x1<<1) // VF read-only zero.
9267 …bit is not set, the request is discarded. A interrupt will be generated setting the SPEM()_PF()_DB…
9269 …SE_E5 (0x1<<3) // Special cycle en…
9270 …CIEIP_VF_REG_PCIEEPVF_CMD_SCSE_E5_SHIFT 3
9281 … (0x1<<9) // Fast back-to-back transaction ena…
9283 …S_E5 (0x1<<10) // VF read-only zero.
9289 … (0x1<<19) // INTx status. Not applicable for SR-IOV. Hardwired to 0.
9295 … (0x1<<23) // Fast back-to-back capable. Not ap…
9312 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9314 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9318 …ND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_K2 (0x1<<3) // Special Cycle En…
9319 …CIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_K2_SHIFT 3
9352 …_ERR_K2 (0x1<<30) // Fatal or Non-Fatal Error Message s…
9359 … (0xff<<8) // Read-only copy of the asso…
9361 … (0xff<<16) // Read-only copy of the asso…
9363 … (0xff<<24) // Read-only copy of the asso…
9375 … (0xff<<0) // Read-only copy of the asso…
9381 … (0x1<<23) // Read-only copy of the asso…
9397 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
9400 …E_K2 (0x3<<1) // BAR0 32-bit or 64-bit.
9402 …0_PREFETCH_K2 (0x1<<3) // BAR0 Prefetchabl…
9403 …CIEIP_VF_REG_VF_BAR0_REG_BAR0_PREFETCH_K2_SHIFT 3
9407 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
9410 …E_K2 (0x3<<1) // BAR1 32-bit or 64-bit.
9412 …1_PREFETCH_K2 (0x1<<3) // BAR1 Prefetchabl…
9413 …CIEIP_VF_REG_VF_BAR1_REG_BAR1_PREFETCH_K2_SHIFT 3
9417 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
9420 …E_K2 (0x3<<1) // BAR2 32-bit or 64-bit.
9422 …2_PREFETCH_K2 (0x1<<3) // BAR2 Prefetchabl…
9423 …CIEIP_VF_REG_VF_BAR2_REG_BAR2_PREFETCH_K2_SHIFT 3
9427 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
9430 …E_K2 (0x3<<1) // BAR3 32-bit or 64-bit.
9432 …3_PREFETCH_K2 (0x1<<3) // BAR3 Prefetchabl…
9433 …CIEIP_VF_REG_VF_BAR3_REG_BAR3_PREFETCH_K2_SHIFT 3
9437 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
9440 …E_K2 (0x3<<1) // BAR4 32-bit or 64-bit.
9442 …4_PREFETCH_K2 (0x1<<3) // BAR4 Prefetchabl…
9443 …CIEIP_VF_REG_VF_BAR4_REG_BAR4_PREFETCH_K2_SHIFT 3
9447 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
9450 …E_K2 (0x3<<1) // BAR5 32-bit or 64-bit.
9452 …5_PREFETCH_K2 (0x1<<3) // BAR5 Prefetchabl…
9453 …CIEIP_VF_REG_VF_BAR5_REG_BAR5_PREFETCH_K2_SHIFT 3
9459 … (0xffff<<0) // Read-only copy of the asso…
9461 … (0xffff<<16) // Read-only copy of the asso…
9464 …tem Vendor ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9466 …tem Device ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9469 … (0x1<<0) // Read-only copy of the asso…
9471 … (0x1fff<<19) // Read-only copy of the asso…
9480 … (0xff<<0) // VF's read-only zeros.
9482 … (0xff<<8) // VF's read-only zeros.
9484 … (0xff<<16) // VF's read-only zeros.
9486 … (0xff<<24) // VF's read-only zeros.
9496 … (0xff<<8) // Next capability pointer. Points to the MSI-X capabilities by def…
9498 …_E5 (0xf<<16) // Read-only copy of the asso…
9500 … (0xf<<20) // Read-only copy of the asso…
9502 … (0x1<<24) // Read-only copy of the asso…
9504 … (0x1f<<25) // Read-only copy of the asso…
9515 …emented Valid. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9522 … (0x7<<0) // Read-only copy of the asso…
9524 …_E5 (0x3<<3) // Read-only copy of the…
9525 …CIEIP_VF_REG_PCIEEPVF_DEV_CAP_PFS_E5_SHIFT 3
9526 … (0x1<<5) // Read-only copy of the asso…
9528 … (0x7<<6) // Read-only copy of the asso…
9530 … (0x7<<9) // Read-only copy of the asso…
9532 … (0x1<<15) // Read-only copy of the asso…
9538 … (0x1<<28) // Function level reset capability. Set to 1 for SR-IOV core.
9543 …ILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_K2 (0x3<<3) // Phantom Function…
9544 …CIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_K2_SHIFT 3
9545 …eld Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9551 …_PCIE_CAP_ROLE_BASED_ERR_REPORT_K2 (0x1<<15) // Role-based Error Reporting…
9566 …F_DEV_CTL_UR_EN_E5 (0x1<<3) // VF RsvdP.
9567 …CIEIP_VF_REG_PCIEEPVF_DEV_CTL_UR_EN_E5_SHIFT 3
9584 …e receive any of the errors in PCIEEPVF()_COR_ERR_STAT, for example a replay-timer timeout. Also,…
9590 …ests are nonfatal errors, so [UR_D] should cause [NFE_D]. Receiving a vendor-defined message shoul…
9592 …D_E5 (0x1<<20) // VF's read-only zeros.
9599 …_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2 (0x1<<1) // Non-fatal Error Reporting…
9603 …OL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_K2 (0x1<<3) // Unsupported Requ…
9604 …CIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_K2_SHIFT 3
9609 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
9611 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
9613 …PM_EN_K2 (0x1<<10) // Aux Power PM Enable. This bit is derived by sampl…
9615 …(0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R
9623 …STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2 (0x1<<17) // Non-Fatal Error Detected …
9629 …ED_K2 (0x1<<20) // Aux Power Detected Status. This bit is derived by sampl…
9634 … (0xf<<0) // Read-only copy of the asso…
9636 … (0x3f<<4) // Read-only copy of the asso…
9638 …5 (0x3<<10) // Read-only copy of the asso…
9640 … (0x7<<12) // Read-only copy of the asso…
9642 … (0x7<<15) // Read-only copy of the asso…
9644 … (0x1<<18) // Read-only copy of the asso…
9646 … (0x1<<19) // Read-only copy of the asso…
9648 …5 (0x1<<20) // Read-only copy of the asso…
9650 … (0x1<<21) // Read-only copy of the asso…
9652 … (0x1<<22) // Read-only copy of the asso…
9654 … (0xff<<24) // Read-only copy of the asso…
9657 …D_K2 (0xf<<0) // Maximum Link Speed. In M-PCIe mode, the reset …
9659 …_K2 (0x3f<<4) // Maximum Link Width. In M-PCIe mode, the reset …
9663 …bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) deter…
9665 …bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) deter…
9667 …er Management. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9675 … ASPM Optionality Compliance. Note: The access attributes of this field are as follows: - Dbi: R
9682 …F_LINK_CTL_RCB_E5 (0x1<<3) // VF RsvdP.
9683 …CIEIP_VF_REG_PCIEEPVF_LINK_CTL_RCB_E5_SHIFT 3
9696 … (0x1<<10) // Link bandwidth management interrupt enable. This bit is not applicable a…
9698 … (0x1<<11) // Link autonomous bandwidth interrupt enable. This bit is not applicable a…
9702 …bit location in the supported link speeds vector (in the link capabilities 2 register) that corres…
9719 …_LINK_STATUS_REG_PCIE_CAP_RCB_K2 (0x1<<3) // Read Completion …
9720 …CIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_K2_SHIFT 3
9721 …_LINK_CTRL_OFF. Note: The access attributes of this field are as follows: - Dbi: CX_CROSSLINK_EN…
9723 …e Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description
9729 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9733 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9735 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9743 …figuration or Recovery State. Note: The access attributes of this field are as follows: - Dbi: R
9745 …Configuration. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9749 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9751 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9762 …_E5 (0x1<<7) // 32-bit AtomicOp supported.…
9764 …_E5 (0x1<<8) // 64-bit AtomicOp supported.…
9766 …_E5 (0x1<<9) // 128-bit AtomicOp supported.…
9768 … (0x1<<10) // No RO-enabled PR-PR passing. (This bit appl…
9776 …PL_SUPP_E5 (0x1<<16) // 10-bit tag completer suppo…
9778 …EQ_SUPP_E5 (0x1<<17) // 10-bit tag requestor suppo…
9784 …5 (0x1<<21) // End-end TLP prefix suppor…
9786 … (0x3<<22) // Read-only copy of the asso…
9797 …EG_PCIE_CAP_32_ATOMIC_CPL_SUPP_K2 (0x1<<7) // 32 Bit AtomicOp Completer …
9799 …EG_PCIE_CAP_64_ATOMIC_CPL_SUPP_K2 (0x1<<8) // 64 Bit AtomicOp Completer …
9801 …G_PCIE_CAP_128_CAS_CPL_SUPP_K2 (0x1<<9) // 128 Bit CAS Completer Suppo…
9803 …O_EN_PR2PR_PAR_K2 (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
9807 …CIE_CAP_TPH_CMPLT_SUPPORT_0_K2 (0x1<<12) // TPH Completer Supported Bit 0.
9809 …CIE_CAP_TPH_CMPLT_SUPPORT_1_K2 (0x1<<13) // TPH Completer Supported Bit 1.
9828 …EQ_EN_E5 (0x1<<12) // 10-bit tag requestor enabl…
9832 … (0x1<<15) // Unsupported end-end TLP prefix blocki…
9854 … (0x7f<<1) // Read-only copy of the asso…
9867 …DRS Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9870 …TLS_E5 (0xf<<0) // VF's read-only zeros.
9872 …EC_E5 (0x1<<4) // VF's read-only zeros.
9874 …HASD_E5 (0x1<<5) // VF's read-only zeros.
9876 …SDE_E5 (0x1<<6) // VF's read-only zeros.
9878 …TM_E5 (0x7<<7) // VF's read-only zeros.
9880 …MC_E5 (0x1<<10) // VF's read-only zeros.
9882 …SOS_E5 (0x1<<11) // VF's read-only zeros.
9884 …DE_E5 (0xf<<12) // VF's read-only zeros.
9886 … (0x1<<16) // Read-only copy of the asso…
9894 … (0x1<<20) // Equalization phase 3 successful
9909 …ET_LINK_SPEED_K2 (0xf<<0) // Target Link Speed. In M-PCIe mode, the conten…
9913 …Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9915 …SEL_DEEMPHASIS_K2 (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. …
9919 …ed Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9921 … transmission. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9923 … // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The access attributes of thi…
9925 … (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is alwa…
9933 …_P3_K2 (0x1<<20) // Equalization 8.0GT/s Phase 3 Successful. Note: …
9942 …NTRL_MSIXCID_E5 (0xff<<0) // MSI-X capability ID.
9946 … (0x7ff<<16) // MSI-X table size encoded as (table size - 1)…
9948 …ask bit determines whether the vector is masked or not. 1 = All vectors associated with the funct…
9950 …X_CAP_CNTRL_MSIXEN_E5 (0x1<<31) // MSI-X enable.
9952 … 0x0000b0UL //Access:RW DataWidth:0x20 // MSI-X Capability ID, Next…
9953 …NEXT_CTRL_REG_PCI_MSIX_CAP_ID_K2 (0xff<<0) // MSI-X Capability ID.
9955 …TRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2 (0xff<<8) // MSI-X Next Capability Poi…
9957 …-X Table Size. SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PC…
9959 …(0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W
9961 … (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are…
9964 …BIR_E5 (0x7<<0) // Read-only copy of the asso…
9966 …FS_E5 (0x1fffffff<<3) // Read-only copy of the…
9967 …CIEIP_VF_REG_PCIEEPVF_MSIX_TABLE_MSIXTOFFS_E5_SHIFT 3
9968 … 0x0000b4UL //Access:R DataWidth:0x20 // MSI-X Table Offset and BI…
9969 …_PCI_MSIX_BIR_K2 (0x7<<0) // MSI-X Table Bar Indicator…
9971 …_PCI_MSIX_TABLE_OFFSET_K2 (0x1fffffff<<3) // MSI-X Table Offset.
9972 …CIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_K2_SHIFT 3
9974 …R_E5 (0x7<<0) // Read-only copy of the asso…
9976 … (0x1fffffff<<3) // MSI-X table offset register. Base address of …
9977 …CIEIP_VF_REG_PCIEEPVF_MSIX_PBA_MSIXPOFFS_E5_SHIFT 3
9978 … 0x0000b8UL //Access:R DataWidth:0x20 // MSI-X PBA Offset and BIR …
9979 …OFFSET_REG_PCI_MSIX_PBA_K2 (0x7<<0) // MSI-X PBA BIR.
9981 …_PCI_MSIX_PBA_OFFSET_K2 (0x1fffffff<<3) // MSI-X PBA Offset.
9982 …CIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_K2_SHIFT 3
9991 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9993 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9995 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10031 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10033 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10035 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10046 … (0x1<<9) // Steering Tag Table Location bit 0
10048 … (0x1<<10) // Steering Tag Table Location bit 1
10052 …orm a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10061 …BLE_LOC_0_K2 (0x1<<9) // ST Table Location Bit 0. Note: This reg…
10063 …LE_LOC_1_K2 (0x1<<10) // ST Table Location Bit 1. Note: This reg…
10070 …EN_E5 (0x3<<8) // TPH Requestor Enable bit.
10073 …(0x7<<0) // ST Mode Select. Note: The access attributes of this field are as follows: - Dbi: R/W
10075 …REG_TPH_REQ_CTRL_REQ_EN_K2 (0x3<<8) // TPH Requester Enable Bit.
10083 … 0 Lower Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
10085 … 0 Upper Byte. Note: The access attributes of this field are as follows: - Dbi: this field is R…
10101 …P_CTL_CR_E5 (0x1<<3) // ACS P2P completi…
10102 …CIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_CR_E5_SHIFT 3
10127 …Bit 0 is interpreted as BAR enable when writing to the BAR mask register rather than as a mask bit…
10131 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10132 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10134 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10137 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10138 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10140 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10143 …Bit 0 is interpreted as BAR enable when writing to the BAR mask register rather than as a mask bit…
10149 …Bit 0 is interpreted as BAR enable when writing to the BAR mask register rather than as a mask bit…
10153 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10154 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10156 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10159 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10160 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10162 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10165 …Bit 0 is interpreted as BAR enable when writing to the BAR mask register rather than as a mask bit…
10169 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10170 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: if RO…
10172 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: if RO…
10174 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10175 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10177 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10180 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10182 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10184 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10185 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10187 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10189 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10190 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10192 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10194 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10195 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10197 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10199 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10200 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10202 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10204 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10205 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10207 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10209 …he assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge)…
10210 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10212 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10219 … (0x1<<0) // This bit masks, when set, the Interrupt bit: S…
10230 … (0x1<<0) // This bit masks, when set, the Parity bit: SE…
10232 … (0x1<<1) // This bit masks, when set, the Parity bit: SE…
10234 … (0x1<<2) // This bit masks, when set, the Parity bit: SE…
10236 … (0x1<<3) // This bit masks, when set, the Parity bi…
10237 …EM_FAST_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_E5_SHIFT 3
10238 … (0x1<<4) // This bit masks, when set, the Parity bit: SE…
10240 … (0x1<<5) // This bit masks, when set, the Parity bit: SE…
10242 … (0x1<<6) // This bit masks, when set, the Parity bit: SE…
10244 … (0x1<<7) // This bit masks, when set, the Parity bit: SE…
10246 … (0x1<<0) // This bit masks, when set, the Parity bit: SE…
10248 … (0x1<<1) // This bit masks, when set, the Parity bit: SE…
10250 … (0x1<<2) // This bit masks, when set, the Parity bit: SE…
10252 … (0x1<<3) // This bit masks, when set, the Parity bi…
10253 …EM_FAST_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_SHIFT 3
10254 … (0x1<<4) // This bit masks, when set, the Parity bit: SE…
10256 … (0x1<<5) // This bit masks, when set, the Parity bit: SE…
10258 … (0x1<<6) // This bit masks, when set, the Parity bit: SE…
10290 …-only access of the GPRE registers. Register can be accessed only when storm is stalled. Address b…
10292 … 0x000480UL //Access:R DataWidth:0x20 // 15-0 STORM0 GPRE0 bits 15:0. 31-16 STOR…
10293 …- misc_local_mux_other_stall, 20 - ram_mux_bkpt_stall, 19 - mux_lock_stall, 18 - pram_mux_pipe_st…
10298 …ether or not the Storm is currently stalled. bit0- STORM A. bit1- STORM B. bit2- Pram Breakpoint. …
10303 …R DataWidth:0xf // This register delivers the PRAM address for the low-word instruction that…
10304 … DataWidth:0xf // This register delivers the PRAM address for the high-word instruction that…
10307 …s that the PortID will be taken as a single bit , a value of 2 means that the PortID will be taken…
10308 …efines the offset (in bits) from the lsb of the CID in which to assign to bit-0 of the port ID. I.…
10309 …dth:0x1 // Defines the Storm register file set that is currently active. 0 - STORM A 1 - STORM B
10310 …- DRA WR STM Core_A, 3:5 - DRA WR STM Core_B, 6:8 - DRA RD STM Core_A, 9:11 - DRA RD STM Core_B, …
10313 …bit in the data field will result in a corresponding bit inversion in the written data while ECC i…
10315 …th:0x20 // This register delivers the Storm PC for read-only debug access. 15-0 - STORM A. 31-16…
10316 …e access type defined in data_breakpoint_access_set), the STORMs bits 15:0 - IRAM stall start add…
10317 …efined in data_breakpoint_access_set), the STORMs will be stalled. bit15:0 - IRAM stall end addre…
10318 …- stall on read access. bit1 - stall on write access. bit3:2 - stall on write BE (bit2 -to IRAM'…
10319 …er defines the IRAM address for which the data breakpoint stall was set. bits 0:15 - IRAM address.
10323 … indirect registers defines the modulus (roll-over) values for the corresponding real time clocks.…
10326 …-time clock with regard to the associated RTClkTickValue. The Storm decode assignments used for th…
10329 …-time clocks. This value is assigned to the corresponding real-time clock only when the Storm corr…
10332 …-time clock with the value provided by the associated RTClkInitValue register. The Storm decode as…
10335 …direct registers provides read access to the real time clock values. The sub-address for this indi…
10337 … vector containing a bit per RTC used to enable each of the ten real-time clocks. The bit index co…
10346 …ad request issued. The data returned is defined as follows: cam_rd_data_msb[3:0] = cam_read_data[6…
10347 …is register delivers the valid bit from CAM for the most recent RBC read request issued. The valid…
10350 … (0x1<<0) // Writing a one to this register bit (transition from 0 …
10352 … (0x1<<1) // When set, this bit enables hit parity …
10354 … (0x1<<2) // When set, this bit enables miss parity…
10357 …0x20 // This array of registers returns the 128-bit CAM match vector returned in the most recent…
10360 …-PRINTF; 0x1-PRAM address; 0x2-Reserved; 0x3-DRA read + DRA write; 0x4-load/store address; 0x5-fas…
10361 …ollowing debug sources for modes 2 and 3 on the fast debug channel: b0-DRA write disable; b1-DRA r…
10362 …able any of the following debug sources for mode-4 on the fast debug channel: b0-store data disabl…
10363 …ces for mode-6 on the fast debug channel: b0-dra_in disable; b1-fin disable; b2-load disable; b3-t…
10364 …0 // Connection id that should compared with cid field of the data (in Dra-In message); Note: ap…
10365 …aWidth:0x8 // Event id that should compared with event id field of the data (in Dra-In message).
10366 …//Access:RW DataWidth:0x8 // Mask for event id. 1- specified bit is ignored; 0 - specified bi…
10367 …e event ID range filter. A range of event IDs to capture for fast debug mode-6 and for active stat…
10368 …e event ID range filter. A range of event IDs to capture for fast debug mode-6 and for active stat…
10370 …- Filter off; in that case all data should be transmitted to the DBG block without any filtering i…
10372 …- use the recorded connection id field which arrives from the DBG block (dbg_sem_cid interface) fo…
10374 …ABLE_REC_FILTER_CID_EN (0x1<<3) // Used to enable C…
10375 …EM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_CID_EN_SHIFT 3
10378 … (0x3<<5) // Used to define the DRA-In source that should…
10388 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
10402 … (0x3<<2) // Used to define the DRA-In source that should…
10408 … 0x000a44UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10409 … 0x000a44UL //Access:RC DataWidth:0x20 // Statistics - The accumulated numb…
10411 … 0x000a4cUL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10412 … 0x000a4cUL //Access:RC DataWidth:0x20 // Statistics - The accumulated numb…
10413 … 0x000a50UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10414 …- The accumulated number of Storm cycles in which the Storm has been idle due to having no threads…
10415 … 0x000a54UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10416 … 0x000a54UL //Access:RC DataWidth:0x20 // Statistics - The accumulated numb…
10417 … 0x000a58UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10418 … 0x000a5cUL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10419 … 0x000a60UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10420 … 0x000a64UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10425 …- response is ready. It is set when response cycle of 32 bit is ready from VFC block. It is reset …
10429 … 0x000c4cUL //Access:R DataWidth:0x20 // Provides read-only access to the BI…
10434 … lsb=0=>read from bits 31:0; otherway from bits 63:32. Upper bit 9 selects the RF. Upper bit 10 se…
10437 …-address. Bits [3:0] of the data bus provide the OpCode for the request where the following numera…
10439 … 0x00a000UL //Access:RW DataWidth:0x20 // Provides a memory-mapped region for VFC…
10441 …quished). If lsb bit of addr = 0 => write to lock ID of addr[3:1] LOCK_VAL[31:0] if lsb bit of ad…
10447 … 0x020000UL //Access:RW DataWidth:0x20 // Internal RAM (if bit lsb of addr =0 => w…
10450 … that are used for search and add commands. 1 means the corresponding data bit should be compared …
10451 … that are used for search and add commands. 1 means the corresponding data bit should be compared …
10452 … that are used for search and add commands. 1 means the corresponding data bit should be compared …
10453 … that are used for search and add commands. 1 means the corresponding data bit should be compared …
10454 …k that are used for search and add commands.1 means the corresponding data bit should be compared …
10455 … that are used for search and add commands. 1 means the corresponding data bit should be compared …
10456 …k that are used for search and add commands.1 means the corresponding data bit should be compared …
10457 … that are used for search and add commands. 1 means the corresponding data bit should be compared …
10458 …ister includes bit per ALU vector: 0-4 long vectors; 5-11 short vectors. When it is set then appro…
10461 …asserted when there is attempt to write to read only register. It will be de-asserted aftre write …
10467 …_INTERRUPT (0x1<<3) // This is error in…
10468 …FC_REG_INTERRUPT_IND_INP_BUF_INTERRUPT_SHIFT 3
10471 …d with address not equal to 12 bit or data cycle not equal 64 bit or number of data cycles bigger …
10473 …asserted when waitp is asserted and output FIFO is also full. It will be de-asserted aftre write …
10475 …asserted when it was address overflow of INFO part of RSS RAM. It will be de-asserted aftre write …
10477 …ted when it was address overflow of KEY LSB part of RSS RAM. It will be de-asserted aftre write …
10479 …erted when it was address overflow of KEY MSB part of RSS RAM. It will be de-asserted aftre write …
10482 …ty interrupt. It may be asserted when it was CAM parity error. It will be de-asserted aftre write …
10484 …pt. It may be asserted when it was parity error inside TT RAM. It will be de-asserted aftre write …
10486 …terrupt. It may be asserted when it was RSS RAM parity error. It will be de-asserted aftre write …
10495 …_EMPTY (0x1<<3) // Empty indication…
10496 …FC_REG_INDICATIONS1_OUT_FIFO_EMPTY_SHIFT 3
10532 … 0x000038UL //Access:W DataWidth:0x1 // Write to this bit will cause to block…
10534 …bit will cause reset of all CAM rows including valid bit and all bits in a row. Write 0 to it will…
10536 …bit will cause reset of all Target tables rows. Write 0 to it will have no effect. Read 1 from thi…
10538 …bit will cause reset of all RSS RAM rows. Write 0 to it will have no effect. Read 1 from this bit …
10540 …Width:0x1 // REQUIRED -If this bit is set then background mechanism for parity check will be en…
10542 … 0x000048UL //Access:RW DataWidth:0x3 // REQUIRED - 0 - parity is enabled;…
10543 … 0x00004cUL //Access:RW DataWidth:0xa // REQUIRED - 0 - interrupt is enabled;1- interr…
10548 … 0x000060UL //Access:RW DataWidth:0x1 // Bist enable bit for Cam.
10553 …allow for RBC to configurate block. STORM command may be executed when this bit will be deasserted.
10556 …UL //Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_…
10557 …UL //Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_…
10561 …PTY (0x1<<3) // Empty indication…
10562 …FC_REG_DEBUG_DATA_CUR_MSG_EMPTY_SHIFT 3
10597 … 0x000104UL //Access:R DataWidth:0x9 // Last analyze offset for ALU vector 3.
10602 … 0x000118UL //Access:RW DataWidth:0x1 // If this bit set to 0 then allow…
10607 … (0x1<<0) // This bit masks, when set, the Parity bit: VF…
10609 … (0x1<<1) // This bit masks, when set, the Parity bit: VF…
10611 … (0x1<<2) // This bit masks, when set, the Parity bit: VF…
10613 … (0x1<<5) // This bit masks, when set, the Parity bit: VF…
10615 … (0x1<<3) // This bit masks, when set, the Parity bi…
10616 …FC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_E5_SHIFT 3
10617 … (0x1<<4) // This bit masks, when set, the Parity bit: VF…
10619 … (0x1<<0) // This bit masks, when set, the Parity bit: VF…
10621 … (0x1<<1) // This bit masks, when set, the Parity bit: VF…
10623 … (0x1<<2) // This bit masks, when set, the Parity bit: VF…
10625 … (0x1<<3) // This bit masks, when set, the Parity bi…
10626 …FC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT 3
10627 … (0x1<<4) // This bit masks, when set, the Parity bit: VF…
10629 … (0x1<<2) // This bit masks, when set, the Parity bit: VF…
10666 … (0x1<<3) // Parameter FIFO e…
10667 …B_REG_INT_STS_PFIFO_ERROR_SHIFT 3
10679 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
10681 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
10683 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
10685 … (0x1<<3) // This bit masks, when set, the Interrupt …
10686 …B_REG_INT_MASK_PFIFO_ERROR_SHIFT 3
10687 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
10689 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
10691 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
10693 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
10695 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
10704 … (0x1<<3) // Parameter FIFO e…
10705 …B_REG_INT_STS_WR_PFIFO_ERROR_SHIFT 3
10723 …R (0x1<<3) // Parameter FIFO e…
10724 …B_REG_INT_STS_CLR_PFIFO_ERROR_SHIFT 3
10736 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
10745 …BLE (0x1<<3) // Disables EOP che…
10746 …B_REG_CONTROL_EOP_CHECK_DISABLE_SHIFT 3
10757 …ived on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
10759 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
10760 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
10761 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
10762 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
10763 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
10764 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
10765 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
10766 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
10767 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
10768 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
10769 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
10770 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
10781 …bit of this register. Bits 31:29 provide additional information about the instruction. Bit 31 in…
10783 …er being executed at the time EOP error is detected. The task passthrough bit is not kept and is …
10791 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
10792 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
10793 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
10794 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
10795 … 0x002000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
10800 …5 (0xff<<0) // 8-bit value from package …
10802 … (0xff<<8) // 8-bit value from package …
10814 …CONFIG_MACCC_RSV3_K2_E5 (0x1<<3) // reserved
10815 …TH_MAC_REG_COMMAND_CONFIG_MACCC_RSV3_K2_E5_SHIFT 3
10820 …o '0' (Reset value), the CRC field is stripped from the frame. Note - If padding (Bit PAD_EN set t…
10832 …5 (0x1<<12) // Self-Clearing Software Res…
10860 …_K2_E5 (0x1<<26) // Self-Clearing TX FIFO rese…
10913 … (0x1<<5) // MDIO transaction preamble disable. Shortens transaction but is non-standard.
10924 … (0x1<<14) // If written with 1, a read with address post-increment will be performed. Post-incr…
10929 …-bit data word. When written- Initiates a write transaction to the PHY. The MDIO_COMMAND register …
10931 …PHY device to read from or write to. After writing this register, an address-write transaction wil…
10939 … (0x1<<2) // PHY indicates loss-of-signal. Represents v…
10941 …3) // Transmit Timestamp Available. Indicates that the timestamp of the last transmitted 1588 even…
10942 …TH_MAC_REG_STATUS_TS_AVAIL_K2_E5_SHIFT 3
10959 …E5 (0x1<<0) // Credit-based FIFO only: When…
10962 …5 (0xff<<0) // Credit-based FIFO only: Spec…
10970 …C quanta value for that class when a class XOFF is triggered. Each Quanta specifies a 512 bit-time.
10972 … 0x000058UL //Access:RW DataWidth:0x20 // Class 2 and 3 pause quanta
10992 … 0x000068UL //Access:RW DataWidth:0x20 // Class 2 and 3 refresh threshold
10997 … 0x00006cUL //Access:RW DataWidth:0x20 // Class 2 and 3 refresh threshold
11008 … (0xff<<0) // Status bit for software to read the current received pause sta…
11012 … (0x1<<0) // Enable XGMII-64 (4byte alignment)
11016 … (0x1<<5) // Enable 1-step capable datapath…
11019 …/ Configure saturation behavior. When set to 1, the counters saturate at all-1. Otherwise counters…
11021 … (0x1<<1) // Configure clear-on-read behavior. When …
11023 … (0x1<<2) // Clear all counters command (self-clearing). When writt…
11025 … 0x0000e4UL //Access:RW DataWidth:0x20 // Lower 32bit of 64bit value written i…
11026 … 0x0000e8UL //Access:RW DataWidth:0x20 // Upper 32bit of 64bit value written i…
11124 … 0x000384UL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11126 … 0x00038cUL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11128 … 0x000394UL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11130 … 0x00039cUL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11132 … 0x0003a4UL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11134 … 0x0003acUL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11136 … 0x0003b4UL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11138 … 0x0003bcUL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11140 … 0x0003c4UL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11142 … 0x0003ccUL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11144 … 0x0003d4UL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11146 … 0x0003dcUL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11148 … 0x0003e4UL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11150 … 0x0003ecUL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11152 … 0x0003f4UL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11154 … 0x0003fcUL //Access:R DataWidth:0x20 // Upper 32bit of 64bit counter.
11167 … (0xf<<8) // RS-FEC receive lane locked and aligned; One bit per lane: Bit 8 = lane 0, Bit 9 = l…
11169 … (0x1<<14) // Indicates, when 1 that the RS-FEC receiver has lock…
11173 …x20 // Counts number of corrected FEC codewords lower 16-bits; None roll-over when upper 16-bits…
11174 …umber of corrected FEC codewords lower 16-bits; Must be read before upper 16-bits; None roll-over …
11176 …h:0x20 // Counts number of corrected FEC codewords upper 16-bits; Clears on read; None roll-over.
11177 … (0xffff<<0) // Counts number of corrected FEC codewords upper 16-bits; None roll-over; Clears …
11179 …0 // Counts number of uncorrected FEC codewords lower 16-bits; None roll-over when upper 16-bits…
11180 …ber of uncorrected FEC codewords lower 16-bits; Must be read before upper 16-bits; None roll-over …
11182 …0x20 // Counts number of uncorrected FEC codewords upper 16-bits; Clears on read; None roll-over.
11183 … (0xffff<<0) // Counts number of uncorrected FEC codewords upper 16-bits; None roll-over; Clears …
11192 …_E5 (0x3<<6) // FEC lane mapped to PMA lane 3.
11194 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 0; None roll-over whe…
11195 … (corrected) 10-bit symbol errors found in lane 0 for correctable codewords only; Lower 16-bit of …
11197 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11198 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 0; Clears o…
11200 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 1; None roll-over whe…
11201 … (corrected) 10-bit symbol errors found in lane 1 for correctable codewords only; Lower 16-bit of …
11203 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11204 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 1; Clears o…
11206 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 2; None roll-over whe…
11207 … (corrected) 10-bit symbol errors found in lane 2 for correctable codewords only; Lower 16-bit of …
11209 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11210 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 2; Clears o…
11212 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 3; None roll-over whe…
11213 … (corrected) 10-bit symbol errors found in lane 3 for correctable codewords only; Lower 16-bit of …
11215 … //Access:R DataWidth:0x20 // Upper 16 bit of counter (with above register); Clears on read; …
11216 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 3; Clears o…
11218 … 0x000200UL //Access:RW DataWidth:0x20 // Additional control to enable RS-FEC operation.
11221 … (0x1<<15) // Indicates the operatyional outcome of the (above) enable bit control; When 1 = F…
11224 … (0xf<<0) // Per PMA lane FEC synchronization status; Bit 0=lane 0 up to Bit 3 = lane 3; Lat…
11240 … (0xf<<12) // Real-time indication from FEC deskew FIFO per lane; bit 12 = l…
11243 …er PMA lane FEC synchronization status; Realtime updates; Bit 0 = lane 0 upto bit 3 = lane 3; Cl…
11248 …W DataWidth:0x20 // Bits 7:0; Must be written with the 8-bit value of 0x57 to enable RS-FEC tr…
11249 … (0xff<<0) // Bits 7:0; Must be written with 8-bit value 0x57 to enable RS-FEC tra…
11251 … 0x000214UL //Access:RW DataWidth:0x20 // Bits 15:0. One bit per 10-bit Symbol; Each bit is ap…
11252 … (0xffff<<0) // Bits 15:0. One bit per 10-bit Symbol; When a bit is 1…
11254 … 0x000218UL //Access:RW DataWidth:0x20 // Bits 9:0; A 10-bit value which XORed w…
11255 …TEST_PATTERN_K2_E5 (0x3ff<<0) // A 10-bit value which will be…
11257 …VERWRITE_K2_E5 (0x1<<10) // If the bit is set the 10B symb…
11259 …x20 // Enable register to control the triggers with the error insertion; Bit 0 clears on operati…
11260 … (0x1<<0) // For bit 0 only, when written with 1 triggers the error insertion (on one wo…
11265 … (0x1<<8) // Indicate full-duplex operation; alw…
11279 … (0x1<<15) // PCS soft-reset command; self-clearing
11284 … (0x1<<2) // Indicate link status; latch-low
11286 …ITY_K2_E5 (0x1<<3) // Autonegotiation …
11287 …TH_PCS1G_REG_STATUS_ANEGABILITY_K2_E5_SHIFT 3
11296 …x20 // Local Device Abilities for Autonegotiation. Contents differs for 1000Base-X or SGMII mode.
11299 … (0x1<<5) // Indicate full-duplex support; SGMII…
11301 … (0x1<<6) // Indicate half-duplex support; SGMII…
11317 …/ Received Abilities during Autonegotiation. Contents differ depending on 1000Base-X or SGMII mode.
11320 … (0x1<<5) // Indicate full-duplex support; SGMII…
11322 … (0x1<<6) // Indicate half-duplex support; SGMII…
11341 … (0x1<<1) // Autoneg page received indication; latch-high
11348 … (0x1<<11) // Next Page toggle handshaking bit
11361 … (0x1<<11) // Next Page toggle handshaking bit
11378 …_E5 (0x1<<0) // Bit 0 of link timer val…
11383 … (0x1f<<0) // Link timer uppest 5 bits of 21bit timer
11392 … (0x1<<4) // Set SGMII half-duplex mode when not …
11427 …20 // PHY Identifier constant from package parameter PHY_IDENTIFIER bits 15:4. Bits 3:0 always 0.
11436 … (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-TL capable.
11440 …TY_C100G_K2_E5 (0x1<<3) // When 1, this PCS…
11441 …TH_PCS10_50G_REG_SPEED_ABILITY_C100G_K2_E5_SHIFT 3
11449 …PKG1_PCS_PRES_K2_E5 (0x1<<3) // PCS present when…
11450 …TH_PCS10_50G_REG_DEVICES_IN_PKG1_PCS_PRES_K2_E5_SHIFT 3
11468 … (0x1<<0) // When 1, this PCS is 10GBase-R capable.
11470 … (0x1<<1) // When 1, this PCS is 10GBase-X capable.
11472 … (0x1<<2) // When 1, this PCS is 10GBase-W capable.
11474 … (0x1<<3) // When 1, this PCS is 10GBase-T cap…
11475 …TH_PCS10_50G_REG_STATUS2_C10GBASE_T_K2_E5_SHIFT 3
11476 … (0x1<<4) // When 1, this PCS is 40GBase-R capable.
11478 … (0x1<<5) // When 1, this PCS is 100GBase-R capable.
11495 …_K2_E5 (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
11497 …5 (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
11499 … (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-R.
11502 … Increments each time the LPI enters the RX_WTF state indicating a wake time fault; None roll-over.
11512 … (0xff<<0) // Errored blocks counter; None roll-over.
11514 …ER_K2_E5 (0x3f<<8) // BER counter; None roll-over.
11520 … 0x000088UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11521 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11523 … 0x00008cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11524 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11526 … 0x000090UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11527 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11529 … 0x000094UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11530 … (0x3ff<<0) // 10GBase-R Test Pattern Seed A…
11532 … 0x000098UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11533 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11535 … 0x00009cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11536 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11538 … 0x0000a0UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11539 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11541 … 0x0000a4UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11542 … (0x3ff<<0) // 10GBase-R Test Pattern Seed B…
11549 …TESTPATTERN_K2_E5 (0x1<<2) // Receive test-pattern enable.
11551 …_TESTPATTERN_K2_E5 (0x1<<3) // Transmit test-pattern enab…
11552 …TH_PCS10_50G_REG_BASER_TEST_CONTROL_TX_TESTPATTERN_K2_E5_SHIFT 3
11555 …0acUL //Access:R DataWidth:0x20 // Test Pattern Error Counter; Clears on read; None roll-over.
11556 … (0xffff<<0) // Test pattern error counter; Clears on read; None roll-over.
11558 …0000b0UL //Access:R DataWidth:0x20 // BER High Order Counter of BER bits 21:6; None roll-over.
11559 … (0xffff<<0) // Bits 21:6 of BER counter; None roll-over.
11561 …00b4UL //Access:R DataWidth:0x20 // Error Blocks High Order Counter bits 21:8; None roll-over.
11562 …2_E5 (0x3fff<<0) // Bits 21:8 of Error Blocks counter; None roll-over.
11573 …IGN_STAT1_LANE3_BLOCK_LOCK_K2_E5 (0x1<<3) // Lane 3 block lock.
11574 …TH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE3_BLOCK_LOCK_K2_E5_SHIFT 3
11584 …TAT3_LANE3_MARKER_LOCK_K2_E5 (0x1<<3) // Lane 3 alignment marke…
11585 …TH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE3_MARKER_LOCK_K2_E5_SHIFT 3
11586 …00320UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 0; Clears on read; None roll-over.
11587 …_E5 (0xffff<<0) // BIP error counter lane 0; None roll-over.
11589 …00324UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 1; Clears on read; None roll-over.
11590 …_E5 (0xffff<<0) // BIP error counter lane 1; None roll-over.
11592 …00328UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 2; Clears on read; None roll-over.
11593 …_E5 (0xffff<<0) // BIP error counter lane 2; None roll-over.
11595 …0032cUL //Access:R DataWidth:0x20 // BIP Error Counter Lane 3; Clears on read; None roll-over.
11596 …_E5 (0xffff<<0) // BIP error counter lane 3; None roll-over.
11607 … 0x00064cUL //Access:R DataWidth:0x20 // Lane Channel 3 mapping bits 1:0.
11608 …_MAPPING_K2_E5 (0x3<<0) // Lane 3 mapping bits 1:0.
11616 …x20 // Vendor Specific Reg; Set the amount of data between markers. (I.e. distance of markers-1).
11617 … (0xffff<<0) // A 16-bit value defining the amount of data between markers; (dis…
11620 …HRESHOLD_K2_E5 (0xf<<0) // A 4-bit value to define the…
11622 …0010UL //Access:RW DataWidth:0x20 // Vendor Specific Reg; Define Reduced-XLAUI PMA mode using …
11623 …_K2_E5 (0x1<<0) // Enable Reduced-XLAUI PMA mode using …
11627 …LANE0_K2_E5 (0xf<<4) // Set VL (0..3) to transmit to RXLA…
11629 …LANE1_K2_E5 (0xf<<8) // Set VL (0..3) to transmit to RXLA…
11657 …038UL //Access:RW DataWidth:0x20 // Vendor Specific Reg; Marker pattern for PCS Virtual Lane 3.
11658 … (0xff<<0) // Lane 3 Marker pattern for m…
11660 … (0xff<<8) // Lane 3 Marker pattern for m…
11662 …ccess:RW DataWidth:0x20 // Vendor Specific Reg; Last byte of PCS Virtual Lane 3 marker pattern.
11663 … (0xff<<0) // Lane 3 last btye of Marker …
11668 …2_E5 (0x1<<1) // When 0 PCS 4-lane MLD function is …
11702 …20 // PHY Identifier constant from package parameter PHY_IDENTIFIER bits 15:4. Bits 3:0 always 0.
11711 … (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-TL capable.
11715 …TY_C100G_K2_E5 (0x1<<3) // When 1, this PCS…
11716 …TH_PCS10_25G_REG_SPEED_ABILITY_C100G_K2_E5_SHIFT 3
11724 …PKG1_PCS_PRES_K2_E5 (0x1<<3) // PCS present when…
11725 …TH_PCS10_25G_REG_DEVICES_IN_PKG1_PCS_PRES_K2_E5_SHIFT 3
11743 … (0x1<<0) // When 1, this PCS is 10GBase-R capable.
11745 … (0x1<<1) // When 1, this PCS is 10GBase-X capable.
11747 … (0x1<<2) // When 1, this PCS is 10GBase-W capable.
11749 … (0x1<<3) // When 1, this PCS is 10GBase-T cap…
11750 …TH_PCS10_25G_REG_STATUS2_C10GBASE_T_K2_E5_SHIFT 3
11751 … (0x1<<4) // When 1, this PCS is 40GBase-R capable.
11753 … (0x1<<5) // When 1, this PCS is 100GBase-R capable.
11770 …_K2_E5 (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
11772 …5 (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
11774 … (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-R.
11777 … Increments each time the LPI enters the RX_WTF state indicating a wake time fault; None roll-over.
11787 … (0xff<<0) // Errored blocks counter; None roll-over.
11789 …ER_K2_E5 (0x3f<<8) // BER counter; None roll-over.
11795 … 0x000088UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11796 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11798 … 0x00008cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11799 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11801 … 0x000090UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11802 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11804 … 0x000094UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11805 … (0x3ff<<0) // 10GBase-R Test Pattern Seed A…
11807 … 0x000098UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11808 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11810 … 0x00009cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11811 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11813 … 0x0000a0UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11814 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11816 … 0x0000a4UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11817 … (0x3ff<<0) // 10GBase-R Test Pattern Seed B…
11824 …TESTPATTERN_K2_E5 (0x1<<2) // Receive test-pattern enable.
11826 …_TESTPATTERN_K2_E5 (0x1<<3) // Transmit test-pattern enab…
11827 …TH_PCS10_25G_REG_BASER_TEST_CONTROL_TX_TESTPATTERN_K2_E5_SHIFT 3
11830 …0acUL //Access:R DataWidth:0x20 // Test Pattern Error Counter; Clears on read; None roll-over.
11831 … (0xffff<<0) // Test pattern error counter; Clears on read; None roll-over.
11833 …0000b0UL //Access:R DataWidth:0x20 // BER High Order Counter of BER bits 21:6; None roll-over.
11834 … (0xffff<<0) // Bits 21:6 of BER counter; None roll-over.
11836 …00b4UL //Access:R DataWidth:0x20 // Error Blocks High Order Counter bits 21:8; None roll-over.
11837 …2_E5 (0x3fff<<0) // Bits 21:8 of Error Blocks counter; None roll-over.
11851 …TAT3_LANE3_MARKER_LOCK_K2_E5 (0x1<<3) // Lane 3 alignment marke…
11852 …TH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE3_MARKER_LOCK_K2_E5_SHIFT 3
11853 …00320UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 0; Clears on read; None roll-over.
11854 …_E5 (0xffff<<0) // BIP error counter lane 0; None roll-over.
11856 …00324UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 1; Clears on read; None roll-over.
11857 …_E5 (0xffff<<0) // BIP error counter lane 1; None roll-over.
11859 …00328UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 2; Clears on read; None roll-over.
11860 …_E5 (0xffff<<0) // BIP error counter lane 2; None roll-over.
11862 …0032cUL //Access:R DataWidth:0x20 // BIP Error Counter Lane 3; Clears on read; None roll-over.
11863 …_E5 (0xffff<<0) // BIP error counter lane 3; None roll-over.
11871 …x20 // Vendor Specific Reg; Set the amount of data between markers. (I.e. distance of markers-1).
11872 … (0xffff<<0) // A 16-bit value defining the amount of data between markers; (dis…
11875 …HRESHOLD_K2_E5 (0xf<<0) // A 4-bit value to define the…
11901 …038UL //Access:RW DataWidth:0x20 // Vendor Specific Reg; Marker pattern for PCS Virtual Lane 3.
11902 … (0xff<<0) // Lane 3 Marker pattern for m…
11904 … (0xff<<8) // Lane 3 Marker pattern for m…
11906 …ccess:RW DataWidth:0x20 // Vendor Specific Reg; Last byte of PCS Virtual Lane 3 marker pattern.
11907 … (0xff<<0) // Lane 3 last btye of Marker …
11912 …2_E5 (0x1<<1) // When 0 PCS 4-lane MLD function is …
11962 …- off high-impedance 0x1 - CMU 0 0x3 - Lane 0 0x4 - Lane 1 0x5 - Lane 2 0x6 - Lane 3 0x15 - SoC ci…
11992 …OP_RESERVEDREGISTER13_RESERVEDFIELD28_K2_E5 (0x1<<3) // Reserved
11993 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER13_RESERVEDFIELD28_K2_E5_SHIFT 3
12007 …OP_RESERVEDREGISTER14_RESERVEDFIELD35_K2_E5 (0x1<<3) // Reserved
12008 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER14_RESERVEDFIELD35_K2_E5_SHIFT 3
12022 …OP_RESERVEDREGISTER15_RESERVEDFIELD42_K2_E5 (0x1<<3) // Reserved
12023 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER15_RESERVEDFIELD42_K2_E5_SHIFT 3
12037 …OP_RESERVEDREGISTER16_RESERVEDFIELD49_K2_E5 (0x1<<3) // Reserved
12038 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER16_RESERVEDFIELD49_K2_E5_SHIFT 3
12086 …OP_RESERVEDREGISTER23_RESERVEDFIELD70_K2_E5 (0x1<<3) // Reserved
12087 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER23_RESERVEDFIELD70_K2_E5_SHIFT 3
12097 …P_RESERVEDREGISTER24_RESERVEDFIELD75_K2_E5 (0x1f<<3) // Reserved
12098 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER24_RESERVEDFIELD75_K2_E5_SHIFT 3
12109 …P_RESERVEDREGISTER25_RESERVEDFIELD79_K2_E5 (0x1f<<3) // Reserved
12110 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER25_RESERVEDFIELD79_K2_E5_SHIFT 3
12126 …OP_RESERVEDREGISTER27_RESERVEDFIELD85_K2_E5 (0x1<<3) // Reserved
12127 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER27_RESERVEDFIELD85_K2_E5_SHIFT 3
12137 …P_RESERVEDREGISTER28_RESERVEDFIELD90_K2_E5 (0x1f<<3) // Reserved
12138 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER28_RESERVEDFIELD90_K2_E5_SHIFT 3
12149 …P_RESERVEDREGISTER29_RESERVEDFIELD94_K2_E5 (0x1f<<3) // Reserved
12150 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER29_RESERVEDFIELD94_K2_E5_SHIFT 3
12161 …P_RESERVEDREGISTER30_RESERVEDFIELD98_K2_E5 (0x1f<<3) // Reserved
12162 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER30_RESERVEDFIELD98_K2_E5_SHIFT 3
12173 …P_RESERVEDREGISTER31_RESERVEDFIELD102_K2_E5 (0x1f<<3) // Reserved
12174 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER31_RESERVEDFIELD102_K2_E5_SHIFT 3
12353 …OP_RESERVEDREGISTER48_RESERVEDFIELD162_K2_E5 (0x1<<3) // Reserved
12354 …HY_NW_IP_REG_PHY0_TOP_RESERVEDREGISTER48_RESERVEDFIELD162_K2_E5_SHIFT 3
12362 … (0x1<<0) // PHY error status. 0x0 - no error 0x1 - PHY has an in…
12364 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit PHY error code. 0x0 - indicates that there i…
12365 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit PHY error code. 0x0 - indicates that there i…
12382 … 0x000630UL //Access:R DataWidth:0x8 // Errored register transfer write data bit enable
12383 … 0x000680UL //Access:RW DataWidth:0x8 // lower 8-bits of the 16-bit digital tes…
12384 … 0x000684UL //Access:RW DataWidth:0x8 // higher 8-bits of the 16-bit digital tes…
12407 … 0x000818UL //Access:RW DataWidth:0x8 // Command auxiliary data or argument 3
12419 … 0x000858UL //Access:RW DataWidth:0x8 // Response auxiliary data or argument 3
14323 …0_TOP_RESERVEDREGISTER686_RESERVEDFIELD173_K2_E5 (0x1<<3) // Reserved
14324 …HY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER686_RESERVEDFIELD173_K2_E5_SHIFT 3
14398 …used in gearbox applications. 0x0 - DIV4 0x1 - DIV8 0x2 - DIV16 0x3 - DIV20 0x4 - DIV32 0x5 - DIV…
14429 …to the half-rate TX clock path to provide visibility at the TX driver output. 0x0 - mission mode …
14431 …CMU macro to all lanes macros. 0x0 - DIV1 0x1 - DIV2 0x2 - DIV4 0x3 - DIV5 0x4 - DIV8 0x5 - DIV10…
14438 …0_TOP_RESERVEDREGISTER705_RESERVEDFIELD218_K2_E5 (0x3<<3) // Reserved
14439 …HY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER705_RESERVEDFIELD218_K2_E5_SHIFT 3
14448 …0_TOP_RESERVEDREGISTER707_RESERVEDFIELD222_K2_E5 (0x3<<3) // Reserved
14449 …HY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER707_RESERVEDFIELD222_K2_E5_SHIFT 3
14463 …0_TOP_RESERVEDREGISTER710_RESERVEDFIELD228_K2_E5 (0x1<<3) // Reserved
14464 …HY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER710_RESERVEDFIELD228_K2_E5_SHIFT 3
14468 …0_TOP_RESERVEDREGISTER711_RESERVEDFIELD230_K2_E5 (0x1<<3) // Reserved
14469 …HY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER711_RESERVEDFIELD230_K2_E5_SHIFT 3
14473 … (0x1<<0) // CMU OK status. 0x0 - CMU PLL is not locked 0x1 - indica…
14477 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14478 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14480 … (0x1<<0) // CMU macro error status. 0x0 - no error 0x1 - PHY CMU macro…
14495 …0_TOP_RESERVEDREGISTER716_RESERVEDFIELD237_K2_E5 (0x1<<3) // Reserved
14496 …HY_NW_IP_REG_CMU_LC0_TOP_RESERVEDREGISTER716_RESERVEDFIELD237_K2_E5_SHIFT 3
14515 … (0x1<<0) // CMU PLL regulator vddha setting. 0x0 - vddha is 1.5V nominal 0x1 - vddha …
14539 …0_PLL_RESERVEDREGISTER723_RESERVEDFIELD254_K2_E5 (0x1<<3) // Reserved
14540 …HY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER723_RESERVEDFIELD254_K2_E5_SHIFT 3
14586 …0_PLL_RESERVEDREGISTER732_RESERVEDFIELD273_K2_E5 (0x7<<3) // Reserved
14587 …HY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER732_RESERVEDFIELD273_K2_E5_SHIFT 3
14658 …0_PLL_RESERVEDREGISTER762_RESERVEDFIELD285_K2_E5 (0x1<<3) // Reserved
14659 …HY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER762_RESERVEDFIELD285_K2_E5_SHIFT 3
14670 … (0x1<<0) // CMU PLL lock detector status. 0x0 - CMU PLL is not locked 0x1 - CMU PL…
14696 …0_PLL_RESERVEDREGISTER775_RESERVEDFIELD304_K2_E5 (0xf<<3) // Reserved
14697 …HY_NW_IP_REG_CMU_LC0_PLL_RESERVEDREGISTER775_RESERVEDFIELD304_K2_E5_SHIFT 3
14779 …0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD343_K2_E5 (0x1<<3) // Reserved
14780 …HY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER808_RESERVEDFIELD343_K2_E5_SHIFT 3
14794 …0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD350_K2_E5 (0x1<<3) // Reserved
14795 …HY_NW_IP_REG_CMU_LC0_FEATURE_RESERVEDREGISTER809_RESERVEDFIELD350_K2_E5_SHIFT 3
14841 …_TOP_RESERVEDREGISTER824_RESERVEDFIELD366_K2_E5 (0x1<<3) // Reserved
14842 …HY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER824_RESERVEDFIELD366_K2_E5_SHIFT 3
14852 …_TOP_RESERVEDREGISTER825_RESERVEDFIELD371_K2_E5 (0x1<<3) // Reserved
14853 …HY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER825_RESERVEDFIELD371_K2_E5_SHIFT 3
14877 …_TOP_RESERVEDREGISTER830_RESERVEDFIELD382_K2_E5 (0x7<<3) // Reserved
14878 …HY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER830_RESERVEDFIELD382_K2_E5_SHIFT 3
14900 …_TOP_RESERVEDREGISTER835_RESERVEDFIELD392_K2_E5 (0x1<<3) // Reserved
14901 …HY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER835_RESERVEDFIELD392_K2_E5_SHIFT 3
14905 …_TOP_RESERVEDREGISTER836_RESERVEDFIELD394_K2_E5 (0x1<<3) // Reserved
14906 …HY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER836_RESERVEDFIELD394_K2_E5_SHIFT 3
14910 … (0x1<<0) // CMU OK status. 0x0 - CMU PLL is not locked 0x1 - indica…
14914 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14915 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14917 … (0x1<<0) // CMU macro error status. 0x0 - no error 0x1 - PHY CMU macro…
14932 …_TOP_RESERVEDREGISTER841_RESERVEDFIELD401_K2_E5 (0x1<<3) // Reserved
14933 …HY_NW_IP_REG_CMU_R0_TOP_RESERVEDREGISTER841_RESERVEDFIELD401_K2_E5_SHIFT 3
14950 … (0x1<<0) // Select the reference clock. 0 - clk_ref 1- clk_pllref
14998 …MU_R0_RPLL_AFE_INT_CTRL2_CMPLL2_V2I_LPF_K2_E5 (0x1<<3) // TBD
14999 …HY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL2_CMPLL2_V2I_LPF_K2_E5_SHIFT 3
15068 …_RPLL_RESERVEDREGISTER869_RESERVEDFIELD410_K2_E5 (0x1<<3) // Reserved
15069 …HY_NW_IP_REG_CMU_R0_RPLL_RESERVEDREGISTER869_RESERVEDFIELD410_K2_E5_SHIFT 3
15105 …_RPLL_FRACN_CTRL3_RESERVEDFIELD416_K2_E5 (0xf<<3) // Reserved
15106 …HY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL3_RESERVEDFIELD416_K2_E5_SHIFT 3
15204 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
15206 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
15208 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
15210 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mis…
15211 …HY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_K2_E5_SHIFT 3
15273 …P_RESERVEDREGISTER927_RESERVEDFIELD480_K2_E5 (0x1<<3) // Reserved
15274 …HY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER927_RESERVEDFIELD480_K2_E5_SHIFT 3
15286 …a from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4…
15290 …K2_E5 (0x1<<5) // Controls tx_en for Far-End-Digital FED loopbac…
15293 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
15295 …IT_STRIP_EVEN_K2_E5 (0x1<<1) // A bit stripping selection…
15300 …P_RESERVEDREGISTER930_RESERVEDFIELD485_K2_E5 (0x1<<3) // Reserved
15301 …HY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER930_RESERVEDFIELD485_K2_E5_SHIFT 3
15305 …P_RESERVEDREGISTER931_RESERVEDFIELD487_K2_E5 (0x1<<3) // Reserved
15306 …HY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER931_RESERVEDFIELD487_K2_E5_SHIFT 3
15315 …P_RESERVEDREGISTER932_RESERVEDFIELD490_K2_E5 (0x7<<3) // Reserved
15316 …HY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER932_RESERVEDFIELD490_K2_E5_SHIFT 3
15320 …P_RESERVEDREGISTER933_RESERVEDFIELD492_K2_E5 (0x7<<3) // Reserved
15321 …HY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER933_RESERVEDFIELD492_K2_E5_SHIFT 3
15336 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
15343 …P_RESERVEDREGISTER936_RESERVEDFIELD497_K2_E5 (0x1<<3) // Reserved
15344 …HY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER936_RESERVEDFIELD497_K2_E5_SHIFT 3
15366 …P_RESERVEDREGISTER939_RESERVEDFIELD507_K2_E5 (0x1<<3) // Reserved
15367 …HY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER939_RESERVEDFIELD507_K2_E5_SHIFT 3
15388 …P_RESERVEDREGISTER943_RESERVEDFIELD516_K2_E5 (0x7<<3) // Reserved
15389 …HY_NW_IP_REG_LN0_TOP_RESERVEDREGISTER943_RESERVEDFIELD516_K2_E5_SHIFT 3
15418 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
15419 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
15421 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
15476 …R_RXCLK_RESERVEDREGISTER966_RESERVEDFIELD551_K2_E5 (0x1<<3) // Reserved
15477 …HY_NW_IP_REG_LN0_CDR_RXCLK_RESERVEDREGISTER966_RESERVEDFIELD551_K2_E5_SHIFT 3
15488 … 0x0062fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
15490 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
15497 …ce lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by set…
15556 …R_REFCLK_RESERVEDREGISTER991_RESERVEDFIELD582_K2_E5 (0x7<<3) // Reserved
15557 …HY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER991_RESERVEDFIELD582_K2_E5_SHIFT 3
15590 …R_REFCLK_RESERVEDREGISTER999_RESERVEDFIELD596_K2_E5 (0xf<<3) // Reserved
15591 …HY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER999_RESERVEDFIELD596_K2_E5_SHIFT 3
15608 …R_REFCLK_RESERVEDREGISTER1003_RESERVEDFIELD603_K2_E5 (0x3<<3) // Reserved
15609 …HY_NW_IP_REG_LN0_CDR_REFCLK_RESERVEDREGISTER1003_RESERVEDFIELD603_K2_E5_SHIFT 3
15655 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
15673 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
15677 …3) // Autoneg ability. When read as a one, it indicates that the PMA/PMD has the ability to perfo…
15678 …HY_NW_IP_REG_LN0_ANEG_STATUS0_AUTONEG_ABILITY_K2_E5_SHIFT 3
15690 …1_NP_LOADED_K2_E5 (0x1<<3) // mr_np_loaded sta…
15691 …HY_NW_IP_REG_LN0_ANEG_STATUS1_NP_LOADED_K2_E5_SHIFT 3
15696 … 0x006650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
15697 … 0x006654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
15701 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
15704 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller ge…
15708 …AGE1_ASM_DIR_K2_E5 (0x1<<3) // Pause ASM_DIR ad…
15709 …HY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_ASM_DIR_K2_E5_SHIFT 3
15720 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
15722 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
15724 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
15726 …H0_ABILITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology …
15727 …HY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT 3
15728 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
15730 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
15732 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
15734 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
15737 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
15739 …TY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR technolog…
15741 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
15743 …1_K2_E5 (0x1f<<3) // technology advertised ability Field A15…
15744 …HY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5_SHIFT 3
15746 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
15749 …TY_K2_E5 (0x1<<0) // base page bit F0. It advertises …
15751 …2_E5 (0x1<<1) // base page bit F1. It requests FE…
15753 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR…
15755 … (0x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-G…
15756 …HY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5_SHIFT 3
15758 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
15760 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
15762 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
15764 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consor…
15765 …HY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_50G_CR2_K2_E5_SHIFT 3
15766 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
15768 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
15770 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
15772 …ed FEC field 3. It requests Fire code FEC to be turned on when supported at the both ends of link…
15778 …EG_RESERVEDREGISTER1024_RESERVEDFIELD632_K2_E5 (0x1<<3) // Reserved
15779 …HY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1024_RESERVEDFIELD632_K2_E5_SHIFT 3
15797 …EG_RESERVEDREGISTER1029_RESERVEDFIELD639_K2_E5 (0x1<<3) // Reserved
15798 …HY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1029_RESERVEDFIELD639_K2_E5_SHIFT 3
15814 …EG_RESERVEDREGISTER1030_RESERVEDFIELD647_K2_E5 (0x1<<3) // Reserved
15815 …HY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1030_RESERVEDFIELD647_K2_E5_SHIFT 3
15825 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
15828 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
15832 …E_PAGE1_ASM_DIR_K2_E5 (0x1<<3) // Link partner Pau…
15833 …HY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_ASM_DIR_K2_E5_SHIFT 3
15846 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
15848 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
15850 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
15852 …ABILITY_40G_KR4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 tech…
15853 …HY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT 3
15854 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
15856 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
15858 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
15860 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
15863 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
15865 …S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or CR technolog…
15867 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
15869 …2_E5 (0x1f<<3) // Link partner technology advertised ability Fi…
15870 …HY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5_SHIFT 3
15872 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
15875 … (0x1<<0) // Link partner base page bit F0. It advertises …
15877 … (0x1<<1) // Link partner base page bit F1. It requests FE…
15879 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR…
15881 … (0x1<<3) // Link partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or…
15882 …HY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5_SHIFT 3
15884 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
15886 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
15888 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
15890 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G …
15891 …HY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_50G_CR2_K2_E5_SHIFT 3
15892 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
15894 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
15896 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
15898 …ed FEC field 3. It requests Fire code FEC to be turned on when supported at the both ends of link…
15904 …EG_RESERVEDREGISTER1032_RESERVEDFIELD652_K2_E5 (0x1<<3) // Reserved
15905 …HY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1032_RESERVEDFIELD652_K2_E5_SHIFT 3
15923 …EG_RESERVEDREGISTER1037_RESERVEDFIELD659_K2_E5 (0x1<<3) // Reserved
15924 …HY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1037_RESERVEDFIELD659_K2_E5_SHIFT 3
15940 …EG_RESERVEDREGISTER1038_RESERVEDFIELD667_K2_E5 (0x1<<3) // Reserved
15941 …HY_NW_IP_REG_LN0_ANEG_RESERVEDREGISTER1038_RESERVEDFIELD667_K2_E5_SHIFT 3
15949 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
15951 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
15953 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
15955 …_40G_KR4_K2_E5 (0x1<<3) // Resolution result for 40GBase-KR4.…
15956 …HY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT 3
15957 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
15959 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
15961 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
15963 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
15966 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
15968 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
15970 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
15972 …_25G_KR_K2_E5 (0x1<<3) // Resolution result for 25GBase-KR. …
15973 …HY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR_K2_E5_SHIFT 3
15974 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
15976 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
15978 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
15981 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
15994 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
15996 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
15998 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
16000 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
16001 …HY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_40G_KR4_K2_E5_SHIFT 3
16002 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
16004 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
16006 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
16008 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
16011 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
16013 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
16015 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
16016 …HY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_25G_KR_K2_E5_SHIFT 3
16017 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
16019 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
16021 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
16039 …E_RESERVEDREGISTER1042_RESERVEDFIELD677_K2_E5 (0x1<<3) // Reserved
16040 …HY_NW_IP_REG_LN0_EEE_RESERVEDREGISTER1042_RESERVEDFIELD677_K2_E5_SHIFT 3
16057 …Q_REFCLK_RESERVEDREGISTER1048_RESERVEDFIELD686_K2_E5 (0x3<<3) // Reserved
16058 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1048_RESERVEDFIELD686_K2_E5_SHIFT 3
16064 …Q_REFCLK_RESERVEDREGISTER1049_RESERVEDFIELD689_K2_E5 (0x1<<3) // Reserved
16065 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1049_RESERVEDFIELD689_K2_E5_SHIFT 3
16075 …Q_REFCLK_RESERVEDREGISTER1052_RESERVEDFIELD693_K2_E5 (0x7<<3) // Reserved
16076 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1052_RESERVEDFIELD693_K2_E5_SHIFT 3
16080 …Q_REFCLK_RESERVEDREGISTER1053_RESERVEDFIELD695_K2_E5 (0x7<<3) // Reserved
16081 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1053_RESERVEDFIELD695_K2_E5_SHIFT 3
16094 …Q_REFCLK_RESERVEDREGISTER1055_RESERVEDFIELD701_K2_E5 (0x7<<3) // Reserved
16095 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1055_RESERVEDFIELD701_K2_E5_SHIFT 3
16099 …Q_REFCLK_RESERVEDREGISTER1056_RESERVEDFIELD703_K2_E5 (0x7<<3) // Reserved
16100 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1056_RESERVEDFIELD703_K2_E5_SHIFT 3
16104 …Q_REFCLK_RESERVEDREGISTER1057_RESERVEDFIELD705_K2_E5 (0x7<<3) // Reserved
16105 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1057_RESERVEDFIELD705_K2_E5_SHIFT 3
16109 …Q_REFCLK_RESERVEDREGISTER1058_RESERVEDFIELD707_K2_E5 (0x7<<3) // Reserved
16110 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1058_RESERVEDFIELD707_K2_E5_SHIFT 3
16126 …Q_REFCLK_RESERVEDREGISTER1063_RESERVEDFIELD715_K2_E5 (0x7<<3) // Reserved
16127 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1063_RESERVEDFIELD715_K2_E5_SHIFT 3
16236 …Q_REFCLK_RESERVEDREGISTER1090_RESERVEDFIELD761_K2_E5 (0x1<<3) // Reserved
16237 …HY_NW_IP_REG_LN0_LEQ_REFCLK_RESERVEDREGISTER1090_RESERVEDFIELD761_K2_E5_SHIFT 3
16598 …_REFCLK_RESERVEDREGISTER1177_RESERVEDFIELD905_K2_E5 (0x1f<<3) // Reserved
16599 …HY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1177_RESERVEDFIELD905_K2_E5_SHIFT 3
16603 …V_REFCLK_RESERVEDREGISTER1178_RESERVEDFIELD907_K2_E5 (0x3<<3) // Reserved
16604 …HY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1178_RESERVEDFIELD907_K2_E5_SHIFT 3
16613 …V_REFCLK_RESERVEDREGISTER1180_RESERVEDFIELD911_K2_E5 (0x3<<3) // Reserved
16614 …HY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1180_RESERVEDFIELD911_K2_E5_SHIFT 3
16627 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
16633 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
16664 …V_REFCLK_RESERVEDREGISTER1186_RESERVEDFIELD926_K2_E5 (0x3<<3) // Reserved
16665 …HY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1186_RESERVEDFIELD926_K2_E5_SHIFT 3
16669 …V_REFCLK_RESERVEDREGISTER1187_RESERVEDFIELD928_K2_E5 (0x3<<3) // Reserved
16670 …HY_NW_IP_REG_LN0_DRV_REFCLK_RESERVEDREGISTER1187_RESERVEDFIELD928_K2_E5_SHIFT 3
16687 …E_REFCLK_RESERVEDREGISTER1191_RESERVEDFIELD935_K2_E5 (0x7<<3) // Reserved
16688 …HY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1191_RESERVEDFIELD935_K2_E5_SHIFT 3
16744 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
16774 …E_REFCLK_FSM_STATUS0_RESERVEDFIELD969_K2_E5 (0x1<<3) // Reserved
16775 …HY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD969_K2_E5_SHIFT 3
16777 …les updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
16779 …les updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
16781 …bles updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
16783 … (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command e…
16784 …HY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_K2_E5_SHIFT 3
16785 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16787 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disable…
16789 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16791 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16819 …_E5 (0x7<<0) // Starting value for Tap 3 for Tap Adaptations
16859 …_E5 (0x7<<0) // Loading value for Tap 3 for Tap Adaptations
16899 … (0x7<<0) // binary value for Tap 3 for Tap Adaptations
16920 …E_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD973_K2_E5 (0x1<<3) // Reserved
16921 …HY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1211_RESERVEDFIELD973_K2_E5_SHIFT 3
16991 …E_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD999_K2_E5 (0x1<<3) // Reserved
16992 …HY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1230_RESERVEDFIELD999_K2_E5_SHIFT 3
17015 …E_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1010_K2_E5 (0x1<<3) // Reserved
17016 …HY_NW_IP_REG_LN0_DFE_REFCLK_RESERVEDREGISTER1232_RESERVEDFIELD1010_K2_E5_SHIFT 3
17203 …2_E5 (0x1<<0) // Enables the run-length detection digi…
17205 … 0x007410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
17207 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
17209 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
17265 …S_REFCLK_RESERVEDREGISTER1322_RESERVEDFIELD1123_K2_E5 (0xf<<3) // Reserved
17266 …HY_NW_IP_REG_LN0_LOS_REFCLK_RESERVEDREGISTER1322_RESERVEDFIELD1123_K2_E5_SHIFT 3
17295 …STATUS0_LOS_RAW_K2_E5 (0x1<<3) // The unfiltered L…
17296 …HY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS_RAW_K2_E5_SHIFT 3
17380 … 0x00781cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
17381 … 0x007820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
17416 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
17418 …K2_E5 (0x1<<5) // Clears the bit error counter.
17422 …ces the PRBS LFSR to reseed with Rx data every cycle. This will cause the bit error counter to be…
17427 …TUS_PATTERN_DET_K2_E5 (0xf<<3) // Indicates the pa…
17428 …HY_NW_IP_REG_LN0_BIST_RX_STATUS_PATTERN_DET_K2_E5_SHIFT 3
17429 … 0x007a20UL //Access:R DataWidth:0x8 // Number of bit errors.
17430 … 0x007a24UL //Access:R DataWidth:0x8 // Number of bit errors.
17431 … 0x007a28UL //Access:R DataWidth:0x8 // Number of bit errors.
17439 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
17440 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
17441 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
17442 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
17444 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
17490 …ATURE_RESERVEDREGISTER1364_RESERVEDFIELD1177_K2_E5 (0x1<<3) // Reserved
17491 …HY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1364_RESERVEDFIELD1177_K2_E5_SHIFT 3
17503 …ATURE_RESERVEDREGISTER1365_RESERVEDFIELD1183_K2_E5 (0x1<<3) // Reserved
17504 …HY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1365_RESERVEDFIELD1183_K2_E5_SHIFT 3
17512 …ATURE_RESERVEDREGISTER1366_RESERVEDFIELD1187_K2_E5 (0x1<<3) // Reserved
17513 …HY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1366_RESERVEDFIELD1187_K2_E5_SHIFT 3
17529 …ATURE_RESERVEDREGISTER1367_RESERVEDFIELD1195_K2_E5 (0x1<<3) // Reserved
17530 …HY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1367_RESERVEDFIELD1195_K2_E5_SHIFT 3
17590 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
17592 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
17605 …E_ADAPT_HFG_CFG0_INIT1_DATA_EN_K2_E5 (0x1<<3) // Enables CTLE EQ …
17606 …HY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_K2_E5_SHIFT 3
17634 …ATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD1226_K2_E5 (0x1<<3) // Reserved
17635 …HY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD1226_K2_E5_SHIFT 3
17643 …ATURE_RESERVEDREGISTER1378_RESERVEDFIELD1230_K2_E5 (0x1<<3) // Reserved
17644 …HY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1378_RESERVEDFIELD1230_K2_E5_SHIFT 3
17658 … (0x1<<2) // Enables DFE Tap 3. Tap3 will not be po…
17660 …_CFG_TAP4_EN_K2_E5 (0x1<<3) // Enables DFE Tap …
17661 …HY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP4_EN_K2_E5_SHIFT 3
17665 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
17674 …ATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD1237_K2_E5 (0x1<<3) // Reserved
17675 …HY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD1237_K2_E5_SHIFT 3
17683 …ATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD1240_K2_E5 (0x1<<3) // Reserved
17684 …HY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD1240_K2_E5_SHIFT 3
17686 …_INIT_EN_K2_E5 (0x1<<0) // Enables initial adaptations for Tap 3
17692 …ATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD1243_K2_E5 (0x1<<3) // Reserved
17693 …HY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD1243_K2_E5_SHIFT 3
17701 …ATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD1246_K2_E5 (0x1<<3) // Reserved
17702 …HY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD1246_K2_E5_SHIFT 3
17710 …ATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD1249_K2_E5 (0x1<<3) // Reserved
17711 …HY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD1249_K2_E5_SHIFT 3
17738 …TURE_RESERVEDREGISTER1388_RESERVEDFIELD1262_K2_E5 (0x1f<<3) // Reserved
17739 …HY_NW_IP_REG_LN0_FEATURE_RESERVEDREGISTER1388_RESERVEDFIELD1262_K2_E5_SHIFT 3
17757 …ATURE_TEST_CFG0_RESERVEDFIELD1269_K2_E5 (0x1<<3) // Reserved
17758 …HY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_RESERVEDFIELD1269_K2_E5_SHIFT 3
17774 …TRL0_CLEAR_K2_E5 (0x1<<3) // Synchronous rese…
17775 …HY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_CLEAR_K2_E5_SHIFT 3
17794 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
17799 …11 1 � CL93 1 + x^5 + x^6 + x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6…
17806 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
17810 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
17817 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
17821 …E5 (0x3<<4) // Status report field for pre-cursor tap.
17841 …11 1 � CL93 1 + x^5 + x^6 + x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6…
17843 … 0x007f0cUL //Access:RW DataWidth:0x8 // Maximum number of PRBS bit errors allowed in s…
17849 … 0x007f18UL //Access:R DataWidth:0x8 // Number of bit errors in PRBS patt…
17864 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
17868 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
17875 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
17879 … (0x3<<4) // Received status report field for pre-cursor tap.
17886 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
17888 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
17890 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
17892 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mis…
17893 …HY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_K2_E5_SHIFT 3
17955 …P_RESERVEDREGISTER1411_RESERVEDFIELD1294_K2_E5 (0x1<<3) // Reserved
17956 …HY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1411_RESERVEDFIELD1294_K2_E5_SHIFT 3
17968 …a from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4…
17972 …K2_E5 (0x1<<5) // Controls tx_en for Far-End-Digital FED loopbac…
17975 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
17977 …IT_STRIP_EVEN_K2_E5 (0x1<<1) // A bit stripping selection…
17982 …P_RESERVEDREGISTER1414_RESERVEDFIELD1299_K2_E5 (0x1<<3) // Reserved
17983 …HY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1414_RESERVEDFIELD1299_K2_E5_SHIFT 3
17987 …P_RESERVEDREGISTER1415_RESERVEDFIELD1301_K2_E5 (0x1<<3) // Reserved
17988 …HY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1415_RESERVEDFIELD1301_K2_E5_SHIFT 3
17997 …P_RESERVEDREGISTER1416_RESERVEDFIELD1304_K2_E5 (0x7<<3) // Reserved
17998 …HY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1416_RESERVEDFIELD1304_K2_E5_SHIFT 3
18002 …P_RESERVEDREGISTER1417_RESERVEDFIELD1306_K2_E5 (0x7<<3) // Reserved
18003 …HY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1417_RESERVEDFIELD1306_K2_E5_SHIFT 3
18018 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
18025 …P_RESERVEDREGISTER1420_RESERVEDFIELD1311_K2_E5 (0x1<<3) // Reserved
18026 …HY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1420_RESERVEDFIELD1311_K2_E5_SHIFT 3
18048 …P_RESERVEDREGISTER1423_RESERVEDFIELD1321_K2_E5 (0x1<<3) // Reserved
18049 …HY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1423_RESERVEDFIELD1321_K2_E5_SHIFT 3
18070 …P_RESERVEDREGISTER1427_RESERVEDFIELD1330_K2_E5 (0x7<<3) // Reserved
18071 …HY_NW_IP_REG_LN1_TOP_RESERVEDREGISTER1427_RESERVEDFIELD1330_K2_E5_SHIFT 3
18100 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
18101 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
18103 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
18158 …R_RXCLK_RESERVEDREGISTER1450_RESERVEDFIELD1365_K2_E5 (0x1<<3) // Reserved
18159 …HY_NW_IP_REG_LN1_CDR_RXCLK_RESERVEDREGISTER1450_RESERVEDFIELD1365_K2_E5_SHIFT 3
18170 … 0x0082fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
18172 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
18179 …ce lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by set…
18238 …R_REFCLK_RESERVEDREGISTER1475_RESERVEDFIELD1396_K2_E5 (0x7<<3) // Reserved
18239 …HY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1475_RESERVEDFIELD1396_K2_E5_SHIFT 3
18272 …R_REFCLK_RESERVEDREGISTER1483_RESERVEDFIELD1410_K2_E5 (0xf<<3) // Reserved
18273 …HY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1483_RESERVEDFIELD1410_K2_E5_SHIFT 3
18290 …R_REFCLK_RESERVEDREGISTER1487_RESERVEDFIELD1417_K2_E5 (0x3<<3) // Reserved
18291 …HY_NW_IP_REG_LN1_CDR_REFCLK_RESERVEDREGISTER1487_RESERVEDFIELD1417_K2_E5_SHIFT 3
18337 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
18355 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
18359 …3) // Autoneg ability. When read as a one, it indicates that the PMA/PMD has the ability to perfo…
18360 …HY_NW_IP_REG_LN1_ANEG_STATUS0_AUTONEG_ABILITY_K2_E5_SHIFT 3
18372 …1_NP_LOADED_K2_E5 (0x1<<3) // mr_np_loaded sta…
18373 …HY_NW_IP_REG_LN1_ANEG_STATUS1_NP_LOADED_K2_E5_SHIFT 3
18378 … 0x008650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
18379 … 0x008654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
18383 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
18386 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller ge…
18390 …AGE1_ASM_DIR_K2_E5 (0x1<<3) // Pause ASM_DIR ad…
18391 …HY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_ASM_DIR_K2_E5_SHIFT 3
18402 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
18404 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
18406 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
18408 …H0_ABILITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology …
18409 …HY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT 3
18410 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
18412 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
18414 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
18416 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
18419 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
18421 …TY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR technolog…
18423 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
18425 …1_K2_E5 (0x1f<<3) // technology advertised ability Field A15…
18426 …HY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5_SHIFT 3
18428 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
18431 …TY_K2_E5 (0x1<<0) // base page bit F0. It advertises …
18433 …2_E5 (0x1<<1) // base page bit F1. It requests FE…
18435 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR…
18437 … (0x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-G…
18438 …HY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5_SHIFT 3
18440 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
18442 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
18444 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
18446 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consor…
18447 …HY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_50G_CR2_K2_E5_SHIFT 3
18448 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
18450 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
18452 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
18454 …ed FEC field 3. It requests Fire code FEC to be turned on when supported at the both ends of link…
18460 …EG_RESERVEDREGISTER1508_RESERVEDFIELD1446_K2_E5 (0x1<<3) // Reserved
18461 …HY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1508_RESERVEDFIELD1446_K2_E5_SHIFT 3
18479 …EG_RESERVEDREGISTER1513_RESERVEDFIELD1453_K2_E5 (0x1<<3) // Reserved
18480 …HY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1513_RESERVEDFIELD1453_K2_E5_SHIFT 3
18496 …EG_RESERVEDREGISTER1514_RESERVEDFIELD1461_K2_E5 (0x1<<3) // Reserved
18497 …HY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1514_RESERVEDFIELD1461_K2_E5_SHIFT 3
18507 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
18510 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
18514 …E_PAGE1_ASM_DIR_K2_E5 (0x1<<3) // Link partner Pau…
18515 …HY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_ASM_DIR_K2_E5_SHIFT 3
18528 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
18530 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
18532 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
18534 …ABILITY_40G_KR4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 tech…
18535 …HY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT 3
18536 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
18538 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
18540 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
18542 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
18545 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
18547 …S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or CR technolog…
18549 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
18551 …2_E5 (0x1f<<3) // Link partner technology advertised ability Fi…
18552 …HY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5_SHIFT 3
18554 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
18557 … (0x1<<0) // Link partner base page bit F0. It advertises …
18559 … (0x1<<1) // Link partner base page bit F1. It requests FE…
18561 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR…
18563 … (0x1<<3) // Link partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or…
18564 …HY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5_SHIFT 3
18566 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
18568 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
18570 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
18572 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G …
18573 …HY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_50G_CR2_K2_E5_SHIFT 3
18574 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
18576 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
18578 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
18580 …ed FEC field 3. It requests Fire code FEC to be turned on when supported at the both ends of link…
18586 …EG_RESERVEDREGISTER1516_RESERVEDFIELD1466_K2_E5 (0x1<<3) // Reserved
18587 …HY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1516_RESERVEDFIELD1466_K2_E5_SHIFT 3
18605 …EG_RESERVEDREGISTER1521_RESERVEDFIELD1473_K2_E5 (0x1<<3) // Reserved
18606 …HY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1521_RESERVEDFIELD1473_K2_E5_SHIFT 3
18622 …EG_RESERVEDREGISTER1522_RESERVEDFIELD1481_K2_E5 (0x1<<3) // Reserved
18623 …HY_NW_IP_REG_LN1_ANEG_RESERVEDREGISTER1522_RESERVEDFIELD1481_K2_E5_SHIFT 3
18631 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
18633 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
18635 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
18637 …_40G_KR4_K2_E5 (0x1<<3) // Resolution result for 40GBase-KR4.…
18638 …HY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT 3
18639 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
18641 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
18643 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
18645 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
18648 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
18650 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
18652 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
18654 …_25G_KR_K2_E5 (0x1<<3) // Resolution result for 25GBase-KR. …
18655 …HY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR_K2_E5_SHIFT 3
18656 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
18658 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
18660 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
18663 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
18676 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
18678 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
18680 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
18682 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
18683 …HY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_40G_KR4_K2_E5_SHIFT 3
18684 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
18686 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
18688 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
18690 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
18693 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
18695 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
18697 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
18698 …HY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_25G_KR_K2_E5_SHIFT 3
18699 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
18701 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
18703 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
18721 …E_RESERVEDREGISTER1526_RESERVEDFIELD1491_K2_E5 (0x1<<3) // Reserved
18722 …HY_NW_IP_REG_LN1_EEE_RESERVEDREGISTER1526_RESERVEDFIELD1491_K2_E5_SHIFT 3
18739 …Q_REFCLK_RESERVEDREGISTER1532_RESERVEDFIELD1500_K2_E5 (0x3<<3) // Reserved
18740 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1532_RESERVEDFIELD1500_K2_E5_SHIFT 3
18746 …Q_REFCLK_RESERVEDREGISTER1533_RESERVEDFIELD1503_K2_E5 (0x1<<3) // Reserved
18747 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1533_RESERVEDFIELD1503_K2_E5_SHIFT 3
18757 …Q_REFCLK_RESERVEDREGISTER1536_RESERVEDFIELD1507_K2_E5 (0x7<<3) // Reserved
18758 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1536_RESERVEDFIELD1507_K2_E5_SHIFT 3
18762 …Q_REFCLK_RESERVEDREGISTER1537_RESERVEDFIELD1509_K2_E5 (0x7<<3) // Reserved
18763 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1537_RESERVEDFIELD1509_K2_E5_SHIFT 3
18776 …Q_REFCLK_RESERVEDREGISTER1539_RESERVEDFIELD1515_K2_E5 (0x7<<3) // Reserved
18777 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1539_RESERVEDFIELD1515_K2_E5_SHIFT 3
18781 …Q_REFCLK_RESERVEDREGISTER1540_RESERVEDFIELD1517_K2_E5 (0x7<<3) // Reserved
18782 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1540_RESERVEDFIELD1517_K2_E5_SHIFT 3
18786 …Q_REFCLK_RESERVEDREGISTER1541_RESERVEDFIELD1519_K2_E5 (0x7<<3) // Reserved
18787 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1541_RESERVEDFIELD1519_K2_E5_SHIFT 3
18791 …Q_REFCLK_RESERVEDREGISTER1542_RESERVEDFIELD1521_K2_E5 (0x7<<3) // Reserved
18792 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1542_RESERVEDFIELD1521_K2_E5_SHIFT 3
18808 …Q_REFCLK_RESERVEDREGISTER1547_RESERVEDFIELD1529_K2_E5 (0x7<<3) // Reserved
18809 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1547_RESERVEDFIELD1529_K2_E5_SHIFT 3
18918 …Q_REFCLK_RESERVEDREGISTER1574_RESERVEDFIELD1575_K2_E5 (0x1<<3) // Reserved
18919 …HY_NW_IP_REG_LN1_LEQ_REFCLK_RESERVEDREGISTER1574_RESERVEDFIELD1575_K2_E5_SHIFT 3
19280 …_REFCLK_RESERVEDREGISTER1661_RESERVEDFIELD1719_K2_E5 (0x1f<<3) // Reserved
19281 …HY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1661_RESERVEDFIELD1719_K2_E5_SHIFT 3
19285 …V_REFCLK_RESERVEDREGISTER1662_RESERVEDFIELD1721_K2_E5 (0x3<<3) // Reserved
19286 …HY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1662_RESERVEDFIELD1721_K2_E5_SHIFT 3
19295 …V_REFCLK_RESERVEDREGISTER1664_RESERVEDFIELD1725_K2_E5 (0x3<<3) // Reserved
19296 …HY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1664_RESERVEDFIELD1725_K2_E5_SHIFT 3
19309 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
19315 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
19346 …V_REFCLK_RESERVEDREGISTER1670_RESERVEDFIELD1740_K2_E5 (0x3<<3) // Reserved
19347 …HY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1670_RESERVEDFIELD1740_K2_E5_SHIFT 3
19351 …V_REFCLK_RESERVEDREGISTER1671_RESERVEDFIELD1742_K2_E5 (0x3<<3) // Reserved
19352 …HY_NW_IP_REG_LN1_DRV_REFCLK_RESERVEDREGISTER1671_RESERVEDFIELD1742_K2_E5_SHIFT 3
19369 …E_REFCLK_RESERVEDREGISTER1675_RESERVEDFIELD1749_K2_E5 (0x7<<3) // Reserved
19370 …HY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1675_RESERVEDFIELD1749_K2_E5_SHIFT 3
19426 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
19456 …E_REFCLK_FSM_STATUS0_RESERVEDFIELD1783_K2_E5 (0x1<<3) // Reserved
19457 …HY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD1783_K2_E5_SHIFT 3
19459 …les updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
19461 …les updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
19463 …bles updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
19465 … (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command e…
19466 …HY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_K2_E5_SHIFT 3
19467 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19469 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disable…
19471 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19473 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19501 …_E5 (0x7<<0) // Starting value for Tap 3 for Tap Adaptations
19541 …_E5 (0x7<<0) // Loading value for Tap 3 for Tap Adaptations
19581 … (0x7<<0) // binary value for Tap 3 for Tap Adaptations
19602 …E_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1787_K2_E5 (0x1<<3) // Reserved
19603 …HY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1695_RESERVEDFIELD1787_K2_E5_SHIFT 3
19673 …E_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1813_K2_E5 (0x1<<3) // Reserved
19674 …HY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1714_RESERVEDFIELD1813_K2_E5_SHIFT 3
19697 …E_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1824_K2_E5 (0x1<<3) // Reserved
19698 …HY_NW_IP_REG_LN1_DFE_REFCLK_RESERVEDREGISTER1716_RESERVEDFIELD1824_K2_E5_SHIFT 3
19885 …2_E5 (0x1<<0) // Enables the run-length detection digi…
19887 … 0x009410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
19889 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
19891 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
19947 …S_REFCLK_RESERVEDREGISTER1806_RESERVEDFIELD1937_K2_E5 (0xf<<3) // Reserved
19948 …HY_NW_IP_REG_LN1_LOS_REFCLK_RESERVEDREGISTER1806_RESERVEDFIELD1937_K2_E5_SHIFT 3
19977 …STATUS0_LOS_RAW_K2_E5 (0x1<<3) // The unfiltered L…
19978 …HY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS_RAW_K2_E5_SHIFT 3
20062 … 0x00981cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
20063 … 0x009820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
20098 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
20100 …K2_E5 (0x1<<5) // Clears the bit error counter.
20104 …ces the PRBS LFSR to reseed with Rx data every cycle. This will cause the bit error counter to be…
20109 …TUS_PATTERN_DET_K2_E5 (0xf<<3) // Indicates the pa…
20110 …HY_NW_IP_REG_LN1_BIST_RX_STATUS_PATTERN_DET_K2_E5_SHIFT 3
20111 … 0x009a20UL //Access:R DataWidth:0x8 // Number of bit errors.
20112 … 0x009a24UL //Access:R DataWidth:0x8 // Number of bit errors.
20113 … 0x009a28UL //Access:R DataWidth:0x8 // Number of bit errors.
20121 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
20122 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
20123 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
20124 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
20126 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
20172 …ATURE_RESERVEDREGISTER1848_RESERVEDFIELD1991_K2_E5 (0x1<<3) // Reserved
20173 …HY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1848_RESERVEDFIELD1991_K2_E5_SHIFT 3
20185 …ATURE_RESERVEDREGISTER1849_RESERVEDFIELD1997_K2_E5 (0x1<<3) // Reserved
20186 …HY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1849_RESERVEDFIELD1997_K2_E5_SHIFT 3
20194 …ATURE_RESERVEDREGISTER1850_RESERVEDFIELD2001_K2_E5 (0x1<<3) // Reserved
20195 …HY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1850_RESERVEDFIELD2001_K2_E5_SHIFT 3
20211 …ATURE_RESERVEDREGISTER1851_RESERVEDFIELD2009_K2_E5 (0x1<<3) // Reserved
20212 …HY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1851_RESERVEDFIELD2009_K2_E5_SHIFT 3
20272 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
20274 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
20287 …E_ADAPT_HFG_CFG0_INIT1_DATA_EN_K2_E5 (0x1<<3) // Enables CTLE EQ …
20288 …HY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_K2_E5_SHIFT 3
20316 …ATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD2040_K2_E5 (0x1<<3) // Reserved
20317 …HY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD2040_K2_E5_SHIFT 3
20325 …ATURE_RESERVEDREGISTER1862_RESERVEDFIELD2044_K2_E5 (0x1<<3) // Reserved
20326 …HY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1862_RESERVEDFIELD2044_K2_E5_SHIFT 3
20340 … (0x1<<2) // Enables DFE Tap 3. Tap3 will not be po…
20342 …_CFG_TAP4_EN_K2_E5 (0x1<<3) // Enables DFE Tap …
20343 …HY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP4_EN_K2_E5_SHIFT 3
20347 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
20356 …ATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2051_K2_E5 (0x1<<3) // Reserved
20357 …HY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2051_K2_E5_SHIFT 3
20365 …ATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2054_K2_E5 (0x1<<3) // Reserved
20366 …HY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2054_K2_E5_SHIFT 3
20368 …_INIT_EN_K2_E5 (0x1<<0) // Enables initial adaptations for Tap 3
20374 …ATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2057_K2_E5 (0x1<<3) // Reserved
20375 …HY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2057_K2_E5_SHIFT 3
20383 …ATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2060_K2_E5 (0x1<<3) // Reserved
20384 …HY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2060_K2_E5_SHIFT 3
20392 …ATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2063_K2_E5 (0x1<<3) // Reserved
20393 …HY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2063_K2_E5_SHIFT 3
20420 …TURE_RESERVEDREGISTER1872_RESERVEDFIELD2076_K2_E5 (0x1f<<3) // Reserved
20421 …HY_NW_IP_REG_LN1_FEATURE_RESERVEDREGISTER1872_RESERVEDFIELD2076_K2_E5_SHIFT 3
20439 …ATURE_TEST_CFG0_RESERVEDFIELD2083_K2_E5 (0x1<<3) // Reserved
20440 …HY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_RESERVEDFIELD2083_K2_E5_SHIFT 3
20456 …TRL0_CLEAR_K2_E5 (0x1<<3) // Synchronous rese…
20457 …HY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_CLEAR_K2_E5_SHIFT 3
20476 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
20481 …11 1 � CL93 1 + x^5 + x^6 + x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6…
20488 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
20492 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
20499 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
20503 …E5 (0x3<<4) // Status report field for pre-cursor tap.
20523 …11 1 � CL93 1 + x^5 + x^6 + x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6…
20525 … 0x009f0cUL //Access:RW DataWidth:0x8 // Maximum number of PRBS bit errors allowed in s…
20531 … 0x009f18UL //Access:R DataWidth:0x8 // Number of bit errors in PRBS patt…
20546 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
20550 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
20557 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
20561 … (0x3<<4) // Received status report field for pre-cursor tap.
20568 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
20570 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
20572 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
20574 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mis…
20575 …HY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_K2_E5_SHIFT 3
20637 …P_RESERVEDREGISTER1895_RESERVEDFIELD2108_K2_E5 (0x1<<3) // Reserved
20638 …HY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1895_RESERVEDFIELD2108_K2_E5_SHIFT 3
20650 …a from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4…
20654 …K2_E5 (0x1<<5) // Controls tx_en for Far-End-Digital FED loopbac…
20657 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
20659 …IT_STRIP_EVEN_K2_E5 (0x1<<1) // A bit stripping selection…
20664 …P_RESERVEDREGISTER1898_RESERVEDFIELD2113_K2_E5 (0x1<<3) // Reserved
20665 …HY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1898_RESERVEDFIELD2113_K2_E5_SHIFT 3
20669 …P_RESERVEDREGISTER1899_RESERVEDFIELD2115_K2_E5 (0x1<<3) // Reserved
20670 …HY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1899_RESERVEDFIELD2115_K2_E5_SHIFT 3
20679 …P_RESERVEDREGISTER1900_RESERVEDFIELD2118_K2_E5 (0x7<<3) // Reserved
20680 …HY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1900_RESERVEDFIELD2118_K2_E5_SHIFT 3
20684 …P_RESERVEDREGISTER1901_RESERVEDFIELD2120_K2_E5 (0x7<<3) // Reserved
20685 …HY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1901_RESERVEDFIELD2120_K2_E5_SHIFT 3
20700 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
20707 …P_RESERVEDREGISTER1904_RESERVEDFIELD2125_K2_E5 (0x1<<3) // Reserved
20708 …HY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1904_RESERVEDFIELD2125_K2_E5_SHIFT 3
20730 …P_RESERVEDREGISTER1907_RESERVEDFIELD2135_K2_E5 (0x1<<3) // Reserved
20731 …HY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1907_RESERVEDFIELD2135_K2_E5_SHIFT 3
20752 …P_RESERVEDREGISTER1911_RESERVEDFIELD2144_K2_E5 (0x7<<3) // Reserved
20753 …HY_NW_IP_REG_LN2_TOP_RESERVEDREGISTER1911_RESERVEDFIELD2144_K2_E5_SHIFT 3
20782 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
20783 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
20785 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
20840 …R_RXCLK_RESERVEDREGISTER1934_RESERVEDFIELD2179_K2_E5 (0x1<<3) // Reserved
20841 …HY_NW_IP_REG_LN2_CDR_RXCLK_RESERVEDREGISTER1934_RESERVEDFIELD2179_K2_E5_SHIFT 3
20852 … 0x00a2fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
20854 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
20861 …ce lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by set…
20920 …R_REFCLK_RESERVEDREGISTER1959_RESERVEDFIELD2210_K2_E5 (0x7<<3) // Reserved
20921 …HY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1959_RESERVEDFIELD2210_K2_E5_SHIFT 3
20954 …R_REFCLK_RESERVEDREGISTER1967_RESERVEDFIELD2224_K2_E5 (0xf<<3) // Reserved
20955 …HY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1967_RESERVEDFIELD2224_K2_E5_SHIFT 3
20972 …R_REFCLK_RESERVEDREGISTER1971_RESERVEDFIELD2231_K2_E5 (0x3<<3) // Reserved
20973 …HY_NW_IP_REG_LN2_CDR_REFCLK_RESERVEDREGISTER1971_RESERVEDFIELD2231_K2_E5_SHIFT 3
21019 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
21037 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
21041 …3) // Autoneg ability. When read as a one, it indicates that the PMA/PMD has the ability to perfo…
21042 …HY_NW_IP_REG_LN2_ANEG_STATUS0_AUTONEG_ABILITY_K2_E5_SHIFT 3
21054 …1_NP_LOADED_K2_E5 (0x1<<3) // mr_np_loaded sta…
21055 …HY_NW_IP_REG_LN2_ANEG_STATUS1_NP_LOADED_K2_E5_SHIFT 3
21060 … 0x00a650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
21061 … 0x00a654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
21065 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
21068 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller ge…
21072 …AGE1_ASM_DIR_K2_E5 (0x1<<3) // Pause ASM_DIR ad…
21073 …HY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_ASM_DIR_K2_E5_SHIFT 3
21084 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
21086 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
21088 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
21090 …H0_ABILITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology …
21091 …HY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT 3
21092 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
21094 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
21096 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
21098 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
21101 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
21103 …TY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR technolog…
21105 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
21107 …1_K2_E5 (0x1f<<3) // technology advertised ability Field A15…
21108 …HY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5_SHIFT 3
21110 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
21113 …TY_K2_E5 (0x1<<0) // base page bit F0. It advertises …
21115 …2_E5 (0x1<<1) // base page bit F1. It requests FE…
21117 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR…
21119 … (0x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-G…
21120 …HY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5_SHIFT 3
21122 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
21124 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
21126 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
21128 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consor…
21129 …HY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_50G_CR2_K2_E5_SHIFT 3
21130 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
21132 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
21134 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
21136 …ed FEC field 3. It requests Fire code FEC to be turned on when supported at the both ends of link…
21142 …EG_RESERVEDREGISTER1992_RESERVEDFIELD2260_K2_E5 (0x1<<3) // Reserved
21143 …HY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1992_RESERVEDFIELD2260_K2_E5_SHIFT 3
21161 …EG_RESERVEDREGISTER1997_RESERVEDFIELD2267_K2_E5 (0x1<<3) // Reserved
21162 …HY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1997_RESERVEDFIELD2267_K2_E5_SHIFT 3
21178 …EG_RESERVEDREGISTER1998_RESERVEDFIELD2275_K2_E5 (0x1<<3) // Reserved
21179 …HY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER1998_RESERVEDFIELD2275_K2_E5_SHIFT 3
21189 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
21192 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
21196 …E_PAGE1_ASM_DIR_K2_E5 (0x1<<3) // Link partner Pau…
21197 …HY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_ASM_DIR_K2_E5_SHIFT 3
21210 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
21212 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
21214 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
21216 …ABILITY_40G_KR4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 tech…
21217 …HY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT 3
21218 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
21220 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
21222 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
21224 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
21227 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
21229 …S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or CR technolog…
21231 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
21233 …2_E5 (0x1f<<3) // Link partner technology advertised ability Fi…
21234 …HY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5_SHIFT 3
21236 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
21239 … (0x1<<0) // Link partner base page bit F0. It advertises …
21241 … (0x1<<1) // Link partner base page bit F1. It requests FE…
21243 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR…
21245 … (0x1<<3) // Link partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or…
21246 …HY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5_SHIFT 3
21248 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
21250 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
21252 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
21254 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G …
21255 …HY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_50G_CR2_K2_E5_SHIFT 3
21256 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
21258 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
21260 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
21262 …ed FEC field 3. It requests Fire code FEC to be turned on when supported at the both ends of link…
21268 …EG_RESERVEDREGISTER2000_RESERVEDFIELD2280_K2_E5 (0x1<<3) // Reserved
21269 …HY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2000_RESERVEDFIELD2280_K2_E5_SHIFT 3
21287 …EG_RESERVEDREGISTER2005_RESERVEDFIELD2287_K2_E5 (0x1<<3) // Reserved
21288 …HY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2005_RESERVEDFIELD2287_K2_E5_SHIFT 3
21304 …EG_RESERVEDREGISTER2006_RESERVEDFIELD2295_K2_E5 (0x1<<3) // Reserved
21305 …HY_NW_IP_REG_LN2_ANEG_RESERVEDREGISTER2006_RESERVEDFIELD2295_K2_E5_SHIFT 3
21313 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
21315 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
21317 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
21319 …_40G_KR4_K2_E5 (0x1<<3) // Resolution result for 40GBase-KR4.…
21320 …HY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT 3
21321 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
21323 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
21325 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
21327 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
21330 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
21332 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
21334 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
21336 …_25G_KR_K2_E5 (0x1<<3) // Resolution result for 25GBase-KR. …
21337 …HY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR_K2_E5_SHIFT 3
21338 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
21340 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
21342 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
21345 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
21358 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
21360 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
21362 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
21364 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
21365 …HY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_40G_KR4_K2_E5_SHIFT 3
21366 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
21368 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
21370 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
21372 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
21375 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
21377 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
21379 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
21380 …HY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_25G_KR_K2_E5_SHIFT 3
21381 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
21383 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
21385 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
21403 …E_RESERVEDREGISTER2010_RESERVEDFIELD2305_K2_E5 (0x1<<3) // Reserved
21404 …HY_NW_IP_REG_LN2_EEE_RESERVEDREGISTER2010_RESERVEDFIELD2305_K2_E5_SHIFT 3
21421 …Q_REFCLK_RESERVEDREGISTER2016_RESERVEDFIELD2314_K2_E5 (0x3<<3) // Reserved
21422 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2016_RESERVEDFIELD2314_K2_E5_SHIFT 3
21428 …Q_REFCLK_RESERVEDREGISTER2017_RESERVEDFIELD2317_K2_E5 (0x1<<3) // Reserved
21429 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2017_RESERVEDFIELD2317_K2_E5_SHIFT 3
21439 …Q_REFCLK_RESERVEDREGISTER2020_RESERVEDFIELD2321_K2_E5 (0x7<<3) // Reserved
21440 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2020_RESERVEDFIELD2321_K2_E5_SHIFT 3
21444 …Q_REFCLK_RESERVEDREGISTER2021_RESERVEDFIELD2323_K2_E5 (0x7<<3) // Reserved
21445 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2021_RESERVEDFIELD2323_K2_E5_SHIFT 3
21458 …Q_REFCLK_RESERVEDREGISTER2023_RESERVEDFIELD2329_K2_E5 (0x7<<3) // Reserved
21459 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2023_RESERVEDFIELD2329_K2_E5_SHIFT 3
21463 …Q_REFCLK_RESERVEDREGISTER2024_RESERVEDFIELD2331_K2_E5 (0x7<<3) // Reserved
21464 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2024_RESERVEDFIELD2331_K2_E5_SHIFT 3
21468 …Q_REFCLK_RESERVEDREGISTER2025_RESERVEDFIELD2333_K2_E5 (0x7<<3) // Reserved
21469 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2025_RESERVEDFIELD2333_K2_E5_SHIFT 3
21473 …Q_REFCLK_RESERVEDREGISTER2026_RESERVEDFIELD2335_K2_E5 (0x7<<3) // Reserved
21474 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2026_RESERVEDFIELD2335_K2_E5_SHIFT 3
21490 …Q_REFCLK_RESERVEDREGISTER2031_RESERVEDFIELD2343_K2_E5 (0x7<<3) // Reserved
21491 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2031_RESERVEDFIELD2343_K2_E5_SHIFT 3
21600 …Q_REFCLK_RESERVEDREGISTER2058_RESERVEDFIELD2389_K2_E5 (0x1<<3) // Reserved
21601 …HY_NW_IP_REG_LN2_LEQ_REFCLK_RESERVEDREGISTER2058_RESERVEDFIELD2389_K2_E5_SHIFT 3
21962 …_REFCLK_RESERVEDREGISTER2145_RESERVEDFIELD2533_K2_E5 (0x1f<<3) // Reserved
21963 …HY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2145_RESERVEDFIELD2533_K2_E5_SHIFT 3
21967 …V_REFCLK_RESERVEDREGISTER2146_RESERVEDFIELD2535_K2_E5 (0x3<<3) // Reserved
21968 …HY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2146_RESERVEDFIELD2535_K2_E5_SHIFT 3
21977 …V_REFCLK_RESERVEDREGISTER2148_RESERVEDFIELD2539_K2_E5 (0x3<<3) // Reserved
21978 …HY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2148_RESERVEDFIELD2539_K2_E5_SHIFT 3
21991 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
21997 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
22028 …V_REFCLK_RESERVEDREGISTER2154_RESERVEDFIELD2554_K2_E5 (0x3<<3) // Reserved
22029 …HY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2154_RESERVEDFIELD2554_K2_E5_SHIFT 3
22033 …V_REFCLK_RESERVEDREGISTER2155_RESERVEDFIELD2556_K2_E5 (0x3<<3) // Reserved
22034 …HY_NW_IP_REG_LN2_DRV_REFCLK_RESERVEDREGISTER2155_RESERVEDFIELD2556_K2_E5_SHIFT 3
22051 …E_REFCLK_RESERVEDREGISTER2159_RESERVEDFIELD2563_K2_E5 (0x7<<3) // Reserved
22052 …HY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2159_RESERVEDFIELD2563_K2_E5_SHIFT 3
22108 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
22138 …E_REFCLK_FSM_STATUS0_RESERVEDFIELD2597_K2_E5 (0x1<<3) // Reserved
22139 …HY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD2597_K2_E5_SHIFT 3
22141 …les updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
22143 …les updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
22145 …bles updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
22147 … (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command e…
22148 …HY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_K2_E5_SHIFT 3
22149 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22151 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disable…
22153 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22155 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22183 …_E5 (0x7<<0) // Starting value for Tap 3 for Tap Adaptations
22223 …_E5 (0x7<<0) // Loading value for Tap 3 for Tap Adaptations
22263 … (0x7<<0) // binary value for Tap 3 for Tap Adaptations
22284 …E_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2601_K2_E5 (0x1<<3) // Reserved
22285 …HY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2179_RESERVEDFIELD2601_K2_E5_SHIFT 3
22355 …E_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2627_K2_E5 (0x1<<3) // Reserved
22356 …HY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2198_RESERVEDFIELD2627_K2_E5_SHIFT 3
22379 …E_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2638_K2_E5 (0x1<<3) // Reserved
22380 …HY_NW_IP_REG_LN2_DFE_REFCLK_RESERVEDREGISTER2200_RESERVEDFIELD2638_K2_E5_SHIFT 3
22567 …2_E5 (0x1<<0) // Enables the run-length detection digi…
22569 … 0x00b410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
22571 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
22573 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
22629 …S_REFCLK_RESERVEDREGISTER2290_RESERVEDFIELD2751_K2_E5 (0xf<<3) // Reserved
22630 …HY_NW_IP_REG_LN2_LOS_REFCLK_RESERVEDREGISTER2290_RESERVEDFIELD2751_K2_E5_SHIFT 3
22659 …STATUS0_LOS_RAW_K2_E5 (0x1<<3) // The unfiltered L…
22660 …HY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS_RAW_K2_E5_SHIFT 3
22744 … 0x00b81cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
22745 … 0x00b820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
22780 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
22782 …K2_E5 (0x1<<5) // Clears the bit error counter.
22786 …ces the PRBS LFSR to reseed with Rx data every cycle. This will cause the bit error counter to be…
22791 …TUS_PATTERN_DET_K2_E5 (0xf<<3) // Indicates the pa…
22792 …HY_NW_IP_REG_LN2_BIST_RX_STATUS_PATTERN_DET_K2_E5_SHIFT 3
22793 … 0x00ba20UL //Access:R DataWidth:0x8 // Number of bit errors.
22794 … 0x00ba24UL //Access:R DataWidth:0x8 // Number of bit errors.
22795 … 0x00ba28UL //Access:R DataWidth:0x8 // Number of bit errors.
22803 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
22804 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
22805 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
22806 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
22808 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
22854 …ATURE_RESERVEDREGISTER2332_RESERVEDFIELD2805_K2_E5 (0x1<<3) // Reserved
22855 …HY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2332_RESERVEDFIELD2805_K2_E5_SHIFT 3
22867 …ATURE_RESERVEDREGISTER2333_RESERVEDFIELD2811_K2_E5 (0x1<<3) // Reserved
22868 …HY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2333_RESERVEDFIELD2811_K2_E5_SHIFT 3
22876 …ATURE_RESERVEDREGISTER2334_RESERVEDFIELD2815_K2_E5 (0x1<<3) // Reserved
22877 …HY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2334_RESERVEDFIELD2815_K2_E5_SHIFT 3
22893 …ATURE_RESERVEDREGISTER2335_RESERVEDFIELD2823_K2_E5 (0x1<<3) // Reserved
22894 …HY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2335_RESERVEDFIELD2823_K2_E5_SHIFT 3
22954 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
22956 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
22969 …E_ADAPT_HFG_CFG0_INIT1_DATA_EN_K2_E5 (0x1<<3) // Enables CTLE EQ …
22970 …HY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_K2_E5_SHIFT 3
22998 …ATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD2854_K2_E5 (0x1<<3) // Reserved
22999 …HY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD2854_K2_E5_SHIFT 3
23007 …ATURE_RESERVEDREGISTER2346_RESERVEDFIELD2858_K2_E5 (0x1<<3) // Reserved
23008 …HY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2346_RESERVEDFIELD2858_K2_E5_SHIFT 3
23022 … (0x1<<2) // Enables DFE Tap 3. Tap3 will not be po…
23024 …_CFG_TAP4_EN_K2_E5 (0x1<<3) // Enables DFE Tap …
23025 …HY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP4_EN_K2_E5_SHIFT 3
23029 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
23038 …ATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2865_K2_E5 (0x1<<3) // Reserved
23039 …HY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD2865_K2_E5_SHIFT 3
23047 …ATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2868_K2_E5 (0x1<<3) // Reserved
23048 …HY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD2868_K2_E5_SHIFT 3
23050 …_INIT_EN_K2_E5 (0x1<<0) // Enables initial adaptations for Tap 3
23056 …ATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2871_K2_E5 (0x1<<3) // Reserved
23057 …HY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD2871_K2_E5_SHIFT 3
23065 …ATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2874_K2_E5 (0x1<<3) // Reserved
23066 …HY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD2874_K2_E5_SHIFT 3
23074 …ATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2877_K2_E5 (0x1<<3) // Reserved
23075 …HY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD2877_K2_E5_SHIFT 3
23102 …TURE_RESERVEDREGISTER2356_RESERVEDFIELD2890_K2_E5 (0x1f<<3) // Reserved
23103 …HY_NW_IP_REG_LN2_FEATURE_RESERVEDREGISTER2356_RESERVEDFIELD2890_K2_E5_SHIFT 3
23121 …ATURE_TEST_CFG0_RESERVEDFIELD2897_K2_E5 (0x1<<3) // Reserved
23122 …HY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_RESERVEDFIELD2897_K2_E5_SHIFT 3
23138 …TRL0_CLEAR_K2_E5 (0x1<<3) // Synchronous rese…
23139 …HY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_CLEAR_K2_E5_SHIFT 3
23158 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
23163 …11 1 � CL93 1 + x^5 + x^6 + x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6…
23170 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
23174 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
23181 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
23185 …E5 (0x3<<4) // Status report field for pre-cursor tap.
23205 …11 1 � CL93 1 + x^5 + x^6 + x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6…
23207 … 0x00bf0cUL //Access:RW DataWidth:0x8 // Maximum number of PRBS bit errors allowed in s…
23213 … 0x00bf18UL //Access:R DataWidth:0x8 // Number of bit errors in PRBS patt…
23228 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
23232 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
23239 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
23243 … (0x3<<4) // Received status report field for pre-cursor tap.
23250 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
23252 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
23254 … (0x1<<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission …
23256 … (0x1<<3) // Near-End Analog NEA loopback mode enable. 0x0 - mis…
23257 …HY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_K2_E5_SHIFT 3
23319 …P_RESERVEDREGISTER2379_RESERVEDFIELD2922_K2_E5 (0x1<<3) // Reserved
23320 …HY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2379_RESERVEDFIELD2922_K2_E5_SHIFT 3
23332 …a from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4…
23336 …K2_E5 (0x1<<5) // Controls tx_en for Far-End-Digital FED loopbac…
23339 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
23341 …IT_STRIP_EVEN_K2_E5 (0x1<<1) // A bit stripping selection…
23346 …P_RESERVEDREGISTER2382_RESERVEDFIELD2927_K2_E5 (0x1<<3) // Reserved
23347 …HY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2382_RESERVEDFIELD2927_K2_E5_SHIFT 3
23351 …P_RESERVEDREGISTER2383_RESERVEDFIELD2929_K2_E5 (0x1<<3) // Reserved
23352 …HY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2383_RESERVEDFIELD2929_K2_E5_SHIFT 3
23361 …P_RESERVEDREGISTER2384_RESERVEDFIELD2932_K2_E5 (0x7<<3) // Reserved
23362 …HY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2384_RESERVEDFIELD2932_K2_E5_SHIFT 3
23366 …P_RESERVEDREGISTER2385_RESERVEDFIELD2934_K2_E5 (0x7<<3) // Reserved
23367 …HY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2385_RESERVEDFIELD2934_K2_E5_SHIFT 3
23382 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
23389 …P_RESERVEDREGISTER2388_RESERVEDFIELD2939_K2_E5 (0x1<<3) // Reserved
23390 …HY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2388_RESERVEDFIELD2939_K2_E5_SHIFT 3
23412 …P_RESERVEDREGISTER2391_RESERVEDFIELD2949_K2_E5 (0x1<<3) // Reserved
23413 …HY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2391_RESERVEDFIELD2949_K2_E5_SHIFT 3
23434 …P_RESERVEDREGISTER2395_RESERVEDFIELD2958_K2_E5 (0x7<<3) // Reserved
23435 …HY_NW_IP_REG_LN3_TOP_RESERVEDREGISTER2395_RESERVEDFIELD2958_K2_E5_SHIFT 3
23464 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
23465 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
23467 … (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macr…
23522 …R_RXCLK_RESERVEDREGISTER2418_RESERVEDFIELD2993_K2_E5 (0x1<<3) // Reserved
23523 …HY_NW_IP_REG_LN3_CDR_RXCLK_RESERVEDREGISTER2418_RESERVEDFIELD2993_K2_E5_SHIFT 3
23534 … 0x00c2fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control in…
23536 …BINARY_VAL_8_K2_E5 (0x1<<0) // Binary-coded DLPF control in…
23543 …ce lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by set…
23602 …R_REFCLK_RESERVEDREGISTER2443_RESERVEDFIELD3024_K2_E5 (0x7<<3) // Reserved
23603 …HY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2443_RESERVEDFIELD3024_K2_E5_SHIFT 3
23636 …R_REFCLK_RESERVEDREGISTER2451_RESERVEDFIELD3038_K2_E5 (0xf<<3) // Reserved
23637 …HY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2451_RESERVEDFIELD3038_K2_E5_SHIFT 3
23654 …R_REFCLK_RESERVEDREGISTER2455_RESERVEDFIELD3045_K2_E5 (0x3<<3) // Reserved
23655 …HY_NW_IP_REG_LN3_CDR_REFCLK_RESERVEDREGISTER2455_RESERVEDFIELD3045_K2_E5_SHIFT 3
23701 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
23719 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
23723 …3) // Autoneg ability. When read as a one, it indicates that the PMA/PMD has the ability to perfo…
23724 …HY_NW_IP_REG_LN3_ANEG_STATUS0_AUTONEG_ABILITY_K2_E5_SHIFT 3
23736 …1_NP_LOADED_K2_E5 (0x1<<3) // mr_np_loaded sta…
23737 …HY_NW_IP_REG_LN3_ANEG_STATUS1_NP_LOADED_K2_E5_SHIFT 3
23742 … 0x00c650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
23743 … 0x00c654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
23747 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
23750 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller ge…
23754 …AGE1_ASM_DIR_K2_E5 (0x1<<3) // Pause ASM_DIR ad…
23755 …HY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_ASM_DIR_K2_E5_SHIFT 3
23766 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
23768 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
23770 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
23772 …H0_ABILITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology …
23773 …HY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT 3
23774 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
23776 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
23778 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
23780 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
23783 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
23785 …TY_25G_GR_S_K2_E5 (0x1<<1) // 25GBase-GR-S KR or CR technolog…
23787 …LITY_25G_GR_K2_E5 (0x1<<2) // 25GBase-GR KR or CR technolog…
23789 …1_K2_E5 (0x1f<<3) // technology advertised ability Field A15…
23790 …HY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5_SHIFT 3
23792 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
23795 …TY_K2_E5 (0x1<<0) // base page bit F0. It advertises …
23797 …2_E5 (0x1<<1) // base page bit F1. It requests FE…
23799 … (0x1<<2) // base page bit F2. It requests RS-FEC for 25G-GR 25G-KR…
23801 … (0x1<<3) // base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or 25G-G…
23802 …HY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5_SHIFT 3
23804 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
23806 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
23808 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
23810 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consor…
23811 …HY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_50G_CR2_K2_E5_SHIFT 3
23812 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
23814 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
23816 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
23818 …ed FEC field 3. It requests Fire code FEC to be turned on when supported at the both ends of link…
23824 …EG_RESERVEDREGISTER2476_RESERVEDFIELD3074_K2_E5 (0x1<<3) // Reserved
23825 …HY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2476_RESERVEDFIELD3074_K2_E5_SHIFT 3
23843 …EG_RESERVEDREGISTER2481_RESERVEDFIELD3081_K2_E5 (0x1<<3) // Reserved
23844 …HY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2481_RESERVEDFIELD3081_K2_E5_SHIFT 3
23860 …EG_RESERVEDREGISTER2482_RESERVEDFIELD3089_K2_E5 (0x1<<3) // Reserved
23861 …HY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2482_RESERVEDFIELD3089_K2_E5_SHIFT 3
23871 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
23874 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
23878 …E_PAGE1_ASM_DIR_K2_E5 (0x1<<3) // Link partner Pau…
23879 …HY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_ASM_DIR_K2_E5_SHIFT 3
23892 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
23894 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
23896 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
23898 …ABILITY_40G_KR4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 tech…
23899 …HY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT 3
23900 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
23902 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
23904 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
23906 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
23909 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
23911 …S_K2_E5 (0x1<<1) // Link partner 25GBase-GR-S KR or CR technolog…
23913 …R_K2_E5 (0x1<<2) // Link partner 25GBase-GR KR or CR technolog…
23915 …2_E5 (0x1f<<3) // Link partner technology advertised ability Fi…
23916 …HY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11_K2_E5_SHIFT 3
23918 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
23921 … (0x1<<0) // Link partner base page bit F0. It advertises …
23923 … (0x1<<1) // Link partner base page bit F1. It requests FE…
23925 … (0x1<<2) // Link partner base page bit F2. It requests RS-FEC for 25G-GR 25G-KR…
23927 … (0x1<<3) // Link partner base page bit F3. It requests FC-FEC Base-R FEC for 25G-GR or…
23928 …HY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G_K2_E5_SHIFT 3
23930 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
23932 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
23934 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
23936 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G …
23937 …HY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_50G_CR2_K2_E5_SHIFT 3
23938 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
23940 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
23942 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
23944 …ed FEC field 3. It requests Fire code FEC to be turned on when supported at the both ends of link…
23950 …EG_RESERVEDREGISTER2484_RESERVEDFIELD3094_K2_E5 (0x1<<3) // Reserved
23951 …HY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2484_RESERVEDFIELD3094_K2_E5_SHIFT 3
23969 …EG_RESERVEDREGISTER2489_RESERVEDFIELD3101_K2_E5 (0x1<<3) // Reserved
23970 …HY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2489_RESERVEDFIELD3101_K2_E5_SHIFT 3
23986 …EG_RESERVEDREGISTER2490_RESERVEDFIELD3109_K2_E5 (0x1<<3) // Reserved
23987 …HY_NW_IP_REG_LN3_ANEG_RESERVEDREGISTER2490_RESERVEDFIELD3109_K2_E5_SHIFT 3
23995 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
23997 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
23999 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
24001 …_40G_KR4_K2_E5 (0x1<<3) // Resolution result for 40GBase-KR4.…
24002 …HY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4_K2_E5_SHIFT 3
24003 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
24005 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
24007 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
24009 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
24012 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
24014 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
24016 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
24018 …_25G_KR_K2_E5 (0x1<<3) // Resolution result for 25GBase-KR. …
24019 …HY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR_K2_E5_SHIFT 3
24020 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
24022 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
24024 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
24027 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
24040 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
24042 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
24044 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
24046 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
24047 …HY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_40G_KR4_K2_E5_SHIFT 3
24048 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
24050 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
24052 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
24054 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
24057 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
24059 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
24061 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
24062 …HY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_25G_KR_K2_E5_SHIFT 3
24063 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
24065 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
24067 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
24085 …E_RESERVEDREGISTER2494_RESERVEDFIELD3119_K2_E5 (0x1<<3) // Reserved
24086 …HY_NW_IP_REG_LN3_EEE_RESERVEDREGISTER2494_RESERVEDFIELD3119_K2_E5_SHIFT 3
24103 …Q_REFCLK_RESERVEDREGISTER2500_RESERVEDFIELD3128_K2_E5 (0x3<<3) // Reserved
24104 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2500_RESERVEDFIELD3128_K2_E5_SHIFT 3
24110 …Q_REFCLK_RESERVEDREGISTER2501_RESERVEDFIELD3131_K2_E5 (0x1<<3) // Reserved
24111 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2501_RESERVEDFIELD3131_K2_E5_SHIFT 3
24121 …Q_REFCLK_RESERVEDREGISTER2504_RESERVEDFIELD3135_K2_E5 (0x7<<3) // Reserved
24122 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2504_RESERVEDFIELD3135_K2_E5_SHIFT 3
24126 …Q_REFCLK_RESERVEDREGISTER2505_RESERVEDFIELD3137_K2_E5 (0x7<<3) // Reserved
24127 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2505_RESERVEDFIELD3137_K2_E5_SHIFT 3
24140 …Q_REFCLK_RESERVEDREGISTER2507_RESERVEDFIELD3143_K2_E5 (0x7<<3) // Reserved
24141 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2507_RESERVEDFIELD3143_K2_E5_SHIFT 3
24145 …Q_REFCLK_RESERVEDREGISTER2508_RESERVEDFIELD3145_K2_E5 (0x7<<3) // Reserved
24146 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2508_RESERVEDFIELD3145_K2_E5_SHIFT 3
24150 …Q_REFCLK_RESERVEDREGISTER2509_RESERVEDFIELD3147_K2_E5 (0x7<<3) // Reserved
24151 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2509_RESERVEDFIELD3147_K2_E5_SHIFT 3
24155 …Q_REFCLK_RESERVEDREGISTER2510_RESERVEDFIELD3149_K2_E5 (0x7<<3) // Reserved
24156 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2510_RESERVEDFIELD3149_K2_E5_SHIFT 3
24172 …Q_REFCLK_RESERVEDREGISTER2515_RESERVEDFIELD3157_K2_E5 (0x7<<3) // Reserved
24173 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2515_RESERVEDFIELD3157_K2_E5_SHIFT 3
24282 …Q_REFCLK_RESERVEDREGISTER2542_RESERVEDFIELD3203_K2_E5 (0x1<<3) // Reserved
24283 …HY_NW_IP_REG_LN3_LEQ_REFCLK_RESERVEDREGISTER2542_RESERVEDFIELD3203_K2_E5_SHIFT 3
24644 …_REFCLK_RESERVEDREGISTER2629_RESERVEDFIELD3347_K2_E5 (0x1f<<3) // Reserved
24645 …HY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2629_RESERVEDFIELD3347_K2_E5_SHIFT 3
24649 …V_REFCLK_RESERVEDREGISTER2630_RESERVEDFIELD3349_K2_E5 (0x3<<3) // Reserved
24650 …HY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2630_RESERVEDFIELD3349_K2_E5_SHIFT 3
24659 …V_REFCLK_RESERVEDREGISTER2632_RESERVEDFIELD3353_K2_E5 (0x3<<3) // Reserved
24660 …HY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2632_RESERVEDFIELD3353_K2_E5_SHIFT 3
24673 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
24679 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
24710 …V_REFCLK_RESERVEDREGISTER2638_RESERVEDFIELD3368_K2_E5 (0x3<<3) // Reserved
24711 …HY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2638_RESERVEDFIELD3368_K2_E5_SHIFT 3
24715 …V_REFCLK_RESERVEDREGISTER2639_RESERVEDFIELD3370_K2_E5 (0x3<<3) // Reserved
24716 …HY_NW_IP_REG_LN3_DRV_REFCLK_RESERVEDREGISTER2639_RESERVEDFIELD3370_K2_E5_SHIFT 3
24733 …E_REFCLK_RESERVEDREGISTER2643_RESERVEDFIELD3377_K2_E5 (0x7<<3) // Reserved
24734 …HY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2643_RESERVEDFIELD3377_K2_E5_SHIFT 3
24790 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
24820 …E_REFCLK_FSM_STATUS0_RESERVEDFIELD3411_K2_E5 (0x1<<3) // Reserved
24821 …HY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0_RESERVEDFIELD3411_K2_E5_SHIFT 3
24823 …les updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
24825 …les updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
24827 …bles updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note t…
24829 … (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command e…
24830 …HY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_K2_E5_SHIFT 3
24831 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24833 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disable…
24835 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24837 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24865 …_E5 (0x7<<0) // Starting value for Tap 3 for Tap Adaptations
24905 …_E5 (0x7<<0) // Loading value for Tap 3 for Tap Adaptations
24945 … (0x7<<0) // binary value for Tap 3 for Tap Adaptations
24966 …E_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3415_K2_E5 (0x1<<3) // Reserved
24967 …HY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2663_RESERVEDFIELD3415_K2_E5_SHIFT 3
25037 …E_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3441_K2_E5 (0x1<<3) // Reserved
25038 …HY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2682_RESERVEDFIELD3441_K2_E5_SHIFT 3
25061 …E_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3452_K2_E5 (0x1<<3) // Reserved
25062 …HY_NW_IP_REG_LN3_DFE_REFCLK_RESERVEDREGISTER2684_RESERVEDFIELD3452_K2_E5_SHIFT 3
25249 …2_E5 (0x1<<0) // Enables the run-length detection digi…
25251 … 0x00d410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
25253 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
25255 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
25311 …S_REFCLK_RESERVEDREGISTER2774_RESERVEDFIELD3565_K2_E5 (0xf<<3) // Reserved
25312 …HY_NW_IP_REG_LN3_LOS_REFCLK_RESERVEDREGISTER2774_RESERVEDFIELD3565_K2_E5_SHIFT 3
25341 …STATUS0_LOS_RAW_K2_E5 (0x1<<3) // The unfiltered L…
25342 …HY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS_RAW_K2_E5_SHIFT 3
25426 … 0x00d81cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
25427 … 0x00d820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
25462 …S 0xC001 0x5 � PRBS 0x840001 0x6 � PRBS 0x90000001 0x7 � User defined pattern UDP 0x8 � Auto-detect
25464 …K2_E5 (0x1<<5) // Clears the bit error counter.
25468 …ces the PRBS LFSR to reseed with Rx data every cycle. This will cause the bit error counter to be…
25473 …TUS_PATTERN_DET_K2_E5 (0xf<<3) // Indicates the pa…
25474 …HY_NW_IP_REG_LN3_BIST_RX_STATUS_PATTERN_DET_K2_E5_SHIFT 3
25475 … 0x00da20UL //Access:R DataWidth:0x8 // Number of bit errors.
25476 … 0x00da24UL //Access:R DataWidth:0x8 // Number of bit errors.
25477 … 0x00da28UL //Access:R DataWidth:0x8 // Number of bit errors.
25485 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
25486 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
25487 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
25488 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
25490 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
25536 …ATURE_RESERVEDREGISTER2816_RESERVEDFIELD3619_K2_E5 (0x1<<3) // Reserved
25537 …HY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2816_RESERVEDFIELD3619_K2_E5_SHIFT 3
25549 …ATURE_RESERVEDREGISTER2817_RESERVEDFIELD3625_K2_E5 (0x1<<3) // Reserved
25550 …HY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2817_RESERVEDFIELD3625_K2_E5_SHIFT 3
25558 …ATURE_RESERVEDREGISTER2818_RESERVEDFIELD3629_K2_E5 (0x1<<3) // Reserved
25559 …HY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2818_RESERVEDFIELD3629_K2_E5_SHIFT 3
25575 …ATURE_RESERVEDREGISTER2819_RESERVEDFIELD3637_K2_E5 (0x1<<3) // Reserved
25576 …HY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2819_RESERVEDFIELD3637_K2_E5_SHIFT 3
25636 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
25638 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
25651 …E_ADAPT_HFG_CFG0_INIT1_DATA_EN_K2_E5 (0x1<<3) // Enables CTLE EQ …
25652 …HY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_K2_E5_SHIFT 3
25680 …ATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD3668_K2_E5 (0x1<<3) // Reserved
25681 …HY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_RESERVEDFIELD3668_K2_E5_SHIFT 3
25689 …ATURE_RESERVEDREGISTER2830_RESERVEDFIELD3672_K2_E5 (0x1<<3) // Reserved
25690 …HY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2830_RESERVEDFIELD3672_K2_E5_SHIFT 3
25704 … (0x1<<2) // Enables DFE Tap 3. Tap3 will not be po…
25706 …_CFG_TAP4_EN_K2_E5 (0x1<<3) // Enables DFE Tap …
25707 …HY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP4_EN_K2_E5_SHIFT 3
25711 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Base…
25720 …ATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD3679_K2_E5 (0x1<<3) // Reserved
25721 …HY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG_RESERVEDFIELD3679_K2_E5_SHIFT 3
25729 …ATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD3682_K2_E5 (0x1<<3) // Reserved
25730 …HY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG_RESERVEDFIELD3682_K2_E5_SHIFT 3
25732 …_INIT_EN_K2_E5 (0x1<<0) // Enables initial adaptations for Tap 3
25738 …ATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD3685_K2_E5 (0x1<<3) // Reserved
25739 …HY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG_RESERVEDFIELD3685_K2_E5_SHIFT 3
25747 …ATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD3688_K2_E5 (0x1<<3) // Reserved
25748 …HY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG_RESERVEDFIELD3688_K2_E5_SHIFT 3
25756 …ATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD3691_K2_E5 (0x1<<3) // Reserved
25757 …HY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG_RESERVEDFIELD3691_K2_E5_SHIFT 3
25784 …TURE_RESERVEDREGISTER2840_RESERVEDFIELD3704_K2_E5 (0x1f<<3) // Reserved
25785 …HY_NW_IP_REG_LN3_FEATURE_RESERVEDREGISTER2840_RESERVEDFIELD3704_K2_E5_SHIFT 3
25803 …ATURE_TEST_CFG0_RESERVEDFIELD3711_K2_E5 (0x1<<3) // Reserved
25804 …HY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_RESERVEDFIELD3711_K2_E5_SHIFT 3
25820 …TRL0_CLEAR_K2_E5 (0x1<<3) // Synchronous rese…
25821 …HY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_CLEAR_K2_E5_SHIFT 3
25840 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
25845 …11 1 � CL93 1 + x^5 + x^6 + x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6…
25852 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
25856 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
25863 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
25867 …E5 (0x3<<4) // Status report field for pre-cursor tap.
25887 …11 1 � CL93 1 + x^5 + x^6 + x^10 + x^11 2 � CL93 1 + x^5 + x^6 + x^9 + x^11 3 � CL93 1 + x^4 + x^6…
25889 … 0x00df0cUL //Access:RW DataWidth:0x8 // Maximum number of PRBS bit errors allowed in s…
25895 … 0x00df18UL //Access:R DataWidth:0x8 // Number of bit errors in PRBS patt…
25910 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
25914 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
25921 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
25925 … (0x3<<4) // Received status report field for pre-cursor tap.
25937 …7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Ov…
25939 …0_X1_PMA_CM_REF_CLK_DIV_O_K2_E5 (0x3<<3) // Divider for pma_…
25940 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_PMA_CM_REF_CLK_DIV_O_K2_E5_SHIFT 3
25948 …0_X2_CDR_REFCLK_SEL_O_2_0_K2_E5 (0x7<<3) // Selects one lane…
25949 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X2_CDR_REFCLK_SEL_O_2_0_K2_E5_SHIFT 3
25950 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
25953 …AHB_PMA_CM_DIVNSEL_O_6_0_K2_E5 (0x7f<<0) // CMU N-divider setting
25961 …0_X5_AHB_PMA_CM_PREDIV4_ENA_O_K2_E5 (0x1<<3) // CMU FL prediv4 e…
25962 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PREDIV4_ENA_O_K2_E5_SHIFT 3
25965 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25966 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25967 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25969 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25971 … 0x000028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
25972 … 0x00002cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
25973 … 0x000030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
25974 … 0x000034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
25975 … 0x000038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
25976 … 0x00003cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
25977 … 0x000040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
25978 … 0x000044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
25979 … 0x000048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
25980 … 0x00004cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
25981 … 0x000050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
25982 … 0x000054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
25983 … 0x000058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
25984 … 0x00005cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
25985 … 0x000060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
25986 … 0x000064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
26004 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
26006 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
26008 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
26010 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26013 …he following functions: [0] - active high, Override Enable [1] - SOC clock output…
26015 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26017 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26019 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
26022 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26024 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26026 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26028 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26031 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
26033 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26035 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26037 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
26040 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
26042 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26044 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26096 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
26104 …<3) // Overrides for PLL lock signals [2] - Active high, override enable [1] - PLL ok override, by…
26105 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_OVR_O_K2_E5_SHIFT 3
26120 …0_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O_K2_E5 (0x1<<3) // Charge pump chop…
26121 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O_K2_E5_SHIFT 3
26138 …2_E5 (0x1<<2) // Override enable for overriding N-div value
26140 …0_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O_K2_E5 (0x1<<3) // CMU V2I filter e…
26141 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O_K2_E5_SHIFT 3
26154 …_X100_AHB_PMA_CM_P_KVCO_SEL_O_K2_E5 (0x1f<<3) // CMU PLL KVCO set…
26155 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_P_KVCO_SEL_O_K2_E5_SHIFT 3
26157 …1_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
26162 …0_X102_AHB_PMA_CM_VCOFR_SEL_O_K2_E5 (0x1<<3) // Override enable …
26163 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_SEL_O_K2_E5_SHIFT 3
26170 …0_X108_PMA_REFCLK_OUTPUT_SEL_O_3_0_K2_E5 (0xf<<3) // Reference clock …
26171 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_OUTPUT_SEL_O_3_0_K2_E5_SHIFT 3
26181 …0_X109_PMA_RXCLK_OE_R_O_K2_E5 (0x1<<3) // Override for pri…
26182 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_R_O_K2_E5_SHIFT 3
26207 … // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down…
26214 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
26216 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
26225 …TEMP_CAL_POLARITY_O_K2_E5 (0x1<<6) // chicken bit for counter polarity
26229 … 0x0001e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
26231 …P_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
26254 …HB_RX_TC_BIAS_OVR_K2_E5 (0x7<<1) // Bit 3:1 RX termination c…
26261 … 0x000200UL //Access:RW DataWidth:0x8 // Bit 7:5 amux_ena[2:0] Bit 4:0 amux…
26263 …erride for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pi…
26271 … 0x000210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
26273 …BUS_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
26287 … function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - …
26324 …0_X191_PD_CMU_IDDQ_SETVAL_O_K2_E5 (0x1<<3) // MSM Function IDD…
26325 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_CMU_IDDQ_SETVAL_O_K2_E5_SHIFT 3
26341 …0_X192_RESET_CMUREGREF_IDDQ_SETVAL_O_K2_E5 (0x1<<3) // MSM Function IDD…
26342 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREGREF_IDDQ_SETVAL_O_K2_E5_SHIFT 3
26358 …_CMU_CSR_0_X193_RESET_TXCLK_IDDQ_SETVAL_O_K2_E5 (0x1<<3) // Not used
26359 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_RESET_TXCLK_IDDQ_SETVAL_O_K2_E5_SHIFT 3
26375 …0_X194_PD_CMU_RST_SETVAL_O_K2_E5 (0x1<<3) // MSM Function RST…
26376 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_CMU_RST_SETVAL_O_K2_E5_SHIFT 3
26392 …0_X195_RESET_CMUREGREF_RST_SETVAL_O_K2_E5 (0x1<<3) // MSM Function RST…
26393 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREGREF_RST_SETVAL_O_K2_E5_SHIFT 3
26409 …_CMU_CSR_0_X196_RESET_TXCLK_RST_SETVAL_O_K2_E5 (0x1<<3) // Not used
26410 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_RESET_TXCLK_RST_SETVAL_O_K2_E5_SHIFT 3
26426 …0_X197_PD_CMU_NORM_SETVAL_O_K2_E5 (0x1<<3) // MSM Function NOR…
26427 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_CMU_NORM_SETVAL_O_K2_E5_SHIFT 3
26443 …0_X198_RESET_CMUREGREF_NORM_SETVAL_O_K2_E5 (0x1<<3) // MSM Function NOR…
26444 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREGREF_NORM_SETVAL_O_K2_E5_SHIFT 3
26460 …_CMU_CSR_0_X199_RESET_TXCLK_NORM_SETVAL_O_K2_E5 (0x1<<3) // Not used
26461 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_RESET_TXCLK_NORM_SETVAL_O_K2_E5_SHIFT 3
26477 …0_X200_PD_CMU_PD_SETVAL_O_K2_E5 (0x1<<3) // MSM Function POW…
26478 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_CMU_PD_SETVAL_O_K2_E5_SHIFT 3
26494 …0_X201_RESET_CMUREGREF_PD_SETVAL_O_K2_E5 (0x1<<3) // MSM Function POW…
26495 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREGREF_PD_SETVAL_O_K2_E5_SHIFT 3
26511 …_CMU_CSR_0_X202_RESET_TXCLK_PD_SETVAL_O_K2_E5 (0x1<<3) // Not used
26512 …HY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_RESET_TXCLK_PD_SETVAL_O_K2_E5_SHIFT 3
26523 …k : 3'b000 - lnX_clk_i 3'b001- qd_ck_i 3'b010 - pma_lX_rxb_iRecovered byte clock 3'b011 - ck_soc1…
26525 …_O_K2_E5 (0x1<<3) // Clock divider for TX path branch 1 : 0-No divi…
26526 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH1_DIV_SEL_O_K2_E5_SHIFT 3
26527 …path branch 2 clock : 3'b000 - lnX_clk_i 3'b001- qd_ck_i 3'b011 - ck_soc1_int_root 3'b010,3'b100,3…
26529 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
26532 …clock : 3'b000 - pma_lX_rxb_iRecovered byte clock 3'b001- pma_lX_txb_iTransmit byte clock 3'b010,3…
26534 …_O_K2_E5 (0x1<<3) // Clock divider for RX path branch 1 : 0-No divi…
26535 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_K2_E5_SHIFT 3
26536 …clock : 3'b000 - pma_lX_rxb_iRecovered byte clock 3'b001- pma_lX_txb_iTransmit byte clock 3'b010,3…
26538 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
26541 …3 clock : 3'b000 - qd_ck_i 3'b001- pma_lX_rxb_iRecovered byte clock 3'b010 - lnX_clk_i 3'b011 - pm…
26543 …_O_K2_E5 (0x1<<3) // Clock divider for RX path branch 3 : 0-No divi…
26544 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH3_DIV_SEL_O_K2_E5_SHIFT 3
26545 …3'b000 - qd_ck_i 3'b001- pma_lX_rxb_iRecovered byte clock 3'b010 - lnX_clk_i 3'b011 - pma_lX_txb_i…
26547 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
26550 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
26552 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
26555 …0_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
26560 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
26562 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
26567 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
26569 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outpu…
26570 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_ERR_O_K2_E5_SHIFT 3
26575 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
26577 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
26582 … (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist…
26583 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_SEND_PREAM_O_K2_E5_SHIFT 3
26584 …/ Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ev…
26586 … 0x001024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
26587 … 0x001028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
26588 … 0x00102cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
26589 … 0x001030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
26590 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
26592 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
26599 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
26601 …_1_X15_BIST_CHK_DATA_MODE_O_K2_E5 (0x1<<3) // Bist checker mod…
26602 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_DATA_MODE_O_K2_E5_SHIFT 3
26607 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
26609 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
26613 …_ON_ZEROS_K2_E5 (0x1<<5) // Setting this bit allows BIST to sync…
26619 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
26620 … 0x001054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26621 … 0x001058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26622 … 0x00105cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26623 … 0x001060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26631 … 0x001080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
26632 … 0x001084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
26633 … 0x001088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
26634 … 0x00108cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
26635 … 0x001090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
26636 … 0x001094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
26637 … 0x001098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
26638 … 0x00109cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
26639 … 0x0010a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
26640 … 0x0010a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
26641 … 0x0010a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
26642 … 0x0010acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
26643 … 0x0010b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
26644 … 0x0010b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
26645 … 0x0010b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
26646 … 0x0010bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
26647 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
26648 …L //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA met…
26649 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
26650 …/Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA met…
26655 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
26657 …E5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
26659 …_K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
26661 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
26662 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
26663 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
26665 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
26667 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
26679 … enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a…
26680 … enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a…
26682 …K2_E5 (0x3<<0) // Bit 0: Override enable for msm_ln_req Bit …
26684 …_E5 (0x3f<<2) // Bit 2: Override enable for msm_func Bits [7:…
26712 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
26714 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
26716 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
26718 …_1_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5 (0x7<<3) // Number of clock …
26719 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5_SHIFT 3
26720 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
26721 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
26722 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
26724 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
26726 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
26742 …_1_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5 (0x1<<3) // Override for ei_…
26743 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5_SHIFT 3
26776 …EL_DIV2_O_K2_E5 (0x7<<3) // Signal detect threshold select for div-b…
26777 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_K2_E5_SHIFT 3
26783 …_O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
26785 …_1_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5 (0x7<<3) // AGC threshold se…
26786 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5_SHIFT 3
26815 …_1_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5 (0x1<<3) // Override enable …
26816 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5_SHIFT 3
26826 …0x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit…
26828 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
26830 …-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2…
26834 …_1_X101_PMA_LN_SD_BWSEL_K2_E5 (0x1<<3) // RX signal detect…
26835 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_SD_BWSEL_K2_E5_SHIFT 3
26846 … // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 bit 2: C1
26875 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
26877 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
26889 … (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not …
26891 … (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_sle…
26894 …11f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx_slew_sld3f[2…
26900 … (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is l…
26902 … (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is l…
26904 … (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is l…
26906 … (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is l…
26909 …3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6:…
26912 …3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6:…
26962 …_K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
26964 …K2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
26973 …_CSR_1_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5 (0x1<<3) // boost_adj_dir
26974 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5_SHIFT 3
26975 …2_E5 (0xf<<4) // boost_adj_val This register Is not bit reversed
27003 …: 1: Calibrate DFE comparator 1 2: Calibrate DFE comparator 2 3: Calibrate DFE comparator 3 4: Cal…
27005 …_1_X150_RXEQ_ATT_GAIN_OVR_K2_E5 (0x3<<3) // Override the val…
27006 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_ATT_GAIN_OVR_K2_E5_SHIFT 3
27029 …DFE_TAP3_OVR_VAL_O_5_0_K2_E5 (0x3f<<0) // DFE Tap 3 Override Value
27041 … (0x1<<0) // This bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is l…
27044 …_K2_E5 (0x1<<0) // cdfe enable bit. 1: enable cdfe wh…
27046 …o 0 8-bit or 10-bit mode. 2'b11: the word_i …
27048 …3) // The cdfe input mode_8b_i overwrite. …
27049 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_CDFE_MODE_8B_OV_O_1_0_K2_E5_SHIFT 3
27050 … 3'b0xx: the rate_i input for cdfe block is internally generated. …
27069 …_1_X204_CDFE_LN_RATE3_CAL_EN_K2_E5 (0x1<<3) // Enables the cdfe…
27070 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_CAL_EN_K2_E5_SHIFT 3
27073 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
27074 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
27075 …-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
27083 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
27084 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
27085 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
27086 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
27087 …-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
27092 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
27095 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
27104 …) // Override for CMP1 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[3]
27119 …) // Override for CMP2 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[3]
27134 …) // Override for CMP3 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[3]
27149 …) // Override for CMP4 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[3]
27179 …_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5 (0x1<<3) //
27180 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT 3
27192 …_1_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5 (0x1<<3) // Override enable …
27193 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5_SHIFT 3
27212 …Register override for overriding adaptation comparator select bit [0] : override enable bit [4:1] …
27214 …er override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] …
27216 …er override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] …
27219 …Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3…
27265 …1_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
27266 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5_SHIFT 3
27270 …1_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
27271 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5_SHIFT 3
27275 …1_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
27276 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5_SHIFT 3
27280 …1_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
27281 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5_SHIFT 3
27285 …1_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
27286 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5_SHIFT 3
27288 …O_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_ra Bit…
27290 …_O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_p2s Bi…
27292 …R_O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_lnregh B…
27294 …R_O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_reset_lnreg B…
27297 …_O_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr Bi…
27299 …_O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_dfe Bi…
27301 …_O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_pd_lnregh Bi…
27303 …_O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco_buf Bi…
27306 …VR_O_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr_gcrx …
27308 …_O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_rxgate_en Bi…
27310 …_O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_vco Bi…
27312 …O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_iddq_sd Bit…
27315 …_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_dfe Bit …
27317 …R_O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_dfe_bias B…
27319 …VR_O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_txdrv_lp_idle …
27321 …OVR_O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_txreg_bleed_ena…
27324 …O_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_txreg Bit…
27326 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_lnreg Bit…
27328 …_O_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_p2s Bit 1:…
27330 …_O_K2_E5 (0x3<<6) // Bit 0: Override enable for pd_ra Bit 1:…
27333 …OVR_O_K2_E5 (0x3<<2) // Bit 0: Override enable for pd_slv_bias Bit…
27335 …R_O_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_txdrv Bit 1…
27337 …_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco Bit …
27340 …_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_cdr_en Bit …
27342 …_O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_s2p Bi…
27344 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_rxclk_en Bit…
27346 …K2_E5 (0x3<<6) // Bit 0: Override enable for msm_word Bit 1…
27349 …K2_E5 (0x7<<0) // Bit 0: Override enable for msm_rate Bit […
27351 …VR_O_K2_E5 (0x7<<3) // Bit 0: Override enable for msm_rxvcodiv …
27352 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RXVCODIV_OVR_O_K2_E5_SHIFT 3
27356 …O_K2_E5 (0x7<<0) // Bit 0: Override enable for msm_txvcodiv Bit…
27359 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
27361 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
27363 …0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
27365 … (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not…
27366 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_TREG0_WORD_O_K2_E5_SHIFT 3
27369 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
27372 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
27374 …0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
27376 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27378 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmo…
27379 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG1_POL_O_K2_E5_SHIFT 3
27380 …(0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
27382 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27387 …(0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
27389 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27393 …03_TX_CTRL_O_24_K2_E5 (0x1<<5) // Bit 24: txdrv_c2_in[3]
27395 …CHNG_EN_O_K2_E5 (0x1<<6) // Enable bit for width_chng modu…
27402 … (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2�b00: no bit stripping 2�b01: 2x bit…
27403 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X304_AHB_LN_RXBIT_STRIP_O_K2_E5_SHIFT 3
27407 …included to handle the communication between the external 64-bit data and the internal 20-bit data…
27409 …Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2�b00: no bit stuf…
27411 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
27437 …_1_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5 (0x1<<3) // Receive amplifie…
27438 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5_SHIFT 3
27450 …_1_X317_ENC_EN_OVR_O_K2_E5 (0x1<<3) // Enables 16b/20b …
27451 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_ENC_EN_OVR_O_K2_E5_SHIFT 3
27452 …f<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty…
27455 …O_1_0_K2_E5 (0x3<<0) // Bit[0]: Overide value. Bit[1] :Over…
27457 …x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 …
27459 … (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable…
27462 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is …
27464 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is …
27466 …x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 …
27472 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
27473 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
27474 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
27475 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
27476 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
27477 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
27479 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
27481 …nd each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writi…
27488 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
27495 …_1_X330_LN_IN_OVR_O_50_K2_E5 (0x1<<3) // Override signals…
27496 …HY_SGMII_IP_REG_AHB_LANE_CSR_1_X330_LN_IN_OVR_O_50_K2_E5_SHIFT 3
27498 … (0x1<<0) // Lane Reference Clock Enable. 0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - …
27501 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
27503 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
27509 …818UL //Access:RW DataWidth:0x8 // Symbol aligner alignment word. Expects bit 0 received first
27511 … (0x3<<0) // Symbol aligner alignment word. Expects bit 0 received first
27537 …CSR_5_X49_EYE_SCAN_SHIFT_DIR_O_K2_E5 (0x1<<3) // Determines shift…
27538 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_DIR_O_K2_E5_SHIFT 3
27553 … 0x0028e0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
27554 … 0x0028e4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
27555 … 0x0028e8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
27556 … 0x0028ecUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
27557 … 0x0028f0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
27558 … 0x0028f4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
27559 … 0x0028f8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
27560 … 0x0028fcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
27561 … 0x002900UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
27562 … 0x002904UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
27563 … 0x002908UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
27564 … 0x00290cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
27565 … 0x002910UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
27566 … 0x002914UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
27567 … 0x002918UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
27568 … 0x00291cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
27571 …nction. Varies depending on function number. Bits 15-7: Address of first command to run Bits: 6-…
27640 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
27641 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
27649 …CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREG_O_K2_E5 (0x1<<3) // MSM Function IDD…
27650 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREG_O_K2_E5_SHIFT 3
27666 …CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_O_K2_E5 (0x1<<3) // MSM Function IDD…
27667 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_O_K2_E5_SHIFT 3
27683 …CSR_5_X145_MSM_SAPI_IDDQ_RESET_RA_O_K2_E5 (0x1<<3) // MSM Function IDD…
27684 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_RA_O_K2_E5_SHIFT 3
27700 …CSR_5_X146_MSM_SAPI_IDDQ_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MSM Function IDD…
27701 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
27709 …CSR_5_X147_MSM_SAPI_RST_PD_LNREG_O_K2_E5 (0x1<<3) // MSM Function RES…
27710 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREG_O_K2_E5_SHIFT 3
27726 …CSR_5_X148_MSM_SAPI_RST_PD_VCO_O_K2_E5 (0x1<<3) // MSM Function RES…
27727 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_O_K2_E5_SHIFT 3
27743 …CSR_5_X149_MSM_SAPI_RST_RESET_RA_O_K2_E5 (0x1<<3) // MSM Function RES…
27744 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_RA_O_K2_E5_SHIFT 3
27760 …CSR_5_X150_MSM_SAPI_RST_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MSM Function RES…
27761 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
27769 …CSR_5_X151_MSM_SAPI_NORM_PD_LNREG_O_K2_E5 (0x1<<3) // MSM Function NOR…
27770 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREG_O_K2_E5_SHIFT 3
27786 …CSR_5_X152_MSM_SAPI_NORM_PD_VCO_O_K2_E5 (0x1<<3) // MSM Function NOR…
27787 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_O_K2_E5_SHIFT 3
27803 …CSR_5_X153_MSM_SAPI_NORM_RESET_RA_O_K2_E5 (0x1<<3) // MSM Function NOR…
27804 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_RA_O_K2_E5_SHIFT 3
27820 …CSR_5_X154_MSM_SAPI_NORM_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MSM Function NOR…
27821 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
27829 …CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREG_O_K2_E5 (0x1<<3) // MSM Function PAR…
27830 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREG_O_K2_E5_SHIFT 3
27846 …CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_O_K2_E5 (0x1<<3) // MSM Function PAR…
27847 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_O_K2_E5_SHIFT 3
27863 …CSR_5_X157_MSM_SAPI_PARTIAL_RESET_RA_O_K2_E5 (0x1<<3) // MSM Function PAR…
27864 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_RA_O_K2_E5_SHIFT 3
27880 …CSR_5_X158_MSM_SAPI_PARTIAL_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MSM Function PAR…
27881 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
27889 …CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREG_O_K2_E5 (0x1<<3) // MSM Function SLU…
27890 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREG_O_K2_E5_SHIFT 3
27906 …CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_O_K2_E5 (0x1<<3) // MSM Function SLU…
27907 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_O_K2_E5_SHIFT 3
27923 …CSR_5_X161_MSM_SAPI_SLUMBER_RESET_RA_O_K2_E5 (0x1<<3) // MSM Function SLU…
27924 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_RA_O_K2_E5_SHIFT 3
27940 …CSR_5_X162_MSM_SAPI_SLUMBER_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MSM Function SLU…
27941 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
27978 …_LOW_EN_O_K2_E5 (0x1<<6) // Brings the TxEq pre-cursor down to a prog…
27980 …LOW_EN_O_K2_E5 (0x1<<7) // Brings the TxEq pre-cursor down to a prog…
27985 …CSR_5_X211_RX_BIAS_01_O_2_0_K2_E5 (0x7<<3) // AFE rx_bias sett…
27986 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X211_RX_BIAS_01_O_2_0_K2_E5_SHIFT 3
27994 …E5 (0xf<<0) // Number of wait cycles for the CDR to lock [3:0] times 64
27998 … (0x1<<6) // Set all DFE calibration values to mid-scale instead of usin…
28000 … 0x002b5cUL //Access:RW DataWidth:0x8 // DFE block -continuous calibratio…
28002 …ONT_LENGTH_O_14_8_K2_E5 (0x7f<<0) // DFE block -continuous calibratio…
28004 … 0x002b64UL //Access:RW DataWidth:0x8 // DFE block - ATT calibration cycl…
28005 … 0x002b68UL //Access:RW DataWidth:0x8 // DFE block - Boost calibration cy…
28006 … 0x002b6cUL //Access:RW DataWidth:0x8 // DFE block - TAP1 calibration cyc…
28007 … 0x002b70UL //Access:RW DataWidth:0x8 // DFE block - TAP2 calibration cyc…
28008 … 0x002b74UL //Access:RW DataWidth:0x8 // DFE block - TAP3 calibration cyc…
28009 … 0x002b78UL //Access:RW DataWidth:0x8 // DFE block - TAP4 calibration cyc…
28010 … 0x002b7cUL //Access:RW DataWidth:0x8 // DFE block - TAP5 calibration cyc…
28014 …ECAL_O_6_0_K2_E5 (0x7f<<1) // Enables re-calibration for { Tap…
28017 …bit [0]: Enables ATT calibration when asserted bit [1]: Enables Boost calibration when asserted bi…
28020 …bit [0]: Enables ATT calibration when asserted bit [1]: Enables Boost calibration when asserted bi…
28023 …ATE2_RECAL_O_6_0_K2_E5 (0x7f<<0) // Enables re-calibration for { Tap…
28057 …bit [0]: Reverses polarity of ATT calibration when asserted bit [1]: Reverses polarity of Boost ca…
28173 …NE_I_3_0_K2_E5 (0xf<<0) // RXEQ calibration done status - per lane
28175 …ADAPT_DONE_I_3_0_K2_E5 (0xf<<4) // TXEQ Adapt Done status - per lane
28199 …ning pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding…
28202 …ning pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding…
28205 …ning pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding…
28208 …ning pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding…
28211 …ning pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding…
28214 …ning pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding…
28235 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
28238 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
28241 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
28244 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
28247 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
28250 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
28253 …bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enabl…
28256 …bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enabl…
28259 …bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enabl…
28262 …bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enabl…
28283 …coarse calibration 0: last data, 1: avg of last two data, 2: avg of last four data, 3: last data
28285 …l fine calibration 0: last data, 1: avg of last two data, 2: avg of last four data, 3: last data
28287 …e dlev calibration 0: last data, 1: avg of last two data, 2: avg of last four data, 3: last data
28369 …_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_FINAL_CMP_WRITE_EN_O_K2_E5 (0x1<<3) //
28370 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_FINAL_CMP_WRITE_EN_O_K2_E5_SHIFT 3
28381 …CSR_5_X376_MSM_PIPE_RST_PD_LNREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28382 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREG_O_K2_E5_SHIFT 3
28398 …CSR_5_X377_MSM_PIPE_RST_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28399 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_O_K2_E5_SHIFT 3
28415 …CSR_5_X378_MSM_PIPE_RST_RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28416 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_RA_O_K2_E5_SHIFT 3
28432 …CSR_5_X379_MSM_PIPE_RST_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28433 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
28441 …CSR_5_X380_MSM_PIPE_P0_PD_LNREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28442 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREG_O_K2_E5_SHIFT 3
28458 …CSR_5_X381_MSM_PIPE_P0_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28459 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_O_K2_E5_SHIFT 3
28475 …CSR_5_X382_MSM_PIPE_P0_RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28476 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_RA_O_K2_E5_SHIFT 3
28492 …CSR_5_X383_MSM_PIPE_P0_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28493 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
28501 …CSR_5_X384_MSM_PIPE_P1_PD_LNREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28502 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREG_O_K2_E5_SHIFT 3
28518 …CSR_5_X385_MSM_PIPE_P1_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28519 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_O_K2_E5_SHIFT 3
28535 …CSR_5_X386_MSM_PIPE_P1_RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28536 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_RA_O_K2_E5_SHIFT 3
28552 …CSR_5_X387_MSM_PIPE_P1_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28553 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
28561 …CSR_5_X388_MSM_PIPE_P2_PD_LNREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28562 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREG_O_K2_E5_SHIFT 3
28578 …CSR_5_X389_MSM_PIPE_P2_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28579 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_O_K2_E5_SHIFT 3
28595 …CSR_5_X390_MSM_PIPE_P2_RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28596 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_RA_O_K2_E5_SHIFT 3
28612 …CSR_5_X391_MSM_PIPE_P2_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28613 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
28628 …CSR_5_X401_L3_MASTER_CDN_O_K2_E5 (0x1<<3) // Lane3 master res…
28629 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L3_MASTER_CDN_O_K2_E5_SHIFT 3
28637 …E_I_2_0_K2_E5 (0x7<<0) // 1000Base-KX Mode status for CPU
28639 …ANE_CSR_5_X406_CMU_OK_I_0_K2_E5 (0x1<<3) // CMU OK Status
28640 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X406_CMU_OK_I_0_K2_E5_SHIFT 3
28650 …X407_LN3_SIG_LEVEL_VALID_I_3_K2_E5 (0x1<<3) // Lane 3 Signal Detect V…
28651 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_SIG_LEVEL_VALID_I_3_K2_E5_SHIFT 3
28658 …_CSR_5_X407_LN3_OK_I_7_K2_E5 (0x1<<7) // Lane 3 OK Status
28667 …X408_LN3_RX_LOCKED_I_7_6_K2_E5 (0x3<<6) // Lane 3 RX Locked Status
28715 …CSR_5_X483_MSM_PIPE_P1_0_RX_GATE_EN_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28716 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RX_GATE_EN_O_K2_E5_SHIFT 3
28732 …CSR_5_X484_MSM_PIPE_P1_0_RESET_LNREGH_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28733 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_LNREGH_O_K2_E5_SHIFT 3
28749 …CSR_5_X485_MSM_PIPE_P1_0_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28750 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_VCO_O_K2_E5_SHIFT 3
28766 …CSR_5_X486_MSM_PIPE_P1_0_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28767 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
28775 …CSR_5_X487_MSM_PIPE_P1_1_RX_GATE_EN_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28776 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RX_GATE_EN_O_K2_E5_SHIFT 3
28792 …CSR_5_X488_MSM_PIPE_P1_1_RESET_LNREGH_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28793 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_LNREGH_O_K2_E5_SHIFT 3
28809 …CSR_5_X489_MSM_PIPE_P1_1_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28810 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_VCO_O_K2_E5_SHIFT 3
28826 …CSR_5_X490_MSM_PIPE_P1_1_PD_TXREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28827 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_PD_TXREG_O_K2_E5_SHIFT 3
28835 …CSR_5_X491_MSM_PIPE_P1_2_RX_GATE_EN_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28836 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RX_GATE_EN_O_K2_E5_SHIFT 3
28852 …CSR_5_X492_MSM_PIPE_P1_2_RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28853 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_RA_O_K2_E5_SHIFT 3
28869 …CSR_5_X493_MSM_PIPE_P1_2_PD_TXDRV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28870 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_TXDRV_O_K2_E5_SHIFT 3
28886 …CSR_5_X494_MSM_PIPE_P1_2_PD_TXREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
28887 …HY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_PD_TXREG_O_K2_E5_SHIFT 3
28901 …7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Ov…
28903 …_6_X1_PMA_CM_REF_CLK_DIV_O_K2_E5 (0x3<<3) // Divider for pma_…
28904 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_PMA_CM_REF_CLK_DIV_O_K2_E5_SHIFT 3
28912 …_6_X2_CDR_REFCLK_SEL_O_2_0_K2_E5 (0x7<<3) // Selects one lane…
28913 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X2_CDR_REFCLK_SEL_O_2_0_K2_E5_SHIFT 3
28914 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
28917 …_AHB_PMA_CM_DIVNSEL_O_6_0_K2_E5 (0x7f<<0) // CMU N-divider setting
28925 …_6_X5_AHB_PMA_CM_PREDIV4_ENA_O_K2_E5 (0x1<<3) // CMU FL prediv4 e…
28926 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_PREDIV4_ENA_O_K2_E5_SHIFT 3
28929 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28930 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28931 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28933 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28935 … 0x003028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
28936 … 0x00302cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
28937 … 0x003030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
28938 … 0x003034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
28939 … 0x003038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
28940 … 0x00303cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
28941 … 0x003040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
28942 … 0x003044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
28943 … 0x003048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
28944 … 0x00304cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
28945 … 0x003050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
28946 … 0x003054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
28947 … 0x003058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
28948 … 0x00305cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
28949 … 0x003060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
28950 … 0x003064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
28968 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
28970 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
28972 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
28974 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28977 …he following functions: [0] - active high, Override Enable [1] - SOC clock output…
28979 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28981 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28983 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
28986 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28988 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28990 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28992 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28995 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
28997 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28999 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29001 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
29004 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
29006 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29008 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29060 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
29068 …<3) // Overrides for PLL lock signals [2] - Active high, override enable [1] - PLL ok override, by…
29069 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X94_PLL_CTRL_OVR_O_K2_E5_SHIFT 3
29084 …_6_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O_K2_E5 (0x1<<3) // Charge pump chop…
29085 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O_K2_E5_SHIFT 3
29102 …K2_E5 (0x1<<2) // Override enable for overriding N-div value
29104 …_6_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O_K2_E5 (0x1<<3) // CMU V2I filter e…
29105 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O_K2_E5_SHIFT 3
29118 …6_X100_AHB_PMA_CM_P_KVCO_SEL_O_K2_E5 (0x1f<<3) // CMU PLL KVCO set…
29119 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X100_AHB_PMA_CM_P_KVCO_SEL_O_K2_E5_SHIFT 3
29121 …01_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
29126 …_6_X102_AHB_PMA_CM_VCOFR_SEL_O_K2_E5 (0x1<<3) // Override enable …
29127 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X102_AHB_PMA_CM_VCOFR_SEL_O_K2_E5_SHIFT 3
29134 …_6_X108_PMA_REFCLK_OUTPUT_SEL_O_3_0_K2_E5 (0xf<<3) // Reference clock …
29135 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X108_PMA_REFCLK_OUTPUT_SEL_O_3_0_K2_E5_SHIFT 3
29145 …_6_X109_PMA_RXCLK_OE_R_O_K2_E5 (0x1<<3) // Override for pri…
29146 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_RXCLK_OE_R_O_K2_E5_SHIFT 3
29171 … // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down…
29178 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
29180 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
29189 …_TEMP_CAL_POLARITY_O_K2_E5 (0x1<<6) // chicken bit for counter polarity
29193 … 0x0031e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
29195 …MP_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
29218 …AHB_RX_TC_BIAS_OVR_K2_E5 (0x7<<1) // Bit 3:1 RX termination c…
29227 …erride for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pi…
29235 … 0x003210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
29237 …TBUS_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
29251 … function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - …
29288 …_6_X191_PD_CMU_IDDQ_SETVAL_O_K2_E5 (0x1<<3) // MSM Function IDD…
29289 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_CMU_IDDQ_SETVAL_O_K2_E5_SHIFT 3
29305 …_6_X192_RESET_CMUREGREF_IDDQ_SETVAL_O_K2_E5 (0x1<<3) // MSM Function IDD…
29306 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUREGREF_IDDQ_SETVAL_O_K2_E5_SHIFT 3
29322 …_CMU1_CSR_6_X193_RESET_TXCLK_IDDQ_SETVAL_O_K2_E5 (0x1<<3) // Not used
29323 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_RESET_TXCLK_IDDQ_SETVAL_O_K2_E5_SHIFT 3
29339 …_6_X194_PD_CMU_RST_SETVAL_O_K2_E5 (0x1<<3) // MSM Function RST…
29340 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_CMU_RST_SETVAL_O_K2_E5_SHIFT 3
29356 …_6_X195_RESET_CMUREGREF_RST_SETVAL_O_K2_E5 (0x1<<3) // MSM Function RST…
29357 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUREGREF_RST_SETVAL_O_K2_E5_SHIFT 3
29373 …_CMU1_CSR_6_X196_RESET_TXCLK_RST_SETVAL_O_K2_E5 (0x1<<3) // Not used
29374 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_RESET_TXCLK_RST_SETVAL_O_K2_E5_SHIFT 3
29390 …_6_X197_PD_CMU_NORM_SETVAL_O_K2_E5 (0x1<<3) // MSM Function NOR…
29391 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_CMU_NORM_SETVAL_O_K2_E5_SHIFT 3
29407 …_6_X198_RESET_CMUREGREF_NORM_SETVAL_O_K2_E5 (0x1<<3) // MSM Function NOR…
29408 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUREGREF_NORM_SETVAL_O_K2_E5_SHIFT 3
29424 …_CMU1_CSR_6_X199_RESET_TXCLK_NORM_SETVAL_O_K2_E5 (0x1<<3) // Not used
29425 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_RESET_TXCLK_NORM_SETVAL_O_K2_E5_SHIFT 3
29441 …_6_X200_PD_CMU_PD_SETVAL_O_K2_E5 (0x1<<3) // MSM Function POW…
29442 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_CMU_PD_SETVAL_O_K2_E5_SHIFT 3
29458 …_6_X201_RESET_CMUREGREF_PD_SETVAL_O_K2_E5 (0x1<<3) // MSM Function POW…
29459 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUREGREF_PD_SETVAL_O_K2_E5_SHIFT 3
29475 …_CMU1_CSR_6_X202_RESET_TXCLK_PD_SETVAL_O_K2_E5 (0x1<<3) // Not used
29476 …HY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_RESET_TXCLK_PD_SETVAL_O_K2_E5_SHIFT 3
29492 …7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Ov…
29494 …_X1_PMA_CM_REF_CLK_DIV_O_K2_E5 (0x3<<3) // Divider for pma_…
29495 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_PMA_CM_REF_CLK_DIV_O_K2_E5_SHIFT 3
29503 …_X2_CDR_REFCLK_SEL_O_2_0_K2_E5 (0x7<<3) // Selects one lane…
29504 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X2_CDR_REFCLK_SEL_O_2_0_K2_E5_SHIFT 3
29505 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
29508 …HB_PMA_CM_DIVNSEL_6_0_O_K2_E5 (0x7f<<0) // CMU N-divider setting
29516 …_X5_AHB_PMA_CM_PREDIV4_ENA_O_K2_E5 (0x1<<3) // CMU FL prediv4 e…
29517 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PREDIV4_ENA_O_K2_E5_SHIFT 3
29520 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29521 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29522 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29524 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29526 … 0x000028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
29527 … 0x00002cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
29528 … 0x000030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
29529 … 0x000034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
29530 … 0x000038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
29531 … 0x00003cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
29532 … 0x000040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
29533 … 0x000044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
29534 … 0x000048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
29535 … 0x00004cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
29536 … 0x000050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
29537 … 0x000054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
29538 … 0x000058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
29539 … 0x00005cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
29540 … 0x000060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
29541 … 0x000064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
29559 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
29561 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
29563 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
29565 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29568 …he following functions: [0] - active high, Override Enable [1] - SOC clock output…
29570 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29572 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29574 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
29577 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29579 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29581 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29583 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29586 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
29588 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29590 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29592 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
29595 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
29597 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29599 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29640 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
29648 …<3) // Overrides for PLL lock signals [2] - Active high, override enable [1] - PLL ok override, by…
29649 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_OVR_O_K2_E5_SHIFT 3
29664 …_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O_K2_E5 (0x1<<3) // Charge pump chop…
29665 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O_K2_E5_SHIFT 3
29682 …_E5 (0x1<<2) // Override enable for overriding N-div value
29684 …_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O_K2_E5 (0x1<<3) // CMU V2I filter e…
29685 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O_K2_E5_SHIFT 3
29698 …X100_AHB_PMA_CM_P_KVCO_SEL_O_K2_E5 (0x1f<<3) // CMU PLL KVCO set…
29699 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_P_KVCO_SEL_O_K2_E5_SHIFT 3
29701 …_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
29706 …_X102_AHB_PMA_CM_VCOFR_SEL_O_K2_E5 (0x1<<3) // Override enable …
29707 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_SEL_O_K2_E5_SHIFT 3
29709 …_X108_PMA_REFCLK_OUTPUT_SEL_O_3_0_K2_E5 (0xf<<3) // Reference clock …
29710 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_OUTPUT_SEL_O_3_0_K2_E5_SHIFT 3
29720 …_X109_PMA_RXCLK_OE_R_O_K2_E5 (0x1<<3) // Override for pri…
29721 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_R_O_K2_E5_SHIFT 3
29746 … // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down…
29753 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
29755 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
29764 …EMP_CAL_POLARITY_O_K2_E5 (0x1<<6) // chicken bit for counter polarity
29768 … 0x0001e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
29770 …_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
29793 …B_RX_TC_BIAS_OVR_K2_E5 (0x7<<1) // Bit 3:1 RX termination c…
29802 …erride for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pi…
29810 … 0x000210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
29812 …US_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
29827 …_X136_CMU_RATE_IS_GEN3_OVR_O_K2_E5 (0x1<<3) // Override for int…
29828 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X136_CMU_RATE_IS_GEN3_OVR_O_K2_E5_SHIFT 3
29843 …_X138_AHB_PMA_CM_CHPMP_CHOP_ENAN_GEN3_O_K2_E5 (0x1<<3) // Charge pump chop…
29844 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_CHPMP_CHOP_ENAN_GEN3_O_K2_E5_SHIFT 3
29863 …_X140_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_GEN3_O_K2_E5 (0x1<<3) // CMU VCO PMOS pro…
29864 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_GEN3_O_K2_E5_SHIFT 3
29875 …X142_AHB_PMA_CM_P_KVCO_SEL_GEN3_O_K2_E5 (0x1f<<3) // CMU PLL KVCO set…
29876 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X142_AHB_PMA_CM_P_KVCO_SEL_GEN3_O_K2_E5_SHIFT 3
29878 …A_CM_DIVPSEL_GEN3_O_K2_E5 (0x7f<<0) // CMU P-divider setting in ge…
29883 …CMU_CSR_0_X144_AHB_PMA_CM_PLL_REFDIV2_ENA_GEN3_O_K2_E5 (0x1<<3) // Not used
29884 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_AHB_PMA_CM_PLL_REFDIV2_ENA_GEN3_O_K2_E5_SHIFT 3
29906 … function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - …
29941 …_X191_PD_CMU_IDDQ_SETVAL_O_K2_E5 (0x1<<3) // MSM Function IDD…
29942 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_CMU_IDDQ_SETVAL_O_K2_E5_SHIFT 3
29958 …_X192_RESET_CMUREGREF_IDDQ_SETVAL_O_K2_E5 (0x1<<3) // MSM Function IDD…
29959 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREGREF_IDDQ_SETVAL_O_K2_E5_SHIFT 3
29975 …CMU_CSR_0_X193_RESET_TXCLK_IDDQ_SETVAL_O_K2_E5 (0x1<<3) // Not used
29976 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_RESET_TXCLK_IDDQ_SETVAL_O_K2_E5_SHIFT 3
29992 …_X194_PD_CMU_RST_SETVAL_O_K2_E5 (0x1<<3) // MSM Function RST…
29993 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_CMU_RST_SETVAL_O_K2_E5_SHIFT 3
30009 …_X195_RESET_CMUREGREF_RST_SETVAL_O_K2_E5 (0x1<<3) // MSM Function RST…
30010 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREGREF_RST_SETVAL_O_K2_E5_SHIFT 3
30026 …CMU_CSR_0_X196_RESET_TXCLK_RST_SETVAL_O_K2_E5 (0x1<<3) // Not used
30027 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_RESET_TXCLK_RST_SETVAL_O_K2_E5_SHIFT 3
30043 …_X197_PD_CMU_NORM_SETVAL_O_K2_E5 (0x1<<3) // MSM Function NOR…
30044 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_CMU_NORM_SETVAL_O_K2_E5_SHIFT 3
30060 …_X198_RESET_CMUREGREF_NORM_SETVAL_O_K2_E5 (0x1<<3) // MSM Function NOR…
30061 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREGREF_NORM_SETVAL_O_K2_E5_SHIFT 3
30077 …CMU_CSR_0_X199_RESET_TXCLK_NORM_SETVAL_O_K2_E5 (0x1<<3) // Not used
30078 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_RESET_TXCLK_NORM_SETVAL_O_K2_E5_SHIFT 3
30094 …_X200_PD_CMU_PD_SETVAL_O_K2_E5 (0x1<<3) // MSM Function POW…
30095 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_CMU_PD_SETVAL_O_K2_E5_SHIFT 3
30111 …_X201_RESET_CMUREGREF_PD_SETVAL_O_K2_E5 (0x1<<3) // MSM Function POW…
30112 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREGREF_PD_SETVAL_O_K2_E5_SHIFT 3
30128 …CMU_CSR_0_X202_RESET_TXCLK_PD_SETVAL_O_K2_E5 (0x1<<3) // Not used
30129 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_RESET_TXCLK_PD_SETVAL_O_K2_E5_SHIFT 3
30145 …_X203_PD_CMU_NORM_REFCLK_SETVAL_O_K2_E5 (0x1<<3) // MSM Function NOR…
30146 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_CMU_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT 3
30162 …_X204_RESET_CMUREGREF_NORM_REFCLK_SETVAL_O_K2_E5 (0x1<<3) // MSM Function NOR…
30163 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUREGREF_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT 3
30179 …CMU_CSR_0_X205_RESET_TXCLK_NORM_REFCLK_SETVAL_O_K2_E5 (0x1<<3) // Not used
30180 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_RESET_TXCLK_NORM_REFCLK_SETVAL_O_K2_E5_SHIFT 3
30196 …_X206_PD_CMU_P1_2_SETVAL_O_K2_E5 (0x1<<3) // MSM Function P1_…
30197 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_CMU_P1_2_SETVAL_O_K2_E5_SHIFT 3
30213 …_X207_RESET_CMUREGREF_P1_2_SETVAL_O_K2_E5 (0x1<<3) // MSM Function P1_…
30214 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUREGREF_P1_2_SETVAL_O_K2_E5_SHIFT 3
30230 …CMU_CSR_0_X208_RESET_TXCLK_P1_2_SETVAL_O_K2_E5 (0x1<<3) // Not used
30231 …HY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_RESET_TXCLK_P1_2_SETVAL_O_K2_E5_SHIFT 3
30245 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
30248 …O_K2_E5 (0x1<<3) // Clock divider for RX path branch 1 : 0-No divi…
30249 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_K2_E5_SHIFT 3
30250 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
30253 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
30256 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
30258 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
30261 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
30270 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
30272 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
30277 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
30279 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outpu…
30280 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_ERR_O_K2_E5_SHIFT 3
30285 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
30287 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
30292 … (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist…
30293 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_SEND_PREAM_O_K2_E5_SHIFT 3
30294 …/ Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ev…
30296 … 0x000824UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
30297 … 0x000828UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
30298 … 0x00082cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
30299 … 0x000830UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
30300 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
30302 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
30309 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
30311 …1_X15_BIST_CHK_DATA_MODE_O_K2_E5 (0x1<<3) // Bist checker mod…
30312 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_DATA_MODE_O_K2_E5_SHIFT 3
30317 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
30319 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
30323 …ON_ZEROS_K2_E5 (0x1<<5) // Setting this bit allows BIST to sync…
30329 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
30330 … 0x000854UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30331 … 0x000858UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30332 … 0x00085cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30333 … 0x000860UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30341 … 0x000880UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
30342 … 0x000884UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
30343 … 0x000888UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
30344 … 0x00088cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
30345 … 0x000890UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
30346 … 0x000894UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
30347 … 0x000898UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
30348 … 0x00089cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
30349 … 0x0008a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
30350 … 0x0008a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
30351 … 0x0008a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
30352 … 0x0008acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
30353 … 0x0008b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
30354 … 0x0008b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
30355 … 0x0008b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
30356 … 0x0008bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
30357 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
30358 …L //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA met…
30359 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
30360 …/Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA met…
30365 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
30367 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
30369 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
30371 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
30372 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
30373 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
30375 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
30377 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
30389 … enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a…
30390 … enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a…
30392 …2_E5 (0x3<<0) // Bit 0: Override enable for msm_ln_req Bit …
30394 …E5 (0x3f<<2) // Bit 2: Override enable for msm_func Bits [7:…
30421 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
30423 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
30425 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
30427 …1_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5 (0x7<<3) // Number of clock …
30428 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5_SHIFT 3
30429 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
30430 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
30431 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
30433 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
30435 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
30451 …1_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5 (0x1<<3) // Override for ei_…
30452 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5_SHIFT 3
30485 …L_DIV2_O_K2_E5 (0x7<<3) // Signal detect threshold select for div-b…
30486 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_K2_E5_SHIFT 3
30492 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
30494 …1_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5 (0x7<<3) // AGC threshold se…
30495 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5_SHIFT 3
30524 …1_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5 (0x1<<3) // Override enable …
30525 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5_SHIFT 3
30534 …0x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit…
30536 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
30538 …-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2…
30542 …1_X101_PMA_LN_SD_BWSEL_K2_E5 (0x1<<3) // RX signal detect…
30543 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_SD_BWSEL_K2_E5_SHIFT 3
30554 … // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 bit 2: C1
30575 …1_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_K2_E5 (0x7<<3) // AGC threshold se…
30576 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_K2_E5_SHIFT 3
30607 …1_X114_AHB_PMA_LN_RX_SELR_GEN3_O_K2_E5 (0x7<<3) // CTLE R degenerat…
30608 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X114_AHB_PMA_LN_RX_SELR_GEN3_O_K2_E5_SHIFT 3
30627 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
30629 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
30641 … (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not …
30643 … (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_sle…
30646 …09f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx_slew_sld3f[2…
30652 … (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is l…
30654 … (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is l…
30656 … (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is l…
30658 … (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is l…
30661 …3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6:…
30664 …3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6:…
30714 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
30716 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
30725 …CSR_1_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5 (0x1<<3) // boost_adj_dir
30726 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5_SHIFT 3
30727 …_E5 (0xf<<4) // boost_adj_val This register Is not bit reversed
30755 …: 1: Calibrate DFE comparator 1 2: Calibrate DFE comparator 2 3: Calibrate DFE comparator 3 4: Cal…
30757 …1_X150_RXEQ_ATT_GAIN_OVR_K2_E5 (0x3<<3) // Override the val…
30758 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_ATT_GAIN_OVR_K2_E5_SHIFT 3
30781 …FE_TAP3_OVR_VAL_O_5_0_K2_E5 (0x3f<<0) // DFE Tap 3 Override Value
30794 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
30800 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
30802 … 0x000a80UL //Access:R DataWidth:0x8 // Over equalization count 7-0
30804 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
30806 … 0x000a88UL //Access:R DataWidth:0x8 // Under equalization count 7-0
30811 … 0x000a94UL //Access:RW DataWidth:0x8 // Mask bit for Txeq training p…
30813 …DONT_CARE_O_8_K2_E5 (0x1<<0) // Mask bit for Txeq training p…
30816 … (0x1<<0) // This bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is l…
30824 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
30830 …K2_E5 (0x1<<0) // cdfe enable bit. 1: enable cdfe wh…
30832 …o 0 8-bit or 10-bit mode. 2'b11: the word_i …
30834 …3) // The cdfe input mode_8b_i overwrite. …
30835 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_CDFE_MODE_8B_OV_O_1_0_K2_E5_SHIFT 3
30836 … 3'b0xx: the rate_i input for cdfe block is internally generated. …
30855 …1_X204_CDFE_LN_RATE3_CAL_EN_K2_E5 (0x1<<3) // Enables the cdfe…
30856 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_CAL_EN_K2_E5_SHIFT 3
30859 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
30860 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
30861 …-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
30865 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
30866 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
30867 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
30868 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
30869 …-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
30872 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
30875 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
30884 …) // Override for CMP1 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[3]
30899 …) // Override for CMP2 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[3]
30914 …) // Override for CMP3 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[3]
30929 …) // Override for CMP4 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[3]
30959 …REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5 (0x1<<3) //
30960 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT 3
30972 …1_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5 (0x1<<3) // Override enable …
30973 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5_SHIFT 3
30992 …Register override for overriding adaptation comparator select bit [0] : override enable bit [4:1] …
30994 …er override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] …
30996 …er override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] …
30999 …Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3…
31045 …_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
31046 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5_SHIFT 3
31050 …_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
31051 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5_SHIFT 3
31055 …_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
31056 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5_SHIFT 3
31060 …_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
31061 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5_SHIFT 3
31065 …_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
31066 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5_SHIFT 3
31068 …_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_ra Bit…
31070 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_p2s Bi…
31072 …_O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_lnregh B…
31074 …_O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_reset_lnreg B…
31077 …O_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr Bi…
31079 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_dfe Bi…
31081 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_pd_lnregh Bi…
31083 …O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco_buf Bi…
31086 …R_O_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr_gcrx …
31088 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_rxgate_en Bi…
31090 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_vco Bi…
31092 …_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_iddq_sd Bit…
31095 …K2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_dfe Bit …
31097 …_O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_dfe_bias B…
31099 …R_O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_txdrv_lp_idle …
31101 …VR_O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_txreg_bleed_ena…
31104 …_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_txreg Bit…
31106 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_lnreg Bit…
31108 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_p2s Bit 1:…
31110 …O_K2_E5 (0x3<<6) // Bit 0: Override enable for pd_ra Bit 1:…
31113 …VR_O_K2_E5 (0x3<<2) // Bit 0: Override enable for pd_slv_bias Bit…
31115 …_O_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_txdrv Bit 1…
31117 …K2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco Bit …
31120 …K2_E5 (0x3<<0) // Bit 0: Override enable for msm_cdr_en Bit …
31122 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_s2p Bi…
31124 …_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_rxclk_en Bit…
31126 …2_E5 (0x3<<6) // Bit 0: Override enable for msm_word Bit 1…
31129 …2_E5 (0x7<<0) // Bit 0: Override enable for msm_rate Bit […
31131 …R_O_K2_E5 (0x7<<3) // Bit 0: Override enable for msm_rxvcodiv …
31132 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RXVCODIV_OVR_O_K2_E5_SHIFT 3
31136 …_K2_E5 (0x7<<0) // Bit 0: Override enable for msm_txvcodiv Bit…
31139 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
31141 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
31143 …0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
31145 … (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not…
31146 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_TREG0_WORD_O_K2_E5_SHIFT 3
31149 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
31152 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
31154 …0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
31156 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31158 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmo…
31159 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG1_POL_O_K2_E5_SHIFT 3
31160 …(0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
31162 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31167 …(0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
31169 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31173 …3_TX_CTRL_O_24_K2_E5 (0x1<<5) // Bit 24: txdrv_c2_in[3]
31175 …HNG_EN_O_K2_E5 (0x1<<6) // Enable bit for width_chng modu…
31182 … (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2�b00: no bit stripping 2�b01: 2x bit…
31183 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X304_AHB_LN_RXBIT_STRIP_O_K2_E5_SHIFT 3
31187 …included to handle the communication between the external 64-bit data and the internal 20-bit data…
31189 …Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2�b00: no bit stuf…
31191 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
31200 …// Per lane common synchronous clock between PMA, PCS and SoC logic enable bit. 1: in NORM state, …
31214 …1_X308_BLOCK_DEC_EN_ERR_CHK_O_K2_E5 (0x1<<3) // 130b/128b error …
31215 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_DEC_EN_ERR_CHK_O_K2_E5_SHIFT 3
31232 …1_X310_RBUF_RSTN_O_K2_E5 (0x1<<3) // TX FIFO synchron…
31233 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_RBUF_RSTN_O_K2_E5_SHIFT 3
31244 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
31246 … (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to gen 3
31262 …1_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5 (0x1<<3) // Receive amplifie…
31263 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5_SHIFT 3
31277 …1_X317_ENC_EN_OVR_O_K2_E5 (0x1<<3) // Enables 16b/20b …
31278 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_ENC_EN_OVR_O_K2_E5_SHIFT 3
31279 …f<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty…
31282 …_1_0_K2_E5 (0x3<<0) // Bit[0]: Overide value. Bit[1] :Over…
31284 …x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 …
31286 … (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable…
31289 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is …
31291 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is …
31293 …x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 …
31299 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
31300 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
31301 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
31302 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
31303 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
31304 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
31306 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
31308 …nd each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writi…
31310 …it_regp1 Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty…
31317 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
31322 …1_X330_LN_IN_OVR_O_50_K2_E5 (0x1<<3) // Override signals…
31323 …HY_PCIE_IP_REG_AHB_LANE_CSR_1_X330_LN_IN_OVR_O_50_K2_E5_SHIFT 3
31325 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
31328 …O_K2_E5 (0x1<<3) // Clock divider for RX path branch 1 : 0-No divi…
31329 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_K2_E5_SHIFT 3
31330 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
31333 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
31336 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
31338 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
31341 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
31350 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
31352 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
31357 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
31359 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outpu…
31360 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_ERR_O_K2_E5_SHIFT 3
31365 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
31367 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
31372 … (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist…
31373 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X8_BIST_GEN_SEND_PREAM_O_K2_E5_SHIFT 3
31374 …/ Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ev…
31376 … 0x001024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
31377 … 0x001028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
31378 … 0x00102cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
31379 … 0x001030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
31380 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
31382 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
31389 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
31391 …2_X15_BIST_CHK_DATA_MODE_O_K2_E5 (0x1<<3) // Bist checker mod…
31392 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BIST_CHK_DATA_MODE_O_K2_E5_SHIFT 3
31397 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
31399 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
31403 …ON_ZEROS_K2_E5 (0x1<<5) // Setting this bit allows BIST to sync…
31409 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
31410 … 0x001054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31411 … 0x001058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31412 … 0x00105cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31413 … 0x001060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31421 … 0x001080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
31422 … 0x001084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
31423 … 0x001088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
31424 … 0x00108cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
31425 … 0x001090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
31426 … 0x001094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
31427 … 0x001098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
31428 … 0x00109cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
31429 … 0x0010a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
31430 … 0x0010a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
31431 … 0x0010a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
31432 … 0x0010acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
31433 … 0x0010b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
31434 … 0x0010b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
31435 … 0x0010b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
31436 … 0x0010bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
31437 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
31438 …L //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA met…
31439 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
31440 …/Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA met…
31445 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
31447 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
31449 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
31451 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
31452 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
31453 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
31455 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
31457 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
31469 … enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a…
31470 … enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a…
31472 …2_E5 (0x3<<0) // Bit 0: Override enable for msm_ln_req Bit …
31474 …E5 (0x3f<<2) // Bit 2: Override enable for msm_func Bits [7:…
31501 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
31503 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
31505 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
31507 …2_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5 (0x7<<3) // Number of clock …
31508 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5_SHIFT 3
31509 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
31510 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
31511 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
31513 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
31515 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
31531 …2_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5 (0x1<<3) // Override for ei_…
31532 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5_SHIFT 3
31565 …L_DIV2_O_K2_E5 (0x7<<3) // Signal detect threshold select for div-b…
31566 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_K2_E5_SHIFT 3
31572 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
31574 …2_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5 (0x7<<3) // AGC threshold se…
31575 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5_SHIFT 3
31604 …2_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5 (0x1<<3) // Override enable …
31605 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5_SHIFT 3
31614 …0x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit…
31616 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
31618 …-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2…
31622 …2_X101_PMA_LN_SD_BWSEL_K2_E5 (0x1<<3) // RX signal detect…
31623 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_SD_BWSEL_K2_E5_SHIFT 3
31634 … // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 bit 2: C1
31655 …2_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_K2_E5 (0x7<<3) // AGC threshold se…
31656 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_K2_E5_SHIFT 3
31687 …2_X114_AHB_PMA_LN_RX_SELR_GEN3_O_K2_E5 (0x7<<3) // CTLE R degenerat…
31688 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X114_AHB_PMA_LN_RX_SELR_GEN3_O_K2_E5_SHIFT 3
31707 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
31709 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
31721 … (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not …
31723 … (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_sle…
31726 …11f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx_slew_sld3f[2…
31732 … (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is l…
31734 … (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is l…
31736 … (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is l…
31738 … (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is l…
31741 …3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6:…
31744 …3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6:…
31794 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
31796 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
31805 …CSR_2_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5 (0x1<<3) // boost_adj_dir
31806 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5_SHIFT 3
31807 …_E5 (0xf<<4) // boost_adj_val This register Is not bit reversed
31835 …: 1: Calibrate DFE comparator 1 2: Calibrate DFE comparator 2 3: Calibrate DFE comparator 3 4: Cal…
31837 …2_X150_RXEQ_ATT_GAIN_OVR_K2_E5 (0x3<<3) // Override the val…
31838 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_RXEQ_ATT_GAIN_OVR_K2_E5_SHIFT 3
31861 …FE_TAP3_OVR_VAL_O_5_0_K2_E5 (0x3f<<0) // DFE Tap 3 Override Value
31874 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
31880 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
31882 … 0x001280UL //Access:R DataWidth:0x8 // Over equalization count 7-0
31884 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
31886 … 0x001288UL //Access:R DataWidth:0x8 // Under equalization count 7-0
31891 … 0x001294UL //Access:RW DataWidth:0x8 // Mask bit for Txeq training p…
31893 …DONT_CARE_O_8_K2_E5 (0x1<<0) // Mask bit for Txeq training p…
31896 … (0x1<<0) // This bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is l…
31904 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
31910 …K2_E5 (0x1<<0) // cdfe enable bit. 1: enable cdfe wh…
31912 …o 0 8-bit or 10-bit mode. 2'b11: the word_i …
31914 …3) // The cdfe input mode_8b_i overwrite. …
31915 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_CDFE_MODE_8B_OV_O_1_0_K2_E5_SHIFT 3
31916 … 3'b0xx: the rate_i input for cdfe block is internally generated. …
31935 …2_X204_CDFE_LN_RATE3_CAL_EN_K2_E5 (0x1<<3) // Enables the cdfe…
31936 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE3_CAL_EN_K2_E5_SHIFT 3
31939 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
31940 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
31941 …-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
31945 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
31946 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
31947 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
31948 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
31949 …-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
31952 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
31955 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
31964 …) // Override for CMP1 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[3]
31979 …) // Override for CMP2 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[3]
31994 …) // Override for CMP3 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[3]
32009 …) // Override for CMP4 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[3]
32039 …REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5 (0x1<<3) //
32040 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT 3
32052 …2_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5 (0x1<<3) // Override enable …
32053 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5_SHIFT 3
32072 …Register override for overriding adaptation comparator select bit [0] : override enable bit [4:1] …
32074 …er override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] …
32076 …er override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] …
32079 …Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3…
32125 …_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
32126 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5_SHIFT 3
32130 …_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
32131 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5_SHIFT 3
32135 …_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
32136 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5_SHIFT 3
32140 …_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
32141 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5_SHIFT 3
32145 …_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
32146 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5_SHIFT 3
32148 …_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_ra Bit…
32150 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_p2s Bi…
32152 …_O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_lnregh B…
32154 …_O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_reset_lnreg B…
32157 …O_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr Bi…
32159 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_dfe Bi…
32161 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_pd_lnregh Bi…
32163 …O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco_buf Bi…
32166 …R_O_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr_gcrx …
32168 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_rxgate_en Bi…
32170 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_vco Bi…
32172 …_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_iddq_sd Bit…
32175 …K2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_dfe Bit …
32177 …_O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_dfe_bias B…
32179 …R_O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_txdrv_lp_idle …
32181 …VR_O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_txreg_bleed_ena…
32184 …_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_txreg Bit…
32186 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_lnreg Bit…
32188 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_p2s Bit 1:…
32190 …O_K2_E5 (0x3<<6) // Bit 0: Override enable for pd_ra Bit 1:…
32193 …VR_O_K2_E5 (0x3<<2) // Bit 0: Override enable for pd_slv_bias Bit…
32195 …_O_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_txdrv Bit 1…
32197 …K2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco Bit …
32200 …K2_E5 (0x3<<0) // Bit 0: Override enable for msm_cdr_en Bit …
32202 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_s2p Bi…
32204 …_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_rxclk_en Bit…
32206 …2_E5 (0x3<<6) // Bit 0: Override enable for msm_word Bit 1…
32209 …2_E5 (0x7<<0) // Bit 0: Override enable for msm_rate Bit […
32211 …R_O_K2_E5 (0x7<<3) // Bit 0: Override enable for msm_rxvcodiv …
32212 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X284_LN_MSM_RXVCODIV_OVR_O_K2_E5_SHIFT 3
32216 …_K2_E5 (0x7<<0) // Bit 0: Override enable for msm_txvcodiv Bit…
32219 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
32221 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
32223 …0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
32225 … (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not…
32226 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_TREG0_WORD_O_K2_E5_SHIFT 3
32229 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
32232 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
32234 …0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
32236 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32238 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmo…
32239 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG1_POL_O_K2_E5_SHIFT 3
32240 …(0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
32242 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32247 …(0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
32249 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32253 …3_TX_CTRL_O_24_K2_E5 (0x1<<5) // Bit 24: txdrv_c2_in[3]
32255 …HNG_EN_O_K2_E5 (0x1<<6) // Enable bit for width_chng modu…
32262 … (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2�b00: no bit stripping 2�b01: 2x bit…
32263 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X304_AHB_LN_RXBIT_STRIP_O_K2_E5_SHIFT 3
32267 …included to handle the communication between the external 64-bit data and the internal 20-bit data…
32269 …Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2�b00: no bit stuf…
32271 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
32280 …// Per lane common synchronous clock between PMA, PCS and SoC logic enable bit. 1: in NORM state, …
32294 …2_X308_BLOCK_DEC_EN_ERR_CHK_O_K2_E5 (0x1<<3) // 130b/128b error …
32295 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_DEC_EN_ERR_CHK_O_K2_E5_SHIFT 3
32312 …2_X310_RBUF_RSTN_O_K2_E5 (0x1<<3) // TX FIFO synchron…
32313 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_RBUF_RSTN_O_K2_E5_SHIFT 3
32324 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
32326 … (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to gen 3
32342 …2_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5 (0x1<<3) // Receive amplifie…
32343 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5_SHIFT 3
32357 …2_X317_ENC_EN_OVR_O_K2_E5 (0x1<<3) // Enables 16b/20b …
32358 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_ENC_EN_OVR_O_K2_E5_SHIFT 3
32359 …f<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty…
32362 …_1_0_K2_E5 (0x3<<0) // Bit[0]: Overide value. Bit[1] :Over…
32364 …x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 …
32366 … (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable…
32369 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is …
32371 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is …
32373 …x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 …
32379 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
32380 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
32381 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
32382 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
32383 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
32384 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
32386 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
32388 …nd each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writi…
32390 …it_regp1 Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty…
32397 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
32402 …2_X330_LN_IN_OVR_O_50_K2_E5 (0x1<<3) // Override signals…
32403 …HY_PCIE_IP_REG_AHB_LANE_CSR_2_X330_LN_IN_OVR_O_50_K2_E5_SHIFT 3
32405 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
32408 …O_K2_E5 (0x1<<3) // Clock divider for RX path branch 1 : 0-No divi…
32409 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_K2_E5_SHIFT 3
32410 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
32413 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
32416 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
32418 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
32421 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
32430 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
32432 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
32437 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
32439 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outpu…
32440 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_ERR_O_K2_E5_SHIFT 3
32445 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
32447 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
32452 … (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist…
32453 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X8_BIST_GEN_SEND_PREAM_O_K2_E5_SHIFT 3
32454 …/ Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ev…
32456 … 0x001824UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
32457 … 0x001828UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
32458 … 0x00182cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
32459 … 0x001830UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
32460 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
32462 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
32469 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
32471 …3_X15_BIST_CHK_DATA_MODE_O_K2_E5 (0x1<<3) // Bist checker mod…
32472 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BIST_CHK_DATA_MODE_O_K2_E5_SHIFT 3
32477 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
32479 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
32483 …ON_ZEROS_K2_E5 (0x1<<5) // Setting this bit allows BIST to sync…
32489 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
32490 … 0x001854UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32491 … 0x001858UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32492 … 0x00185cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32493 … 0x001860UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32501 … 0x001880UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
32502 … 0x001884UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
32503 … 0x001888UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
32504 … 0x00188cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
32505 … 0x001890UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
32506 … 0x001894UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
32507 … 0x001898UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
32508 … 0x00189cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
32509 … 0x0018a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
32510 … 0x0018a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
32511 … 0x0018a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
32512 … 0x0018acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
32513 … 0x0018b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
32514 … 0x0018b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
32515 … 0x0018b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
32516 … 0x0018bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
32517 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
32518 …L //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA met…
32519 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
32520 …/Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA met…
32525 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
32527 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
32529 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
32531 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
32532 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
32533 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
32535 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
32537 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
32549 … enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a…
32550 … enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a…
32552 …2_E5 (0x3<<0) // Bit 0: Override enable for msm_ln_req Bit …
32554 …E5 (0x3f<<2) // Bit 2: Override enable for msm_func Bits [7:…
32581 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
32583 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
32585 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
32587 …3_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5 (0x7<<3) // Number of clock …
32588 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5_SHIFT 3
32589 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
32590 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
32591 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
32593 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
32595 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
32611 …3_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5 (0x1<<3) // Override for ei_…
32612 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5_SHIFT 3
32645 …L_DIV2_O_K2_E5 (0x7<<3) // Signal detect threshold select for div-b…
32646 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_K2_E5_SHIFT 3
32652 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
32654 …3_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5 (0x7<<3) // AGC threshold se…
32655 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5_SHIFT 3
32684 …3_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5 (0x1<<3) // Override enable …
32685 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5_SHIFT 3
32694 …0x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit…
32696 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
32698 …-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2…
32702 …3_X101_PMA_LN_SD_BWSEL_K2_E5 (0x1<<3) // RX signal detect…
32703 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_SD_BWSEL_K2_E5_SHIFT 3
32714 … // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 bit 2: C1
32735 …3_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_K2_E5 (0x7<<3) // AGC threshold se…
32736 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_K2_E5_SHIFT 3
32767 …3_X114_AHB_PMA_LN_RX_SELR_GEN3_O_K2_E5 (0x7<<3) // CTLE R degenerat…
32768 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X114_AHB_PMA_LN_RX_SELR_GEN3_O_K2_E5_SHIFT 3
32787 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
32789 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
32801 … (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not …
32803 … (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_sle…
32806 …19f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx_slew_sld3f[2…
32812 … (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is l…
32814 … (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is l…
32816 … (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is l…
32818 … (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is l…
32821 …3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6:…
32824 …3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6:…
32874 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
32876 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
32885 …CSR_3_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5 (0x1<<3) // boost_adj_dir
32886 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5_SHIFT 3
32887 …_E5 (0xf<<4) // boost_adj_val This register Is not bit reversed
32915 …: 1: Calibrate DFE comparator 1 2: Calibrate DFE comparator 2 3: Calibrate DFE comparator 3 4: Cal…
32917 …3_X150_RXEQ_ATT_GAIN_OVR_K2_E5 (0x3<<3) // Override the val…
32918 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_RXEQ_ATT_GAIN_OVR_K2_E5_SHIFT 3
32941 …FE_TAP3_OVR_VAL_O_5_0_K2_E5 (0x3f<<0) // DFE Tap 3 Override Value
32954 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
32960 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
32962 … 0x001a80UL //Access:R DataWidth:0x8 // Over equalization count 7-0
32964 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
32966 … 0x001a88UL //Access:R DataWidth:0x8 // Under equalization count 7-0
32971 … 0x001a94UL //Access:RW DataWidth:0x8 // Mask bit for Txeq training p…
32973 …DONT_CARE_O_8_K2_E5 (0x1<<0) // Mask bit for Txeq training p…
32976 … (0x1<<0) // This bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is l…
32984 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
32990 …K2_E5 (0x1<<0) // cdfe enable bit. 1: enable cdfe wh…
32992 …o 0 8-bit or 10-bit mode. 2'b11: the word_i …
32994 …3) // The cdfe input mode_8b_i overwrite. …
32995 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_CDFE_MODE_8B_OV_O_1_0_K2_E5_SHIFT 3
32996 … 3'b0xx: the rate_i input for cdfe block is internally generated. …
33015 …3_X204_CDFE_LN_RATE3_CAL_EN_K2_E5 (0x1<<3) // Enables the cdfe…
33016 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE3_CAL_EN_K2_E5_SHIFT 3
33019 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
33020 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
33021 …-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
33025 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
33026 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
33027 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
33028 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
33029 …-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
33032 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
33035 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
33044 …) // Override for CMP1 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[3]
33059 …) // Override for CMP2 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[3]
33074 …) // Override for CMP3 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[3]
33089 …) // Override for CMP4 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[3]
33119 …REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5 (0x1<<3) //
33120 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT 3
33132 …3_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5 (0x1<<3) // Override enable …
33133 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5_SHIFT 3
33152 …Register override for overriding adaptation comparator select bit [0] : override enable bit [4:1] …
33154 …er override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] …
33156 …er override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] …
33159 …Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3…
33205 …_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
33206 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5_SHIFT 3
33210 …_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
33211 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5_SHIFT 3
33215 …_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
33216 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5_SHIFT 3
33220 …_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
33221 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5_SHIFT 3
33225 …_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
33226 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5_SHIFT 3
33228 …_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_ra Bit…
33230 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_p2s Bi…
33232 …_O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_lnregh B…
33234 …_O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_reset_lnreg B…
33237 …O_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr Bi…
33239 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_dfe Bi…
33241 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_pd_lnregh Bi…
33243 …O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco_buf Bi…
33246 …R_O_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr_gcrx …
33248 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_rxgate_en Bi…
33250 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_vco Bi…
33252 …_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_iddq_sd Bit…
33255 …K2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_dfe Bit …
33257 …_O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_dfe_bias B…
33259 …R_O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_txdrv_lp_idle …
33261 …VR_O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_txreg_bleed_ena…
33264 …_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_txreg Bit…
33266 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_lnreg Bit…
33268 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_p2s Bit 1:…
33270 …O_K2_E5 (0x3<<6) // Bit 0: Override enable for pd_ra Bit 1:…
33273 …VR_O_K2_E5 (0x3<<2) // Bit 0: Override enable for pd_slv_bias Bit…
33275 …_O_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_txdrv Bit 1…
33277 …K2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco Bit …
33280 …K2_E5 (0x3<<0) // Bit 0: Override enable for msm_cdr_en Bit …
33282 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_s2p Bi…
33284 …_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_rxclk_en Bit…
33286 …2_E5 (0x3<<6) // Bit 0: Override enable for msm_word Bit 1…
33289 …2_E5 (0x7<<0) // Bit 0: Override enable for msm_rate Bit […
33291 …R_O_K2_E5 (0x7<<3) // Bit 0: Override enable for msm_rxvcodiv …
33292 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X284_LN_MSM_RXVCODIV_OVR_O_K2_E5_SHIFT 3
33296 …_K2_E5 (0x7<<0) // Bit 0: Override enable for msm_txvcodiv Bit…
33299 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
33301 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
33303 …0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
33305 … (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not…
33306 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_TREG0_WORD_O_K2_E5_SHIFT 3
33309 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
33312 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
33314 …0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
33316 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33318 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmo…
33319 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG1_POL_O_K2_E5_SHIFT 3
33320 …(0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
33322 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33327 …(0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
33329 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33333 …3_TX_CTRL_O_24_K2_E5 (0x1<<5) // Bit 24: txdrv_c2_in[3]
33335 …HNG_EN_O_K2_E5 (0x1<<6) // Enable bit for width_chng modu…
33342 … (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2�b00: no bit stripping 2�b01: 2x bit…
33343 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X304_AHB_LN_RXBIT_STRIP_O_K2_E5_SHIFT 3
33347 …included to handle the communication between the external 64-bit data and the internal 20-bit data…
33349 …Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2�b00: no bit stuf…
33351 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
33360 …// Per lane common synchronous clock between PMA, PCS and SoC logic enable bit. 1: in NORM state, …
33374 …3_X308_BLOCK_DEC_EN_ERR_CHK_O_K2_E5 (0x1<<3) // 130b/128b error …
33375 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_DEC_EN_ERR_CHK_O_K2_E5_SHIFT 3
33392 …3_X310_RBUF_RSTN_O_K2_E5 (0x1<<3) // TX FIFO synchron…
33393 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_RBUF_RSTN_O_K2_E5_SHIFT 3
33404 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
33406 … (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to gen 3
33422 …3_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5 (0x1<<3) // Receive amplifie…
33423 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5_SHIFT 3
33437 …3_X317_ENC_EN_OVR_O_K2_E5 (0x1<<3) // Enables 16b/20b …
33438 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_ENC_EN_OVR_O_K2_E5_SHIFT 3
33439 …f<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty…
33442 …_1_0_K2_E5 (0x3<<0) // Bit[0]: Overide value. Bit[1] :Over…
33444 …x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 …
33446 … (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable…
33449 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is …
33451 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is …
33453 …x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 …
33459 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
33460 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
33461 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
33462 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
33463 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
33464 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
33466 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
33468 …nd each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writi…
33470 …it_regp1 Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty…
33477 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
33482 …3_X330_LN_IN_OVR_O_50_K2_E5 (0x1<<3) // Override signals…
33483 …HY_PCIE_IP_REG_AHB_LANE_CSR_3_X330_LN_IN_OVR_O_50_K2_E5_SHIFT 3
33485 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
33488 …O_K2_E5 (0x1<<3) // Clock divider for RX path branch 1 : 0-No divi…
33489 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_K2_E5_SHIFT 3
33490 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
33493 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
33496 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
33498 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
33501 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
33510 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
33512 …x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
33517 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
33519 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outpu…
33520 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_ERR_O_K2_E5_SHIFT 3
33525 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
33527 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
33532 … (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist…
33533 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X8_BIST_GEN_SEND_PREAM_O_K2_E5_SHIFT 3
33534 …/ Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ev…
33536 … 0x002024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
33537 … 0x002028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
33538 … 0x00202cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
33539 … 0x002030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer…
33540 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
33542 …// Bist generator - Number of words between insert word insertions. Insertions are done in both pr…
33549 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
33551 …4_X15_BIST_CHK_DATA_MODE_O_K2_E5 (0x1<<3) // Bist checker mod…
33552 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BIST_CHK_DATA_MODE_O_K2_E5_SHIFT 3
33557 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
33559 …checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be…
33563 …ON_ZEROS_K2_E5 (0x1<<5) // Setting this bit allows BIST to sync…
33569 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
33570 … 0x002054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33571 … 0x002058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33572 … 0x00205cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33573 … 0x002060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33581 … 0x002080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
33582 … 0x002084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
33583 … 0x002088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
33584 … 0x00208cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
33585 … 0x002090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
33586 … 0x002094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
33587 … 0x002098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
33588 … 0x00209cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
33589 … 0x0020a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
33590 … 0x0020a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
33591 … 0x0020a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
33592 … 0x0020acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
33593 … 0x0020b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
33594 … 0x0020b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
33595 … 0x0020b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
33596 … 0x0020bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
33597 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
33598 …L //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA met…
33599 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
33600 …/Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA met…
33605 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
33607 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
33609 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
33611 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
33612 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
33613 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
33615 …/ Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow B…
33617 …4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes dat…
33629 … enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a…
33630 … enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a…
33632 …2_E5 (0x3<<0) // Bit 0: Override enable for msm_ln_req Bit …
33634 …E5 (0x3f<<2) // Bit 2: Override enable for msm_func Bits [7:…
33661 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
33663 …hout CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration before …
33665 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
33667 …4_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5 (0x7<<3) // Number of clock …
33668 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_CDR_CTRL_DLY_CDR_O_9_7_K2_E5_SHIFT 3
33669 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
33670 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
33671 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
33673 …Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_cont…
33675 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
33691 …4_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5 (0x1<<3) // Override for ei_…
33692 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EI_INFERRED_O_K2_E5_SHIFT 3
33725 …L_DIV2_O_K2_E5 (0x7<<3) // Signal detect threshold select for div-b…
33726 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_K2_E5_SHIFT 3
33732 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
33734 …4_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5 (0x7<<3) // AGC threshold se…
33735 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X90_AHB_PMA_LN_AGC_THSEL_O_K2_E5_SHIFT 3
33764 …4_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5 (0x1<<3) // Override enable …
33765 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X96_AHB_PMA_LN_RXVCOFR_SEL_O_K2_E5_SHIFT 3
33774 …0x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit…
33776 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
33778 …-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2…
33782 …4_X101_PMA_LN_SD_BWSEL_K2_E5 (0x1<<3) // RX signal detect…
33783 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_SD_BWSEL_K2_E5_SHIFT 3
33794 … // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 bit 2: C1
33815 …4_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_K2_E5 (0x7<<3) // AGC threshold se…
33816 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_K2_E5_SHIFT 3
33847 …4_X114_AHB_PMA_LN_RX_SELR_GEN3_O_K2_E5 (0x7<<3) // CTLE R degenerat…
33848 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X114_AHB_PMA_LN_RX_SELR_GEN3_O_K2_E5_SHIFT 3
33867 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
33869 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
33881 … (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not …
33883 … (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_sle…
33886 …21f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx_slew_sld3f[2…
33892 … (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is l…
33894 … (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is l…
33896 … (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is l…
33898 … (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is l…
33901 …3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6:…
33904 …3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6:…
33954 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
33956 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
33965 …CSR_4_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5 (0x1<<3) // boost_adj_dir
33966 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_RXEQ_BOOST_ADJ_DIR_O_K2_E5_SHIFT 3
33967 …_E5 (0xf<<4) // boost_adj_val This register Is not bit reversed
33995 …: 1: Calibrate DFE comparator 1 2: Calibrate DFE comparator 2 3: Calibrate DFE comparator 3 4: Cal…
33997 …4_X150_RXEQ_ATT_GAIN_OVR_K2_E5 (0x3<<3) // Override the val…
33998 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_RXEQ_ATT_GAIN_OVR_K2_E5_SHIFT 3
34021 …FE_TAP3_OVR_VAL_O_5_0_K2_E5 (0x3f<<0) // DFE Tap 3 Override Value
34034 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
34040 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
34042 … 0x002280UL //Access:R DataWidth:0x8 // Over equalization count 7-0
34044 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
34046 … 0x002288UL //Access:R DataWidth:0x8 // Under equalization count 7-0
34051 … 0x002294UL //Access:RW DataWidth:0x8 // Mask bit for Txeq training p…
34053 …DONT_CARE_O_8_K2_E5 (0x1<<0) // Mask bit for Txeq training p…
34056 … (0x1<<0) // This bit has similar function as txeq_rxrecal_init in COMLANE CSR. It is l…
34064 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
34070 …K2_E5 (0x1<<0) // cdfe enable bit. 1: enable cdfe wh…
34072 …o 0 8-bit or 10-bit mode. 2'b11: the word_i …
34074 …3) // The cdfe input mode_8b_i overwrite. …
34075 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_CDFE_MODE_8B_OV_O_1_0_K2_E5_SHIFT 3
34076 … 3'b0xx: the rate_i input for cdfe block is internally generated. …
34095 …4_X204_CDFE_LN_RATE3_CAL_EN_K2_E5 (0x1<<3) // Enables the cdfe…
34096 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE3_CAL_EN_K2_E5_SHIFT 3
34099 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
34100 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
34101 …-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
34105 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
34106 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
34107 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
34108 …bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bi…
34109 …-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables d…
34112 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
34115 …bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enabl…
34124 …) // Override for CMP1 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[3]
34139 …) // Override for CMP2 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[3]
34154 …) // Override for CMP3 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[3]
34169 …) // Override for CMP4 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[3]
34199 …REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5 (0x1<<3) //
34200 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_K2_E5_SHIFT 3
34212 …4_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5 (0x1<<3) // Override enable …
34213 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_ENA90_OVR_EN_O_K2_E5_SHIFT 3
34232 …Register override for overriding adaptation comparator select bit [0] : override enable bit [4:1] …
34234 …er override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] …
34236 …er override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] …
34239 …Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3…
34285 …_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
34286 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X272_CDFE_TAP1_SHIFT_O_4_0_K2_E5_SHIFT 3
34290 …_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
34291 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X273_CDFE_TAP2_SHIFT_O_4_0_K2_E5_SHIFT 3
34295 …_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
34296 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X274_CDFE_TAP3_SHIFT_O_4_0_K2_E5_SHIFT 3
34300 …_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
34301 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5_SHIFT 3
34305 …_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDF…
34306 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X276_CDFE_TAP5_SHIFT_O_4_0_K2_E5_SHIFT 3
34308 …_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_ra Bit…
34310 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_p2s Bi…
34312 …_O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_lnregh B…
34314 …_O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_reset_lnreg B…
34317 …O_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr Bi…
34319 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_dfe Bi…
34321 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_pd_lnregh Bi…
34323 …O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco_buf Bi…
34326 …R_O_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_reset_cdr_gcrx …
34328 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_rxgate_en Bi…
34330 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_reset_vco Bi…
34332 …_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_iddq_sd Bit…
34335 …K2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_dfe Bit …
34337 …_O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_dfe_bias B…
34339 …R_O_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_txdrv_lp_idle …
34341 …VR_O_K2_E5 (0x3<<6) // Bit 0: Override enable for msm_txreg_bleed_ena…
34344 …_K2_E5 (0x3<<0) // Bit 0: Override enable for msm_pd_txreg Bit…
34346 …_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_pd_lnreg Bit…
34348 …O_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_p2s Bit 1:…
34350 …O_K2_E5 (0x3<<6) // Bit 0: Override enable for pd_ra Bit 1:…
34353 …VR_O_K2_E5 (0x3<<2) // Bit 0: Override enable for pd_slv_bias Bit…
34355 …_O_K2_E5 (0x3<<4) // Bit 0: Override enable for pd_txdrv Bit 1…
34357 …K2_E5 (0x3<<6) // Bit 0: Override enable for msm_pd_vco Bit …
34360 …K2_E5 (0x3<<0) // Bit 0: Override enable for msm_cdr_en Bit …
34362 …O_K2_E5 (0x3<<2) // Bit 0: Override enable for msm_reset_s2p Bi…
34364 …_K2_E5 (0x3<<4) // Bit 0: Override enable for msm_rxclk_en Bit…
34366 …2_E5 (0x3<<6) // Bit 0: Override enable for msm_word Bit 1…
34369 …2_E5 (0x7<<0) // Bit 0: Override enable for msm_rate Bit […
34371 …R_O_K2_E5 (0x7<<3) // Bit 0: Override enable for msm_rxvcodiv …
34372 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X284_LN_MSM_RXVCODIV_OVR_O_K2_E5_SHIFT 3
34376 …_K2_E5 (0x7<<0) // Bit 0: Override enable for msm_txvcodiv Bit…
34379 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
34381 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
34383 …0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
34385 … (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not…
34386 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_TREG0_WORD_O_K2_E5_SHIFT 3
34389 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
34392 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
34394 …0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
34396 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34398 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmo…
34399 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG1_POL_O_K2_E5_SHIFT 3
34400 …(0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
34402 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34407 …(0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - …
34409 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34413 …3_TX_CTRL_O_24_K2_E5 (0x1<<5) // Bit 24: txdrv_c2_in[3]
34415 …HNG_EN_O_K2_E5 (0x1<<6) // Enable bit for width_chng modu…
34422 … (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2�b00: no bit stripping 2�b01: 2x bit…
34423 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X304_AHB_LN_RXBIT_STRIP_O_K2_E5_SHIFT 3
34427 …included to handle the communication between the external 64-bit data and the internal 20-bit data…
34429 …Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2�b00: no bit stuf…
34431 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
34440 …// Per lane common synchronous clock between PMA, PCS and SoC logic enable bit. 1: in NORM state, …
34454 …4_X308_BLOCK_DEC_EN_ERR_CHK_O_K2_E5 (0x1<<3) // 130b/128b error …
34455 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_DEC_EN_ERR_CHK_O_K2_E5_SHIFT 3
34472 …4_X310_RBUF_RSTN_O_K2_E5 (0x1<<3) // TX FIFO synchron…
34473 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_RBUF_RSTN_O_K2_E5_SHIFT 3
34484 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
34486 … (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to gen 3
34502 …4_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5 (0x1<<3) // Receive amplifie…
34503 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_K2_E5_SHIFT 3
34517 …4_X317_ENC_EN_OVR_O_K2_E5 (0x1<<3) // Enables 16b/20b …
34518 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_ENC_EN_OVR_O_K2_E5_SHIFT 3
34519 …f<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty…
34522 …_1_0_K2_E5 (0x3<<0) // Bit[0]: Overide value. Bit[1] :Over…
34524 …x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 …
34526 … (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable…
34529 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is …
34531 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is …
34533 …x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 …
34539 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
34540 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
34541 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
34542 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
34543 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
34544 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
34546 …bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] …
34548 …nd each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writi…
34550 …it_regp1 Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty…
34557 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
34562 …4_X330_LN_IN_OVR_O_50_K2_E5 (0x1<<3) // Override signals…
34563 …HY_PCIE_IP_REG_AHB_LANE_CSR_4_X330_LN_IN_OVR_O_50_K2_E5_SHIFT 3
34565 … (0x1<<0) // Lane Reference Clock Enable. 0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - …
34568 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
34570 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
34577 …818UL //Access:RW DataWidth:0x8 // Symbol aligner alignment word. Expects bit 0 received first
34579 … (0x3<<0) // Symbol aligner alignment word. Expects bit 0 received first
34589 … 0x002830UL //Access:RW DataWidth:0x8 // The remaining 16 bit words of an EIEOS i…
34590 … 0x002834UL //Access:RW DataWidth:0x8 // The remaining 16 bit words of an EIEOS i…
34593 … 0x002840UL //Access:RW DataWidth:0x8 // The remaining 16 bit words of an SDSOS i…
34594 … 0x002844UL //Access:RW DataWidth:0x8 // The remaining 16 bit words of an SDSOS i…
34597 … 0x002850UL //Access:RW DataWidth:0x8 // The remaining 16 bit words of a SKPOS in…
34598 … 0x002854UL //Access:RW DataWidth:0x8 // The remaining 16 bit words of a SKPOS in…
34621 … 0x002880UL //Access:RW DataWidth:0x8 // SKP symbol for PCIe Gen3 SKP OS ---8'hAA
34631 … 0x002898UL //Access:RW DataWidth:0x8 // 10-bit align symbol for eb…
34633 …0_LB_P_O_9_8_K2_E5 (0x3<<0) // 10-bit align symbol for eb…
34635 … 0x0028a0UL //Access:RW DataWidth:0x8 // 10-bit align symbol for eb…
34637 …1_LB_P_O_9_8_K2_E5 (0x3<<0) // 10-bit align symbol for eb…
34677 …REG_AHB_COMLANE_CSR_5_X48_LOS_LN3_INTRPT_I_3_K2_E5 (0x1<<3) //
34678 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN3_INTRPT_I_3_K2_E5_SHIFT 3
34686 …SR_5_X49_EYE_SCAN_SHIFT_DIR_O_K2_E5 (0x1<<3) // Determines shift…
34687 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_DIR_O_K2_E5_SHIFT 3
34702 … 0x0028e0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
34703 … 0x0028e4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
34704 … 0x0028e8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
34705 … 0x0028ecUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
34706 … 0x0028f0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
34707 … 0x0028f4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
34708 … 0x0028f8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
34709 … 0x0028fcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
34710 … 0x002900UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
34711 … 0x002904UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
34712 … 0x002908UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
34713 … 0x00290cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
34714 … 0x002910UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
34715 … 0x002914UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
34716 … 0x002918UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
34717 … 0x00291cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
34720 …nction. Varies depending on function number. Bits 15-7: Address of first command to run Bits: 6-…
34789 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
34790 …M state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity to rec…
34798 …SR_5_X143_MSM_SAPI_IDDQ_PD_LNREG_O_K2_E5 (0x1<<3) // MSM Function IDD…
34799 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREG_O_K2_E5_SHIFT 3
34815 …SR_5_X144_MSM_SAPI_IDDQ_PD_VCO_O_K2_E5 (0x1<<3) // MSM Function IDD…
34816 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_O_K2_E5_SHIFT 3
34832 …SR_5_X145_MSM_SAPI_IDDQ_RESET_RA_O_K2_E5 (0x1<<3) // MSM Function IDD…
34833 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_RA_O_K2_E5_SHIFT 3
34849 …SR_5_X146_MSM_SAPI_IDDQ_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MSM Function IDD…
34850 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
34858 …SR_5_X147_MSM_SAPI_RST_PD_LNREG_O_K2_E5 (0x1<<3) // MSM Function RES…
34859 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREG_O_K2_E5_SHIFT 3
34875 …SR_5_X148_MSM_SAPI_RST_PD_VCO_O_K2_E5 (0x1<<3) // MSM Function RES…
34876 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_O_K2_E5_SHIFT 3
34892 …SR_5_X149_MSM_SAPI_RST_RESET_RA_O_K2_E5 (0x1<<3) // MSM Function RES…
34893 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_RA_O_K2_E5_SHIFT 3
34909 …SR_5_X150_MSM_SAPI_RST_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MSM Function RES…
34910 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
34918 …SR_5_X151_MSM_SAPI_NORM_PD_LNREG_O_K2_E5 (0x1<<3) // MSM Function NOR…
34919 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREG_O_K2_E5_SHIFT 3
34935 …SR_5_X152_MSM_SAPI_NORM_PD_VCO_O_K2_E5 (0x1<<3) // MSM Function NOR…
34936 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_O_K2_E5_SHIFT 3
34952 …SR_5_X153_MSM_SAPI_NORM_RESET_RA_O_K2_E5 (0x1<<3) // MSM Function NOR…
34953 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_RA_O_K2_E5_SHIFT 3
34969 …SR_5_X154_MSM_SAPI_NORM_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MSM Function NOR…
34970 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
34978 …SR_5_X155_MSM_SAPI_PARTIAL_PD_LNREG_O_K2_E5 (0x1<<3) // MSM Function PAR…
34979 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREG_O_K2_E5_SHIFT 3
34995 …SR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_O_K2_E5 (0x1<<3) // MSM Function PAR…
34996 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_O_K2_E5_SHIFT 3
35012 …SR_5_X157_MSM_SAPI_PARTIAL_RESET_RA_O_K2_E5 (0x1<<3) // MSM Function PAR…
35013 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_RA_O_K2_E5_SHIFT 3
35029 …SR_5_X158_MSM_SAPI_PARTIAL_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MSM Function PAR…
35030 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
35038 …SR_5_X159_MSM_SAPI_SLUMBER_PD_LNREG_O_K2_E5 (0x1<<3) // MSM Function SLU…
35039 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREG_O_K2_E5_SHIFT 3
35055 …SR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_O_K2_E5 (0x1<<3) // MSM Function SLU…
35056 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_O_K2_E5_SHIFT 3
35072 …SR_5_X161_MSM_SAPI_SLUMBER_RESET_RA_O_K2_E5 (0x1<<3) // MSM Function SLU…
35073 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_RA_O_K2_E5_SHIFT 3
35089 …SR_5_X162_MSM_SAPI_SLUMBER_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MSM Function SLU…
35090 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
35210 …SR_5_X198_TXCTRL_MASTER_TX_SLEW_SLD3F_OVR_2_0_K2_E5 (0x7<<3) // TX enable fastes…
35211 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X198_TXCTRL_MASTER_TX_SLEW_SLD3F_OVR_2_0_K2_E5_SHIFT 3
35260 …LOW_EN_O_K2_E5 (0x1<<6) // Brings the TxEq pre-cursor down to a prog…
35262 …OW_EN_O_K2_E5 (0x1<<7) // Brings the TxEq pre-cursor down to a prog…
35267 …SR_5_X211_RX_BIAS_01_O_2_0_K2_E5 (0x7<<3) // AFE rx_bias sett…
35268 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X211_RX_BIAS_01_O_2_0_K2_E5_SHIFT 3
35276 …5 (0xf<<0) // Number of wait cycles for the CDR to lock [3:0] times 64
35280 … (0x1<<6) // Set all DFE calibration values to mid-scale instead of usin…
35282 … 0x002b5cUL //Access:RW DataWidth:0x8 // DFE block -continuous calibratio…
35284 …NT_LENGTH_O_14_8_K2_E5 (0x7f<<0) // DFE block -continuous calibratio…
35286 … 0x002b64UL //Access:RW DataWidth:0x8 // DFE block - ATT calibration cycl…
35287 … 0x002b68UL //Access:RW DataWidth:0x8 // DFE block - Boost calibration cy…
35288 … 0x002b6cUL //Access:RW DataWidth:0x8 // DFE block - TAP1 calibration cyc…
35289 … 0x002b70UL //Access:RW DataWidth:0x8 // DFE block - TAP2 calibration cyc…
35290 … 0x002b74UL //Access:RW DataWidth:0x8 // DFE block - TAP3 calibration cyc…
35291 … 0x002b78UL //Access:RW DataWidth:0x8 // DFE block - TAP4 calibration cyc…
35292 … 0x002b7cUL //Access:RW DataWidth:0x8 // DFE block - TAP5 calibration cyc…
35296 …CAL_O_6_0_K2_E5 (0x7f<<1) // Enables re-calibration for { Tap…
35299 …bit [0]: Enables ATT calibration when asserted bit [1]: Enables Boost calibration when asserted bi…
35302 …bit [0]: Enables ATT calibration when asserted bit [1]: Enables Boost calibration when asserted bi…
35305 …TE2_RECAL_O_6_0_K2_E5 (0x7f<<0) // Enables re-calibration for { Tap…
35339 …bit [0]: Reverses polarity of ATT calibration when asserted bit [1]: Reverses polarity of Boost ca…
35464 …E_I_3_0_K2_E5 (0xf<<0) // RXEQ calibration done status - per lane
35466 …DAPT_DONE_I_3_0_K2_E5 (0xf<<4) // TXEQ Adapt Done status - per lane
35475 …O_K2_E5 (0x1f<<0) // Bit 4 - latency check control enable Bit 3:0 …
35547 …ning pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding…
35550 …ning pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding…
35553 …ning pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding…
35556 …ning pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding…
35559 …ning pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding…
35562 …ning pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding…
35582 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
35585 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
35588 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
35591 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
35594 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
35597 …g bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern b…
35600 …bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enabl…
35603 …bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enabl…
35606 …bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enabl…
35609 …bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enabl…
35624 …coarse calibration 0: last data, 1: avg of last two data, 2: avg of last four data, 3: last data
35626 …l fine calibration 0: last data, 1: avg of last two data, 2: avg of last four data, 3: last data
35628 …e dlev calibration 0: last data, 1: avg of last two data, 2: avg of last four data, 3: last data
35704 …REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_FINAL_CMP_WRITE_EN_O_K2_E5 (0x1<<3) //
35705 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_FINAL_CMP_WRITE_EN_O_K2_E5_SHIFT 3
35714 …SR_5_X376_MSM_PIPE_RST_PD_LNREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
35715 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREG_O_K2_E5_SHIFT 3
35731 …SR_5_X377_MSM_PIPE_RST_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
35732 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_O_K2_E5_SHIFT 3
35748 …SR_5_X378_MSM_PIPE_RST_RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
35749 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_RA_O_K2_E5_SHIFT 3
35765 …SR_5_X379_MSM_PIPE_RST_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
35766 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
35774 …SR_5_X380_MSM_PIPE_P0_PD_LNREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
35775 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREG_O_K2_E5_SHIFT 3
35791 …SR_5_X381_MSM_PIPE_P0_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
35792 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_O_K2_E5_SHIFT 3
35808 …SR_5_X382_MSM_PIPE_P0_RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
35809 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_RA_O_K2_E5_SHIFT 3
35825 …SR_5_X383_MSM_PIPE_P0_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
35826 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
35834 …SR_5_X384_MSM_PIPE_P1_PD_LNREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
35835 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREG_O_K2_E5_SHIFT 3
35851 …SR_5_X385_MSM_PIPE_P1_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
35852 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_O_K2_E5_SHIFT 3
35868 …SR_5_X386_MSM_PIPE_P1_RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
35869 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_RA_O_K2_E5_SHIFT 3
35885 …SR_5_X387_MSM_PIPE_P1_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
35886 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
35894 …SR_5_X388_MSM_PIPE_P2_PD_LNREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
35895 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREG_O_K2_E5_SHIFT 3
35911 …SR_5_X389_MSM_PIPE_P2_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
35912 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_O_K2_E5_SHIFT 3
35928 …SR_5_X390_MSM_PIPE_P2_RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
35929 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_RA_O_K2_E5_SHIFT 3
35945 …SR_5_X391_MSM_PIPE_P2_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
35946 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
35960 …SR_5_X401_L3_MASTER_CDN_O_K2_E5 (0x1<<3) // Lane3 master res…
35961 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L3_MASTER_CDN_O_K2_E5_SHIFT 3
35968 …(0x3<<3) // Controls the number of clk cycles delay from data_en of p2s_rbuf to propagate to the i…
35969 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X403_TXDP_IDLE_IN_DELAY_K2_E5_SHIFT 3
35973 …_I_2_0_K2_E5 (0x7<<0) // 1000Base-KX Mode status for CPU
35975 …NE_CSR_5_X406_CMU_OK_I_0_K2_E5 (0x1<<3) // CMU OK Status
35976 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X406_CMU_OK_I_0_K2_E5_SHIFT 3
35986 …407_LN3_SIG_LEVEL_VALID_I_3_K2_E5 (0x1<<3) // Lane 3 Signal Detect V…
35987 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_SIG_LEVEL_VALID_I_3_K2_E5_SHIFT 3
35994 …CSR_5_X407_LN3_OK_I_7_K2_E5 (0x1<<7) // Lane 3 OK Status
36003 …408_LN3_RX_LOCKED_I_7_6_K2_E5 (0x3<<6) // Lane 3 RX Locked Status
36015 …SR_5_X410_LANE_RATE_CHNG_OVR_O_K2_E5 (0x1<<3) // Newly added for …
36016 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_CHNG_OVR_O_K2_E5_SHIFT 3
36036 …X414_TXPRESET_COEFF_P0CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P0 C-1
36045 …X417_TXPRESET_COEFF_P1CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P1 C-1
36054 …X420_TXPRESET_COEFF_P2CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P2 C-1
36063 …X423_TXPRESET_COEFF_P3CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P3 C-1
36072 …X426_TXPRESET_COEFF_P4CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P4 C-1
36081 …X429_TXPRESET_COEFF_P5CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P5 C-1
36090 …X432_TXPRESET_COEFF_P6CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P6 C-1
36099 …X435_TXPRESET_COEFF_P7CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P7 C-1
36108 …X438_TXPRESET_COEFF_P8CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P8 C-1
36117 …X441_TXPRESET_COEFF_P9CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P9 C-1
36126 …444_TXPRESET_COEFF_P10CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P10 C-1
36175 …SR_5_X483_MSM_PIPE_P1_0_RX_GATE_EN_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
36176 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RX_GATE_EN_O_K2_E5_SHIFT 3
36192 …SR_5_X484_MSM_PIPE_P1_0_RESET_LNREGH_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
36193 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_LNREGH_O_K2_E5_SHIFT 3
36209 …SR_5_X485_MSM_PIPE_P1_0_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
36210 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_VCO_O_K2_E5_SHIFT 3
36226 …SR_5_X486_MSM_PIPE_P1_0_RESET_TX_CLKDIV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
36227 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_RESET_TX_CLKDIV_O_K2_E5_SHIFT 3
36235 …SR_5_X487_MSM_PIPE_P1_1_RX_GATE_EN_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
36236 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RX_GATE_EN_O_K2_E5_SHIFT 3
36252 …SR_5_X488_MSM_PIPE_P1_1_RESET_LNREGH_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
36253 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_LNREGH_O_K2_E5_SHIFT 3
36269 …SR_5_X489_MSM_PIPE_P1_1_PD_VCO_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
36270 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_VCO_O_K2_E5_SHIFT 3
36286 …SR_5_X490_MSM_PIPE_P1_1_PD_TXREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
36287 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_PD_TXREG_O_K2_E5_SHIFT 3
36295 …SR_5_X491_MSM_PIPE_P1_2_RX_GATE_EN_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
36296 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RX_GATE_EN_O_K2_E5_SHIFT 3
36312 …SR_5_X492_MSM_PIPE_P1_2_RESET_RA_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
36313 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_RA_O_K2_E5_SHIFT 3
36329 …SR_5_X493_MSM_PIPE_P1_2_PD_TXDRV_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
36330 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_TXDRV_O_K2_E5_SHIFT 3
36346 …SR_5_X494_MSM_PIPE_P1_2_PD_TXREG_O_K2_E5 (0x1<<3) // MFSM's PMA pd/re…
36347 …HY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_PD_TXREG_O_K2_E5_SHIFT 3
36355 …- no auto deassertion; 1 - auto deassertion); [1] rst_pswrd_auto_mode (0- no auto deassertion; 1 -…
36356 …-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out…
36357 …C_REG_RESET_PL_UA_SIZE 3
36358 …-shared blocks which can be reset also by driver in HV (PL=HV); Read: read one = the specific bloc…
36359 …C_REG_RESET_PL_HV_SIZE 3
36360 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36361 …C_REG_RESET_PL_PDA_VMAIN_1_SIZE 3
36362 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36363 …C_REG_RESET_PL_PDA_VMAIN_2_SIZE 3
36364 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36365 …C_REG_RESET_PL_PDA_VAUX_SIZE 3
36366 …-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out…
36367 …C_REG_RESET_PL_UA_VMAIN_SIZE 3
36372 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
36380 …ccess:RW DataWidth:0x1 // Set/clr general attention 0; this will set/clr bit 48 in AEU vector.
36381 …cess:RW DataWidth:0x1 // Set/clr general attention 1; this will set/clr bit 49 in AEU vector.
36382 …cess:RW DataWidth:0x1 // Set/clr general attention 2; this will set/clr bit 50 in AEU vector.
36383 …UL //Access:RW DataWidth:0x1 // Set/clr general attention 3; this will set/clr bit 51 in AEU…
36384 …ccess:RW DataWidth:0x1 // Set/clr general attention 4; this will set/clr bit 52 in AEU vector.
36385 …ccess:RW DataWidth:0x1 // Set/clr general attention 5; this will set/clr bit 53 in AEU vector.
36386 …ccess:RW DataWidth:0x1 // Set/clr general attention 6; this will set/clr bit 54 in AEU vector.
36387 …ccess:RW DataWidth:0x1 // Set/clr general attention 7; this will set/clr bit 55 in AEU vector.
36388 …ccess:RW DataWidth:0x1 // Set/clr general attention 8; this will set/clr bit 56 in AEU vector.
36389 …ccess:RW DataWidth:0x1 // Set/clr general attention 9; this will set/clr bit 57 in AEU vector.
36390 …cess:RW DataWidth:0x1 // Set/clr general attention 10; this will set/clr bit 58 in AEU vector.
36391 …cess:RW DataWidth:0x1 // Set/clr general attention 11; this will set/clr bit 59 in AEU vector.
36392 …cess:RW DataWidth:0x1 // Set/clr general attention 12; this will set/clr bit 60 in AEU vector.
36393 …cess:RW DataWidth:0x1 // Set/clr general attention 13; this will set/clr bit 61 in AEU vector.
36394 …cess:RW DataWidth:0x1 // Set/clr general attention 14; this will set/clr bit 62 in AEU vector.
36395 …cess:RW DataWidth:0x1 // Set/clr general attention 15; this will set/clr bit 63 in AEU vector.
36396 …cess:RW DataWidth:0x1 // Set/clr general attention 16; this will set/clr bit 64 in AEU vector.
36397 …cess:RW DataWidth:0x1 // Set/clr general attention 17; this will set/clr bit 65 in AEU vector.
36398 …cess:RW DataWidth:0x1 // Set/clr general attention 18; this will set/clr bit 66 in AEU vector.
36399 …cess:RW DataWidth:0x1 // Set/clr general attention 19; this will set/clr bit 67 in AEU vector.
36400 …cess:RW DataWidth:0x1 // Set/clr general attention 20; this will set/clr bit 68 in AEU vector.
36401 …cess:RW DataWidth:0x1 // Set/clr general attention 21; this will set/clr bit 69 in AEU vector.
36402 …cess:RW DataWidth:0x1 // Set/clr general attention 22; this will set/clr bit 70 in AEU vector.
36403 …cess:RW DataWidth:0x1 // Set/clr general attention 23; this will set/clr bit 71 in AEU vector.
36404 …cess:RW DataWidth:0x1 // Set/clr general attention 24; this will set/clr bit 72 in AEU vector.
36405 …cess:RW DataWidth:0x1 // Set/clr general attention 25; this will set/clr bit 73 in AEU vector.
36406 …cess:RW DataWidth:0x1 // Set/clr general attention 26; this will set/clr bit 74 in AEU vector.
36407 …cess:RW DataWidth:0x1 // Set/clr general attention 27; this will set/clr bit 75 in AEU vector.
36408 …cess:RW DataWidth:0x1 // Set/clr general attention 28; this will set/clr bit 76 in AEU vector.
36409 …cess:RW DataWidth:0x1 // Set/clr general attention 29; this will set/clr bit 77 in AEU vector.
36410 …cess:RW DataWidth:0x1 // Set/clr general attention 30; this will set/clr bit 78 in AEU vector.
36411 …cess:RW DataWidth:0x1 // Set/clr general attention 31; this will set/clr bit 79 in AEU vector.
36412 …cess:RW DataWidth:0x1 // Set/clr general attention 32; this will set/clr bit 80 in AEU vector.
36413 …cess:RW DataWidth:0x1 // Set/clr general attention 33; this will set/clr bit 81 in AEU vector.
36414 …cess:RW DataWidth:0x1 // Set/clr general attention 34; this will set/clr bit 82 in AEU vector.
36415 …cess:RW DataWidth:0x1 // Set/clr general attention 35; this will set/clr bit 83 in AEU vector.
36416 …008490UL //Access:RW DataWidth:0x1 // Event_enable control; when this bit is clear the event …
36419 …he output for output0. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36420 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36421 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36422 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36423 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36424 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36425 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36426 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36427 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36428 …he output for output1. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36429 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36430 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36431 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36432 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36433 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36434 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36435 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36436 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36437 …he output for output2. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36438 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36439 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36440 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36441 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36442 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36443 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36444 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36445 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36446 …he output for output3. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36447 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36448 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36449 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36450 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36451 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36452 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36453 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36454 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36455 …he output for output4. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36456 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36457 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36458 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36459 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36460 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36461 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36462 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36463 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36464 …he output for output5. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36465 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36466 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36467 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36468 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36469 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36470 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36471 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36472 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36473 …he output for output6. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36474 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36475 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36476 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36477 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36478 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36479 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36480 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36481 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36482 …he output for output7. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36483 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36484 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36485 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36486 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36487 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36488 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36489 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36490 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36491 …or close the gate nig. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36492 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36493 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36494 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36495 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36496 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36497 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36498 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36499 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36500 …or close the gate pxp. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36501 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36502 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36503 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36504 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36505 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36506 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36507 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36508 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36509 …utput for system kill. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36510 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36511 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36512 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36513 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36514 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36515 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36516 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36517 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36518 …he output for output0. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36519 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36520 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36521 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36522 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36523 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36524 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36525 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36526 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36527 …he output for output1. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36528 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36529 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36530 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36531 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36532 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36533 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36534 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36535 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36536 …he output for output2. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36537 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36538 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36539 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36540 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36541 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36542 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36543 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36544 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36545 …he output for output3. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36546 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36547 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36548 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36549 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36550 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36551 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36552 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36553 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36554 …he output for output4. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36555 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36556 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36557 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36558 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36559 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36560 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36561 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36562 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36563 …he output for output5. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36564 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36565 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36566 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36567 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36568 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36569 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36570 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36571 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36572 …he output for output6. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36573 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36574 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36575 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36576 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36577 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36578 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36579 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36580 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36581 …he output for output7. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36582 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36583 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36584 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36585 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36586 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36587 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36588 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36589 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36590 …al uncorrectable eror. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36591 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36592 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36593 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36594 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36595 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36596 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36597 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36598 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36599 …r inverting the input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36600 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36601 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36602 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36603 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36604 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36605 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36606 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36607 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36608 …r inverting the input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36609 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36610 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36611 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36612 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36613 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36614 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36615 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36616 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36617 …after invert of input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36618 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36619 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36620 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36621 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36622 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36623 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36624 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36625 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36626 …after invert of input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36627 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36628 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36629 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36630 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36631 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36632 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36633 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36634 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36636 …0x008800UL //Access:RW DataWidth:0x1 // The System Kill enable: 0 - none; 1 - hard reset. Res…
36637 … system kill occurred. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; […
36638 …3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main p…
36639 …apped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] …
36640 …3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW in…
36641 …: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw inter…
36642 …3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM …
36643 …llows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4…
36644 …3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSW…
36645 …hed memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; […
36647 … (0x1<<0) // Pxp close the gate mask bit; 0 = masked; 1 = un…
36649 … (0x1<<1) // Nig close the gate mask bit; 0 = masked; 1 = un…
36651 … (0x1<<2) // System kill mask bit; 0 = masked; 1 = un…
36653 … (0x1<<3) // Global uncorrectable error mask bit;…
36654 …ISC_REG_AEU_GENERAL_MASK_AEU_GLB_UNC_ERR_MASK_SHIFT 3
36655 …3:2] reserved; [4] one clears pglue_misc_mps_attn; [5] one clears pxp_misc_exp_rom_attn; [6] one c…
36657 …ister results with the clear of the latched signals; [0] - clears pglue_misc_vpd_attn[0], [1] - cl…
36659 …- latches first attention number within attentions vector. The number is produced as the index of …
36660 … 0x008c00UL //Access:RW DataWidth:0x2 // Port mode. 0 - single port; 1 - 2 ports; 2 - 4 por…
36661 … Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - Dual Port Mode; 1x …
36662 …s is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - Dual Port Mode; 10 - Tri Port…
36663 …- disabled, 1 - enabled. When OPTE mode is enabled, it connects two engines to one MAC port. Port…
36664 …bit; 1: clk_nw and main clk are asynchronous and sync FIFOs should be used. (clk_nw = 425 MHz); 0…
36665 …igBear) it should be set to 1 in 100G and 50G modes. Reset on Hard reset. [0]- BRB; [1] - BTB, PBF;
36667 …- Storms stall is disallowed; AEU unifier bit[7] output to MCP is disabled; 1 - All Storms are for…
36668 … 0x008c20UL //Access:RW DataWidth:0x17 // 23 bit GRC address where the scratch-pad o…
36669 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36670 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36671 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36672 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36673 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36674 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36675 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36676 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36677 …eload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW…
36678 …eload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW…
36679 …x20 // Reload value for counter 3 if reload; the value will be reload if the counter reached zer…
36680 …eload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW…
36681 …eload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW…
36682 …eload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW…
36683 …eload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW…
36684 …eload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW…
36685 …bit will clear the appropriate event to the AEU (if the attn bit (bit 2) in the MISC_REGISTERS_SW_…
36686 …he appropriate timer had reach to zero. [0] timer1; [1]timer2; [2] timer3; [3] timer4; [4] timer5;…
36701 …he counter for sw timers1-8. there are 8 addresses in this register. address 0 - timer 1; address …
36703 …- no auto deassertion; 1 - auto deassertion); [1] rst_umac_on_core_rst (0- no auto deassertion; 1 …
36704 …- is not reset on hard reset; 1 - is reset on hard reset); [1] rst_n_hard_misc_rbc_pcie (0 - is no…
36705 …3-ignore; The order of the bits is: [0] rst_cgrc; [1] rst_mcp_n_reset_reg_hard_core; [2] rst_mcp_n…
36706 …CS_REG_RESET_PL_UA_SIZE 3
36707 … writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_cnig; [1] rst_pglc…
36708 …CS_REG_RESET_PL_HV_SIZE 3
36711 …- source of privilege level, 0 - the source is external pin, 1 - the source are bits[2:1] of this …
36712 … // Privilege level as defined by external pin. 0 - non-secured mode; 1 - secured mode; 2 - full…
36713 …-disable to the NVM block is generated. '0' - PROTECT: This value protects the NVM from any writes…
36714 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36716 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36718 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36720 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36722 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36724 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36726 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36728 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36730 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36732 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36734 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36736 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36738 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36740 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36742 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36744 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36746 …bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client …
36748 …bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client …
36750 …bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client …
36752 …bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client …
36754 …bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client …
36756 …bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client …
36758 …bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client …
36760 …bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client …
36762 …iting "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_nwm; [1] rst_nwm_mac0…
36763 …CS_REG_RESET_PL_HV_2_SIZE 3
36777 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
36779 … (0x1<<1) // This bit masks, when set, the Interrupt bit: M…
36781 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
36804 …FIFO_ERR_ENG0_BB (0x1<<3) // DBG FIFO error i…
36805 …ISCS_REG_INT_STS_1_OPTE_DBG_FIFO_ERR_ENG0_BB_SHIFT 3
36821 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
36823 … (0x1<<1) // This bit masks, when set, the Interrupt bit: M…
36825 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
36827 … (0x1<<3) // This bit masks, when set, the Interrupt …
36828 …ISCS_REG_INT_MASK_1_OPTE_DBG_FIFO_ERR_ENG0_BB_SHIFT 3
36829 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
36831 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
36833 … (0x1<<6) // This bit masks, when set, the Interrupt bit: M…
36835 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
36837 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
36839 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
36841 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
36850 …BG_FIFO_ERR_ENG0_BB (0x1<<3) // DBG FIFO error i…
36851 …ISCS_REG_INT_STS_WR_1_OPTE_DBG_FIFO_ERR_ENG0_BB_SHIFT 3
36873 …DBG_FIFO_ERR_ENG0_BB (0x1<<3) // DBG FIFO error i…
36874 …ISCS_REG_INT_STS_CLR_1_OPTE_DBG_FIFO_ERR_ENG0_BB_SHIFT 3
36890 … (0x1<<0) // This bit masks, when set, the Parity bit: MI…
36892 …state of the ptw_miscs_pcie_link_up signal which is driven by the PCIE core - a pulse at the begin…
36893 …ate of the ptw_miscs_pcie_hot_reset signal which is driven by the PCIE core - a pulse at the begin…
36895 … DataWidth:0x10 // Accounts for HOT RESET assertion when the chip is in un-prepared state. Is re…
36897 …Width:0x1 // Set to 1 when main PLL lock indication is de-asserted when hard reset is de-assert…
36898 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36899 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36900 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36901 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36902 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36903 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36904 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36905 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36906 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36907 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36908 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36909 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36910 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36911 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36912 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36913 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36914 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36915 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36916 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36917 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36918 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36919 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36920 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36921 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36922 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36923 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36924 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36925 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36926 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36927 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36928 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36929 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36930 … FLOAT: When any of these bits is written as a '1'; the corresponding GPIO bit will turn off it's …
36931 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36932 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36933 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36934 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36935 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36936 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36937 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36938 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36939 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36940 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36941 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36942 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36943 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36944 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36945 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36946 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36947 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36948 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36949 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36950 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36951 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36952 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36953 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36954 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36955 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36956 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36957 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36958 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36959 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36960 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36961 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36962 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36963 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36964 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36965 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36966 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36967 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36968 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36969 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36970 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36971 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36972 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36973 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36974 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36975 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36976 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36977 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36978 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36979 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36980 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36981 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36982 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36983 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36984 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36985 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36986 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36987 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36988 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36989 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36990 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36991 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36992 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36993 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36994 …bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if correspond…
36996 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
36997 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
36998 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
36999 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37000 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37001 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37002 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37003 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37004 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37005 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37006 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37007 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37008 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37009 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37010 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37011 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37012 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37013 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37014 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37015 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37016 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37017 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37018 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37019 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37020 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37021 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37022 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37023 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37024 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37025 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37026 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37027 …3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. Thi…
37029 …bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client …
37031 …bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client …
37033 …bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client …
37035 …bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client …
37037 …bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client …
37039 …bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client …
37041 …bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client …
37043 …bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client …
37046 …Bit[0]: PERST# IO de-assertion. If == 1, triggers chip core reset. If == 0, doesn't trigger chip c…
37047 …Bit[0]: Out of the Box (OOB) WOL enable. Set to 1 to enable use of NIC magic packet detection to a…
37050 …0x0096b8UL //Access:R DataWidth:0x1 // Chip core_rst_n status. 0 - asserted; 1 - de-asserted.
37051 …Bit 0 : LINK_HOLDOFF_SUCCESS When =1, indicates the PCIE link is successfully being held from sta…
37052 …bit is written to a '1' to request that the PCIE link not begin training yet. Software should set …
37057 …RW DataWidth:0x20 // Debug only: spare RW register reset by por reset. bit 0 is used for Vmain…
37059 …Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to use all of the 32 Extended GPIO p…
37060 …W DataWidth:0x20 // Debug only: spare RW register reset by core reset. Bit[0]: used for VCCMIN…
37061 …- spare RW register reset by por reset; [10:8] : PCIe Device Type: 3'b000 - Endpoint mode; 3'b010 …
37063 … DataWidth:0x2 // 0-bypass the Vmain PORBG. for Vmain POR; if sel=1 the output wil be MISC_REGI…
37064 … // Bypass to the FUNC_HIDE pin. Bit 0 - bypass select; Bits[15:1] - bypass value per function (…
37065 … 0x0096f4UL //Access:RW DataWidth:0x1 // This bit indicates that a Vm…
37069 … DataWidth:0x1 // NIG debug mux vector control. 0 - NIG0 debug vector is output to IFMUX; 1 -…
37070 …Drives misc_cnig_mux_4port_shared_mdio_en output. Applicable both in 2-port and 4-port mode. TBD: …
37071 …1 // NIG EMAC debug source selector. If 0 - path0 gmii/mii emac debug outputs are selected by N…
37072 …s:R DataWidth:0x2 // SEL_VAUX_B - Control to power switching logic. [0] - output value drive…
37073 … 0x009714UL //Access:RW DataWidth:0x1 // PCIE disable register bit. PCIE DIS. Has same…
37075 …bit corresponds to a PF pair i.e. bit 0 for global PFs 0 and 1; bit 1 for global PFs 2 and 3. If t…
37076 … 0x009720UL //Access:RW DataWidth:0x1 // This bit will be set by the …
37078 …-chip PHY devices and MAC ports to the four MDIO domains. It is only used when MISC_REGISTERS_MDIO…
37079 … asserted (Hot Reset / SBR / Link Down / Link Disable) and the chip is in un-prepared state. Reset…
37081 …ess:RW DataWidth:0x1 // Debug only : parity mode to MCP. Setting this bit changes the parity …
37082 …W DataWidth:0x1 // Writing this bit as a '1' will cause the chip to do an internal reset exac…
37083 …bit; when set; the compatible bit in the MISC_REGISTERS_MAIN_SEQ_BYP_VAL.MAIN_SEQ_BYP_VAL affects …
37084 …bit; the written value affects the control only if the compatible bit in the MISC_REGISTERS_MAIN_S…
37087 …-less mux control source: 0-management power sequencer output; 1-glich-less mux manual setting (bi…
37088 …0UL //Access:RW DataWidth:0x1 // [0]clock storm bypass: 0-select Storm SPLL clock; 1-select e…
37089 … by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset…
37090 … by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset…
37091 … the Driver to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset…
37092 … 0x009760UL //Access:R DataWidth:0x1 // 0 - VAUX is not present (external pin is 0); 1 …
37093 …-6] RESERVED (FLOAT: these IOs are outputs only). [5-4] CLR: When any of these bits is written as …
37096 … the chip. This value starts at 0x0 for the A0 tape-out and increments by one for each all-layer t…
37097 …f the chip. This value starts at 0x00 for each all-layer tape-out and increments by one for each t…
37099 … 0x00977cUL //Access:R DataWidth:0x1 // When this bit is 1 it indicates t…
37100 …bit reports the current state of the PCIE_DIS pin. If this bit is 1 it means that the LOM design h…
37103 … 0x00978cUL //Access:RW DataWidth:0x10 // Accounts for Hard reset de-assertion. Is reset o…
37105 … 0x009794UL //Access:RW DataWidth:0x10 // Accounts for Core de-reset assertion. Is r…
37107 … 0x00979cUL //Access:RW DataWidth:0x10 // Accounts for PERST_B reset de-assertion. Is reset o…
37109 … DataWidth:0x10 // Accounts for PCI_RST_N assertion when the chip is in un-prepared state. Is re…
37110 … 0x0097a8UL //Access:RW DataWidth:0x10 // Accounts for PCI_RST_N de-assertion. Is reset o…
37111 …-prepared state, hard reset is asserted. When =0, when ptw_miscs_pcie_hot_reset is asserted (Hot R…
37113 …- used to programm loopback into Emulation (3\|2\|1\|0 (Enable loopback within the same port\|Enab…
37115 …ALID [7:6] OTP_AVS_SRAM_MON_N_PROCESS [5:4] OTP_AVS_SRAM_MON_P_PROCESS [3:0] OTP_ADJUST_VOLT…
37120 …r-ride: When set, over-ride DAC code from AVS monitor with on from this register [20:11] VMgmt DAC…
37121 …- Per-TC packet available status; [10] - STORM FIFO; [9] - BTB SOP FIFO for engine 0; [8] - BTB S…
37122 …- STORM FIFO almost full; [10] - STORM FIFO full; [9] - BTB SOP FIFO full for engine 0; [8] - …
37123 …bit for each statistics. [7] - Received packet from BTB IF0 of engine 0; [6] - Received packet f…
37124 …- storm_init_crd: Credits for the output STORM Packet interface. [3:2] - storm_pkt_dst: Select t…
37125 …-full Threshold. [29:25] - Btb_if0_fifo_almfull_thr: Almost-full threshold for BTB main traffic F…
37126 …//Access:RW DataWidth:0x6 // [31:6] Reserved [5] Divide enable [4] Enable [3:0] Control
37127 … 0x0097f0UL //Access:RW DataWidth:0x3 // [31:3] Reserved [2] Ena…
37131 … (0x1<<0) // This bit will always read '1…
37133 …bit will read '1' if a byte has been received with a framing error. It will continue to read as a …
37135 …s bit will read '1' of a receive overflow has occurred. It will continue to read as a '1' until th…
37138 … (0x1<<0) // This bit will read '1' if there is a valid byte to read in dbu_rxdata. Once …
37140 … (0x1<<1) // This bit will read '1' if there is data pending to be transmitted in the …
37143 … (0x1<<0) // When this bit is set, the UART timing will be determined by the values in the dbu_…
37145 … (0x1<<1) // When this bit is set, the debug s…
37147 … (0x1<<2) // When this bit is set, all line feeds shall be preceded by a carriage retur…
37150 …core_clock cycles after the falling edge of the rx_data pin that the start bit should be sampled. …
37154 … DataWidth:0x8 // This bit indicates that the data currently in bits 7:0 of this register was …
37155 … of data on the serial interface. Firmware should poll the txdata_occupied bit in the status regis…
37161 … (0x1<<16) // The vfid_value bits are valid only if this bit is set. If this bit is cleare…
37163 … (0x1<<20) // Set the path ID if the access is forced as indicated by bit 31.
37167 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
37168 … enable. If 0 - the acknowledge input is disregarded; valid is deasserted; full is asserted; all o…
37169 …t;Master) enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
37173 … 0x00c054UL //Access:RW DataWidth:0x1 // Command 3 go.
37209 … (0x1<<0) // This bit masks, when set, the Interrupt bit: D…
37211 … (0x1<<1) // This bit masks, when set, the Interrupt bit: D…
37224 … (0x1<<0) // This bit masks, when set, the Parity bit: DM…
37226 … (0x1<<1) // This bit masks, when set, the Parity bit: DM…
37228 … (0x1<<2) // This bit masks, when set, the Parity bit: DM…
37231 … 0x00c400UL //Access:RW DataWidth:0x4 // DMAE- PCI Request Interfac…
37232 …404UL //Access:RW DataWidth:0x1 // Relaxed ordering. 0-strict PCI ordering is used;1-PCI-X re…
37233 … 0x00c408UL //Access:RW DataWidth:0x1 // 0-PCI type cache snoop protection is required;…
37234 …00c40cUL //Access:RW DataWidth:0x1 // If 0 - the CRC-16 initial value is all zeroes; if 1 - t…
37235 … //Access:RW DataWidth:0x1 // If 0 - the CRC-16 final calculation result isn't byte swapped; …
37236 …0c414UL //Access:RW DataWidth:0x1 // If 0 - the CRC-16c initial value is all zeroes; if 1 - t…
37237 …c418UL //Access:RW DataWidth:0x1 // If 0 - the CRC-16 T10 initial value is all zeroes; if 1 -…
37238 …00c41cUL //Access:RW DataWidth:0x1 // If 0 - the CRC-32 initial value is all zeroes; if 1 - t…
37239 … //Access:RW DataWidth:0x1 // If 0 - the CRC-32 final calculation result isn't byte swapped; …
37240 …0c424UL //Access:RW DataWidth:0x1 // If 0 - the CRC-32c initial value is all zeroes; if 1 - t…
37241 …//Access:RW DataWidth:0x1 // If 0 - the CRC-32c final calculation result isn't byte swapped; …
37242 …0x00c42cUL //Access:RW DataWidth:0x1 // If 0 - the final checksum equal 0 won't be changed;if…
37243 …st ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Release; …
37244 …st ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Release; …
37245 … 0x00c438UL //Access:RW DataWidth:0x1 // When set discards 1- or 2-Dword PCI transact…
37246 … 0x00c43cUL //Access:RW DataWidth:0x14 // GRC address in case 1- or 2-Dword PCI transact…
37250 …- Bidirectional shared data structure; 01 - Device writes/reads then device reads/writes soon; 10 …
37255 …: 0 - VN Virtualized NIC (Used for VF access); 1 - PDA Physical Device Assignment (Assigned to VM-…
37262 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
37263 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
37264 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
37265 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
37272 …- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; 5- RBCF; 6- RBCX; 7- RBCS; 8-RBCH; 9-RBCZ; 10 - other e…
37273 …- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; 5- RBCF; 6- RBCX; 7- RBCS; 8-RBCH; 9-RBCZ; 10 - other e…
37275 … (0x1<<0) // Debug only: This bit is an enable to PCI output request interface; T…
37277 … (0x1<<1) // Debug only: This bit is an enable to PCI output data interface; Th…
37279 …bit is an enable to NIG output data interface. When DBG_REGISTERS_OUTPUT_ENABLE.PCI_REQ_ENABLE and…
37281 …as follows: 0-NONE; 1-DoubleBwTx (DoubleBw the TX side); 2-DoubleBwRx (DoubleBw the RX side); 3-Cr…
37282 …dex for slot 0 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37283 …dex for slot 1 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37284 …dex for slot 2 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37285 …its are a client index for slot 3 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 …
37286 …dex for slot 4 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37287 …dex for slot 5 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37288 …dex for slot 6 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37289 …dex for slot 7 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37290 …dex for slot 8 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37291 …dex for slot 9 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37292 …ex for slot 10 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37293 …ex for slot 11 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37294 …ex for slot 12 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37295 …ex for slot 13 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37296 …ex for slot 14 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37297 …ex for slot 15 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37298 … 0x010054UL //Access:RW DataWidth:0x8 // Debug only: This bit indicates the calen…
37299 …- 128b STORM (A and B) data is logged 1 - 64b STORM (A and B) data + 4 different (in general case)…
37300 …only: These bits indicate the target of the debug data: 0 - internal buffer; 1 - NIG; 2 - PCI.
37301 …bit indicates whether data will be wrapped (oldest data is thrown) or overflowed-one shot (newest …
37306 … (0x1<<0) // This bit masks, when set, the Interrupt bit: D…
37315 … (0x1<<0) // This bit masks, when set, the Parity bit: DB…
37322 …when DBG_REGISTERS_DEBUG_TARGET =1 (NIG) and DBG_REGISTERS_FULL_MODE =0 (one-shot); WB Read Only (…
37324 … 0x010418UL //Access:R DataWidth:0x1 // Debug only: This bit indicates wheter th…
37325 … 0x01041cUL //Access:R DataWidth:0x1 // Debug only: This bit indicates wheter i…
37326 … 0x010420UL //Access:R DataWidth:0x1 // Debug only: This bit indicates that the …
37327 … 0x010424UL //Access:R DataWidth:0x1 // Debug only: This bit indicates that the …
37328 … 0x010428UL //Access:R DataWidth:0x1 // Debug only: This bit indicates that the …
37329 … 0x01042cUL //Access:R DataWidth:0x1 // Debug only: This bit indicates that the …
37333 …rget_packet_size data byte each); Relevant only when debug_target=1 (NIG) & full_mode=0 (one-shot).
37335 … 0x010444UL //Access:RW DataWidth:0x5 // Debug only: This bit is a handle given t…
37337 … 0x01044cUL //Access:RW DataWidth:0x1 // Debug only: This bit indicate the frame …
37339 …Access:RW DataWidth:0x1 // Debug only: This bit enables the operation of the debug block; Thi…
37340 …bit indicate whether grant will be issued by the dbg block towards the storms in case the internal…
37341 …bit free lines in the internal buffer under which the full would go high; not applicable when DBG_…
37342 …x1 // Debug only: This bit indicates logical/physical address in PCI request as follows: (a) …
37343 … to internal buffer to be output to IFMUX interface. 0 - bits[31:0] 1 - bits[63:32] 2:6 - etc. 7 -…
37344 …h:0x9 // Debug only: together with DBG_REG_BUFFER_THR provides histerezis-like mechanism to set…
37345 …on is done as follows: bits 255:0 - data; bits 263:256 - frame; bits 271:264 - valid; bits 303:272…
37349 …bit vector that refers to the DBG_REGISTERS_EXPECTED_PATTERN vector as follows: (a) 1 - bit is ma…
37351 …nition usage: This bit indicates whether the pattern recognition feature is disabled/enabled as fo…
37352 …bit indicates the trigger behavior of the pattern recognition feature as follows: (a) 1 - stop de…
37353 …bit indicates whether data is continously stored in the dbg block until/from pattern recognition i…
37354 … // (a) 0 - trigger machine is off (all data will bypass the triggering machine); dbg_sem_trgr_…
37355 …010550UL //Access:RW DataWidth:0x1 // (a) 0 - triggering interleaved messages is disabled. (b…
37356 …only bits[2:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what STORM should …
37357 …only bits[2:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what STORM should …
37358 …only bits[2:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what STORM should …
37359 …//Access:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant…
37360 …//Access:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant…
37361 …//Access:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant…
37374 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37375 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37376 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37377 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37378 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37379 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37380 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37381 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37382 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37383 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37384 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37385 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37386 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37387 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37388 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37389 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37390 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37391 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37392 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37393 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37394 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37395 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37396 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37397 …that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger_state_set_c…
37398 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37399 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37400 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37401 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37402 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37403 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37404 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37405 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37406 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37407 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37408 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37409 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37410 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37411 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37412 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37413 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37414 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37415 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37416 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37417 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37418 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37419 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37420 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37421 …/Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 bit vector is determine…
37422 … 0x01065cUL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37423 … 0x010660UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37424 … 0x010664UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37425 … 0x010668UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37426 … 0x01066cUL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37427 … 0x010670UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37428 … 0x010674UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37429 … 0x010678UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37430 … 0x01067cUL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37431 … 0x010680UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37432 … 0x010684UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37433 … 0x010688UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37434 … 0x01068cUL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37435 … 0x010690UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37436 … 0x010694UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37437 … 0x010698UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37438 … 0x01069cUL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37439 … 0x0106a0UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37440 … 0x0106a4UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37441 … 0x0106a8UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37442 … 0x0106acUL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37443 … 0x0106b0UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37444 … 0x0106b4UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37445 … 0x0106b8UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37446 … 0x0106bcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37447 … 0x0106c0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37448 … 0x0106c4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37449 … 0x0106c8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37450 … 0x0106ccUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37451 … 0x0106d0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37452 … 0x0106d4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37453 … 0x0106d8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37454 … 0x0106dcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37455 … 0x0106e0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37456 … 0x0106e4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37457 … 0x0106e8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37458 … 0x0106ecUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37459 … 0x0106f0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37460 … 0x0106f4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37461 … 0x0106f8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37462 … 0x0106fcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37463 … 0x010700UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37464 … 0x010704UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37465 … 0x010708UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37466 … 0x01070cUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37467 … 0x010710UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37468 … 0x010714UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37469 … 0x010718UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37470 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37471 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37472 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37473 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37474 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37475 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37476 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37477 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37478 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37479 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37480 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37481 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37482 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37483 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37484 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37485 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37486 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37487 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37488 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37489 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37490 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37491 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37492 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37493 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37495 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37497 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37500 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37502 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37505 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37507 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37510 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37512 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37515 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37517 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37520 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37522 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37525 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37527 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37530 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37532 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37535 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37537 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37540 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37542 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37545 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37547 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37550 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37552 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37555 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37557 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37560 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37562 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37565 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37567 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37570 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37572 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37575 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37577 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37580 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37582 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37585 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37587 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37590 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37592 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37595 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37597 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37600 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37602 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37605 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37607 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37610 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37612 …e_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_c…
37614 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37615 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37616 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37617 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37618 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37619 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37620 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37621 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37622 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37623 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37624 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37625 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37626 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37627 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37628 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37629 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37630 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37631 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37632 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37633 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37634 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37635 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37636 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37637 …rigger_state_set_cnstr_offseti[11:3] cycles after start of message on data[32*(trigger_state_set_c…
37686 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37687 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37688 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37689 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37690 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37691 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37692 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37693 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37694 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37695 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37696 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37697 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37698 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37699 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37700 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37701 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37702 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37703 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37704 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37705 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37706 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37707 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37708 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37709 … or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37713 …0x010968UL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cycl…
37714 …0x01096cUL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cycl…
37715 …0x010970UL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cycl…
37718 …-1:32*trigger_indirect0_offseti[2:0]] in cycle trigger_indirect0_offseti[11:3] from the last messa…
37719 …-1:32*trigger_indirect0_offseti[2:0]] in cycle trigger_indirect0_offseti[11:3] from the last messa…
37720 …-1:32*trigger_indirect0_offseti[2:0]] in cycle trigger_indirect0_offseti[11:3] from the last messa…
37721 … 0x010988UL //Access:RW DataWidth:0x5 // Shift vector (bit resolution) for the…
37722 … 0x01098cUL //Access:RW DataWidth:0x5 // Shift vector (bit resolution) for the…
37723 … 0x010990UL //Access:RW DataWidth:0x5 // Shift vector (bit resolution) for the…
37724 …bit will be zeroed; if clear then the relevant bit will be registered with its exact data. NOTE: (…
37725 …bit will be zeroed; if clear then the relevant bit will be registered with its exact data. NOTE: (…
37726 …bit will be zeroed; if clear then the relevant bit will be registered with its exact data. NOTE: (…
37729 …-1:32*trigger_indirect1_offseti[2:0]] in cycle trigger_indirect1_offseti[11:3] from the last messa…
37730 …-1:32*trigger_indirect1_offseti[2:0]] in cycle trigger_indirect1_offseti[11:3] from the last messa…
37731 …-1:32*trigger_indirect1_offseti[2:0]] in cycle trigger_indirect1_offseti[11:3] from the last messa…
37732 … 0x0109b4UL //Access:RW DataWidth:0x5 // Shift vector (bit resolution) for the…
37733 … 0x0109b8UL //Access:RW DataWidth:0x5 // Shift vector (bit resolution) for the…
37734 … 0x0109bcUL //Access:RW DataWidth:0x5 // Shift vector (bit resolution) for the…
37735 …bit will be zeroed; if clear then the relevant bit will be registered with its exact data. NOTE: …
37736 …bit will be zeroed; if clear then the relevant bit will be registered with its exact data. NOTE: …
37737 …bit will be zeroed; if clear then the relevant bit will be registered with its exact data. NOTE: …
37739 …- Filter off; in that case all data should be transmitted to the internal buffer without any filte…
37740 …only bits[2:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what STORM should …
37741 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37742 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37743 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37744 …he value that need to be compared with data[32*(filter_cnstr_offseti[2:0]+1)-1:32*filter_cnstr_off…
37749 … 0x0109f8UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37750 … 0x0109fcUL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37751 … 0x010a00UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37752 … 0x010a04UL //Access:RW DataWidth:0x20 // If specific bit is 1 then the matched bit in the…
37753 … 0x010a08UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37754 … 0x010a0cUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37755 … 0x010a10UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37756 … 0x010a14UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37757 …ove value vector (data and frame) should be compared filter_cnstr_offseti[4:3] cycles after start …
37758 …ove value vector (data and frame) should be compared filter_cnstr_offseti[4:3] cycles after start …
37759 …ove value vector (data and frame) should be compared filter_cnstr_offseti[4:3] cycles after start …
37760 …ove value vector (data and frame) should be compared filter_cnstr_offseti[4:3] cycles after start …
37761 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37762 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37763 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37764 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37766 …ilter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_…
37768 …ilter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_…
37771 …ilter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_…
37773 …ilter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_…
37776 …ilter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_…
37778 …ilter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_…
37781 …ilter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_…
37783 …ilter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_…
37793 …0 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37794 …0 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37795 …0 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37796 …0 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b i…
37797 … use filter_msg_length to determine message boundary. (b) 0: use the frame bit to determine messag…
37798 …0x010a7cUL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cycl…
37800 …ess:RW DataWidth:0x8 // The message length-1 of the recorded part size in terms of numbers of…
37801 …nt: (a) 00 - record from time=0; (b) 01 - record rcrd_on_window_pre_num_chunks chunks to internal…
37802 … (a) 0- enable recording data upon triggering event; in that case record for rcrd_on_window_post_…
37803 …bit each within the internal buffer) that should be recorded to the internal buffer prior to trigg…
37805 … 0x010a98UL //Access:RW DataWidth:0x10 // 16-bit opaque FID for pci …
37815 …UL //Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_…
37816 …UL //Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_…
37817 …UL //Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_…
37818 …UL //Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_…
37819 …UL //Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_…
37820 …UL //Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_…
37821 …UL //Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_…
37822 …UL //Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_…
37823 …UL //Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_…
37824 …UL //Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_…
37825 …- bits[31:0]; [5:3] - bits[63:32]; [8:6] - bits[95:64]; [11:9] - bits[127:96]; [14:12] - bits…
37826 …ll be added to trailer when STORM will be selected: B2:0 - TSEM; B5:3- MSEM; B8:6- USEM; B11:9- XS…
37835 …0x4 // Ethernet header width: 0 - 14 MSB bytes; 1- 16 MSB bytes; .. ; 8 - 30 MSB bytes; 9 -32 M…
37836 … in granularity of chunks. The allowed range is 1-48 that suits to packet size of 256B-12KB. Value…
37842 …bit[0] is set and frame[1] is set or bit[1] is set and frame[2] is set or bit[2] is set and frame[…
37843 …bit[0] is set and valid[1] is set or bit[1] is set and valid[2] is set or bit[2] is set and valid[…
37844 …tput from DBG to SEM block as result of trigger event: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is …
37845 …ger block in dbg_trigger.v: states 0-2 are functional state (comparsion is implemented on the cons…
37846 …ock in dbg_trigger_state.v: : state 0 - NOT_HNDLR_MSG; state 1- FRST_HNDLR_MSG; state 2- SCND_HNDL…
37849 …- constraint 0 set0; B1 - constraint 1 set0; B2 - constraint 2 set0; B3 - constraint 3 set0; B4 - …
37851 …taWidth:0x20 // Debug only: These bits represent the total number of 128-bit cycles sent from th…
37855 … status in trailer block : 0 - WAIT_FOR_NEW_LINE; 1- END_OF_CHUNK; 2 - SEND_ADDITIONAL_CHUNK; 3 - …
37857 …Statistics. Match constraint status. B0 - constraint 0; B1 - constraint 1; B2 - constraint 2 ; B3 …
37863 …1 // When set to 0 - only client which HW ID is defined in DBG_REGISTERS_FILTER_ID_NUM.FILTER_I…
37864 …ccess:RW DataWidth:0x1 // When 0 - SEMI core A is selected for all trigger/filter related act…
37873 …bit will execute the OTP "command" in the next field. This bit should be set to Low and high agai…
37876 …bit is used to sample READ data in burst mode; [1]: cmd_done: Command Done, This signal indicates …
37878 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37887 … XCORE_BIAS in normal operation is controlled by straps on the board. This bit allows it SW to ove…
37888 … 0x02021cUL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf s…
37893 … // HIPASS in normal operation is controlled by straps on the board. This bit allows it SW to ove…
37907 … 0x020234UL //Access:RW DataWidth:0x4 // [3:2] LDO Output Stage …
37908 … 0x020238UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): ref…
37909 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37911 … 0x02023cUL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3): refer to…
37913 …ED 1=CMOS output ENABLED Bit[0] = o_xtal_ck0 Bit[1] = o_xtal_ck1 Bit[2] = o_xtal_ck2 Bit[3] = o_xt…
37916 …n 0=CML output ON 1=CML output OFF Bit[0] = o_cml_p/n 0 Bit[1] = o_cml_p/n 1 Bit[2] = o_cml_p/n 2 …
37921 …<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of the register.
37928 …/ 1 : Override the init state machine and control the PLL logic reset using bit[0] of the register.
37940 …x1 // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Glo…
37946 …<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of the register.
37953 …<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of the register.
37957 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
37960 …-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= di…
37965 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37966 …/Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 00000000: 256 00000001: 1 000000…
37967 … 0x020268UL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf s…
37968 …/Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 00000000: 256 00000001: 1 000000…
37970 …/Access:RW DataWidth:0x8 // Post-divider ratio for channel-2 00000000: 256 00000001: 1 000000…
37973 …/Access:RW DataWidth:0x8 // Post-divider ratio for channel-3 00000000: 256 00000001: 1 000000…
37976 …/Access:RW DataWidth:0x8 // Post-divider ratio for channel-4 00000000: 256 00000001: 1 000000…
37979 …/Access:RW DataWidth:0x8 // Post-divider ratio for channel-5 00000000: 256 00000001: 1 000000…
37985 …80UL //Access:RW DataWidth:0x10 // Number to VCO clock to delay Channel 3 Global register. Res…
37986 … 0x020284UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): ref…
37988 … 0x020288UL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3): refer to…
37991 … 0x02028cUL //Access:R DataWidth:0x4 // Delay for each channel 2-5 is completed.
37995 …<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of the register.
38001 …/ 1 : Override the init state machine and control the PLL logic reset using bit[0] of the register.
38003 …3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO l…
38006 …3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO l…
38012 …3, Write 5 For 4, Write 2 For 5, Write 3 For 6, Write 6 For 7, Write 7 For 8, Write 8 For 9, Write…
38018 …x1 // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Glo…
38019 … 0x0202b4UL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf s…
38024 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38026 …-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= di…
38030 …/Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 00000000: 256 00000001: 1 000000…
38032 …/Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 00000000: 256 00000001: 1 000000…
38033 … 0x0202d0UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): ref…
38035 … 0x0202d4UL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3): refer to…
38036 …3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO l…
38038 …3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO l…
38044 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38045 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38046 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38047 …3, Write 5 For 4, Write 2 For 5, Write 3 For 6, Write 6 For 7, Write 7 For 8, Write 8 For 9, Write…
38048 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38049 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38050 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38052 …-> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the…
38053 …-> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the…
38054 …-> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the…
38058 …x1 // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Glo…
38062 … // Setting this bit high will result in the HW to capture the frequency of Main, STORM and NW …
38063 … // Setting this bit high will result in the HW to capture the frequency of Main, STORM and NWM …
38064 … // Setting this bit high will result in the HW to capture the frequency of Main, STORM and NWM …
38069 …or example, it shows X MHz in first measurement, 2*X in second measurement, 3*X MHz in third measu…
38073 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38077 …or example, it shows X MHz in first measurement, 2*X in second measurement, 3*X MHz in third measu…
38084 …or example, it shows X MHz in first measurement, 2*X in second measurement, 3*X MHz in third measu…
38088 … 0x020304UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 000000…
38089 … 0x0204b4UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38090 … 0x0202a8UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38091 … 0x020308UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38092 … 0x020308UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 000000…
38093 … 0x0204b8UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38094 … 0x0202acUL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38095 … 0x02030cUL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38097 … 0x0204bcUL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38098 … 0x0202b0UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38099 … 0x020310UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38100 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38101 … 0x0204c0UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38102 … 0x0202b4UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38103 … 0x020314UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38104 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38105 … 0x0204c4UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38106 … 0x0202b8UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38107 … 0x020318UL //Access:R DataWidth:0x20 // This is a 32-bit free running counte…
38108 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38109 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38110 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38111 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38117 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38118 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38119 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38120 … 0x020324UL //Access:RW DataWidth:0x4 // Control of the non-zero pole in the PLL …
38121 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38122 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38123 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38129 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38130 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38131 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38132 …x1 // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Glo…
38133 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38134 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38135 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38150 … (0x1<<4) // This bit generates an interr…
38152 … (0x1<<5) // This bit generates an interrupt when VMAIN POR is d…
38154 … (0x1<<6) // This bit generates an interr…
38156 … (0x1<<7) // This bit generates an interrupt when PERST# is de…
38158 … (0x1<<8) // This bit generates an interr…
38160 … (0x1<<9) // This bit generates an interr…
38162 … (0x1<<10) // This bit generates an interr…
38164 … (0x1<<11) // This bit generates an interrupt when Fdone Double Error Detection sta…
38166 … (0x1<<12) // This bit generates an interr…
38168 … (0x1<<13) // This bit generates an interr…
38170 … (0x1<<14) // This bit generates an interr…
38172 … (0x1<<15) // This bit generates an interr…
38174 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38178 … (0x1<<0) // This bit masks, when set, the Interrupt bit: I…
38180 … (0x1<<4) // This bit masks, when set, the Interrupt bit: I…
38182 … (0x1<<5) // This bit masks, when set, the Interrupt bit: I…
38184 … (0x1<<6) // This bit masks, when set, the Interrupt bit: I…
38186 … (0x1<<7) // This bit masks, when set, the Interrupt bit: I…
38188 … (0x1<<8) // This bit masks, when set, the Interrupt bit: I…
38190 … (0x1<<9) // This bit masks, when set, the Interrupt bit: I…
38192 … (0x1<<10) // This bit masks, when set, the Interrupt bit: I…
38194 … (0x1<<11) // This bit masks, when set, the Interrupt bit: I…
38196 … (0x1<<12) // This bit masks, when set, the Interrupt bit: I…
38198 … (0x1<<13) // This bit masks, when set, the Interrupt bit: I…
38200 … (0x1<<14) // This bit masks, when set, the Interrupt bit: I…
38202 … (0x1<<15) // This bit masks, when set, the Interrupt bit: I…
38210 … (0x1<<4) // This bit generates an interr…
38212 … (0x1<<5) // This bit generates an interrupt when VMAIN POR is d…
38214 … (0x1<<6) // This bit generates an interr…
38216 … (0x1<<7) // This bit generates an interrupt when PERST# is de…
38218 … (0x1<<8) // This bit generates an interr…
38220 … (0x1<<9) // This bit generates an interr…
38222 … (0x1<<10) // This bit generates an interr…
38224 … (0x1<<11) // This bit generates an interrupt when Fdone Double Error Detection sta…
38226 … (0x1<<12) // This bit generates an interr…
38228 … (0x1<<13) // This bit generates an interr…
38230 … (0x1<<14) // This bit generates an interr…
38232 … (0x1<<15) // This bit generates an interr…
38234 … 0x020344UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 000000…
38240 … (0x1<<4) // This bit generates an interr…
38242 … (0x1<<5) // This bit generates an interrupt when VMAIN POR is d…
38244 … (0x1<<6) // This bit generates an interr…
38246 … (0x1<<7) // This bit generates an interrupt when PERST# is de…
38248 … (0x1<<8) // This bit generates an interr…
38250 … (0x1<<9) // This bit generates an interr…
38252 … (0x1<<10) // This bit generates an interr…
38254 … (0x1<<11) // This bit generates an interrupt when Fdone Double Error Detection sta…
38256 … (0x1<<12) // This bit generates an interr…
38258 … (0x1<<13) // This bit generates an interr…
38260 … (0x1<<14) // This bit generates an interr…
38262 … (0x1<<15) // This bit generates an interr…
38264 … 0x020348UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 000000…
38268 …-bit compliance enable pins on the ballout. These bits are used to override the pins if needed. 2'…
38270 … (0x1<<4) // Set this bit to override the pin…
38273 …ss:RW DataWidth:0x1 // 0 - control of the tcam bist is from the IPC register tcam_bist_contro…
38274 …ss:RW DataWidth:0x1 // 0 - control of the tcam bist is from the IPC register tcam_bist_contro…
38275 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38276 …ing the status of the cam in tcam_bist_status 0 ccfc_ccam 1 ccfc_scam 2 igu 3 msem 4 prs_gft 5 prs…
38277 …ing the status of the cam in tcam_bist_status 0 ccfc_ccam 1 ccfc_scam 2 igu 3 msem 4 prs_gft 5 prs…
38278 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38279 … tcam bist status bus bit 0 - bist_pass bit 1 - bist_failed bit 2 - bist_paused bit 3 - reserved(b…
38280 … tcam bist status bus bit 0 - bist_pass bit 1 - bist_failed bit 2 - bist_paused bit 3 - reserved(b…
38281 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38282 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38283 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38285 …bit 0 - bist_run bit 1 - retention_en bit 3 - reserved(connected the bist_shi,should be zero) bit …
38286 …bit 0 - bist_run bit 1 - retention_en bit 3 - reserved(connected the bist_shi,should be zero) bit …
38288 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38289 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38290 … 0x020364UL //Access:RW DataWidth:0x4 // Control of the non-zero pole in the PLL …
38291 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38292 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38294 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38295 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38297 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38298 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38300 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38301 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38303 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38304 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38306 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38307 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38309 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38310 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38312 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38313 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38315 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38316 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38318 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38319 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38321 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38322 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38324 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38325 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38327 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38328 …bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,…
38329 … 0x020398UL //Access:R DataWidth:0x1 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38330 …ue. this value is output at ipc_clkdec_clk_dft_ms_125m_div 0 - no division 1- divide by 2 2- divid…
38331 …ue. this value is output at ipc_clkdec_clk_dft_ms_125m_div 0 - no division 1- divide by 2 2- divid…
38332 … 0x02039cUL //Access:R DataWidth:0x4 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38362 … 0x0203c4UL //Access:R DataWidth:0x1 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38363 …ess:RW DataWidth:0x6 // Sets the CTL# (# in [0..5]) I/Os of the PADS in non - scan/mbist modes
38365 … 0x0203c8UL //Access:R DataWidth:0x4 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38366 …cess:RW DataWidth:0x2 // Sets the SL# (# in [0..1]) I/Os of the PADS in non - scan/mbist modes
38368 … 0x0203ccUL //Access:R DataWidth:0x8 // PCIe lock signals. 0-unlocked; 1-locked. Global …
38372 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
38373 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
38394 …_BB (0x1<<2) // 1: Bit Alignment Done Glob…
38396 …NC_STATUS_BB (0x1<<3) // 1: Symbol Alignm…
38397 …PC_REG_SGMII_STATUS_SGMII_SYNC_STATUS_BB_SHIFT 3
38414 …//Access:RW DataWidth:0x1 // Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the…
38422 …//Access:RW DataWidth:0x1 // Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the…
38424 …cal 0: Normal Operation Mode 1: Powerdown the RESCAL block Transition from 1->0 to start calibrati…
38426 … 0x020424UL //Access:RW DataWidth:0x1 // By Setting this bit, FW takes control o…
38427 … 0x020428UL //Access:RW DataWidth:0x1 // Setting this bit starts the HW based…
38429 …-up time before starting calibration 2'b00: 32 refclk = 1.28us 2'b01: 128 refclk = 5.12us 2'b10: 2…
38435 …-chip Sheet Resistance 0000 -24% ~ -21% 0001 -21% ~ -18% 0010 -18% ~ -15% 0011 -15% ~ -12% 0100 -1…
38440 …h:0x3 // Internal State machine status 0: INIT 1: WAIT_PWRUP 2: COMP_ACC 3: WAIT_PON_INC 4: CAL…
38441 … DataWidth:0x3 // External State machine status 0: POR 1: INIT 2: RESET 3: PWRDN 4: CALIB 5: P…
38455 … 0x020488UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will enable …
38456 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38457 …-> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the…
38458 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38460 …or example, it shows X MHz in first measurement, 2*X in second measurement, 3*X MHz in third measu…
38464 … 0x0204e8UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38465 … 0x0204ecUL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38466 … 0x0204f0UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38467 … 0x0204f4UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38468 … 0x0204f8UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38469 … 0x0204fcUL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38470 … 0x020500UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38471 … 0x020504UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38473 … (0x1<<0) // This bit masks, when set, the Parity bit: IP…
38478 … If Single Error Correction status flag was 1, this bit is latched with val…
38481 … 0x030204UL //Access:RW DataWidth:0x1 // Setting this bit will enable a speci…
38491 …I_MGMT_EMPTY_EN (0x1<<3) // 0 : Management T…
38492 …PMU_REG_LPI_MODE_ENTRY_EN_LPI_MGMT_EMPTY_EN_SHIFT 3
38508 …MOST_FULL_EN (0x1<<3) // This bit will be used i…
38509 …PMU_REG_LPI_MODE_EXIT_EN_LPI_PBF_ALMOST_FULL_EN_SHIFT 3
38510 …FULL_EN (0x1<<4) // This bit will be used in the…
38512 …IT_EN (0x1<<5) // This bit will be used in the…
38516 …taWidth:0x1 // Setting this bit to "1" will allow software to force an LPI request on the inter…
38517 …bit to "1" will allow software to provide an early indication to exit LPI state. HW will generate …
38524 … (0x1<<2) // Setting this bit forces the CPMU to …
38526 …FF_IGU_PENDING_INTERRUPT_EN (0x1<<3) // 0 : IGU Pending …
38527 …PMU_REG_OBFF_MODE_CONTROL_OBFF_IGU_PENDING_INTERRUPT_EN_SHIFT 3
38538 …bit to "1" will allow software to force an exit from the OBFF related stalls. HW will generate a p…
38543 … bit in this register to "1" will cause the CPMU to launch a timer when the corresponding VOQ is n…
38544 … bit in this register to "1" will cause the CPMU to launch a timer when the corresponding VOQ is n…
38545 … bit in this register to "1" will cause the CPMU to launch a timer when the corresponding VOQ is n…
38546 … bit in this register to "1" will cause the CPMU to launch a timer when the corresponding VOQ is n…
38555 …BFF_ALL_SQ_EMPTY_EN (0x1<<3) // 0 : All Send Que…
38556 …PMU_REG_OBFF_MODE_ENTRY_EN_OBFF_ALL_SQ_EMPTY_EN_SHIFT 3
38596 …EXIT_EN (0x1<<2) // This bit will be used in the…
38610 …ALL_SQ_EMPTY_EN (0x1<<3) // 0 : All Send Que…
38611 …PMU_REG_L1_MODE_ENTRY_EN_L1_ALL_SQ_EMPTY_EN_SHIFT 3
38629 …_EN (0x1<<1) // This bit will be used in the…
38631 …ataWidth:0x1 // Setting this bit to "1" will allow software to force an L1 request on the inter…
38632 …bit to "1" will allow software to provide an early indication to exit L1 state. HW will generate a…
38642 …R_ALL_SQ_EMPTY_EN (0x1<<3) // 0 : All Send Que…
38643 …PMU_REG_LTR_MODE_ENTRY_EN_LTR_ALL_SQ_EMPTY_EN_SHIFT 3
38665 …IT_EN (0x1<<1) // This bit will be used in the…
38667 …taWidth:0x1 // Setting this bit to "1" will allow software to force an LTR request on the inter…
38668 …bit to "1" will allow software to provide an early indication to exit LTR state. HW will generate …
38676 …LK_NM_E1_EN (0x1<<3) // 0 : Shutdown Mai…
38677 …PMU_REG_CLK_EN_CONFIG_MAIN_CLK_NM_E1_EN_SHIFT 3
38727 …WN_PCI_CLK_EN (0x1<<3) // 0 : Slowdown of …
38728 …PMU_REG_CLK_PM_CONFIG_SLOWDOWN_PCI_CLK_EN_SHIFT 3
38751 …TRY_EN_MCS_ALL_SQ_EMPTY_EN (0x1<<3) // 0 : All Send Que…
38752 …PMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_ALL_SQ_EMPTY_EN_SHIFT 3
38796 … 0x0302c8UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will allow s…
38797 … 0x0302ccUL //Access:W DataWidth:0x1 // Setting this bit to "1" will allow s…
38805 …NTRY_EN_SCS_ALL_SQ_EMPTY_EN (0x1<<3) // 0 : All Send Que…
38806 …PMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_ALL_SQ_EMPTY_EN_SHIFT 3
38850 … 0x0302d8UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will allow s…
38851 … 0x0302dcUL //Access:W DataWidth:0x1 // Setting this bit to "1" will allow s…
38859 …Y_EN_NCS_ALL_SQ_EMPTY_EN (0x1<<3) // 0 : All Send Que…
38860 …PMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_ALL_SQ_EMPTY_EN_SHIFT 3
38904 … 0x0302e8UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will allow s…
38905 … 0x0302ecUL //Access:W DataWidth:0x1 // Setting this bit to "1" will allow s…
38913 …RY_EN_PCS_ALL_SQ_EMPTY_EN (0x1<<3) // 0 : All Send Que…
38914 …PMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_ALL_SQ_EMPTY_EN_SHIFT 3
38958 … 0x0302f8UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will allow s…
38959 … 0x0302fcUL //Access:W DataWidth:0x1 // Setting this bit to "1" will allow s…
39012 …S_1_DORQ_TX_WAKEUP_E0_ISIG_STATUS (0x3<<3) // Current status o…
39013 …PMU_REG_CPMU_INPUT_SIG_STATUS_1_DORQ_TX_WAKEUP_E0_ISIG_STATUS_SHIFT 3
39108 …S_3_YSEM_SEM_IDLE_E0_ISIG_STATUS (0x1<<3) // Current status o…
39109 …PMU_REG_CPMU_INPUT_SIG_STATUS_3_YSEM_SEM_IDLE_E0_ISIG_STATUS_SHIFT 3
39145 …US_CNIG_LPI_REQ_P1_E1_OSIG_STATUS (0x1<<3) // Current status o…
39146 …PMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P1_E1_OSIG_STATUS_SHIFT 3
39236 … (0x1<<0) // This bit masks, when set, the Interrupt bit: C…
39249 … 0x030404UL //Access:R DataWidth:0x20 // SDM SQ counter value for Engine 0, port 3.
39251 … (0x1<<0) // This bit masks, when set, the Parity bit: NC…
39253 … (0x1<<1) // This bit masks, when set, the Parity bit: NC…
39255 … (0x1<<2) // This bit masks, when set, the Parity bit: NC…
39259 … (0x1<<0) // Setting this bit to a '1' will resul…
39261 … (0x1<<1) // Setting this bit to a '1' will resul…
39263 … (0x1<<2) // 0 -> Send all broadcast packets to the appropriate networ…
39265 … (0x1<<3) // 0 -> Send all multicast packets to the appropriate ne…
39266 …CSI_REG_CONFIG_FWD_MCAST_TO_MCP_SHIFT 3
39267 … (0x1<<4) // 0 -> only MAC address is used for comparison to detect Host2B…
39269 … (0x1<<5) // 0 -> Do not enable source MAC address learning for packets from…
39271 … (0x1<<6) // 0 -> Entries in SA Learning Cache are valid even after they…
39273 … (0x1<<7) // Setting this bit to a '1' will resul…
39275 … (0x1<<8) // Setting this bit to a '1' will resul…
39277 … (0x1<<9) // Setting this bit to a '1' tells the …
39279 … (0x1<<10) // 0 -> Select NCSI RMII interface as the MII port …
39281 … (0x1<<11) // 0 -> Select NCSI RMII interface as the Management Po…
39283 … (0x1<<12) // 1 -> When BMB asserts any full condition, drop all the p…
39285 … (0x1<<13) // 1 -> When this bit is set, all pass through traffic will be directed to hos…
39287 … 0x040204UL //Access:RW DataWidth:0x1 // When set, this bit indicates that the …
39289 …bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' ind…
39290 …bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' ind…
39291 …bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' ind…
39292 …bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' ind…
39305 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39306 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39307 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39308 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39309 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39310 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39311 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39312 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39313 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39314 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39315 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39316 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39317 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39318 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39319 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39320 …bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. …
39369 …bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware s…
39370 …bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replac…
39371 …bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware s…
39372 …bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replac…
39373 …bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware s…
39374 …bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replac…
39375 …bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware s…
39376 …bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replac…
39377 …bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware s…
39378 …bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replac…
39379 …bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware s…
39380 …bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replac…
39381 …bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware s…
39382 …bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replac…
39383 …bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware s…
39384 …bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replac…
39401 …ly 0 or 1. The only reliable value is 1. If the value is 0, the channel could have been 0, 2 or 3.
39402 …ly 0 or 1. The only reliable value is 1. If the value is 0, the channel could have been 0, 2 or 3.
39403 …ly 0 or 1. The only reliable value is 1. If the value is 0, the channel could have been 0, 2 or 3.
39404 …ly 0 or 1. The only reliable value is 1. If the value is 0, the channel could have been 0, 2 or 3.
39405 …ly 0 or 1. The only reliable value is 1. If the value is 0, the channel could have been 0, 2 or 3.
39406 …ly 0 or 1. The only reliable value is 1. If the value is 0, the channel could have been 0, 2 or 3.
39407 …ly 0 or 1. The only reliable value is 1. If the value is 0, the channel could have been 0, 2 or 3.
39408 …ly 0 or 1. The only reliable value is 1. If the value is 0, the channel could have been 0, 2 or 3.
39418 … 0x040410UL //Access:RW DataWidth:0x1 // When this bit is set, all the ent…
39420 … (0x1<<0) // Setting this bit to "1" will result …
39422 …-to six TAGs present in a packet. This field sets which of the TAGs need to be removed. This field…
39424 …-> Use the configuration bit associated with the Inner VLAN tag to decide whether to remove the ta…
39426 …from the packet before sending it out to BMC. it is expected that once a non-zero value is set, al…
39430 …L //Access:RW DataWidth:0x3 // The length of the info field for L2 tag 3. The length is betw…
39438 …criptor for a BMC to Network packet if there is a VLAN header in the packet and VLAN ID is non-zero
39440 …_INNER_VLAN_IF_NO_VLAN (0x1<<3) // Tells HW to set …
39441 …CSI_REG_TAG_INS_CONFIG_FORCE_INNER_VLAN_IF_NO_VLAN_SHIFT 3
39447 …ARB_UNUSED0 (0x1<<3) // Unused
39448 …CSI_REG_SIDEBAND_ARB_UNUSED0_SHIFT 3
39449 …s field to '1' causes the hardware arbitration scheme to be disabled. This bit should be set when …
39451 …to '1' causes the hardware arbitration scheme to begin. Any NCSI port can re-start the arbitration.
39453 …rmware running to be automatically bypassed. Firmware should also set this bit when there is nothi…
39457 … (0x1f<<8) // This field is a programmable inter-packet gap for when t…
39461 … (0x1<<14) // Setting this bit disables the featur…
39463 … (0x1<<15) // Toggle this bit to update this regi…
39465 …mber of Ingress clock cycles that the arbitration master will wait before re-starting the arbitrat…
39467 … 0x04043cUL //Access:R DataWidth:0x1 // This bit indicates if the ar…
39470 … (0x1<<0) // Setting this bit will create an asyc…
39472 … (0x1<<1) // Setting this bit will create an asyc…
39484 …started. Setting a value of all 1s in this register will guarantee a store-and-forward operation. …
39486 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
39487 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
39488 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
39489 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
39499 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
39509 …e, If = 0 it is read. Bits [27:24]: Master. The decoding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 …
39510 …3:0]: PF. Bits [11:4]: VF. Bit [13:12]: Port. Bits [15:14]: Privilege. The decoding: 0 - VN: Virt…
39511 …t latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
39512 …bytes resolution). Bit [23]: Wr/rd. If = 1 it is write, if = 0 it is read. Bits [27:24]: Maste…
39513 …3:0]: PF. Bits [11:4]: VF. Bit [13:12]: Port. Bits [15:14]: Privilege. The decoding: 0 - VN: Virt…
39514 …t latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
39515 …bytes resolution). Bit [23]: Wr/rd. If = 1 it is write, if = 0 it is read. Bits [27:24]: Maste…
39516 …3:0]: PF. Bits [11:4]: VF. Bit [13:12]: Port. Bits [15:14]: Privilege. The decoding: 0 - VN: Virt…
39517 …t latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
39519 …Bit [37:36]: Port. Bits [39:38]: Privilege. The decoding: 0 - VN: Virtualized NIC (Used for VF ac…
39522 … fields: Bit [0]: pxp. Bit [1]: mcp. Bit [2]: msdm. Bit [3]: psdm. Bit [4]: ysdm. Bit [5]: usdm Bi…
39523 …Bit [0]: no error. Bit [1]: timeout event. Bit [2]: GRC reserved address. Reserved address that is…
39524 …ess is masked, wr/rd access is not written to the trace FIFO. The fields: Bit [0]: wr. Bit [1]: rd.
39525 …-7 are applicable. The fields: Bit [0]: PF #0. Bit [1]: PF #1. Bit [2]: PF #2. Bit [3]:…
39527 …L = 1. Value of all 1s is applicable and represents VF not valid. BB: only bits 0-6 are applicable.
39528 …IFO. BB: only bits 0-1 are applicable. The fields: Bit [0]: port #0. Bit [1]: port #1. …
39529 …ritten to the trace FIFO. The fields: Bit [0]: VN (0). Bit [1]: PDA (1). Bit [2]: HV (2…
39530 …Bit [0]: PRV_DEFAULT. Takes the default protection defined by RF block. Bit [1]: PRV_DEFAULT. Take…
39531 …lects for each address bit if this bit is enforced. The register GRC_REG_TRACE_FIFO_ADDRESS select…
39532 …lue for each address bit. The register GRC_REG_TRACE_FIFO_ADDRESS_SEL selects for each address bit…
39535 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
39536 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
39537 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
39538 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
39552 …ION_ERROR (0x1<<3) // Path Isolation e…
39553 …RC_REG_INT_STS_0_PATH_ISOLATION_ERROR_SHIFT 3
39557 … (0x1<<0) // This bit masks, when set, the Interrupt bit: G…
39559 … (0x1<<1) // This bit masks, when set, the Interrupt bit: G…
39561 … (0x1<<2) // This bit masks, when set, the Interrupt bit: G…
39563 … (0x1<<3) // This bit masks, when set, the Interrupt …
39564 …RC_REG_INT_MASK_0_PATH_ISOLATION_ERROR_SHIFT 3
39565 … (0x1<<4) // This bit masks, when set, the Interrupt bit: G…
39574 …LATION_ERROR (0x1<<3) // Path Isolation e…
39575 …RC_REG_INT_STS_WR_0_PATH_ISOLATION_ERROR_SHIFT 3
39585 …OLATION_ERROR (0x1<<3) // Path Isolation e…
39586 …RC_REG_INT_STS_CLR_0_PATH_ISOLATION_ERROR_SHIFT 3
39590 … (0x1<<0) // This bit masks, when set, the Parity bit: GR…
39592 … (0x1<<1) // This bit masks, when set, the Parity bit: GR…
39596 …his bit enables a timer in the GRC block to timeout any access that does not finish within GRC_REG…
39599 …alue of 0x1). Bit [47]: Rd access. If = 1, the window is applicable for rd access. If = 0, the wi…
39619 …<<2) // Set MAC speed. Ignored when the register bit ENA_EXT_CONFIG is set to '1'. When the Regist…
39623 …o reset value '0'); then no padding is removed on receive by the MAC. This bit has no effect on Tx…
39625 … '0') the CRC field is stripped from the frame. Note: If padding function (Bit PAD_EN set to '1') …
39637 … register bit is not operational (always set to 0). If cleared; disables RX FIFO overflow logic. I…
39639 …X are disabled. Config registers are not affected by sw reset. Write a 0 to de-assert the sw reset.
39667 …-of-band egress flow control is enabled. When this bit is set and input pin ext_tx_flow_control is…
39671 …L //Access:RW DataWidth:0x20 // Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refe…
39672 …Access:RW DataWidth:0x10 // Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1 …
39673 … 0x051014UL //Access:RW DataWidth:0x10 // Defines a 16-Bit maximum frame lengt…
39674 … 0x051018UL //Access:RW DataWidth:0x10 // 16-Bit value; sets; in increment of 512 Ethernet …
39675 …the length of the EFM preamble between 5 and 15 Bytes. When set to 0; 1; 2; 3 or 4; the Preamble E…
39677 … (0x1<<3) // Rx Flow. Setting this bit will cause the receive MAC control to detect and act on …
39678 …MAC_REG_MAC_MODE_PAUSE_RX_EN_K2_E5_SHIFT 3
39679 …w. Setting this bit will allow the transmit MAC control to send PAUSE flow control frames when req…
39685 …E_BB (0x1<<3) // MAC Pause Enable…
39686 …MAC_REG_MAC_MODE_MAC_RX_PAUSE_BB_SHIFT 3
39709 …G between Back-to-Back packets. This is the IPG parameter used exclusively in Full-Duplex mode whe…
39710 …dth:0x10 // Time value sent in the Timer Field for classes in XOFF state (Unit is 512 bit-times).
39712 …_BB (0x1<<3) // If set; the TX L…
39713 …MAC_REG_UMAC_EEE_CTRL_EEE_EN_BB_SHIFT 3
39718 … (0x1<<6) // When this bit is set and link is …
39722 …the end of which MAC transitions to LPI State. The decrement unit is 1 micro-second. This register…
39723 …the end of which MAC transitions to LPI State. The decrement unit is 1 micro-second. This register…
39724 …us. We may consider having 0.5us reference; as timeout values in 802.3az/D1.3 are not always integ…
39725 …eceives an IPG less than programmed RX IPG or less than four bytes. Sticky bit. Clears when SW wri…
39727 …tate when it receives packet for transmission. The decrement unit is 1 micro-second. This register…
39728 …tate when it receives packet for transmission. The decrement unit is 1 micro-second. This register…
39737 … (0x7f<<16) // Non Back-to-Back Transmit IPG pa…
39739 … (0x7f<<24) // Non Back-to-Back Transmit IPG pa…
39743 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
39744 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
39745 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
39746 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
39757 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
39759 … (0x1<<1) // This bit masks, when set, the Interrupt bit: U…
39782 … (0x1<<0) // Set the bit 0 (Tx_Launch_en) lo…
39786 …ruption feature in enabled (TX_CRC_CORUPT_EN set); then in case where this bit when set; replaces …
39788 …3) // When this bit is 1; IPG between pause and data frame is as per the original design; i.e.; 13…
39789 …MAC_REG_MACSEC_CNTRL_DIS_PAUSE_DATA_VAR_IPG_BB_SHIFT 3
39790 …:RW DataWidth:0x20 // This register contains the bits [31:0] in the 48-bit MAC address. The M…
39792 …L_BB (0x1<<0) // Read-only field assertion …
39794 …TY_BB (0x1<<1) // Read-only field assertion …
39798 …RW DataWidth:0x10 // This register contains the bits [47:32] in the 48-bit MAC address. The M…
39799 …orresponding to the preceding seq_id read from the transmit FIFO. Every 49 bit; val_bit + seq_id +…
39801 … frame with the Pause Time Field specified in rf_omac_pause_time. If this bit is cleared send a P…
39803 … frame with the Pause Time Field specified in rf_omac_pause_time. If this bit is cleared send a P…
39809 …riority Pause Frame. Each bit in this field corresponds to a priority that should be set in a Per…
39811 … (0x1ffff<<0) // Each bit in this register represents 512 bit t…
39815 …- skipped (unsupported) 1 - stackvlan (unsupported) 2 - carrerr (on by default) 3 - codeerr (on by…
39816 … 0x051334UL //Access:RW DataWidth:0x1 // Flush enable bit to drop out all pac…
39817 … 0x051338UL //Access:RW DataWidth:0x8 // probe address bit 7 - U/L bit 6 - GMII/XMGII …
39830 … (0x1<<0) // Enables the PPP-Tx functionality.
39832 … (0x1<<1) // Enables the PPP-Rx functionality.
39838 …nters is in full function. Note: it is programming requirement to set this bit when PFC function i…
39846 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
39850 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
39852 … (0x1<<1) // This bit masks, when set, the Parity bit: MC…
39854 … (0x1<<2) // This bit masks, when set, the Parity bit: MC…
39856 … (0x1<<3) // This bit masks, when set, the Parity bi…
39857 …CP2_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_E5_SHIFT 3
39858 … (0x1<<4) // This bit masks, when set, the Parity bit: MC…
39860 … (0x1<<5) // This bit masks, when set, the Parity bit: MC…
39862 … (0x1<<6) // This bit masks, when set, the Parity bit: MC…
39864 … (0x1<<7) // This bit masks, when set, the Parity bit: MC…
39866 … (0x1<<8) // This bit masks, when set, the Parity bit: MC…
39868 … (0x1<<9) // This bit masks, when set, the Parity bit: MC…
39870 … (0x1<<10) // This bit masks, when set, the Parity bit: MC…
39872 … (0x1<<11) // This bit masks, when set, the Parity bit: MC…
39874 … (0x1<<12) // This bit masks, when set, the Parity bit: MC…
39876 … (0x1<<13) // This bit masks, when set, the Parity bit: MC…
39878 … (0x1<<14) // This bit masks, when set, the Parity bit: MC…
39880 … (0x1<<15) // This bit masks, when set, the Parity bit: MC…
39882 … (0x1<<8) // This bit masks, when set, the Parity bit: MC…
39884 … (0x1<<16) // This bit masks, when set, the Parity bit: MC…
39886 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
39888 … (0x1<<1) // This bit masks, when set, the Parity bit: MC…
39890 … (0x1<<2) // This bit masks, when set, the Parity bit: MC…
39892 … (0x1<<3) // This bit masks, when set, the Parity bi…
39893 …CP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_2_RF_INT_BB_K2_SHIFT 3
39894 … (0x1<<4) // This bit masks, when set, the Parity bit: MC…
39896 … (0x1<<5) // This bit masks, when set, the Parity bit: MC…
39898 … (0x1<<6) // This bit masks, when set, the Parity bit: MC…
39900 … (0x1<<7) // This bit masks, when set, the Parity bit: MC…
39902 … (0x1<<9) // This bit masks, when set, the Parity bit: MC…
39904 … (0x1<<11) // This bit masks, when set, the Parity bit: MC…
39906 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39907 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39908 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39909 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39910 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39911 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39912 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39913 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39914 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39915 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39916 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39917 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
39926 …003_I_ECC_1_EN_E5 (0x1<<3) // Enable ECC for m…
39927 …CP2_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_1_EN_E5_SHIFT 3
39946 …006_I_ECC_2_EN_BB_K2 (0x1<<3) // Enable ECC for m…
39947 …CP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_2_EN_BB_K2_SHIFT 3
39960 …0_MEM003_I_ECC_1_PRTY_E5 (0x1<<3) // Set parity only …
39961 …CP2_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_1_PRTY_E5_SHIFT 3
39980 …0_MEM006_I_ECC_2_PRTY_BB_K2 (0x1<<3) // Set parity only …
39981 …CP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_2_PRTY_BB_K2_SHIFT 3
39994 …TED_0_MEM003_I_ECC_1_CORRECT_E5 (0x1<<3) // Record if a corr…
39995 …CP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_1_CORRECT_E5_SHIFT 3
40014 …TED_0_MEM006_I_ECC_2_CORRECT_BB_K2 (0x1<<3) // Record if a corr…
40015 …CP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_2_CORRECT_BB_K2_SHIFT 3
40023 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
40024 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
40027 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
40028 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
40032 … (0x1<<0) // This bit masks, when set, the Parity bit: OP…
40034 … (0x1<<1) // This bit masks, when set, the Parity bit: OP…
40036 … (0x1<<2) // This bit masks, when set, the Parity bit: OP…
40038 … (0x1<<3) // This bit masks, when set, the Parity bi…
40039 …PTE_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT 3
40040 … (0x1<<4) // This bit masks, when set, the Parity bit: OP…
40042 … (0x1<<5) // This bit masks, when set, the Parity bit: OP…
40044 … (0x1<<6) // This bit masks, when set, the Parity bit: OP…
40046 … (0x1<<7) // This bit masks, when set, the Parity bit: OP…
40048 … (0x1<<8) // This bit masks, when set, the Parity bit: OP…
40050 … (0x1<<9) // This bit masks, when set, the Parity bit: OP…
40052 … (0x1<<10) // This bit masks, when set, the Parity bit: OP…
40056 … DORQ FIFO. When the occupancy is more than that number, local edpm_en is de-asserted. It is than …
40058 … (0x1<<0) // This bit masks, when set, the Parity bit: OP…
40061 … (0x1<<4) // This bit masks, when set, the Parity bit: PC…
40063 … (0x1<<0) // This bit masks, when set, the Parity bit: PC…
40065 … (0x1<<1) // This bit masks, when set, the Parity bit: PC…
40067 … (0x1<<7) // This bit masks, when set, the Parity bit: PC…
40069 … (0x1<<2) // This bit masks, when set, the Parity bit: PC…
40071 … (0x1<<3) // This bit masks, when set, the Parity bi…
40072 …CIE_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_E5_SHIFT 3
40073 … (0x1<<4) // This bit masks, when set, the Parity bit: PC…
40075 … (0x1<<16) // This bit masks, when set, the Parity bit: PC…
40077 … (0x1<<5) // This bit masks, when set, the Parity bit: PC…
40079 … (0x1<<6) // This bit masks, when set, the Parity bit: PC…
40081 … (0x1<<6) // This bit masks, when set, the Parity bit: PC…
40083 … (0x1<<7) // This bit masks, when set, the Parity bit: PC…
40085 … (0x1<<0) // This bit masks, when set, the Parity bit: PC…
40087 … (0x1<<1) // This bit masks, when set, the Parity bit: PC…
40089 … (0x1<<2) // This bit masks, when set, the Parity bit: PC…
40091 … (0x1<<3) // This bit masks, when set, the Parity bi…
40092 …CIE_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_BB_SHIFT 3
40093 … (0x1<<5) // This bit masks, when set, the Parity bit: PC…
40095 … (0x1<<8) // This bit masks, when set, the Parity bit: PC…
40097 … (0x1<<9) // This bit masks, when set, the Parity bit: PC…
40099 … (0x1<<10) // This bit masks, when set, the Parity bit: PC…
40101 … (0x1<<11) // This bit masks, when set, the Parity bit: PC…
40103 … (0x1<<12) // This bit masks, when set, the Parity bit: PC…
40105 … (0x1<<13) // This bit masks, when set, the Parity bit: PC…
40107 … (0x1<<14) // This bit masks, when set, the Parity bit: PC…
40109 … (0x1<<15) // This bit masks, when set, the Parity bit: PC…
40124 …009_I_ECC_EN_BB (0x1<<3) // Enable ECC for m…
40125 …CIE_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN_BB_SHIFT 3
40141 …0_MEM009_I_ECC_PRTY_BB (0x1<<3) // Set parity only …
40142 …CIE_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY_BB_SHIFT 3
40158 …TED_0_MEM009_I_ECC_CORRECT_BB (0x1<<3) // Record if a corr…
40159 …CIE_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT_BB_SHIFT 3
40167 …ER_L23_REQ (0x1<<3) // Set to request e…
40168 …CIE_REG_PCIE_CONTROL_BITS_USER_L23_REQ_SHIFT 3
40175 …P_L1SUB_BB (0x1<<5) // Stop L1Sub control bit.
40178 …L0 (0x1<<1) // Link in L0 Status bit.
40180 …23 (0x1<<4) // Link in L23 Status bit.
40184 …11_BB (0x1<<2) // Link in L11 Status bit.
40186 …12_BB (0x1<<3) // Link in L12 Status bit.
40187 …CIE_REG_PCIE_STATUS_BITS_LINK_IN_L12_BB_SHIFT 3
40190 …L_LOCK_BB (0x1<<8) // PLL Lock status bit.
40204 …T_RESET_CONTROL_SOFT_STICKY_RST_N_K2_E5 (0x1<<3) //
40205 …CIE_REG_SOFT_RESET_CONTROL_SOFT_STICKY_RST_N_K2_E5_SHIFT 3
40215 … (0x1<<1) // This bit is set by firmware when host system sets OBFF Enable to 2'b11. Fi…
40217 …) // Set to 1 to indicate that the pcore WakeIn input is active high. This bit should only be set …
40219 …LECPUACTIVEFORCING_K2_E5 (0x1<<3) // Set to 1 to prev…
40220 …CIE_REG_OBFF_CONTROL_1_DISABLECPUACTIVEFORCING_K2_E5_SHIFT 3
40258 … 0x054224UL //Access:RW DataWidth:0x20 // 32 bit value to be sent in…
40259 … 0x054228UL //Access:RW DataWidth:0x20 // 32 bit value to be sent in…
40289 …C_PHY_RXSTANDBY_K2_E5 (0xff<<3) // Indicates whethe…
40290 …CIE_REG_CLK_RST_APM_STATUS_MAC_PHY_RXSTANDBY_K2_E5_SHIFT 3
40294 …update the PTM Requester Context and Clock now. FW must clear this bit after setting this bit to 1.
40314 …ET_STATUS_1_NON_STICKY_RST_N_K2_E5 (0x1<<3) //
40315 …CIE_REG_RESET_STATUS_1_NON_STICKY_RST_N_K2_E5_SHIFT 3
40331 …el indicating that the receive queues contain TLP header/data.There is a 1 bit indication for each…
40342 …MSG_UNLOCK_K2_E5 (0x1<<16) // One-cycle pulse that indi…
40344 …TURNOFF_K2_E5 (0x1<<17) // One-clock-cycle pulse that i…
40349 … (0xffff<<3) // Wake Up. Used by application logic to wake up the PMC state machine from a…
40350 …CIE_REG_PCIE_DIAGNOSTIC_CONTROL_OUTBAND_PWRUP_CMD_K2_E5_SHIFT 3
40352 … (0xffff<<0) // PME Status bit from the PMCSR. There is 1 bit of p…
40357 …_E5 (0x1<<0) // WARNING: this bit should not be used …
40359 … (0xffff<<1) // PME Enable bit in the PMCSR. There is 1 bit of pm…
40368 … (0xffff<<0) // This is the value of the No Soft Reset bit in the Power Manage…
40373 … (0xffff<<0) // Auxiliary Power Enable bit in the Device Control register. There is 1 …
40415 … 0x054328UL //Access:R DataWidth:0x5 // pm_dev_num[4:0]- Device number
40416 … 0x05432cUL //Access:R DataWidth:0x8 // pm_bus_num[7:0]- Bus Number
40423 … 0x054348UL //Access:RW DataWidth:0x15 // Power Budget Table entry 3
40458 …REQ_INT_K2_E5 (0x1<<3) // Link Equalizatio…
40459 …CIE_REG_INT_STS_CFG_LINK_EQ_REQ_INT_K2_E5_SHIFT 3
40472 … (0x1<<10) // Do not use -- keep mask bit set to 1.
40478 … (0x1<<13) // Non-Fatal Error Message s…
40484 … (0x1<<16) // Vendor-Defined Message recei…
40487 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
40489 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
40491 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
40493 … (0x1<<3) // This bit masks, when set, the Interrupt …
40494 …CIE_REG_INT_MASK_CFG_LINK_EQ_REQ_INT_K2_E5_SHIFT 3
40495 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
40497 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
40499 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
40501 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
40503 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
40505 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
40507 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
40509 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
40511 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
40513 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
40515 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
40517 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
40519 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
40528 …EQ_REQ_INT_K2_E5 (0x1<<3) // Link Equalizatio…
40529 …CIE_REG_INT_STS_WR_CFG_LINK_EQ_REQ_INT_K2_E5_SHIFT 3
40542 … (0x1<<10) // Do not use -- keep mask bit set to 1.
40548 …E5 (0x1<<13) // Non-Fatal Error Message s…
40554 … (0x1<<16) // Vendor-Defined Message recei…
40563 …_EQ_REQ_INT_K2_E5 (0x1<<3) // Link Equalizatio…
40564 …CIE_REG_INT_STS_CLR_CFG_LINK_EQ_REQ_INT_K2_E5_SHIFT 3
40577 … (0x1<<10) // Do not use -- keep mask bit set to 1.
40583 …_E5 (0x1<<13) // Non-Fatal Error Message s…
40589 … (0x1<<16) // Vendor-Defined Message recei…
40592 … (0x1<<0) // This bit masks, when set, the Parity bit: PC…
40594 … (0x1<<1) // This bit masks, when set, the Parity bit: PC…
40596 … (0x1<<2) // This bit masks, when set, the Parity bit: PC…
40603 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
40604 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
40605 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
40606 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
40608 …_E5 (0x1<<0) // Power-on reset occurred.
40614 …CH_RST_2_K2_E5 (0x1<<3) // Squelch reset oc…
40615 …CIE_REG_RESET_STATUS_2_SQUELCH_RST_2_K2_E5_SHIFT 3
40618 …_2_K2_E5 (0x1<<5) // Non-sticky register reset…
40630 …_STATUS_REG_SPARE_11_2_K2_E5 (0x1<<11) // Spare status bit
40632 …_STATUS_REG_SPARE_12_2_K2_E5 (0x1<<12) // Spare status bit
40634 …_STATUS_REG_SPARE_13_2_K2_E5 (0x1<<13) // Spare status bit
40636 …_STATUS_REG_SPARE_14_2_K2_E5 (0x1<<14) // Spare status bit
40638 …_STATUS_REG_SPARE_15_2_K2_E5 (0x1<<15) // Spare status bit
40640 …(0x1<<16) // Soft power-on reset occurred. NOTE: This bit is unreliable for indication of a soft p…
40650 …2_K2_E5 (0x1<<21) // Soft non-sticky register reset…
40658 … (0x1<<3) // This bit masks, when set, the Parity bi…
40659 …XPREQBUS_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_SHIFT 3
40660 … (0x1<<0) // This bit masks, when set, the Parity bit: PX…
40662 … (0x1<<1) // This bit masks, when set, the Parity bit: PX…
40664 … (0x1<<13) // This bit masks, when set, the Parity bit: PX…
40666 … (0x1<<2) // This bit masks, when set, the Parity bit: PX…
40668 … (0x1<<4) // This bit masks, when set, the Parity bit: PX…
40670 … (0x1<<3) // This bit masks, when set, the Parity bi…
40671 …XPREQBUS_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5_SHIFT 3
40672 … (0x1<<4) // This bit masks, when set, the Parity bit: PX…
40674 … (0x1<<5) // This bit masks, when set, the Parity bit: PX…
40676 … (0x1<<6) // This bit masks, when set, the Parity bit: PX…
40678 … (0x1<<7) // This bit masks, when set, the Parity bit: PX…
40680 … (0x1<<2) // This bit masks, when set, the Parity bit: PX…
40682 … (0x1<<8) // This bit masks, when set, the Parity bit: PX…
40684 … (0x1<<8) // This bit masks, when set, the Parity bit: PX…
40686 … (0x1<<9) // This bit masks, when set, the Parity bit: PX…
40688 … (0x1<<10) // This bit masks, when set, the Parity bit: PX…
40690 … (0x1<<11) // This bit masks, when set, the Parity bit: PX…
40692 … (0x1<<12) // This bit masks, when set, the Parity bit: PX…
40694 … (0x1<<13) // This bit masks, when set, the Parity bit: PX…
40696 … (0x1<<14) // This bit masks, when set, the Parity bit: PX…
40698 … (0x1<<15) // This bit masks, when set, the Parity bit: PX…
40700 … (0x1<<16) // This bit masks, when set, the Parity bit: PX…
40702 … (0x1<<17) // This bit masks, when set, the Parity bit: PX…
40704 … (0x1<<18) // This bit masks, when set, the Parity bit: PX…
40706 … (0x1<<19) // This bit masks, when set, the Parity bit: PX…
40708 … (0x1<<0) // This bit masks, when set, the Parity bit: PX…
40710 … (0x1<<20) // This bit masks, when set, the Parity bit: PX…
40712 … (0x1<<9) // This bit masks, when set, the Parity bit: PX…
40714 … (0x1<<21) // This bit masks, when set, the Parity bit: PX…
40718 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
40719 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
40727 …ULL (0x1<<3) // DORQ FIFO almost…
40728 …ORQ_REG_INT_STS_DORQ_FIFO_AFULL_SHIFT 3
40737 … (0x1<<8) // CFC load request FIFO under-run
40741 …-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or b) Non-fir…
40746 … (0x1<<0) // This bit masks, when set, the Interrupt bit: D…
40748 … (0x1<<1) // This bit masks, when set, the Interrupt bit: D…
40750 … (0x1<<2) // This bit masks, when set, the Interrupt bit: D…
40752 … (0x1<<3) // This bit masks, when set, the Interrupt …
40753 …ORQ_REG_INT_MASK_DORQ_FIFO_AFULL_SHIFT 3
40754 … (0x1<<4) // This bit masks, when set, the Interrupt bit: D…
40756 … (0x1<<5) // This bit masks, when set, the Interrupt bit: D…
40758 … (0x1<<6) // This bit masks, when set, the Interrupt bit: D…
40760 … (0x1<<7) // This bit masks, when set, the Interrupt bit: D…
40762 … (0x1<<8) // This bit masks, when set, the Interrupt bit: D…
40764 … (0x1<<9) // This bit masks, when set, the Interrupt bit: D…
40766 … (0x1<<10) // This bit masks, when set, the Interrupt bit: D…
40768 … (0x1<<11) // This bit masks, when set, the Interrupt bit: D…
40777 …_AFULL (0x1<<3) // DORQ FIFO almost…
40778 …ORQ_REG_INT_STS_WR_DORQ_FIFO_AFULL_SHIFT 3
40787 …RR (0x1<<8) // CFC load request FIFO under-run
40791 …-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or b) Non-fir…
40802 …O_AFULL (0x1<<3) // DORQ FIFO almost…
40803 …ORQ_REG_INT_STS_CLR_DORQ_FIFO_AFULL_SHIFT 3
40812 …ERR (0x1<<8) // CFC load request FIFO under-run
40816 …-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or b) Non-fir…
40821 … (0x1<<0) // This bit masks, when set, the Parity bit: DO…
40824 … (0x1<<0) // This bit masks, when set, the Parity bit: DO…
40826 … (0x1<<1) // This bit masks, when set, the Parity bit: DO…
40828 … (0x1<<2) // This bit masks, when set, the Parity bit: DO…
40830 … (0x1<<1) // This bit masks, when set, the Parity bit: DO…
40832 … (0x1<<3) // This bit masks, when set, the Parity bi…
40833 …ORQ_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_E5_SHIFT 3
40834 … (0x1<<4) // This bit masks, when set, the Parity bit: DO…
40836 … (0x1<<5) // This bit masks, when set, the Parity bit: DO…
40838 … (0x1<<6) // This bit masks, when set, the Parity bit: DO…
40840 … (0x1<<7) // This bit masks, when set, the Parity bit: DO…
40842 … (0x1<<2) // This bit masks, when set, the Parity bit: DO…
40844 … (0x1<<8) // This bit masks, when set, the Parity bit: DO…
40846 … (0x1<<3) // This bit masks, when set, the Parity bi…
40847 …ORQ_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT 3
40848 … (0x1<<9) // This bit masks, when set, the Parity bit: DO…
40850 … (0x1<<4) // This bit masks, when set, the Parity bit: DO…
40852 … (0x1<<10) // This bit masks, when set, the Parity bit: DO…
40854 … (0x1<<5) // This bit masks, when set, the Parity bit: DO…
40856 … (0x1<<11) // This bit masks, when set, the Parity bit: DO…
40867 …en multiplied by 16, is equal to the maximum ICID plus 1 of connection type 3. This is per PF conf…
40875 …en multiplied by 16, is equal to the maximum ICID plus 1 of connection type 3. This is per PF conf…
40880 …2 // LOG2 of the size of per connection doorbell space footprint in DWORD-s. I.e. value of 0 me…
40881 …2 // LOG2 of the size of per connection doorbell space footprint in DWORD-s. I.e. value of 0 me…
40887 …/Access:RW DataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 1. Bit 2 of AggValSel is a…
40890 …/Access:RW DataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 2. Bit 2 of AggValSel is a…
40892 … 0x100478UL //Access:RW DataWidth:0x2 // Target value used in DEMS mode for DEMS = 3.
40893 …//Access:RW DataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 3. Bit 2 of AggValSel is …
40894 …480UL //Access:RW DataWidth:0x2 // AggCmd used in DEMS mode for DEMS = 3. Reset value = SET_A…
40896 …/Access:RW DataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 4. Bit 2 of AggValSel is a…
40899 …/Access:RW DataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 5. Bit 2 of AggValSel is a…
40902 …/Access:RW DataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 6. Bit 2 of AggValSel is a…
40905 …/Access:RW DataWidth:0x2 // AggValSel used in DEMS mode for DEMS = 7. Bit 2 of AggValSel is a…
40907 … 0x1004f4UL //Access:RW DataWidth:0x2 // AGG command value in PWM non-DPM mode.
40910 …n 2 port mode it is equal to 0 for all PF-s. In 4 port mode, it is equal to 0 for even PF-s and to…
40915 …ccess:RW DataWidth:0x1 // Enable DPM doorbells for all this PF child VF-s. In case not set th…
40929 … 0x100810UL //Access:RW DataWidth:0x1 // If set then CCFC mini-cache is enabled.
40931 …and first DPM doorbell appears it is truncated to one entry and aborted; non-first doorbell is dro…
40932 … doorbell appears it is truncated to one entry and DpmAbort flag is set; non-first doorbell is sil…
40933 …x100824UL //Access:RW DataWidth:0x1 // If set, then XCM bypass enable bit will be masked (XCM…
40934 …0x100828UL //Access:RW DataWidth:0x1 // If set, then QM bypass enable bit will be masked (con…
40935 …x10082cUL //Access:RW DataWidth:0x1 // If set, then PBF bypass enable bit will be masked (con…
40936 …0x100830UL //Access:RW DataWidth:0x1 // If set, then QM bypass enable bit will be masked (con…
40938 …icates which ExistInQm bits are taken into account in the EDPM check. If a bit equals 0 then the c…
40944 … 0x10088cUL //Access:RW DataWidth:0x10 // Tag 3 Ethertype used for p…
40946 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40947 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40948 …ize of the Tag 3 used for packet generation in RDMA EDPM mode not including Ethertype itself. 0 - …
40949 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40952 … 0x1008acUL //Access:RW DataWidth:0x20 // Enable bit per each RoCE Opcode 5 LSB-s. N-th bit …
40953 …Access:RW DataWidth:0x1 // If 0 - the RoCE CRC-32 final calculation result isn't byte swapped…
40954 …ride 1 � External VLAN Id only override 2 � External VLAN Id + PCP override 3 � Internal VLAN Id o…
40955 …ride 1 � External VLAN Id only override 2 � External VLAN Id + PCP override 3 � Internal VLAN Id o…
40956 …ride 1 � External VLAN Id only override 2 � External VLAN Id + PCP override 3 � Internal VLAN Id o…
40957 …ride 1 � External VLAN Id only override 2 � External VLAN Id + PCP override 3 � Internal VLAN Id o…
40958 … 0x1008c4UL //Access:RW DataWidth:0x4 // The priority value and DEI bit of RoCE frames per …
40962 …Q_REG_ROCE_ETHER_TYPE_SIZE 3
40969 … 0x100918UL //Access:RW DataWidth:0x2 // TPH Hint value in case of non-inline L2 EDPM.
40970 … 0x10091cUL //Access:RW DataWidth:0x3 // ATC attribute value of non-inline L2 EDPM.
40972 … 0x100924UL //Access:RW DataWidth:0xe // Maximum non-inline L2 EDPM PktSiz…
40973 … 0x100928UL //Access:RW DataWidth:0x8 // The maximum number of WORD-s which the PBF may a…
40980 …DataWidth:0xb // Counter of DORQ FIFO entries used by corresponding PF or any of its child VF-s.
40982 … number of DORQ FIFO entries used by corresponding PF or any of its child VF-s. This is a per PF c…
40987 …h:0x14 // A bit mask per doorbell drop reason. If a bit is set (1), then corresponding drop reas…
40992 …de is active and all doorbells are dropped at the entrance to DORQ FIFO. De-asserted when auto_di…
40995 … 0x1009fcUL //Access:R DataWidth:0x20 // Accounts for any non-DPM doorbell or first…
41003 …0 // Stores the details of the first dropped doorbell after logging was re-armed by db_drop_deta…
41004 …-armed by db_drop_details_rel. The following details of the transaction will be recorded: Doorbell…
41005 …7 // Stores the details of the first dropped doorbell after logging was re-armed by db_drop_deta…
41007 …bit per reason). It is reset on write to db_drop_details_rel. 0 - Size of the data is not equal to…
41013 …- DPM doorbell and rewind configuration of DPM timer (dpm_timeout) is 0; 1 - PF DPM doorbell and i…
41015 …bit per reason). It is reset on write to db_abort_details_rel. 0 - DPM doorbell and rewind configu…
41027 … be done at first cycle of first DPM doorbell by the size of DpmSize. No non-first DPM doorbells s…
41032 …ue of the single entry in the CID load mini-cache is captured. 49: Valid, 48:40 - LCID, 39:32 - Re…
41034 …-cache was used. 36 - CDU Validation Error; 35 - CFC Load Cancel; 34 - CFC Load Error; 33 - CFC LC…
41039 …Width:0x1 // comment="Selects IEDPM payload endianity. 0 - little endian (lsB first); 1 - big e…
41045 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
41046 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
41047 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
41048 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
41053 …- DPM FSM state [194:192] - DbAggValSel [191:190] - DbAggCmd [189:182] - DbAggFlgCmd [181] - IEDPM…
41058 …odulo 8, i.e. 0, 8, .., 312 to eliminate false parity error of IEDPM buffer 3. The access is allow…
41065 …gister, when multiplied by 16, is equal to the maximum ICID plus 1 of range 3. This is per PF per …
41069 …gister, when multiplied by 16, is equal to the maximum ICID plus 1 of range 3. This is per PF per …
41073 … 0x102834UL //Access:RW DataWidth:0x4 // Maps range 3 to connection type. …
41077 … 0x102844UL //Access:RW DataWidth:0x4 // Mas range 3 to connection type. …
41080 …cates which ExistInQm bits are taken into account in the IEDPM check. If a bit equals 0 then the c…
41087 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41088 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41089 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41090 …used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for RDMA doorbell. P…
41091 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41092 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41093 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41094 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41095 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41096 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41097 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41098 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41099 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41100 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41101 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41102 …PM_AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - …
41106 …lect which one of two QM_AGG_TYPE will be used as AggDecType in XCM message. Per connection type 3.
41125 …//Access:RW DataWidth:0x1 // QM Bypass mode is enabled for XCM messages for connection type 3.
41126 …th:0x1 // QM Bypass mode is enabled for XCM messages for connection type 3. Per connection type.
41149 …ccess:RW DataWidth:0x1 // Indicates whether DPI validation is supported for connection type 3.
41150 …0x1 // Indicates whether DPI validation is supported for connection type 3. Per connection type.
41173 …UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell for connection type 3.
41174 …UL //Access:RW DataWidth:0x8 // Event ID in XCM message in DPM doorbell for connection type 3.
41197 …text to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 3.
41198 …text to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 3.
41221 … 0x100620UL //Access:RW DataWidth:0x8 // Enable for XCM counter flag command for connection 3.
41222 … 0x1029f4UL //Access:RW DataWidth:0x8 // Enable for XCM counter flag command for connection 3.
41245 … 0x100640UL //Access:RW DataWidth:0x8 // Enable for TCM counter flag command for connection 3.
41246 … 0x102a34UL //Access:RW DataWidth:0x8 // Enable for TCM counter flag command for connection 3.
41269 … 0x100660UL //Access:RW DataWidth:0x8 // Enable for UCM counter flag command for connection 3.
41270 … 0x102a74UL //Access:RW DataWidth:0x8 // Enable for UCM counter flag command for connection 3.
41293 …0680UL //Access:RW DataWidth:0x8 // Enable for XCM aggregation value command for connection 3.
41294 …2ab4UL //Access:RW DataWidth:0x8 // Enable for XCM aggregation value command for connection 3.
41317 …06a0UL //Access:RW DataWidth:0x8 // Enable for TCM aggregation value command for connection 3.
41318 …2af4UL //Access:RW DataWidth:0x8 // Enable for TCM aggregation value command for connection 3.
41341 …06c0UL //Access:RW DataWidth:0x8 // Enable for UCM aggregation value command for connection 3.
41342 …2b34UL //Access:RW DataWidth:0x8 // Enable for UCM aggregation value command for connection 3.
41364 …Access:RW DataWidth:0x1 // If 0 - the iWARP CRC-32 final calculation result isn't byte swappe…
41365 … 0x102b80UL //Access:RW DataWidth:0x20 // Enable bit per each iWARP Opcode 5 LSB-s. N-th bit…
41366 … 0x102b84UL //Access:RW DataWidth:0x4 // The priority value and DEI bit in external VLAN TA…
41367 … 0x102b88UL //Access:RW DataWidth:0x4 // The priority value and DEI bit in external VLAN TA…
41368 … 0x102b8cUL //Access:RW DataWidth:0x4 // The priority value and DEI bit in internal VLAN TA…
41369 … 0x102b90UL //Access:RW DataWidth:0x4 // The priority value and DEI bit internal VLAN TAG o…
41377 …cates which ExistInQm bits are taken into account in RoCE EDPM check. If a bit equals 0 then the c…
41378 …ates which ExistInQm bits are taken into account in iWARP EDPM check. If a bit equals 0 then the c…
41379 …dicates which ExistInQm bits are taken into account in L2 EDPM check. If a bit equals 0 then the c…
41380 …the transaction will be recorded: Doorbell DPM type. 0 - Legacy 1 - RDMA 2 - L2 Inline 3 - L2 Non-…
41385 …- First DPM doorbell does not match DPM global start conditions at CFC load response for Internal …
41387 …bit per reason). It is reset on write to db_abort_details_rel. 0 - First DPM doorbell does not mat…
41388 …-armed by iedpm_drop_details_rel. The following details of the transaction will be recorded: IEDPM…
41389 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41390 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41391 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41392 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41394 …bit per reason). It is reset on write to iedpm_drop_details_rel. 4 - First QWord (offset 0) arives…
41395 …h:0x5 // A bit mask per doorbell drop reason. If a bit is set (1), then corresponding drop reas…
41412 …ty type in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 3.
41428 …ve flag in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 3.
41444 …ffinity in CM header sent to XCM in RDMA (RoCE or iWARP) EDPM or legacy DPM. Per connection type 3.
41461 …bit resets the appropriate memory. When the memory reset finished the appropriate bit is cleared. …
41463 …// If enabled the IGU forwards write/read requests to the TPH interface. 1 - enabled; 0 - disabled.
41465 …ed the IGU allows to VF to send cleanup commands on the int ack address. 1 - enabled; 0 - disabled.
41467 …the IGU allows bypass mode of the rate limiter when the system is empty. 1 - enabled; 0 - disabled.
41473 … 0x18006cUL //Access:R DataWidth:0x20 // Provides read-only access to the BI…
41484 …CESS_PROD_UPD (0x1<<3) // Host write produ…
41485 …GU_REG_INT_STS_HOST_TRIES2ACCESS_PROD_UPD_SHIFT 3
41486 … (0x1<<4) // VFID bit is set and the command is to attention bi…
41501 … (0x1<<0) // This bit masks, when set, the Interrupt bit: I…
41503 … (0x1<<1) // This bit masks, when set, the Interrupt bit: I…
41505 … (0x1<<2) // This bit masks, when set, the Interrupt bit: I…
41507 … (0x1<<3) // This bit masks, when set, the Interrupt …
41508 …GU_REG_INT_MASK_HOST_TRIES2ACCESS_PROD_UPD_SHIFT 3
41509 … (0x1<<4) // This bit masks, when set, the Interrupt bit: I…
41511 … (0x1<<5) // This bit masks, when set, the Interrupt bit: I…
41513 … (0x1<<6) // This bit masks, when set, the Interrupt bit: I…
41515 … (0x1<<7) // This bit masks, when set, the Interrupt bit: I…
41517 … (0x1<<8) // This bit masks, when set, the Interrupt bit: I…
41519 … (0x1<<9) // This bit masks, when set, the Interrupt bit: I…
41521 … (0x1<<10) // This bit masks, when set, the Interrupt bit: I…
41530 …2ACCESS_PROD_UPD (0x1<<3) // Host write produ…
41531 …GU_REG_INT_STS_WR_HOST_TRIES2ACCESS_PROD_UPD_SHIFT 3
41532 … (0x1<<4) // VFID bit is set and the command is to attention bi…
41553 …S2ACCESS_PROD_UPD (0x1<<3) // Host write produ…
41554 …GU_REG_INT_STS_CLR_HOST_TRIES2ACCESS_PROD_UPD_SHIFT 3
41555 … (0x1<<4) // VFID bit is set and the command is to attention bi…
41570 … (0x1<<0) // This bit masks, when set, the Parity bit: IG…
41573 … (0x1<<0) // This bit masks, when set, the Parity bit: IG…
41575 … (0x1<<6) // This bit masks, when set, the Parity bit: IG…
41577 … (0x1<<1) // This bit masks, when set, the Parity bit: IG…
41579 … (0x1<<7) // This bit masks, when set, the Parity bit: IG…
41581 … (0x1<<2) // This bit masks, when set, the Parity bit: IG…
41583 … (0x1<<8) // This bit masks, when set, the Parity bit: IG…
41585 … (0x1<<3) // This bit masks, when set, the Parity bi…
41586 …GU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_1_E5_SHIFT 3
41587 … (0x1<<9) // This bit masks, when set, the Parity bit: IG…
41589 … (0x1<<4) // This bit masks, when set, the Parity bit: IG…
41591 … (0x1<<10) // This bit masks, when set, the Parity bit: IG…
41593 … (0x1<<5) // This bit masks, when set, the Parity bit: IG…
41595 … (0x1<<11) // This bit masks, when set, the Parity bit: IG…
41597 … (0x1<<6) // This bit masks, when set, the Parity bit: IG…
41599 … (0x1<<7) // This bit masks, when set, the Parity bit: IG…
41601 … (0x1<<13) // This bit masks, when set, the Parity bit: IG…
41603 … (0x1<<8) // This bit masks, when set, the Parity bit: IG…
41605 … (0x1<<19) // This bit masks, when set, the Parity bit: IG…
41607 … (0x1<<9) // This bit masks, when set, the Parity bit: IG…
41609 … (0x1<<19) // This bit masks, when set, the Parity bit: IG…
41611 … (0x1<<10) // This bit masks, when set, the Parity bit: IG…
41613 … (0x1<<11) // This bit masks, when set, the Parity bit: IG…
41615 … (0x1<<12) // This bit masks, when set, the Parity bit: IG…
41617 … (0x1<<13) // This bit masks, when set, the Parity bit: IG…
41619 … (0x1<<14) // This bit masks, when set, the Parity bit: IG…
41621 … (0x1<<15) // This bit masks, when set, the Parity bit: IG…
41623 … (0x1<<26) // This bit masks, when set, the Parity bit: IG…
41625 … (0x1<<22) // This bit masks, when set, the Parity bit: IG…
41627 … (0x1<<16) // This bit masks, when set, the Parity bit: IG…
41629 … (0x1<<27) // This bit masks, when set, the Parity bit: IG…
41631 … (0x1<<23) // This bit masks, when set, the Parity bit: IG…
41633 … (0x1<<17) // This bit masks, when set, the Parity bit: IG…
41635 … (0x1<<28) // This bit masks, when set, the Parity bit: IG…
41637 … (0x1<<24) // This bit masks, when set, the Parity bit: IG…
41639 … (0x1<<18) // This bit masks, when set, the Parity bit: IG…
41641 … (0x1<<26) // This bit masks, when set, the Parity bit: IG…
41643 … (0x1<<19) // This bit masks, when set, the Parity bit: IG…
41645 … (0x1<<20) // This bit masks, when set, the Parity bit: IG…
41647 … (0x1<<21) // This bit masks, when set, the Parity bit: IG…
41649 … (0x1<<22) // This bit masks, when set, the Parity bit: IG…
41651 … (0x1<<23) // This bit masks, when set, the Parity bit: IG…
41653 … (0x1<<24) // This bit masks, when set, the Parity bit: IG…
41655 … (0x1<<3) // This bit masks, when set, the Parity bi…
41656 …GU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_SHIFT 3
41657 … (0x1<<4) // This bit masks, when set, the Parity bit: IG…
41659 … (0x1<<25) // This bit masks, when set, the Parity bit: IG…
41661 … (0x1<<4) // This bit masks, when set, the Parity bit: IG…
41663 … (0x1<<5) // This bit masks, when set, the Parity bit: IG…
41665 … (0x1<<26) // This bit masks, when set, the Parity bit: IG…
41667 … (0x1<<5) // This bit masks, when set, the Parity bit: IG…
41669 … (0x1<<27) // This bit masks, when set, the Parity bit: IG…
41671 … (0x1<<28) // This bit masks, when set, the Parity bit: IG…
41673 … (0x1<<29) // This bit masks, when set, the Parity bit: IG…
41675 … (0x1<<30) // This bit masks, when set, the Parity bit: IG…
41677 … (0x1<<0) // This bit masks, when set, the Parity bit: IG…
41679 … (0x1<<1) // This bit masks, when set, the Parity bit: IG…
41681 … (0x1<<1) // This bit masks, when set, the Parity bit: IG…
41683 … (0x1<<2) // This bit masks, when set, the Parity bit: IG…
41685 … (0x1<<2) // This bit masks, when set, the Parity bit: IG…
41687 … (0x1<<3) // This bit masks, when set, the Parity bi…
41688 …GU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT 3
41689 … (0x1<<7) // This bit masks, when set, the Parity bit: IG…
41691 … (0x1<<9) // This bit masks, when set, the Parity bit: IG…
41693 … (0x1<<8) // This bit masks, when set, the Parity bit: IG…
41695 … (0x1<<10) // This bit masks, when set, the Parity bit: IG…
41697 … (0x1<<11) // This bit masks, when set, the Parity bit: IG…
41699 … (0x1<<12) // This bit masks, when set, the Parity bit: IG…
41701 … (0x1<<14) // This bit masks, when set, the Parity bit: IG…
41703 … (0x1<<15) // This bit masks, when set, the Parity bit: IG…
41705 … (0x1<<14) // This bit masks, when set, the Parity bit: IG…
41707 … (0x1<<16) // This bit masks, when set, the Parity bit: IG…
41709 … (0x1<<15) // This bit masks, when set, the Parity bit: IG…
41711 … (0x1<<17) // This bit masks, when set, the Parity bit: IG…
41713 … (0x1<<18) // This bit masks, when set, the Parity bit: IG…
41715 … (0x1<<20) // This bit masks, when set, the Parity bit: IG…
41717 … (0x1<<21) // This bit masks, when set, the Parity bit: IG…
41719 … (0x1<<29) // This bit masks, when set, the Parity bit: IG…
41721 … (0x1<<25) // This bit masks, when set, the Parity bit: IG…
41723 … (0x1<<30) // This bit masks, when set, the Parity bit: IG…
41725 … (0x1<<27) // This bit masks, when set, the Parity bit: IG…
41727 … (0x1<<12) // This bit masks, when set, the Parity bit: IG…
41729 … (0x1<<16) // This bit masks, when set, the Parity bit: IG…
41731 … (0x1<<17) // This bit masks, when set, the Parity bit: IG…
41733 … (0x1<<18) // This bit masks, when set, the Parity bit: IG…
41735 … (0x1<<22) // This bit masks, when set, the Parity bit: IG…
41737 … (0x1<<23) // This bit masks, when set, the Parity bit: IG…
41739 … (0x1<<24) // This bit masks, when set, the Parity bit: IG…
41741 … (0x1<<25) // This bit masks, when set, the Parity bit: IG…
41745 … (0x1<<0) // This bit masks, when set, the Parity bit: IG…
41747 … (0x1<<0) // This bit masks, when set, the Parity bit: IG…
41761 …r of MSI/MSIX/ATTN messages sent for the PF: address 0 - number of MSI/MSIX messages; address 1 - …
41771 …Debug: count the number of PXP requests sent on behalf of a specific MSI/MSI-X vector on the SB in…
41785 … 0x180600UL //Access:RW DataWidth:0x14 // IPS statistics - number of messages s…
41787 …- function enable; b1 - MSI/MSIX enable; b2 - INT enable; b3 - attention enable; b4 - single ISR m…
41788 …h:0x9 // d0 - function enable; d1 - MSI/MSIX enable; d3:d2 reserved; d4 - single ISR mode enabl…
41816 …th:0x1 // PF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.
41818 …th:0x1 // VF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.
41819 …80820UL //Access:RW DataWidth:0x20 // For attention message: Attention bit destination address…
41820 …80824UL //Access:RW DataWidth:0x20 // For attention message: Attention bit destination address…
41821 …ss:RW DataWidth:0x10 // Value of attention bit status index (posted toward the driver as atten…
41822 … DataWidth:0x20 // Attention signals leading edge. attn bit condition monitoring; each bit that…
41823 … DataWidth:0x20 // Attention signals trailing edge. attn bit condition monitoring; each bit that…
41824 … 0x180834UL //Access:RW DataWidth:0x20 // 32 bit register with the l…
41825 … 0x180838UL //Access:RW DataWidth:0x20 // 32 bit register with the a…
41826 …tor is 12 bit. If the bit is set to 1, the corresponding bit in the attention vector is enabled. I…
41827 …bit means PBA message wasnt sent due to mask). If address = SIMD with mask 64b/32LSB: 32 LSB of th…
41828 …bit means PBA message wasnt sent due to mask). If address = SIMD with mask 64b/32MSB: 32 MSB of t…
41829 …idth:0x20 // [15:0] - function number: opaque fid. [28:16] - PXP BAR address; [30:29] - Reserved…
41831 … DataWidth:0x20 // Address 0 - MSI address low (two Lsbit are zero). Address 1 - MSI address hig…
41832 …_REG_MSI_MEMORY_SIZE 3
41834 …g is enabled, the match address of the hit response is used to perform a two-cycle …
41836 … read of the entire CAM will be started (or re-started). This will e…
41838 … 0x180864UL //Access:RW DataWidth:0x1 // Enable the RL statistic. 0 - disabled; 1 - enabled.
41840 … 0x180880UL //Access:R DataWidth:0x20 // Each bit represents the pend…
41844 … 0x180900UL //Access:R DataWidth:0x20 // Each bit represent write don…
41848 …0980UL //Access:R DataWidth:0x20 // Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanu…
41852 …0a00UL //Access:R DataWidth:0x20 // Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanu…
41856 …0a80UL //Access:R DataWidth:0x20 // Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanu…
41860 …0b00UL //Access:R DataWidth:0x20 // Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanu…
41864 …0b80UL //Access:R DataWidth:0x20 // Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanu…
41868 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41869 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41870 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41871 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41872 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41873 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41874 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41875 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41876 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41877 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41878 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41879 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41880 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41881 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41882 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41883 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41884 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41885 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41886 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41887 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41888 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41889 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41890 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41891 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41892 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41893 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41894 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41895 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41896 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41897 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41898 …he appropriate vector in the MSIX table (write zero to all fields except the mask bit that is set).
41899 …UL //Access:RW DataWidth:0x20 // SB interrupt before mask. 0 - prod equal cons. 1 - prod not e…
41901 …UL //Access:RW DataWidth:0x20 // SB interrupt before mask. 0 - prod equal cons. 1 - prod not e…
41902 …UL //Access:RW DataWidth:0x20 // SB interrupt before mask. 0 - prod equal cons. 1 - prod not e…
41903 … 0x180ce0UL //Access:RW DataWidth:0x20 // SB interrupt mask. 0 - unmasked. 1 - masked. The b…
41905 … 0x180d00UL //Access:RW DataWidth:0x20 // SB interrupt mask. 0 - unmasked. 1 - masked. The b…
41906 … 0x180d04UL //Access:RW DataWidth:0x20 // SB interrupt mask. 0 - unmasked. 1 - masked. The b…
41907 …ataWidth:0x20 // PBA register. 0 - PBA clear, 1 - PBA set - the appropriate MSIX message was not…
41909 …ataWidth:0x20 // PBA register. 0 - PBA clear, 1 - PBA set - the appropriate MSIX message was not…
41910 …ataWidth:0x20 // PBA register. 0 - PBA clear, 1 - PBA set - the appropriate MSIX message was not…
41911 …- sets the max value that the rate_counter can reach; [19:10] tick_interval - define the max inter…
41913 …- receives the tick_interval value when reaching zero; or when writing to the tick_interval. The t…
41923 …er - incremented by one when Tick_value reaches zero and decremented whenever a message from that …
41925 …riting 1 to this register will clear the PF statistics and clean also attn bit, attn ack and attn …
41927 …Tph field for attention message. Bits 8:0 - steering tag; bits 12:9 - reserved; bits 14:13 - st hi…
41928 … Rate Limiter group enable status bit for groups 0-31. For each bit: 0 - the rate limiter of the g…
41929 …Rate Limiter group enable status bit for groups 32-63. For each bit: 0 - the rate limiter of the g…
41930 …0x20 // Rate Limiter group credit status bit for groups 0-31. For each bit: 0 - the group has no…
41931 …x20 // Rate Limiter group credit status bit for groups 32-63. For each bit: 0 - the group has no…
41932 …/ Rate Limiter group pending status bit for groups 0-31. For each bit: 0 - there are no pending SB…
41933 … Rate Limiter group pending status bit for groups 32-63. For each bit: 0 - there are no pending SB…
41934 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port0.
41935 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port1.
41936 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port2.
41937 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port3.
41938 …Width:0x10 // Debug: messages that wait to be sent; but were not sent yet. One bit for each PFID.
41939 …cess:R DataWidth:0x5 // Debug: [4] - attention write done message is pending (0-no pending; …
41940 …518UL //Access:RW DataWidth:0x1 // Debug only: 0 - FIFO collects 64 first error messages; 1 -…
41942 …- fid ([8] - if set - PF; else VF, [7:0] - FID). [12:9] - source (values 0-7 according to PXP sour…
41944 …//Access:R DataWidth:0x1 // Data available for error memory. If this bit is clear do not rea…
41966 …ff<<0) // Debug: FID number for debug . if VF - [8] = 0; [7:0] = VF number; if PF - [8] = 1; [7:4]…
41973 …0xf<<0) // Debug: source index for the debug. 0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=…
41978 …Bit [0] - MSIX read/write; Bit [1] - PBA read/write; Bit [2] - Producer update (or cleanup command…
41982 … DataWidth:0x2 // The misc port mode signal value. 0 = SPPE; 1 = DPPE; 2 = QPPE; 3 = reserved.
41985 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
41986 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
41987 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
41988 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
41993 … DataWidth:0x18 // Producers only. Address 0-511 match to the mapping memory. Address 512-227:…
41997 …W DataWidth:0x18 // Consumers only. Address 0-511 match to the mapping memory. Address 512-227…
42001 …- valid. [8:1] - vector number (0-128 for PF; 0-63 for VF). [17:9] - FID (if VF: [17] = 0; [16:9] …
42005 …- MSIX message address (bit [1:0] are always zero); [95:64] - MSIX message data; [96] - MSIX mask …
42016 …S_ERROR (0x1<<3) // SB index > CAU_N…
42017 …AU_REG_INT_STS_PXP_SB_ADDRESS_ERROR_SHIFT 3
42039 …DRESS_ERROR (0x1<<3) // SB index > CAU_N…
42040 …AU_REG_INT_STS_CLR_PXP_SB_ADDRESS_ERROR_SHIFT 3
42062 …RESS_ERROR (0x1<<3) // SB index > CAU_N…
42063 …AU_REG_INT_STS_WR_PXP_SB_ADDRESS_ERROR_SHIFT 3
42079 … (0x1<<0) // This bit masks, when set, the Interrupt bit: C…
42081 … (0x1<<1) // This bit masks, when set, the Interrupt bit: C…
42083 … (0x1<<2) // This bit masks, when set, the Interrupt bit: C…
42085 … (0x1<<3) // This bit masks, when set, the Interrupt …
42086 …AU_REG_INT_MASK_PXP_SB_ADDRESS_ERROR_SHIFT 3
42087 … (0x1<<4) // This bit masks, when set, the Interrupt bit: C…
42089 … (0x1<<5) // This bit masks, when set, the Interrupt bit: C…
42091 … (0x1<<6) // This bit masks, when set, the Interrupt bit: C…
42093 … (0x1<<8) // This bit masks, when set, the Interrupt bit: C…
42095 … (0x1<<9) // This bit masks, when set, the Interrupt bit: C…
42097 … (0x1<<10) // This bit masks, when set, the Interrupt bit: C…
42099 … (0x1<<7) // This bit masks, when set, the Interrupt bit: C…
42102 … (0x1<<1) // This bit masks, when set, the Parity bit: CA…
42104 … (0x1<<0) // This bit masks, when set, the Parity bit: CA…
42106 … (0x1<<2) // This bit masks, when set, the Parity bit: CA…
42108 … (0x1<<1) // This bit masks, when set, the Parity bit: CA…
42110 … (0x1<<3) // This bit masks, when set, the Parity bi…
42111 …AU_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_K2_SHIFT 3
42112 … (0x1<<2) // This bit masks, when set, the Parity bit: CA…
42114 … (0x1<<4) // This bit masks, when set, the Parity bit: CA…
42116 … (0x1<<3) // This bit masks, when set, the Parity bi…
42117 …AU_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_E5_SHIFT 3
42118 … (0x1<<3) // This bit masks, when set, the Parity bi…
42119 …AU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_SHIFT 3
42120 … (0x1<<5) // This bit masks, when set, the Parity bit: CA…
42122 … (0x1<<4) // This bit masks, when set, the Parity bit: CA…
42124 … (0x1<<5) // This bit masks, when set, the Parity bit: CA…
42126 … (0x1<<4) // This bit masks, when set, the Parity bit: CA…
42128 … (0x1<<6) // This bit masks, when set, the Parity bit: CA…
42130 … (0x1<<5) // This bit masks, when set, the Parity bit: CA…
42132 … (0x1<<7) // This bit masks, when set, the Parity bit: CA…
42134 … (0x1<<10) // This bit masks, when set, the Parity bit: CA…
42136 … (0x1<<11) // This bit masks, when set, the Parity bit: CA…
42138 … (0x1<<8) // This bit masks, when set, the Parity bit: CA…
42140 … (0x1<<11) // This bit masks, when set, the Parity bit: CA…
42142 … (0x1<<12) // This bit masks, when set, the Parity bit: CA…
42144 … (0x1<<9) // This bit masks, when set, the Parity bit: CA…
42146 … (0x1<<0) // This bit masks, when set, the Parity bit: CA…
42148 … (0x1<<6) // This bit masks, when set, the Parity bit: CA…
42150 … (0x1<<8) // This bit masks, when set, the Parity bit: CA…
42152 … (0x1<<7) // This bit masks, when set, the Parity bit: CA…
42154 … (0x1<<9) // This bit masks, when set, the Parity bit: CA…
42156 … (0x1<<8) // This bit masks, when set, the Parity bit: CA…
42158 … (0x1<<10) // This bit masks, when set, the Parity bit: CA…
42160 … (0x1<<9) // This bit masks, when set, the Parity bit: CA…
42162 … (0x1<<12) // This bit masks, when set, the Parity bit: CA…
42173 …02_I_ECC_EN_K2 (0x1<<3) // Enable ECC for m…
42174 …AU_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_K2_SHIFT 3
42179 …04_I_ECC_EN_E5 (0x1<<3) // Enable ECC for m…
42180 …AU_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_E5_SHIFT 3
42192 …_MEM002_I_ECC_PRTY_K2 (0x1<<3) // Set parity only …
42193 …AU_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_K2_SHIFT 3
42198 …_MEM004_I_ECC_PRTY_E5 (0x1<<3) // Set parity only …
42199 …AU_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_E5_SHIFT 3
42211 …ED_0_MEM002_I_ECC_CORRECT_K2 (0x1<<3) // Record if a corr…
42212 …AU_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_K2_SHIFT 3
42217 …ED_0_MEM004_I_ECC_CORRECT_E5 (0x1<<3) // Record if a corr…
42218 …AU_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_E5_SHIFT 3
42245 … number of outstanding write requests without receiving write done. Values 1-128. Zero is not a va…
42246 …bit will reset the whole memory. When the memory reset finished the appropriate bit will be clear.…
42247 …p on the written SB number. [8:0] - SB absolute index; [9] - Cleanup set/clr (0-clr; 1 - set); [12…
42249 …arvation) priority for the input clients: bits 1:0 PXP input commands. bits 3:2 RBC cleanup. bits …
42251 … 0x1c0600UL //Access:RW DataWidth:0x1 // Indicate the size of the CQE. 0 - 32B; 1 - 64B.
42252 …W DataWidth:0x2 // Indicate the size of the AGG unit. 0 - 64B; 1 - 128B; 2 - 256B; 3 - illega…
42253 … 0x1c0608UL //Access:RW DataWidth:0x1 // Flush all command - will flush all the C…
42259 … 0x1c070cUL //Access:RW DataWidth:0x1 // Setting this bit will disable the ti…
42260 … 0x1c0780UL //Access:R DataWidth:0x20 // Rx timers status. 0 - inactive 1 - active.
42262 … 0x1c0800UL //Access:R DataWidth:0x20 // Tx timers status. 0 - inactive 1 - active.
42266 … 0x1c0980UL //Access:R DataWidth:0x1 // Debug: IGU-CAU request interface…
42267 … 0x1c0984UL //Access:R DataWidth:0x1 // Debug: IGU-CAU command interface…
42279 …istic: client index to collect statistics on. 0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=…
42293 …/ Statistic: enable timer command type. One bit for each timer command type: [0] - rewind; [1] - c…
42311 …- FIFO empty; 1 - FIFO not empty. [0] - PXP command FIFO; [1] - reserved; [2] - timers expiration …
42312 …- error typ (1- read request; 2 - reserved; 3 - sb_index >= CAU_NUM_SB or SB index > CAU_NUM_PI/n…
42313 …3:0] - source (0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NI…
42314 … // Debug; [9] if set data valid; [8] previous FSM_sel; [7:4] - previous state; [3:0] - previous…
42316 …h:0x19 // comment="Debug: [15:0] The PF that caused the error- one bit per PF; [24:16] - SB inde…
42318 …e was writing to agg_units_state_read_en register. (i =0-15). 0 - free; 1 - dirty; 2 - clean; 3 - …
42319 …was writing to agg_units_state_read_en register. (i = 16-31). 0 - free; 1 - dirty; 2 - clean; 3 - …
42320 …was writing to agg_units_state_read_en register. (i = 32-47). 0 - free; 1 - dirty; 2 - clean; 3 - …
42321 …was writing to agg_units_state_read_en register. (i = 48-63). 0 - free; 1 - dirty; 2 - clean; 3 - …
42334 …ff<<0) // Debug: FID number for debug . if VF - [8] = 1; [7:0] = VF number; if PF - [8] = 0; [7:4]…
42341 …0xf<<0) // Debug: source index for the debug. 0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=…
42346 … (0x7<<0) // Debug: command type for the debug. [0] - PI producer update; [1] - cleanup; [2] - …
42348 …_TYPE_EN (0x1<<3) // Debug: if set th…
42349 …AU_REG_DEBUG_RECORD_MASK_CMD_TYPE_EN_SHIFT 3
42358 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
42359 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
42360 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
42361 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
42365 … 0x1c0f0cUL //Access:R DataWidth:0x5 // Debug: FSM state for debug.Idle state value are 0-2
42367 … 0x1c2000UL //Access:WB_R DataWidth:0x80 // Debug: Provides read-only access of the CQ…
42369 … 0x1c2200UL //Access:WB_R DataWidth:0x35 // Debug: Provides read-only access of the IG…
42371 … 0x1c2300UL //Access:WB_R DataWidth:0x62 // Debug: Provides read-only access of the PX…
42373 …2400UL //Access:WB_R DataWidth:0x84 // Debug: Provides read-only access of the PXP write-data FI…
42375 … and PI relative number of each aggregation unit. [0] - valid; [9:1] - absolute SB index; [14:10] …
42377 …3:0] are the event_id. The data is :[3:0] - next state; [5:4] - timer cmd (0 - None; 1 - Rewind; 2…
42379 …-2 only); [49:48] TimerRes1 (This value will determine the TX FSM timer resolution in ticks. Valid…
42387 …ry.[15:0] - protocol producer; [22:16] - PiTimeSet (This value determines the TimeSet that the PI …
42394 …- address; [71:64] - valid slots; [84:72] - FID ([13:9] - PF number (in case of VF the parent PF);…
42396 …h:0x18 // The SB timers. For each SB there are two timers: [11:0] - RX timer; [23:12] - TX timer.
42400 … 0x1f0000UL //Access:RW DataWidth:0x1 // Soft reset - reset all FSM.
42401 …UL //Access:W DataWidth:0x1 // Any write to this register triggers MAC-VLAN Cache initializa…
42408 … (0x1<<1) // Load Request Mini-cache validation error
42411 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
42413 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
42418 … (0x1<<1) // Load Request Mini-cache validation error
42423 … (0x1<<1) // Load Request Mini-cache validation error
42426 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
42428 … (0x1<<1) // This bit masks, when set, the Parity bit: PR…
42432 …0168UL //Access:RW DataWidth:0x10 // Per-PF: If OX_ID exceeds this value on a PF packet, task-…
42433 …016cUL //Access:RW DataWidth:0x10 // Per-PF: If OX_ID exceeds this value on a VF packet, task-…
42434 …0170UL //Access:RW DataWidth:0x10 // Per-PF: If RX_ID exceeds this value on a PF packet, task-…
42435 …0174UL //Access:RW DataWidth:0x10 // Per-PF: If RX_ID exceeds this value on a VF packet, task-…
42442 … 0x1f0190UL //Access:RW DataWidth:0x1 // Per-PF: If set, override …
42443 … 0x1f0194UL //Access:RW DataWidth:0x20 // Per-opcode requester/responder bit to be…
42444 … 0x1f0198UL //Access:RW DataWidth:0x1 // Per-PF: If set, a load re…
42445 … 0x1f019cUL //Access:RW DataWidth:0x1 // If set, CFC load mini-cache is enabled.
42446 … 0x1f01a0UL //Access:RW DataWidth:0x1 // 0-search response initiator type,1-Excha…
42447 … 0x1f01a4UL //Access:RW DataWidth:0x1 // 0-Exchange Context field in the fcoe search req is z…
42450 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
42452 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
42454 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
42456 … (0x1<<1) // This bit masks, when set, the Parity bit: PR…
42458 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
42460 … (0x1<<3) // This bit masks, when set, the Parity bi…
42461 …RS_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT_E5_SHIFT 3
42462 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
42464 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
42466 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
42468 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
42470 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
42472 … (0x1<<10) // This bit masks, when set, the Parity bit: PR…
42474 … (0x1<<7) // This bit masks, when set, the Parity bit: PR…
42476 … (0x1<<23) // This bit masks, when set, the Parity bit: PR…
42478 … (0x1<<8) // This bit masks, when set, the Parity bit: PR…
42480 … (0x1<<9) // This bit masks, when set, the Parity bit: PR…
42482 … (0x1<<19) // This bit masks, when set, the Parity bit: PR…
42484 … (0x1<<10) // This bit masks, when set, the Parity bit: PR…
42486 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
42488 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
42490 … (0x1<<11) // This bit masks, when set, the Parity bit: PR…
42492 … (0x1<<22) // This bit masks, when set, the Parity bit: PR…
42494 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
42496 … (0x1<<30) // This bit masks, when set, the Parity bit: PR…
42498 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
42500 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
42502 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
42504 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
42506 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
42508 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
42510 … (0x1<<26) // This bit masks, when set, the Parity bit: PR…
42512 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
42514 … (0x1<<27) // This bit masks, when set, the Parity bit: PR…
42516 … (0x1<<19) // This bit masks, when set, the Parity bit: PR…
42518 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
42520 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
42522 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
42524 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
42526 … (0x1<<22) // This bit masks, when set, the Parity bit: PR…
42528 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
42530 … (0x1<<1) // This bit masks, when set, the Parity bit: PR…
42532 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
42534 … (0x1<<3) // This bit masks, when set, the Parity bi…
42535 …RS_REG_PRTY_MASK_H_0_MEM017_I_ECC_RF_INT_K2_SHIFT 3
42536 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
42538 … (0x1<<7) // This bit masks, when set, the Parity bit: PR…
42540 … (0x1<<8) // This bit masks, when set, the Parity bit: PR…
42542 … (0x1<<9) // This bit masks, when set, the Parity bit: PR…
42544 … (0x1<<10) // This bit masks, when set, the Parity bit: PR…
42546 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
42548 … (0x1<<11) // This bit masks, when set, the Parity bit: PR…
42550 … (0x1<<25) // This bit masks, when set, the Parity bit: PR…
42552 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
42554 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
42556 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
42558 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
42560 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
42562 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
42564 … (0x1<<29) // This bit masks, when set, the Parity bit: PR…
42566 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
42568 … (0x1<<30) // This bit masks, when set, the Parity bit: PR…
42570 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
42572 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
42574 … (0x1<<24) // This bit masks, when set, the Parity bit: PR…
42576 … (0x1<<19) // This bit masks, when set, the Parity bit: PR…
42578 … (0x1<<28) // This bit masks, when set, the Parity bit: PR…
42580 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
42582 … (0x1<<22) // This bit masks, when set, the Parity bit: PR…
42584 … (0x1<<23) // This bit masks, when set, the Parity bit: PR…
42586 … (0x1<<24) // This bit masks, when set, the Parity bit: PR…
42588 … (0x1<<25) // This bit masks, when set, the Parity bit: PR…
42590 … (0x1<<26) // This bit masks, when set, the Parity bit: PR…
42592 … (0x1<<27) // This bit masks, when set, the Parity bit: PR…
42594 … (0x1<<28) // This bit masks, when set, the Parity bit: PR…
42596 … (0x1<<29) // This bit masks, when set, the Parity bit: PR…
42598 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
42600 … (0x1<<1) // This bit masks, when set, the Parity bit: PR…
42602 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
42604 … (0x1<<3) // This bit masks, when set, the Parity bi…
42605 …RS_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_BB_SHIFT 3
42606 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
42608 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
42610 … (0x1<<7) // This bit masks, when set, the Parity bit: PR…
42612 … (0x1<<8) // This bit masks, when set, the Parity bit: PR…
42614 … (0x1<<9) // This bit masks, when set, the Parity bit: PR…
42616 … (0x1<<11) // This bit masks, when set, the Parity bit: PR…
42618 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
42632 …20_I_ECC_EN_E5 (0x1<<3) // Enable ECC for m…
42633 …RS_REG_MEM_ECC_ENABLE_0_MEM020_I_ECC_EN_E5_SHIFT 3
42642 …17_I_ECC_EN_K2 (0x1<<3) // Enable ECC for m…
42643 …RS_REG_MEM_ECC_ENABLE_0_MEM017_I_ECC_EN_K2_SHIFT 3
42654 …15_I_ECC_EN_BB (0x1<<3) // Enable ECC for m…
42655 …RS_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN_BB_SHIFT 3
42668 …_MEM020_I_ECC_PRTY_E5 (0x1<<3) // Set parity only …
42669 …RS_REG_MEM_ECC_PARITY_ONLY_0_MEM020_I_ECC_PRTY_E5_SHIFT 3
42678 …_MEM017_I_ECC_PRTY_K2 (0x1<<3) // Set parity only …
42679 …RS_REG_MEM_ECC_PARITY_ONLY_0_MEM017_I_ECC_PRTY_K2_SHIFT 3
42690 …_MEM015_I_ECC_PRTY_BB (0x1<<3) // Set parity only …
42691 …RS_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY_BB_SHIFT 3
42693 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
42695 … (0x1<<1) // This bit masks, when set, the Parity bit: PR…
42697 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
42699 … (0x1<<3) // This bit masks, when set, the Parity bi…
42700 …RS_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_K2_SHIFT 3
42701 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
42703 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
42705 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
42707 … (0x1<<7) // This bit masks, when set, the Parity bit: PR…
42709 … (0x1<<8) // This bit masks, when set, the Parity bit: PR…
42711 … (0x1<<9) // This bit masks, when set, the Parity bit: PR…
42713 … (0x1<<10) // This bit masks, when set, the Parity bit: PR…
42715 … (0x1<<11) // This bit masks, when set, the Parity bit: PR…
42717 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
42719 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
42721 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
42723 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
42725 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
42727 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
42729 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
42731 … (0x1<<19) // This bit masks, when set, the Parity bit: PR…
42733 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
42735 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
42737 … (0x1<<22) // This bit masks, when set, the Parity bit: PR…
42739 … (0x1<<23) // This bit masks, when set, the Parity bit: PR…
42741 … (0x1<<24) // This bit masks, when set, the Parity bit: PR…
42743 … (0x1<<25) // This bit masks, when set, the Parity bit: PR…
42745 … (0x1<<26) // This bit masks, when set, the Parity bit: PR…
42747 … (0x1<<27) // This bit masks, when set, the Parity bit: PR…
42749 … (0x1<<28) // This bit masks, when set, the Parity bit: PR…
42751 … (0x1<<3) // This bit masks, when set, the Parity bi…
42752 …RS_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_SHIFT 3
42753 … (0x1<<29) // This bit masks, when set, the Parity bit: PR…
42755 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
42757 … (0x1<<30) // This bit masks, when set, the Parity bit: PR…
42759 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
42761 … (0x1<<1) // This bit masks, when set, the Parity bit: PR…
42763 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
42777 …ED_0_MEM020_I_ECC_CORRECT_E5 (0x1<<3) // Record if a corr…
42778 …RS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM020_I_ECC_CORRECT_E5_SHIFT 3
42787 …ED_0_MEM017_I_ECC_CORRECT_K2 (0x1<<3) // Record if a corr…
42788 …RS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM017_I_ECC_CORRECT_K2_SHIFT 3
42799 …ED_0_MEM015_I_ECC_CORRECT_BB (0x1<<3) // Record if a corr…
42800 …RS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT_BB_SHIFT 3
42803 … 0x1f0400UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42804 … 0x1f0404UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42805 … 0x1f0408UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42806 … 0x1f040cUL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42809 …IPV4 (0x1<<0) // If this bit is 0, the dest_ip_a…
42811 …IPV6 (0x1<<1) // If this bit is 0, the dest_ip_a…
42813 …S_IPV4 (0x1<<2) // If this bit is 0, the source_ip…
42815 …_ADDRESS_IPV6 (0x1<<3) // If this bit is 0, the so…
42816 …RS_REG_TCP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV6_SHIFT 3
42817 … (0x1<<4) // If this bit is 0, the tcp_dest_…
42819 … (0x1<<5) // If this bit is 0, the tcp_sourc…
42821 … (0x1<<6) // If this bit is 0, the ip_versio…
42824 …IPV4 (0x1<<0) // If this bit is 0, the dest_ip_a…
42826 …IPV6 (0x1<<1) // If this bit is 0, the dest_ip_a…
42828 …S_IPV4 (0x1<<2) // If this bit is 0, the source_ip…
42830 …_ADDRESS_IPV6 (0x1<<3) // If this bit is 0, the so…
42831 …RS_REG_UDP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV6_SHIFT 3
42832 … (0x1<<4) // If this bit is 0, the udp_dest_…
42834 … (0x1<<5) // If this bit is 0, the udp_sourc…
42836 … (0x1<<6) // If this bit is 0, the ip_versio…
42838 … 0x1f041cUL //Access:RW DataWidth:0x1 // Per-PF: If set, search re…
42839 … 0x1f0420UL //Access:RW DataWidth:0x1 // Per-PF: Enables VF_ID (if…
42840 … 0x1f0424UL //Access:RW DataWidth:0x1 // Per-PF: Enables load requ…
42842 … 0x1f042cUL //Access:RW DataWidth:0x11 // Per-PF: Max value for tem…
42843 … 0x1f0430UL //Access:RW DataWidth:0x11 // Per-PF: Max value for tem…
42844 … 0x1f0434UL //Access:RW DataWidth:0x1 // Per-PF: Enables openflow …
42845 … 0x1f0438UL //Access:RW DataWidth:0x1 // Per-PF: Enables openflow search for non-IP …
42846 … 0x1f043cUL //Access:RW DataWidth:0x1 // Per-PF: If this field is 1, Over-IPv4-prot…
42848 …PORT (0x1<<0) // If this bit is 0, the tcp_sourc…
42850 …PORT (0x1<<1) // If this bit is 0, the udp_sourc…
42852 …_PORT (0x1<<2) // If this bit is 0, the sctp_sour…
42854 …_TYPE (0x1<<3) // If this bit is 0, the ic…
42855 …RS_REG_OPENFLOW_SEARCH_KEY_MASK_ICMP_TYPE_SHIFT 3
42856 …RT (0x1<<4) // If this bit is 0, the tcp_dest_…
42858 …RT (0x1<<5) // If this bit is 0, the udp_dest_…
42860 …ORT (0x1<<6) // If this bit is 0, the sctp_dest…
42862 … (0x1<<7) // If this bit is 0, the icmp_code…
42864 … (0x1<<8) // If this bit is 0, the priority …
42866 …YPE (0x1<<9) // If this bit is 0, the ipv4_frag…
42868 …RESS (0x1<<10) // If this bit is 0, the dest_mac_…
42870 …OTOCOL (0x1<<11) // If this bit is 0, the over_ipv4…
42872 … (0x1<<12) // If this bit is 0, the arp_opcod…
42874 … (0x1<<13) // If this bit is 0, the ipv4_dscp…
42876 …DDRESS (0x1<<14) // If this bit is 0, the source_ma…
42878 …DRESS_IPV4 (0x1<<15) // If this bit is 0, the source_ip…
42880 …DRESS_ARP (0x1<<16) // If this bit is 0, the source_ip…
42882 …ESS_IPV4 (0x1<<17) // If this bit is 0, the dest_ip_a…
42884 …ESS_ARP (0x1<<18) // If this bit is 0, the dest_ip_a…
42886 … (0x1<<19) // If this bit is 0, the ethertype…
42888 …/ Per-PF: Indicates whether to include the Inner VLAN in the search for each protocol. 0 - TCP, 1 …
42889 …/ Per-PF: Indicates whether to include the Outer TAG in the search for each protocol. 0 - TCP, 1 -…
42890 …-PF: Indicates whether to include Tenant ID (if it exists) in the search for each encapsulation ty…
42891 …ID Exists bit in the search request to be 0 if the ID matches the default value. 0 - L2 GRE, 1 - …
42892 …Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated Ethernet ov…
42893 …Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated IP over GRE…
42894 …Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated VXLAN packe…
42895 …Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated T-tag packe…
42896 …capsulated Ethernet over GRE packet and does not match this value the Tenant ID exists bit is set.
42897 …the encapsulated IP over GRE packet and does not match this value the Tenant ID exists bit is set.
42898 …sts in the encapsulated VXLAN packet and does not match this value the Tenant ID exists bit is set.
42899 … the Tenant ID exists in the encapsulated T-Tag packet and does not match this value the Tenant ID…
42900 …ataWidth:0x3 // Per-Port: Specifies the flexible L2 tag to be used for T-tag. The T-tag bit of …
42901 …Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated nge packet.…
42902 …Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated nge packet.…
42903 …s in the encapsulated ETH NGE packet and does not match this value the Tenant ID exists bit is set.
42904 …ts in the encapsulated IP NGE packet and does not match this value the Tenant ID exists bit is set.
42905 …DataWidth:0x1 // MAC port arbitration guarantees fairness at byte-level (0) or packet-level (1).
42906 … DataWidth:0x1 // Main/LB arbitration guarantees fairness at byte-level (0) or packet-level (1).
42909 … 0x1f0510UL //Access:RW DataWidth:0x8 // Size of inter-packet gap and FCS us…
42910 …ority_client): 0-TC0 traffic; 1-TC1 traffic; 2-TC2 traffic; 3-TC3 traffic; 4-TC4 traffic; 5-TC5 tr…
42911 …ority_client): 0-TC0 traffic; 1-TC1 traffic; 2-TC2 traffic; 3-TC3 traffic; 4-TC4 traffic; 5-TC5 tr…
42912 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
42913 …. Bits [3:0] are for priority 0 client; upper bits are for priority 8 client. The clients are as…
42914 …. Bits [3:0] are for priority 0 client; upper bits are for priority 8 client. The clients are as…
42915 …-robin arbiter stays on the winning input instead of moving to the next one. Bit 0 is for the mai…
42916 … 0x1f052cUL //Access:RW DataWidth:0x1 // Enables pseudo-random round robin ar…
42919 …1f0538UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42922 …1f0544UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42925 …1f0550UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42926 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 3 is allowed to reach.
42927 …idth:0x20 // Specify the weight (in bytes) to be added to credit register 3 when it is time to i…
42928 …R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter credit register 3.
42931 …1f0568UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42934 …1f0574UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42937 …1f0580UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42940 …1f058cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42943 …1f0598UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42946 …1f05a4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit…
42949 …1f05b0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42952 …1f05bcUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit…
42955 …1f05c8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42958 …1f05d4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit…
42961 …1f05e0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42962 …r bound that the credit register is allowed to reach for main traffic on TC 3 during WFQ Main/Loop…
42963 …weight (in bytes) to be added to the credit register for main traffic on TC 3 when it is time to i…
42964 …Width:0x20 // Current upper 32 bits of the 33-bit value in the credit register for main traffic …
42965 …und that the credit register is allowed to reach for loopback traffic on TC 3 during WFQ Main/Loop…
42966 …ht (in bytes) to be added to the credit register for loopback traffic on TC 3 when it is time to i…
42967 …:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter credit register for loopback tr…
42970 …1f0604UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit…
42973 …1f0610UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42976 …1f061cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit…
42979 …1f0628UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42982 …1f0634UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit…
42985 …1f0640UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42988 …1f064cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit…
42991 …1f0658UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
42994 …1f0664UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the credit…
42995 … 0x1f0700UL //Access:RW DataWidth:0x4 // Per-port: Size of the pro…
43007 …ataWidth:0x6 // Per-port: Flag enabling each encapsulation type. 0 - L2 GRE, 1 - IP GRE, 2 - V…
43010 … 0x1f073cUL //Access:RW DataWidth:0x10 // Per-PF: Base value used i…
43011 … 0x1f0740UL //Access:RW DataWidth:0x10 // Per-PF: Base value used i…
43017 … 0x1f0758UL //Access:RW DataWidth:0x10 // The Ethernet type value for L2 tag 3.
43023 …L //Access:RW DataWidth:0x3 // The length of the info field for L2 tag 3. The length is betw…
43026 …-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port. …
43027 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port. This applies to …
43028 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port. This applies to …
43029 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port. This applies to …
43030 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port. This applies to …
43031 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port. This applies to …
43032 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port. This applies to …
43033 …-port: Bit-map indicating which headers must appear in the packet on this port. This applies to t…
43034 … 0x1f079cUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43035 … 0x1f07a0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43036 … 0x1f07a4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43037 … 0x1f07a8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43038 … 0x1f07acUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43039 … 0x1f07b0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43040 … 0x1f07b4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43041 … 0x1f07b8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
43044 …alue. A zero in this register will cause the corresponding bit to not be included …
43045 …alue. A zero in this register will cause the corresponding bit to not be included …
43046 … 0x1f07ccUL //Access:RW DataWidth:0x20 // Per-PF/Per-port: Destination …
43047 … 0x1f07d0UL //Access:RW DataWidth:0x10 // Per-PF/Per-port: Destination …
43048 …L //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - bit 129 indicate…
43049 …L //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - bit 129 indicate…
43050 …L //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - bit 129 indicate…
43051 …L //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - bit 129 indicate…
43052 …L //Access:RW DataWidth:0x2 // Per-PF: Destination IP address match value - bit 129 indicate…
43053 … 0x1f07e8UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43054 … 0x1f07ecUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43055 … 0x1f07f0UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43056 … 0x1f07f4UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43057 … 0x1f07f8UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43058 … 0x1f07fcUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43059 … 0x1f0800UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43060 … 0x1f0804UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43061 … 0x1f0808UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43062 … 0x1f080cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43063 … 0x1f0810UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43064 … 0x1f0814UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43065 … 0x1f0818UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43066 … 0x1f081cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43067 … 0x1f0820UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43068 … 0x1f0824UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43069 … 0x1f0828UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43070 … 0x1f082cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43071 … 0x1f0830UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43072 … 0x1f0834UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43073 … 0x1f0838UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43074 … 0x1f083cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43075 … 0x1f0840UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43076 … 0x1f0844UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43077 … 0x1f0848UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43078 … 0x1f084cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43079 … 0x1f0850UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43080 … 0x1f0854UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43081 … 0x1f0858UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43082 … 0x1f085cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43083 … 0x1f0860UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43084 … 0x1f0864UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43088 … 0x1f0874UL //Access:RW DataWidth:0x1 // Per-port: Flag enabling …
43089 … 0x1f0878UL //Access:RW DataWidth:0x1 // Per-port: Flag to compar…
43093 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43098 … (0xff<<0) // Event ID for tunneled packets with no match in the mac-vlan cache
43100 …ch in the mac-vlan cache. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg;…
43111 … (0xff<<0) // Event ID for tunneled packets with no match in the mac-vlan cache
43113 …ch in the mac-vlan cache. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg;…
43126 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43139 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43146 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43156 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43157 … 0x1f093cUL //Access:RW DataWidth:0x4 // Connection type for no-match packets.
43158 … 0x1f0940UL //Access:RW DataWidth:0x4 // Per-port: PFID for no-match packet…
43159 … 0x1f0944UL //Access:RW DataWidth:0x1 // Per-PF: If set, the PFID may be overridden for n…
43160 … 0x1f0948UL //Access:RW DataWidth:0x20 // Per-PF: CID for no-match packets.
43161 … 0x1f094cUL //Access:RW DataWidth:0x9 // Per-PF: LCID for no-match packets.
43169 … 0x1f096cUL //Access:RW DataWidth:0x1 // Per-PF: If set, and PF cl…
43170 …sulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN 2 - NGE
43171 …sulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN 2 - NGE
43172 …ulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN, 2 - NGE
43173 …-PF: Indicates whether to include Tenant ID (if it exists) in the MAC VLAN Cache entry for each en…
43174 …-VLAN Cache Flexible Field. If two blocks are used, this block is used for the upper bytes. 14:11…
43175 …the MAC-VLAN Cache Flexible Field. This block is only used if the number of bytes in mac_vlan_fle…
43176 … mac_vlan_flex_lower. A zero in this register will mask the corresponding bit in the flexible fie…
43177 … mac_vlan_flex_lower. A zero in this register will mask the corresponding bit in the flexible fie…
43178 … 0x1f09d0UL //Access:RW DataWidth:0x1 // Per-PF: If set, the SACK …
43179 …-FCoE packets. This allows Over-L2-Raw Part2 to be available on non-RoCE packets. The RoCE specifi…
43180 … 0x1f09d8UL //Access:RW DataWidth:0x20 // Per-PF: Mask used in RDMA…
43189 … 0x1f09fcUL //Access:RW DataWidth:0x1 // Per-PF: Enables SYN cooki…
43190 … 0x1f0a00UL //Access:RW DataWidth:0x1 // Per-PF: If set, enables i…
43191 …1 // Per-PF: If set, 4B for Ethernet CRC is included in Packet Length for Statistics field. For…
43192 …-PF: For each bit set, the length of the corresponding tag in the inner header will be subtracted …
43193 …-PF: For each bit set, the length of the corresponding tag in the first header will be subtracted …
43194 … 0x1f0a10UL //Access:RW DataWidth:0x1 // Per-Port: If set and clas…
43195 … 0x1f0a14UL //Access:RW DataWidth:0x8 // Per-Port: If classification failed, for each bi…
43196 …-Port: If classification failed, for each bit set, the length of the corresponding tag in the firs…
43197 … 0x1f0a1cUL //Access:RW DataWidth:0x20 // Per-PF: This value is passed to the per-PF …
43198 … 0x1f0a20UL //Access:RW DataWidth:0x2 // Per-Port: This value goes…
43199 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 0. In …
43200 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 0. In 4…
43201 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 1. In …
43202 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 1. In 4…
43203 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 2. In …
43204 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 2. In 4…
43205 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 3. In …
43206 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 3. In 4…
43207 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 4. In …
43208 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 4. In 4…
43209 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 5. In …
43210 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 5. In 4…
43211 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 6. In …
43212 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 6. In 4…
43213 …:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 7. In …
43214 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 7. In 4…
43215 …s:R DataWidth:0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 8. In 4…
43216 … 0x1f0a68UL //Access:RW DataWidth:0x3 // bit 0 - ignore for VXLAN, bit 1 - ignore for NGE, …
43222 …UL //Access:RC DataWidth:0x18 // The number of processed packets for TC 3. Counts packets as …
43233 …-port): Packet available status of the main and loopback queues of each traffic class, before bein…
43234 …dth:0x18 // Debug only (per-port): STORM backpressure status (blocked priorities) Each set bit r…
43236 …ue of the single entry in the CID load mini-cache is captured. 49: Valid, 48:40 - LCID, 39:32 - Re…
43238 …f0b68UL //Access:R DataWidth:0xd // Debug only: In the case of a mini-cache LCID validation…
43240 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
43241 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
43244 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
43245 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
43250 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
43251 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
43252 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
43253 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
43258 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
43259 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
43260 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
43261 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
43266 …kts sent to TCM: Reserved - 127:66, Parsing and Error flags - 65:50, Start block - 49:37, Priority…
43269 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
43270 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
43273 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
43274 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
43285 … Transaction based. Since the credit limit on this interface is 1, if this bit is high there is a …
43286 …Transaction based. Since the credit limit on this interface is 1, if this bit is high there is a …
43303 … 0x1f0f8cUL //Access:R DataWidth:0x20 // Provides read-only access to the BI…
43307 …-encasulated packet): 40.Source MAC 39.Destination MAC 38.VLAN (12b) ) � Tag 1 37.Provider VLAN (1…
43309 …-14 data 14-11 PF ID (3bit BB 4bit K2) 10-7 Tunnel type (4b) 0000-no tunnel 0001-vxlan 0010-GRE MA…
43324 …ld the priority field in the GFT used frame fields inner header 0- use CVLAN priority 1- use SVLAN…
43325 …d the priority field in the GFT used frame fields tunnel header 0- use CVLAN priority 1- use SVLAN…
43326 … 0x1f11bcUL //Access:RW DataWidth:0x1 // Per-PF: Enables gft searc…
43327 … 0x1f11c0UL //Access:RW DataWidth:0x1 // Per-PF: Enables gft search for non-IP pac…
43332 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43383 …// Context region for received Ethernet packet with a match and packet type 3. Used in CFC load re…
43384 …// Context region for received Ethernet packet with a match and packet type 3. Used in CFC load re…
43435 …:0x8 // Context region for pure acknowledge packets with connection type 3. Used in CFC load re…
43436 …:0x8 // Context region for pure acknowledge packets with connection type 3. Used in CFC load re…
43459 …Width:0x8 // The increment value to send in the CCFC load request message for connection type 3.
43460 …Width:0x8 // The increment value to send in the CCFC load request message for connection type 3.
43481 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43489 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43497 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43503 … (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 3
43505 …d connection type 3. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - …
43513 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43521 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43529 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43537 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43544 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43551 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43558 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43565 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43572 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43579 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43586 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43593 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43609 … // Ordered list of building blocks in TSTORM message for connection type 3. Unused blocks must …
43610 …20 // Ordered list of building blocks in PTLD message for connection type 3. Unused blocks must …
43611 … // Ordered list of building blocks in TSTORM message for connection type 3. Unused blocks must …
43612 …10 // Ordered list of building blocks in PTLD message for connection type 3. Unused blocks must …
43648 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43661 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43674 …sed in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - X…
43685 … 0x1f169cUL //Access:RW DataWidth:0x1 // 1- perform L2 CRC hash on TCP 4 tuple. 0- p…
43686 … 0x1f16a0UL //Access:RW DataWidth:0x1 // 1- perform L2 CRC hash on UDP 4 tuple. 0- p…
43706 …ataWidth:0x1 // Burst mode enabled. Set this bits to have the main round-robin arbiter stays o…
43713 …rom TX to RX. This loopback is on the line side after clock domain crossing - from the last TX pip…
43715 … (0x1<<3) // Local loopback from TX to RX. This loopback is on the core side be…
43716 …MAC_REG_CTRL_CORE_LOCAL_LPBK_BB_SHIFT 3
43717 …om RX to TX. This loopback is on the line side before clock domain crossing - from the first RX pi…
43719 …rom RX to TX. This loopback is on the core side after clock domain crossing - from the last RX pip…
43729 … (0x1<<10) // Resets the RS layer functionality - fault handling.
43731 …ide the one column idle/sequence ordered set check before SOP in XGMII mode - effectively supporti…
43740 …HG_BB (0x1<<3) // If set; exclude …
43741 …MAC_REG_MODE_NO_SOP_FOR_CRC_HG_BB_SHIFT 3
43751 …ART_BB (0x1<<3) // Don't force the …
43752 …MAC_REG_TX_CTRL_LO_TX_ANY_START_BB_SHIFT 3
43775 … (0x1<<1) // True to allow any non-Idle character to sta…
43779 … (0x1<<3) // If set; the MAC checks for IEEE Ethernet format premable - K.SOP + 5 '55' …
43780 …MAC_REG_RX_CTRL_STRICT_PREAMBLE_BB_SHIFT 3
43783 …inimum receive packet size is reduced to 18 bytes from the default 33 bytes - Should be used in MA…
43805 …; the TX faults inputs are used to send out fault sequences - else receive faults are used -- used…
43807 …ERRUPTION_DISABLE_BB (0x1<<3) // True to disable …
43808 …MAC_REG_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_BB_SHIFT 3
43825 … (0x1<<0) // A rising edge on this register bit (0->1); clears the sticky LOCAL_FAULT_STATUS…
43827 … (0x1<<1) // A rising edge on this register bit (0->1); clears the sticky REMOTE_FAULT_STATU…
43829 … (0x1<<2) // A rising edge on this register bit (0->1); clears the sticky LINK_INTERRUPTION_STA…
43832 …<<0) // This field is Threshold for pause timer to cause XOFF to be resent (Unit is 512 bit-times).
43844 …use_xoff_timer register. Time value sent in the Timer Field for XOFF state (Unit is 512 bit-times).
43846 …use_xoff_timer register. Time value sent in the Timer Field for XOFF state (Unit is 512 bit-times).
43848 … (0xffff<<0) // Threshold for pause timer to cause XOFF to be resent (Unit is 512 bit-times).
43850 …xffff<<16) // Time value sent in the Timer Field for classes in XOFF state (Unit is 512 bit-times).
43853 … (0x1<<0) // Enable automatic re-send of PFC packet af…
43859 …S_EN_BB (0x1<<3) // Set to enable in…
43860 …MAC_REG_PFC_CTRL_HI_PFC_STATS_EN_BB_SHIFT 3
43870 … (0x1<<0) // This bit enables llfc for Tx…
43872 … (0x1<<1) // This bit enables llfc for Rx…
43876 … (0x1<<3) // When set and llfc_in_ipg_only =0; GXPORT operat…
43877 …MAC_REG_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_BB_SHIFT 3
43878 … (0x1<<4) // This bit if set to 1; disabl…
43901 … (0x1<<0) // This bit enables HCFC for Tx…
43903 … (0x1<<1) // This bit enables HCFC for Rx…
43905 … (0x1<<2) // The crc check for HCFC messages is ignored if this bit is set.
43907 …_CRC_HCFC_BB (0x1<<3) // When set; HCFC C…
43908 …MAC_REG_HCFC_CTRL_NO_SOM_FOR_CRC_HCFC_BB_SHIFT 3
43922 …VERFLOW_BB (0x1<<3) // Indicates tx pac…
43923 …MAC_REG_FIFO_STATUS_TX_PKT_OVERFLOW_BB_SHIFT 3
43928 … (0x1<<7) // This bit indicates the link …
43931 … (0x1<<0) // A rising edge on this register bit (0->1); clears the sticky RX_PKT_OVERFLOW stat…
43933 … (0x1<<1) // A rising edge on this register bit (0->1); clears the sticky RX_MSG_OVERFLOW stat…
43935 … (0x1<<2) // A rising edge on this register bit (0->1); clears the sticky TX_PKT_UNDERFLOW sta…
43937 … (0x1<<3) // A rising edge on this register bit (0->1); clears the sticky T…
43938 …MAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_BB_SHIFT 3
43939 … (0x1<<4) // A rising edge on this register bit (0->1); clears the sticky TX_HCFC_MSG_OVERFLOW s…
43941 … (0x1<<5) // A rising edge on this register bit (0->1); clears the sticky TX_LLFC_MSG_OVERFLOW s…
43943 … (0x1<<6) // A rising edge on this register bit (0->1); clears the sticky TX_TS_FIFO_OVERFLOW st…
43946 … (0x3f<<0) // Credits for TX FIFO; used by Ports 0/1/2/3 in quad port mode.
43959 …_RX_PAUSE_ACTIVE_BB (0x1<<3) // If set; EEE FSM …
43960 …MAC_REG_EEE_CTRL_EEE_DISABLE_RX_PAUSE_ACTIVE_BB_SHIFT 3
43980 … (0x1<<2) // In CRC corruption mode; if this bit is set; replaces co…
43982 …TX_CRC_LO_BB (0x1fffffff<<3) // Lower 32 bits of…
43983 …MAC_REG_MACSEC_CTRL_LO_MACSEC_PROG_TX_CRC_LO_BB_SHIFT 3
43985 … 0x210130UL //Access:RW DataWidth:0x10 // XMAC IP Version ID - corresponds to RTL/D…
43986 …e fields within this WB register are: 1:0=XMAC CRC_MODE; 2:2=XMAC DISCARD; 3:3=XMAC TX_ANY_START; …
43996 …1=XMAC MACSEC_TX_CRC_CORRUPT_EN; 2:2=XMAC MACSEC_TX_CRC_CORRUPTION_MODE; 31:3=XMAC MACSEC_PROG_TX_…
44005 …<<1) // 00: Map to NWM port 0 01: Map to NWM port 1 10: Map to NWM port 2 11: Map to NWM port 3
44007 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 1…
44008 …NIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT 3
44011 …2_E5 (0x1<<7) // This bit controls the option…
44013 …T_EN_0_K2_E5 (0x1<<8) // This bit controls the option…
44015 …T_ON_ERROR_0_K2_E5 (0x1<<9) // This bit controls the option…
44017 …bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the …
44019 … (0xf<<11) // This 4 bit field sets the value of active cycles within a window of…
44021 … 2x40G (BB), NA (K2) 1 : 2x50G (BB), 2x20G (K2) 2 : 1x100G (BB), 1x40G (K2) 3 : 4x10G_F (BB) (10G …
44025 …<<1) // 00: Map to NWM port 0 01: Map to NWM port 1 10: Map to NWM port 2 11: Map to NWM port 3
44027 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 1…
44028 …NIG_REG_NIG_PORT1_CONF_NIG_PORT_RATE_1_K2_E5_SHIFT 3
44031 …2_E5 (0x1<<7) // This bit controls the option…
44033 …T_EN_1_K2_E5 (0x1<<8) // This bit controls the option…
44035 …T_ON_ERROR_1_K2_E5 (0x1<<9) // This bit controls the option…
44037 …bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the …
44039 … (0xf<<11) // This 4 bit field sets the value of active cycles within a window of…
44045 …<<1) // 00: Map to NWM port 0 01: Map to NWM port 1 10: Map to NWM port 2 11: Map to NWM port 3
44047 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 1…
44048 …NIG_REG_NIG_PORT2_CONF_NIG_PORT_RATE_2_K2_E5_SHIFT 3
44051 …2_E5 (0x1<<7) // This bit controls the option…
44053 …T_EN_2_K2_E5 (0x1<<8) // This bit controls the option…
44055 …T_ON_ERROR_2_K2_E5 (0x1<<9) // This bit controls the option…
44057 …bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the …
44059 … (0xf<<11) // This 4 bit field sets the value of active cycles within a window of…
44064 … (0x1<<1) // Setting this bit to 1 tells the inte…
44068 …e register addresses are index addresses, a 64bit register is considered a single register, the ne…
44077 …<<1) // 00: Map to NWM port 0 01: Map to NWM port 1 10: Map to NWM port 2 11: Map to NWM port 3
44079 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 1…
44080 …NIG_REG_NIG_PORT3_CONF_NIG_PORT_RATE_3_K2_E5_SHIFT 3
44083 …2_E5 (0x1<<7) // This bit controls the option…
44085 …T_EN_3_K2_E5 (0x1<<8) // This bit controls the option…
44087 …T_ON_ERROR_3_K2_E5 (0x1<<9) // This bit controls the option…
44089 …bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the …
44091 … (0xf<<11) // This 4 bit field sets the value of active cycles within a window of…
44101 …1<<0) // This regiseter enables loopback mode (used for debug) 0 - loopback inactive 1 - loopback …
44103 …3 => NIG RX port 3 1: mode1 is used with the following loopback mapping: NIG TX port 0 => NIG RX p…
44113 …_FRAME_K2_E5 (0x1<<3) // Set to 1 for mas…
44114 …NIG_REG_NWM_ERROR_MASK_SHORT_FRAME_K2_E5_SHIFT 3
44128 …e ADD CRC PORT STM occurs. It can result if a packet size is less than 256bit is sent by NIG (whi…
44134 …e ADD CRC PORT STM occurs. It can result if a packet size is less than 256bit is sent by NIG (whi…
44136 …OP_PORT2_K2_E5 (0x1<<3) // This interrupt i…
44137 …NIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT2_K2_E5_SHIFT 3
44148 …B (0x1<<3) // Error from an In…
44149 …NIG_REG_INT_STS_FIFO_ERROR_BB_SHIFT 3
44153 … (0x1<<0) // This bit masks, when set, the Interrupt bit: C…
44155 … (0x1<<4) // This bit masks, when set, the Interrupt bit: C…
44157 … (0x1<<1) // This bit masks, when set, the Interrupt bit: C…
44159 … (0x1<<2) // This bit masks, when set, the Interrupt bit: C…
44161 … (0x1<<5) // This bit masks, when set, the Interrupt bit: C…
44163 … (0x1<<3) // This bit masks, when set, the Interrupt …
44164 …NIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT2_K2_E5_SHIFT 3
44165 … (0x1<<4) // This bit masks, when set, the Interrupt bit: C…
44167 … (0x1<<5) // This bit masks, when set, the Interrupt bit: C…
44169 … (0x1<<6) // This bit masks, when set, the Interrupt bit: C…
44171 … (0x1<<1) // This bit masks, when set, the Interrupt bit: C…
44173 … (0x1<<2) // This bit masks, when set, the Interrupt bit: C…
44175 … (0x1<<3) // This bit masks, when set, the Interrupt …
44176 …NIG_REG_INT_MASK_FIFO_ERROR_BB_SHIFT 3
44180 … (0x1<<1) // Setting this bit to 1 tells the inte…
44184 …e register addresses are index addresses, a 64bit register is considered a single register, the ne…
44194 …e ADD CRC PORT STM occurs. It can result if a packet size is less than 256bit is sent by NIG (whi…
44200 …e ADD CRC PORT STM occurs. It can result if a packet size is less than 256bit is sent by NIG (whi…
44202 …L_SOP_PORT2_K2_E5 (0x1<<3) // This interrupt i…
44203 …NIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT2_K2_E5_SHIFT 3
44214 …R_BB (0x1<<3) // Error from an In…
44215 …NIG_REG_INT_STS_WR_FIFO_ERROR_BB_SHIFT 3
44227 …e ADD CRC PORT STM occurs. It can result if a packet size is less than 256bit is sent by NIG (whi…
44233 …e ADD CRC PORT STM occurs. It can result if a packet size is less than 256bit is sent by NIG (whi…
44235 …AL_SOP_PORT2_K2_E5 (0x1<<3) // This interrupt i…
44236 …NIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT2_K2_E5_SHIFT 3
44247 …OR_BB (0x1<<3) // Error from an In…
44248 …NIG_REG_INT_STS_CLR_FIFO_ERROR_BB_SHIFT 3
44255 … (0x1<<1) // This bit masks, when set, the Parity bit: CN…
44257 … (0x1<<0) // This bit masks, when set, the Parity bit: CN…
44262 …re control of the Traffic LED. The Traffic LED will then be controlled via bit LED_CONTROL_TRAFFIC…
44264 …ng with the LED_CONTROL_OVERRIDE_TRAFFIC bit turns on the Traffic LED. If the LED_CONTROL_BLINK_TR…
44266 … Port0: If set along with the LED_CONTROL_OVERRIDE_TRAFFIC bit and LED_CONTROL_TRAFFIC LED bit; th…
44268 … (0x1<<12) // This bit is set to enable the use of the LED_CONTROL_BLINK_RATE field de…
44270 … cycle (on + off) for Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field is …
44272 … DataWidth:0x8 // This register enable to read and write the cosmap 8 bit value for each NWM …
44274 … // Led mode: 0 -> MAC; 1-3 -> PHY1; 4 -> MAC2; 5-7 -> PHY4; 8 -> MAC3; 9 -…
44275 … // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 1…
44276 … // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 1…
44277 … // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 1…
44280 …-> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused Th…
44283 … corresponding Physical function. 0 -> NW0 connects to PF0 1 -> NW0 connects to PF1 2 -> NW0 co…
44285 … corresponding Physical function. 0 -> NW1 connects to PF0 1 -> NW1 connects to PF1 2 -> NW1 co…
44287 … corresponding Physical function. 0 -> NW2 connects to PF0 1 -> NW2 connects to PF1 2 -> NW2 co…
44289 … corresponding Physical function. 0 -> NW3 connects to PF0 1 -> NW3 connects to PF1 2 -> NW3 co…
44291 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
44292 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44293 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
44294 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44295 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
44296 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44297 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
44298 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44299 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44300 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44301 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44302 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44303 …h:0x1 // When set, PMIF block uses values in following registers to configure NIG - PM interface
44307 … is assigned to each PMEG Port. [1:0] -- PMEG Port 0 [3:2] -- PMEG Port 1 [5:4] -- PMEG Port 2 [7:…
44308 … is assigned to each PMFC Port. [1:0] -- PMFC Port 0 [3:2] -- PMFC Port 1 [5:4] -- PMFC Port 2 [7:…
44309 …e PMEG Port ID every cycle. Valid values are: 0 -- Only Port 0 is used 1 -- All Ports (0-3) are us…
44310 …e PMFC Port ID every cycle. Valid values are: 0 -- Only Port 0 is used 1 -- All Ports (0-3) are us…
44314 …ister latches the FIFO Error bits from the PMFC Rx FIFO (bit [4]) and the NIG Tx FIFOs (bits [3:0]…
44328 …G_DBG_PMEG_STATUS_PMEG_LANE1_STATUS_BB (0x7<<3) //
44329 …NIG_REG_CNIG_DBG_PMEG_STATUS_PMEG_LANE1_STATUS_BB_SHIFT 3
44337 …G_DBG_PMFC_STATUS_PMFC_LANE1_STATUS_BB (0x7<<3) //
44338 …NIG_REG_CNIG_DBG_PMFC_STATUS_PMFC_LANE1_STATUS_BB_SHIFT 3
44374 …FC ports 0,2 and should be used for 100G or 2x50G NW modes. Bit 0 - port0 CRC enable. Bit 1 - port…
44375 …FC ports 0,2 and should be used for 100G or 2x50G NW modes. Bit 0 - port0 CRC enable. Bit 1 - port…
44376 …rrupted independently from this register configuration. Bit 0 - port0 CRC corrupt enable. Bit 1 - …
44377 …rrupted independently from this register configuration. Bit 0 - port0 CRC corrupt enable. Bit 1 - …
44391 …OR (0x1<<3) // Overrun/underrun…
44392 …RM_REG_INT_STS_OFST_PEND_ERROR_SHIFT 3
44399 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44401 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44403 … (0x1<<7) // End of packet error on M-Storm command interfa…
44405 … (0x1<<8) // End of packet error on U-Storm command interfa…
44408 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
44410 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
44412 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
44414 … (0x1<<3) // This bit masks, when set, the Interrupt …
44415 …RM_REG_INT_MASK_OFST_PEND_ERROR_SHIFT 3
44416 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
44418 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
44420 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
44422 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
44424 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
44426 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
44428 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
44437 …ERROR (0x1<<3) // Overrun/underrun…
44438 …RM_REG_INT_STS_WR_OFST_PEND_ERROR_SHIFT 3
44445 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44447 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44449 … (0x1<<7) // End of packet error on M-Storm command interfa…
44451 … (0x1<<8) // End of packet error on U-Storm command interfa…
44460 …_ERROR (0x1<<3) // Overrun/underrun…
44461 …RM_REG_INT_STS_CLR_OFST_PEND_ERROR_SHIFT 3
44468 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44470 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44472 … (0x1<<7) // End of packet error on M-Storm command interfa…
44474 … (0x1<<8) // End of packet error on U-Storm command interfa…
44477 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
44480 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
44482 … (0x1<<0) // This bit masks, when set, the Parity bit: PR…
44484 … (0x1<<1) // This bit masks, when set, the Parity bit: PR…
44486 … (0x1<<1) // This bit masks, when set, the Parity bit: PR…
44488 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
44490 … (0x1<<3) // This bit masks, when set, the Parity bi…
44491 …RM_REG_PRTY_MASK_H_0_MEM024_I_ECC_RF_INT_E5_SHIFT 3
44492 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
44494 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
44496 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
44498 … (0x1<<7) // This bit masks, when set, the Parity bit: PR…
44500 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
44502 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
44504 … (0x1<<7) // This bit masks, when set, the Parity bit: PR…
44506 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
44508 … (0x1<<8) // This bit masks, when set, the Parity bit: PR…
44510 … (0x1<<8) // This bit masks, when set, the Parity bit: PR…
44512 … (0x1<<9) // This bit masks, when set, the Parity bit: PR…
44514 … (0x1<<9) // This bit masks, when set, the Parity bit: PR…
44516 … (0x1<<10) // This bit masks, when set, the Parity bit: PR…
44518 … (0x1<<11) // This bit masks, when set, the Parity bit: PR…
44520 … (0x1<<11) // This bit masks, when set, the Parity bit: PR…
44522 … (0x1<<6) // This bit masks, when set, the Parity bit: PR…
44524 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
44526 … (0x1<<10) // This bit masks, when set, the Parity bit: PR…
44528 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
44530 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
44532 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
44534 … (0x1<<13) // This bit masks, when set, the Parity bit: PR…
44536 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
44538 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
44540 … (0x1<<14) // This bit masks, when set, the Parity bit: PR…
44542 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
44544 … (0x1<<4) // This bit masks, when set, the Parity bit: PR…
44546 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
44548 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
44550 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
44552 … (0x1<<15) // This bit masks, when set, the Parity bit: PR…
44554 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
44556 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
44558 … (0x1<<17) // This bit masks, when set, the Parity bit: PR…
44560 … (0x1<<18) // This bit masks, when set, the Parity bit: PR…
44562 … (0x1<<19) // This bit masks, when set, the Parity bit: PR…
44564 … (0x1<<19) // This bit masks, when set, the Parity bit: PR…
44566 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
44568 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
44570 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
44572 … (0x1<<22) // This bit masks, when set, the Parity bit: PR…
44574 … (0x1<<23) // This bit masks, when set, the Parity bit: PR…
44576 … (0x1<<23) // This bit masks, when set, the Parity bit: PR…
44578 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
44580 … (0x1<<24) // This bit masks, when set, the Parity bit: PR…
44582 … (0x1<<22) // This bit masks, when set, the Parity bit: PR…
44584 … (0x1<<20) // This bit masks, when set, the Parity bit: PR…
44586 … (0x1<<25) // This bit masks, when set, the Parity bit: PR…
44588 … (0x1<<3) // This bit masks, when set, the Parity bi…
44589 …RM_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT_K2_SHIFT 3
44590 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
44592 … (0x1<<5) // This bit masks, when set, the Parity bit: PR…
44594 … (0x1<<21) // This bit masks, when set, the Parity bit: PR…
44596 … (0x1<<16) // This bit masks, when set, the Parity bit: PR…
44598 … (0x1<<2) // This bit masks, when set, the Parity bit: PR…
44600 … (0x1<<3) // This bit masks, when set, the Parity bi…
44601 …RM_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_BB_SHIFT 3
44602 … (0x1<<12) // This bit masks, when set, the Parity bit: PR…
44604 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
44605 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
44606 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
44607 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
44608 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
44609 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
44621 …24_I_ECC_EN_E5 (0x1<<3) // Enable ECC for m…
44622 …RM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_EN_E5_SHIFT 3
44623 …20_I_ECC_EN_K2 (0x1<<3) // Enable ECC for m…
44624 …RM_REG_MEM_ECC_ENABLE_0_MEM020_I_ECC_EN_K2_SHIFT 3
44627 …21_I_ECC_EN_BB (0x1<<3) // Enable ECC for m…
44628 …RM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN_BB_SHIFT 3
44640 …_MEM024_I_ECC_PRTY_E5 (0x1<<3) // Set parity only …
44641 …RM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_PRTY_E5_SHIFT 3
44642 …_MEM020_I_ECC_PRTY_K2 (0x1<<3) // Set parity only …
44643 …RM_REG_MEM_ECC_PARITY_ONLY_0_MEM020_I_ECC_PRTY_K2_SHIFT 3
44646 …_MEM021_I_ECC_PRTY_BB (0x1<<3) // Set parity only …
44647 …RM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY_BB_SHIFT 3
44659 …ED_0_MEM024_I_ECC_CORRECT_E5 (0x1<<3) // Record if a corr…
44660 …RM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_CORRECT_E5_SHIFT 3
44661 …ED_0_MEM020_I_ECC_CORRECT_K2 (0x1<<3) // Record if a corr…
44662 …RM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM020_I_ECC_CORRECT_K2_SHIFT 3
44665 …ED_0_MEM021_I_ECC_CORRECT_BB (0x1<<3) // Record if a corr…
44666 …RM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT_BB_SHIFT 3
44670 … 0x230420UL //Access:RW DataWidth:0x10 // Provides the value of the 16-bit pad that will be in…
44671 … 0x230424UL //Access:RW DataWidth:0x1 // When set, this bit enables the pad ins…
44673 … Initial credit to be used on the RDIF command interface for regular (non-pass-through) requests. …
44674 …on the RDIF command interface for pass-through requests. This value defines the maximum number of …
44678 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
44679 …th:0x9 // Defines the number of occupied entries required in the PXP read-response FIFO before …
44680 … DataWidth:0x20 // Statistics counter provides a count of the number of M-Storm comands that ha…
44681 … DataWidth:0x20 // Statistics counter provides a count of the number of U-Storm comands that ha…
44706 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
44707 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
44708 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
44709 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
44710 … 0x232000UL //Access:WB_R DataWidth:0x80 // Provides read-only access of the M-Storm comma…
44712 … 0x232400UL //Access:WB_R DataWidth:0x80 // Provides read-only access of the U-Storm comma…
44714 … 0x232800UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the BR…
44716 … 0x232c00UL //Access:R DataWidth:0x7 // Provides read-only access of the BR…
44718 … 0x233000UL //Access:WB_R DataWidth:0x2c // Provides read-only access of the ta…
44720 … 0x233400UL //Access:R DataWidth:0x11 // Provides read-only access of the pa…
44722 … 0x233600UL //Access:R DataWidth:0xb // Provides read-only access of the PB…
44724 … 0x233800UL //Access:WB_R DataWidth:0x100 // Provides read-only access of the PR…
44726 … 0x233c00UL //Access:R DataWidth:0x8 // Provides read-only access of the PXP write-done re…
44730 … 0x236000UL //Access:RW DataWidth:0x1 // Chicken Bit for the NOP without…
44760 … (0x1<<0) // This bit masks, when set, the Interrupt bit: S…
44773 … 0x238480UL //Access:RW DataWidth:0x10 // Per-PF Bitmask for inclus…
44774 … 0x238484UL //Access:RW DataWidth:0x8 // Per-StringType Bitmask fo…
44775 …Bit. IF Stat Counters only count when this bit is set. This bit is cleared when any IF Stat C…
44790 …_T1 (0x1<<3) // Controls PXP Req…
44791 …RC_REG_PXP_CTRL_PXP_TPHVALID_T1_SHIFT 3
44799 … 0x238620UL //Access:RW DataWidth:0x20 // Empty bit per bin 256 bins pe…
44802 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
44803 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
44804 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
44805 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
44821 …_E5 (0x1<<3) // RGFS output inte…
44822 …SS_REG_IF_ENABLE_RGFS_OUT_EN_E5_SHIFT 3
44825 …_BB_K2 (0x1<<3) // TSEM output inte…
44826 …SS_REG_IF_ENABLE_TSEM_OUT_EN_BB_K2_SHIFT 3
44864 …OR_BB_K2 (0x1<<3) // Input state mach…
44865 …SS_REG_INT_STS_INP_STATE_ERROR_BB_K2_SHIFT 3
44873 … (0x1<<0) // This bit masks, when set, the Interrupt bit: R…
44875 … (0x1<<7) // This bit masks, when set, the Interrupt bit: R…
44877 … (0x1<<8) // This bit masks, when set, the Interrupt bit: R…
44879 … (0x1<<9) // This bit masks, when set, the Interrupt bit: R…
44881 … (0x1<<10) // This bit masks, when set, the Interrupt bit: R…
44883 … (0x1<<11) // This bit masks, when set, the Interrupt bit: R…
44885 … (0x1<<12) // This bit masks, when set, the Interrupt bit: R…
44887 … (0x1<<13) // This bit masks, when set, the Interrupt bit: R…
44889 … (0x1<<14) // This bit masks, when set, the Interrupt bit: R…
44891 … (0x1<<15) // This bit masks, when set, the Interrupt bit: R…
44893 … (0x1<<16) // This bit masks, when set, the Interrupt bit: R…
44895 … (0x1<<17) // This bit masks, when set, the Interrupt bit: R…
44897 … (0x1<<18) // This bit masks, when set, the Interrupt bit: R…
44899 … (0x1<<19) // This bit masks, when set, the Interrupt bit: R…
44901 … (0x1<<20) // This bit masks, when set, the Interrupt bit: R…
44903 … (0x1<<21) // This bit masks, when set, the Interrupt bit: R…
44905 … (0x1<<1) // This bit masks, when set, the Interrupt bit: R…
44907 … (0x1<<2) // This bit masks, when set, the Interrupt bit: R…
44909 … (0x1<<3) // This bit masks, when set, the Interrupt …
44910 …SS_REG_INT_MASK_INP_STATE_ERROR_BB_K2_SHIFT 3
44911 … (0x1<<4) // This bit masks, when set, the Interrupt bit: R…
44913 … (0x1<<5) // This bit masks, when set, the Interrupt bit: R…
44915 … (0x1<<6) // This bit masks, when set, the Interrupt bit: R…
44954 …ERROR_BB_K2 (0x1<<3) // Input state mach…
44955 …SS_REG_INT_STS_WR_INP_STATE_ERROR_BB_K2_SHIFT 3
44999 …_ERROR_BB_K2 (0x1<<3) // Input state mach…
45000 …SS_REG_INT_STS_CLR_INP_STATE_ERROR_BB_K2_SHIFT 3
45008 … (0x1<<0) // This bit masks, when set, the Parity bit: RS…
45010 … (0x1<<1) // This bit masks, when set, the Parity bit: RS…
45012 … (0x1<<2) // This bit masks, when set, the Parity bit: RS…
45014 … (0x1<<3) // This bit masks, when set, the Parity bi…
45015 …SS_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_E5_SHIFT 3
45016 … (0x1<<4) // This bit masks, when set, the Parity bit: RS…
45018 … (0x1<<5) // This bit masks, when set, the Parity bit: RS…
45020 … (0x1<<0) // This bit masks, when set, the Parity bit: RS…
45022 … (0x1<<1) // This bit masks, when set, the Parity bit: RS…
45024 … (0x1<<2) // This bit masks, when set, the Parity bit: RS…
45026 … (0x1<<3) // This bit masks, when set, the Parity bi…
45027 …SS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT 3
45035 …04_I_ECC_EN_E5 (0x1<<3) // Enable ECC for m…
45036 …SS_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_E5_SHIFT 3
45048 …_MEM004_I_ECC_PRTY_E5 (0x1<<3) // Set parity only …
45049 …SS_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_E5_SHIFT 3
45061 …ED_0_MEM004_I_ECC_CORRECT_E5 (0x1<<3) // Record if a corr…
45062 …SS_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_E5_SHIFT 3
45070 … 0x238c10UL //Access:WB DataWidth:0x80 // RSS RAM bit enable. It will be …
45074 …bit 12 is 1 then bits 11:0 is addr to RSS indirection memory. If bits 12:10 are 0 then bits 6:0 is…
45076 … // Debug register. FIFO empty status: {b0 - MSG FIFO; b1- RSS CMD FIFO; b2- INPUT FIFO; b3 - RSP…
45077 … // Debug register. FIFO empty status: {b0 - MSG FIFO; b1- RSS CMD FIFO; b2- INPUT FIFO; b3 - RSP…
45078 …0x20 // Debug register. FIFO empty status: {b15:8 - inp_fifo_counter; b7:6- cmd_fifo_couter; b5:…
45079 …ster. State of each state machine {b15:12 - calc_cur_state; b11:8 - main_cur_state;b7:4 - msg_cur_…
45082 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
45083 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
45084 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
45085 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
45101 …H_FIFO_FULL_E5 (0x1<<3) // The hash fifo is…
45102 …SS_REG_FIFO_FULL_STATUS1_HASH_FIFO_FULL_E5_SHIFT 3
45128 …SH_FIFO_EMPTY_E5 (0x1<<3) // The hash fifo is…
45129 …SS_REG_FIFO_EMPTY_STATUS1_HASH_FIFO_EMPTY_E5_SHIFT 3
45195 … (0x1<<3) // Parameter FIFO e…
45196 …PB_REG_INT_STS_PFIFO_ERROR_SHIFT 3
45208 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
45210 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
45212 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
45214 … (0x1<<3) // This bit masks, when set, the Interrupt …
45215 …PB_REG_INT_MASK_PFIFO_ERROR_SHIFT 3
45216 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
45218 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
45220 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
45222 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
45224 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
45233 …R (0x1<<3) // Parameter FIFO e…
45234 …PB_REG_INT_STS_WR_PFIFO_ERROR_SHIFT 3
45252 …OR (0x1<<3) // Parameter FIFO e…
45253 …PB_REG_INT_STS_CLR_PFIFO_ERROR_SHIFT 3
45265 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
45274 …ABLE (0x1<<3) // Disables EOP che…
45275 …PB_REG_CONTROL_EOP_CHECK_DISABLE_SHIFT 3
45286 …ived on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
45288 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
45289 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
45290 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
45291 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
45292 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
45293 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
45294 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
45295 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
45296 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
45297 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
45298 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
45299 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
45310 …bit of this register. Bits 31:29 provide additional information about the instruction. Bit 31 in…
45312 …er being executed at the time EOP error is detected. The task passthrough bit is not kept and is …
45320 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
45321 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
45322 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
45323 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
45324 … 0x23e000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
45330 …x1 // MCP writes '1' to this bit to indicate PSWRQ to initialize Steering Tag Table with zeros.…
45331 …x4 // Page size in L2P table for CDU-Task module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-51…
45332 … // Page size in L2P table for CDU module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45333 …4 // Page size in L2P table for TM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45334 …4 // Page size in L2P table for QM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45335 … // Page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45336 … // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45337 … // Page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45338 … // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45339 … // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45346 … 0x240048UL //Access:RW DataWidth:0xe // First memory address base for cdu-connection in ILT.
45347 … 0x24004cUL //Access:RW DataWidth:0xe // Last memory address base for cdu-connection in ILT.
45348 … 0x240050UL //Access:RW DataWidth:0xe // First memory address base for cdu-task in ILT.
45349 … 0x240054UL //Access:RW DataWidth:0xe // Last memory address base for cdu-task in ILT.
45361 …:RW DataWidth:0x2 // Requests from all SDM's and DMAE with endian mode 3 will receive the end…
45378 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
45379 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
45380 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
45381 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
45387 … (0x1<<1) // Overflow in l2p input fifo - removed in E4.
45391 … (0x1<<3) // Overflow of phy addr fifo - remo…
45392 …SWRQ2_REG_INT_STS_PHYADDR_FIFO_OF_SHIFT 3
45393 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45395 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45397 …tten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5.
45401 …) // E4: Indicates a request with: 1. Logical address. 2. Function is a VF. 3. Client is NOT (TM;C…
45403 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5.
45405 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45407 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45409 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45411 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45413 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45422 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
45424 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
45426 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
45428 … (0x1<<3) // This bit masks, when set, the Interrupt …
45429 …SWRQ2_REG_INT_MASK_PHYADDR_FIFO_OF_SHIFT 3
45430 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
45432 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
45434 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
45436 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
45438 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
45440 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
45442 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
45444 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
45446 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
45448 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
45450 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
45452 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
45454 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
45456 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
45461 … (0x1<<1) // Overflow in l2p input fifo - removed in E4.
45465 … (0x1<<3) // Overflow of phy addr fifo - remo…
45466 …SWRQ2_REG_INT_STS_WR_PHYADDR_FIFO_OF_SHIFT 3
45467 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45469 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45471 …tten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5.
45475 …) // E4: Indicates a request with: 1. Logical address. 2. Function is a VF. 3. Client is NOT (TM;C…
45477 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5.
45479 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45481 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45483 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45485 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45487 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45498 … (0x1<<1) // Overflow in l2p input fifo - removed in E4.
45502 … (0x1<<3) // Overflow of phy addr fifo - remo…
45503 …SWRQ2_REG_INT_STS_CLR_PHYADDR_FIFO_OF_SHIFT 3
45504 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45506 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45508 …tten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5.
45512 …) // E4: Indicates a request with: 1. Logical address. 2. Function is a VF. 3. Client is NOT (TM;C…
45514 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5.
45516 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45518 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45520 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45522 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45524 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45533 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
45535 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
45537 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
45539 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
45541 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
45543 … (0x1<<3) // This bit masks, when set, the Parity bi…
45544 …SWRQ2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_E5_SHIFT 3
45545 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
45547 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
45549 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
45551 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
45553 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
45555 … (0x1<<3) // This bit masks, when set, the Parity bi…
45556 …SWRQ2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT 3
45557 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
45559 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
45561 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
45563 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
45565 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
45567 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
45569 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
45571 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
45573 … (0x1<<3) // This bit masks, when set, the Parity bi…
45574 …SWRQ2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_SHIFT 3
45575 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
45577 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
45578 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
45596 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
45634 …W DataWidth:0x3 // Max burst size filed for write requests port 0; 000 - 128B; 001:256B; 010:…
45635 …RW DataWidth:0x3 // Max burst size filed for read requests port 0; 000 - 128B; 001:256B; 010:…
45638 …n a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B…
45639 …n a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B…
45653 …DataWidth:0x8 // Initial value of global counter; This value MUST be 256 - sum of all clients t…
45662 … 0x240460UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 3 in pswrq memory.
45694 … 0x2404e0UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 3.
46001 … 0x2406a0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ5 Read- currently not used.
46104 … (0xf<<0) // Indicates the number of credits for read sub-requests in th reques…
46106 … (0x1f<<4) // Indicates the number of credits for write sub-requests in th reques…
46111 … 0x240724UL //Access:RW DataWidth:0x5 // Sets which vq head pointer to see out of queues 0-31.
46112 … 0x240728UL //Access:RW DataWidth:0x5 // Sets which vq tail pointer to see out of queues 0-31.
46146 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46147 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46148 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46149 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46150 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46151 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46152 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46153 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46154 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46155 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46156 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46157 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46158 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46159 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46160 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46161 …- SR from the VQ can send ATC lookup request to the ATC (assuming all other conditions are met). W…
46162 …ws: b0 - PF enable; b1 - VF enable; PF enable bit is relevant when VF_Valid (in the request) bit i…
46163 …ues of rq_atc_internal_ats_enable as follows: b0 - PF0; b1 - VF0; b2 - PF1; b3 - VF1; b30 - PF15 ;…
46164 …bit per VQ. go translated set means that SR of the matched VQ will be always sent to the GLUE with…
46165 … 0x2407fcUL //Access:RW DataWidth:0x1 // Global ATC enable bit. when reset all ATC…
46166 … 0x240800UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i…
46167 … 0x240804UL //Access:RW DataWidth:0x2 // VQ-s that are enabled (i…
46168 … 0x240808UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i…
46169 … 0x24080cUL //Access:RW DataWidth:0x2 // VQ-s that are enabled (i…
46170 … 0x240810UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i…
46171 … // VQ-s that are enabled (i.e. can be chosen by the GARB) in stall int scenario; VQ32 = TREQ; VQ…
46175 …- assert ilt fail interrupt (rq_elt_addr) in case working in ilt mode and onchip translation fail …
46178 …FOR DBG: when set - data rd from hoq ram is completed (i.e. data is ready in data_rd_0 data_rd_1 d…
46182 …// FOR DBG: bit 0 relaxed ordering; bit 1 no-snoop; bits 5:2 client id; bit 6 done type; bit 7 res…
46183 … 0x240844UL //Access:R DataWidth:0x20 // The total number of WR SR-s that were sent to t…
46184 … 0x240848UL //Access:R DataWidth:0x20 // The total number of RD SR-s that were sent to t…
46185 … 0x24084cUL //Access:R DataWidth:0x20 // The number of PBF RD SR-s that were sent to t…
46186 … 0x240850UL //Access:R DataWidth:0x20 // The number of USDM-DP WR SR-s that were sent …
46187 … 0x240854UL //Access:R DataWidth:0x20 // The number of TREQ SR-s that were sent to t…
46188 … 0x240858UL //Access:R DataWidth:0x20 // The number of ICPL SR-s that were sent to t…
46189 …20 // The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46190 …9 // The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46191 …20 // The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46192 …c // The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46193 …0x20 // The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46194 …0xc // The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46195 …:0x20 // The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_…
46196 …:0x9 // The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_…
46197 … // Counting window mode. 0 - manual window: counting is manually being initiated & stopped by t…
46200 …en working in manual window mode (i.e. Sr_cnt_window_mode = 0). 0 - stop counting. 1 - start count…
46202 …global window counter). 0 - start counting upon any first SR that is sent to the PGLUE. 1 - start …
46205 …atus of the SR count mechanism: 0 - idle: ready to start new counting. 1 - ongoing: counting is cu…
46206 … 0x2408a0UL //Access:R DataWidth:0x20 // SR address - 32 lsb.
46207 … 0x2408a4UL //Access:R DataWidth:0x20 // SR address - 32 msb.
46208 … 0x2408a8UL //Access:R DataWidth:0x20 // B15-0: reqid; b28-16: SR length; b29 - reserved; b…
46209 …dth:0x20 // B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15: client …
46210 … 0x2408b0UL //Access:R DataWidth:0x9 // bit 8-0: srid.
46211 … 0x2408b4UL //Access:R DataWidth:0x20 // SR address - 32 lsb.
46212 … 0x2408b8UL //Access:R DataWidth:0x20 // SR address - 32 msb.
46213 … 0x2408bcUL //Access:R DataWidth:0x20 // B15-0: reqid; b28-16: SR length; b29 - reserved; b…
46214 … DataWidth:0x20 // B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15…
46215 … 0x2408c4UL //Access:R DataWidth:0xa // b1-0: atc code; b2: wdone type; b4-3: endianity; …
46243 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46244 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46245 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46246 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46247 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46258 …l2p_vf_err or rq_elt_addr interrupt. [12:0] - Length in bytes. [16:13] - PFID. [17] - VF_VALID. …
46259 …:16] client ID. [21] - Error type - 0 - rq_l2p_vf_err; 1 - rq_elt_addr. [22] - w_nr - 0 - read; 1 …
46261 …:RW DataWidth:0x9 // Debug only: Total number of available PCI read sub-requests. Must be big…
46263 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46264 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46265 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46266 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46267 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46268 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46269 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46270 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46271 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46272 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46273 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46274 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46275 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46276 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46277 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46278 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46279 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46280 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46281 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46282 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46283 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46284 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46285 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46286 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46287 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46288 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46289 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46290 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46291 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46294 …ed for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.
46295 … 0x2409c4UL //Access:R DataWidth:0x9 // Debug only: The SR counter - number of unused sub…
46328 …0x240a48UL //Access:R DataWidth:0xa // Debug only: The blocks counter - number of unused blo…
46391 … 0x240b44UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46392 … 0x240b48UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46393 … 0x240b4cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46394 … 0x240b50UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46395 … 0x240b54UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46396 … 0x240b58UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46397 … 0x240b5cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46398 … 0x240b60UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46399 … 0x240b64UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46400 … 0x240b68UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46401 … 0x240b6cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46402 … 0x240b70UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46403 … 0x240b74UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46404 … 0x240b78UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46405 … 0x240b7cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46406 … 0x240b80UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46407 … 0x240b84UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46408 … 0x240b88UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46409 … 0x240b8cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46410 … 0x240b90UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46411 … 0x240b94UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46412 … 0x240b98UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46413 … 0x240b9cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46414 … 0x240ba0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46415 … 0x240ba4UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46416 … 0x240ba8UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46417 … 0x240bacUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46418 … 0x240bb0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46419 … 0x240bb4UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46420 … 0x240bb8UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46421 … 0x240bbcUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46422 … 0x240bc0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46429 …n if no BWC is greater or equal to Li. Default value: 0. This is a chicken bit in case there are p…
46430 … 0 - the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW count…
46431 …- the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW counters…
46432 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46433 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46434 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46435 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46436 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46437 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46438 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46439 …priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46440 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46441 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46442 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46443 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46444 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46445 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46446 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46447 … priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE:…
46448 …-PGLUE request interface write credit; 0 - no more credit for wr SR-s (i.e. write SR-s cannot be s…
46449 …-PGLUE request interface read credit; 0 - no more credit for rd SR-s (i.e. read SR-s cannot be sen…
46450 …can be a workaround for possible bugs in the byte counters. Id-s are based on wr client id-s (take…
46451 …-1] between qc_cmg_add_2_q (indication that new request is written into hoq0) and cmg_qc_del_head …
46452 …-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_…
46453 …-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_…
46454 … 0x240c40UL //Access:R DataWidth:0xe // For debug and Idle-check use. The value …
46456 …ite done for them from the PGLUE). Upon reaching the threshold no more wr SR-s will be sent by the…
46462 … 0x240c60UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 3
46491 …bit is set, client can push request to this VQ. Map TSDM to VQs: bit 0 is mapped to VQID 6. bit 1 …
46492 …bit is set, client can push request to this VQ. Map MSDM to VQs: bit 0 is mapped to VQID 6. bit 1 …
46493 …bit is set, client can push request to this VQ. Map USDM to VQs: bit 0 is mapped to VQID 6. bit 1 …
46494 …bit is set, client can push request to this VQ. Map XSDM to VQs: bit 0 is mapped to VQID 6. bit 1 …
46495 …bit is set, client can push request to this VQ. Map YSDM to VQs: bit 0 is mapped to VQID 6. bit 1 …
46496 …bit is set, client can push request to this VQ. Map PSDM to VQs: bit 0 is mapped to VQID 6. bit 1 …
46497 …bit is set, client can push request to this VQ. Map M2P to VQs: bit 0 is mapped to VQID 6. bit 1 i…
46513 … // Page size in L2P table for tgsrc module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
46514 … // Page size in L2P table for RGSRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
46552 …5 // Internal lookup table for logical to physical address translation. Re-instantiated in E4 du…
46559 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
46560 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
46561 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
46562 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
46573 …RFLOW (0x1<<3) // Overflow in qm r…
46574 …SWRQ_REG_INT_STS_QM_FIFO_OVERFLOW_SHIFT 3
46614 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
46616 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
46618 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
46620 … (0x1<<3) // This bit masks, when set, the Interrupt …
46621 …SWRQ_REG_INT_MASK_QM_FIFO_OVERFLOW_SHIFT 3
46622 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
46624 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
46626 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
46628 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
46630 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
46632 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
46634 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
46636 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
46638 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
46640 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
46642 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
46644 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
46646 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
46648 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
46650 … (0x1<<18) // This bit masks, when set, the Interrupt bit: P…
46652 … (0x1<<19) // This bit masks, when set, the Interrupt bit: P…
46654 … (0x1<<20) // This bit masks, when set, the Interrupt bit: P…
46656 … (0x1<<21) // This bit masks, when set, the Interrupt bit: P…
46658 … (0x1<<22) // This bit masks, when set, the Interrupt bit: P…
46667 …OVERFLOW (0x1<<3) // Overflow in qm r…
46668 …SWRQ_REG_INT_STS_WR_QM_FIFO_OVERFLOW_SHIFT 3
46714 …_OVERFLOW (0x1<<3) // Overflow in qm r…
46715 …SWRQ_REG_INT_STS_CLR_QM_FIFO_OVERFLOW_SHIFT 3
46755 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
46772 …bit indicates if full is asserted towards the client. The clients order is according to the increm…
46773 …bit indicates if full was asserted since reset towards the client. The clients order is according …
46775 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
46776 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
46777 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
46778 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
46794 …RFLOW (0x1<<3) // Overflow in tm f…
46795 …SWWR_REG_INT_STS_TM_FIFO_OVERFLOW_SHIFT 3
46827 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
46829 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
46831 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
46833 … (0x1<<3) // This bit masks, when set, the Interrupt …
46834 …SWWR_REG_INT_MASK_TM_FIFO_OVERFLOW_SHIFT 3
46835 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
46837 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
46839 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
46841 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
46843 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
46845 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
46847 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
46849 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
46851 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
46853 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
46855 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
46857 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
46859 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
46861 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
46863 … (0x1<<18) // This bit masks, when set, the Interrupt bit: P…
46872 …OVERFLOW (0x1<<3) // Overflow in tm f…
46873 …SWWR_REG_INT_STS_WR_TM_FIFO_OVERFLOW_SHIFT 3
46911 …_OVERFLOW (0x1<<3) // Overflow in tm f…
46912 …SWWR_REG_INT_STS_CLR_TM_FIFO_OVERFLOW_SHIFT 3
46944 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
46948 …3 EOP interrupts: [4:0] - client ID. [7:5] - (sum1[5:3] + 1) or (sum1[5:4] + 1) according to the d…
46956 …0x29b068UL //Access:RW DataWidth:0x7 // If Number of entries in the PRM-secondary internal fi…
46957 … 0x29b06cUL //Access:R DataWidth:0x7 // Current internal PRM-secondary fill level …
46958 … 0x29b070UL //Access:R DataWidth:0x7 // Maximum internal PRM-secondary fill level …
46966 …OW (0x1<<3) // Underflow in the…
46967 …SWWR2_REG_INT_STS_TM_UNDERFLOW_SHIFT 3
46996 …he last read request from the glue block; but the number of valid 128-bit or 64-bit words in the m…
47005 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
47007 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
47009 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
47011 … (0x1<<3) // This bit masks, when set, the Interrupt …
47012 …SWWR2_REG_INT_MASK_TM_UNDERFLOW_SHIFT 3
47013 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
47015 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
47017 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
47019 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
47021 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
47023 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
47025 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
47027 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
47029 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
47031 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
47033 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
47035 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
47037 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
47039 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
47041 … (0x1<<18) // This bit masks, when set, the Interrupt bit: P…
47043 … (0x1<<19) // This bit masks, when set, the Interrupt bit: P…
47045 … (0x1<<20) // This bit masks, when set, the Interrupt bit: P…
47047 … (0x1<<21) // This bit masks, when set, the Interrupt bit: P…
47056 …RFLOW (0x1<<3) // Underflow in the…
47057 …SWWR2_REG_INT_STS_WR_TM_UNDERFLOW_SHIFT 3
47086 …he last read request from the glue block; but the number of valid 128-bit or 64-bit words in the m…
47101 …ERFLOW (0x1<<3) // Underflow in the…
47102 …SWWR2_REG_INT_STS_CLR_TM_UNDERFLOW_SHIFT 3
47131 …he last read request from the glue block; but the number of valid 128-bit or 64-bit words in the m…
47140 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47143 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47145 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47147 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47149 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47151 … (0x1<<3) // This bit masks, when set, the Parity bi…
47152 …SWWR2_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_0_E5_SHIFT 3
47153 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47155 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47157 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47159 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47161 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47163 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47165 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47167 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47169 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47171 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47173 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47175 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47177 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47179 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47181 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47183 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47185 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47187 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47189 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47191 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47193 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47195 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47197 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47199 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47201 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47203 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47205 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47207 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47209 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47211 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47213 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47215 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47217 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47219 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47221 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47223 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47225 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47227 … (0x1<<3) // This bit masks, when set, the Parity bi…
47228 …SWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_1_BB_K2_SHIFT 3
47229 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47231 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47233 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47235 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47237 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47239 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47241 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47243 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47245 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47247 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47249 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47251 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47253 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47255 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47257 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47259 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47261 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47263 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47266 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47268 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47270 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47272 … (0x1<<3) // This bit masks, when set, the Parity bi…
47273 …SWWR2_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_4_E5_SHIFT 3
47274 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47276 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47278 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47280 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47282 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47284 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47286 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47288 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47290 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47292 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47294 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47296 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47298 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47300 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47302 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47304 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47306 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47308 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47310 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47312 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47314 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47316 … (0x1<<3) // This bit masks, when set, the Parity bi…
47317 …SWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_5_BB_K2_SHIFT 3
47318 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47320 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47322 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47324 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47326 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47328 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47330 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47332 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47334 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47336 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47338 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47340 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47342 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47344 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47346 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47348 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47350 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47352 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47354 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47356 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47358 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47360 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47362 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47364 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47366 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47368 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47370 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47372 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47374 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47376 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47378 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47380 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47382 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47384 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47386 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47388 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47391 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47393 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47395 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47397 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47399 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47401 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47403 … (0x1<<3) // This bit masks, when set, the Parity bi…
47404 …SWWR2_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_8_E5_SHIFT 3
47405 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47407 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47409 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47411 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47413 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47415 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47417 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47419 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47421 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47423 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47425 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47427 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47429 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47431 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47433 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47435 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47437 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47439 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47441 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47443 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47445 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47447 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47449 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47451 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47453 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47455 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47457 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47459 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47461 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47463 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47465 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47467 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47469 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47471 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47473 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47475 … (0x1<<3) // This bit masks, when set, the Parity bi…
47476 …SWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_0_BB_K2_SHIFT 3
47477 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47479 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47481 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47483 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47485 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47487 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47489 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47491 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47493 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47495 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47497 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47499 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47501 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47503 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47505 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47507 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47509 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47511 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47513 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47516 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47518 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47520 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47522 … (0x1<<3) // This bit masks, when set, the Parity bi…
47523 …SWWR2_REG_PRTY_MASK_H_3_MEM019_I_MEM_PRTY_2_E5_SHIFT 3
47524 … (0x1<<3) // This bit masks, when set, the Parity bi…
47525 …SWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_0_BB_K2_SHIFT 3
47526 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47528 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47530 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47532 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47534 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47536 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47538 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47540 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47542 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47544 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47546 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47548 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47550 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47552 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47554 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47556 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47558 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47560 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47562 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47564 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47566 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47568 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47570 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47572 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47574 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47576 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47578 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47580 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47582 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47584 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47586 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47588 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47590 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47592 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47594 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47596 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47598 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47600 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47602 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47604 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47606 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47608 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47610 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47612 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47614 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47616 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47619 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47621 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47623 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47625 … (0x1<<3) // This bit masks, when set, the Parity bi…
47626 …SWWR2_REG_PRTY_MASK_H_4_MEM013_I_MEM_PRTY_8_E5_SHIFT 3
47627 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47629 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47631 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47633 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47635 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47637 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47639 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47641 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47643 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47645 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47646 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47647 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47675 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
47676 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
47677 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
47678 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
47684 … 0x29c0a4UL //Access:R DataWidth:0x12 // Each bit indicates if full i…
47685 … 0x29c0a8UL //Access:R DataWidth:0x12 // Each bit indicates if full w…
47694 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
47696 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
47698 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
47715 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47719 …3 VQs. SR ID of 0x1ff is NULL and means there is no sub request in this VQ in PSWRD. The reset val…
47723 …uld override the data in case of an error. Duplicated 4 times to create 64 bit data. Can be deadde…
47725 …a. Arrowhead: The reset value of 1 should not be changed. It can cause Xs on the outputs - CQ79817.
47727 …-block until end of packet. Note that the override may start a few cycles before or after the last…
47729 …uest with error on receive side: [15:0] - Echo ID. [28:16] - sub-request length minus 1. [29] - fi…
47730 …ils of first request with error on receive side: [4:0] - VQ ID. [9:5] - client ID. [10] - valid - …
47737 …3 VQs. SR ID of 0x1ff is NULL and means there is no sub request in this VQ in PSWRD. The reset val…
47738 …RD2_REG_FIRST_SR_NODES_2_SIZE 3
47763 …s are used in the clock synchronization FIFO; it asserts the 'almost full' bit. This number is com…
47764 … of entries are used in the clock synchronization FIFO; it de-asserts the 'almost full' bit. This …
47765 …e used in the CDU clock synchronization FIFO; it asserts the 'almost full' bit. This is the almost…
47766 …entries are used in the CDU clock synchronization FIFO; it de-asserts the 'almost full' bit. This …
47767 …e used in the PBF clock synchronization FIFO; it asserts the 'almost full' bit. This is the almost…
47768 …entries are used in the PBF clock synchronization FIFO; it de-asserts the 'almost full' bit. This …
47769 …e used in the PRM clock synchronization FIFO; it asserts the 'almost full' bit. This is the almost…
47770 … of entries are used in the clock synchronization FIFO; it de-asserts the 'almost full' bit. This …
47771 …bit indicates if 'almost full' was asserted since reset from the FIFO towards the delivery module.…
47772 … 0x29d144UL //Access:R DataWidth:0x20 // Per-client maximum sync F…
47773 … 0x29d148UL //Access:R DataWidth:0x20 // Per-client maximum sync F…
47774 … 0x29d14cUL //Access:R DataWidth:0x20 // Per-client maximum sync F…
47775 … 0x29d150UL //Access:R DataWidth:0x20 // Per-client maximum sync F…
47779 … 0x29d160UL //Access:R DataWidth:0x8 // Per-client maximum sync F…
47787 … (0x1<<3) // An error in one …
47788 …SWRD2_REG_INT_STS_PUSH_ERROR_SHIFT 3
47792 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
47794 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
47796 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
47798 … (0x1<<3) // This bit masks, when set, the Interrupt …
47799 …SWRD2_REG_INT_MASK_PUSH_ERROR_SHIFT 3
47800 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
47809 …ROR (0x1<<3) // An error in one …
47810 …SWRD2_REG_INT_STS_WR_PUSH_ERROR_SHIFT 3
47820 …RROR (0x1<<3) // An error in one …
47821 …SWRD2_REG_INT_STS_CLR_PUSH_ERROR_SHIFT 3
47825 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47828 … (0x1<<3) // This bit masks, when set, the Parity bi…
47829 …SWRD2_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT_BB_K2_SHIFT 3
47830 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47832 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47834 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47836 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47838 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47840 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47842 … (0x1<<3) // This bit masks, when set, the Parity bi…
47843 …SWRD2_REG_PRTY_MASK_H_0_MEM023_I_ECC_RF_INT_E5_SHIFT 3
47844 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47846 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47848 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47850 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
47852 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
47854 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
47856 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
47858 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47860 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47862 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47864 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47866 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
47868 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47870 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47872 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47874 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
47876 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
47878 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47880 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
47882 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
47884 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47886 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
47888 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47890 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47892 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47894 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47896 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47898 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47900 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47902 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47904 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47906 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47908 … (0x1<<23) // This bit masks, when set, the Parity bit: PS…
47910 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47912 … (0x1<<24) // This bit masks, when set, the Parity bit: PS…
47914 … (0x1<<25) // This bit masks, when set, the Parity bit: PS…
47916 … (0x1<<26) // This bit masks, when set, the Parity bit: PS…
47918 … (0x1<<27) // This bit masks, when set, the Parity bit: PS…
47920 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47922 … (0x1<<28) // This bit masks, when set, the Parity bit: PS…
47924 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47926 … (0x1<<29) // This bit masks, when set, the Parity bit: PS…
47928 … (0x1<<30) // This bit masks, when set, the Parity bit: PS…
47930 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47932 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47934 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
47936 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
47938 … (0x1<<17) // This bit masks, when set, the Parity bit: PS…
47940 … (0x1<<18) // This bit masks, when set, the Parity bit: PS…
47942 … (0x1<<19) // This bit masks, when set, the Parity bit: PS…
47944 … (0x1<<20) // This bit masks, when set, the Parity bit: PS…
47946 … (0x1<<21) // This bit masks, when set, the Parity bit: PS…
47948 … (0x1<<22) // This bit masks, when set, the Parity bit: PS…
47951 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47953 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47955 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
47957 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47959 … (0x1<<3) // This bit masks, when set, the Parity bi…
47960 …SWRD2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5_SHIFT 3
47961 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
47963 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
47965 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
47967 …[3].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an …
47968 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47969 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47970 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47971 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47972 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47973 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47974 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47975 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47976 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47977 …[3].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an …
47978 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47979 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47980 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
47982 …EM020_I_ECC_EN_BB_K2 (0x1<<3) // Enable ECC for m…
47983 …SWRD2_REG_MEM_ECC_ENABLE_0_MEM020_I_ECC_EN_BB_K2_SHIFT 3
47990 … (0x1<<5) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc …
47996 …EM023_I_ECC_EN_E5 (0x1<<3) // Enable ECC for m…
47997 …SWRD2_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_EN_E5_SHIFT 3
48004 … (0x1<<5) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc …
48025 …Y_0_MEM020_I_ECC_PRTY_BB_K2 (0x1<<3) // Set parity only …
48026 …SWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM020_I_ECC_PRTY_BB_K2_SHIFT 3
48033 …(0x1<<5) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc …
48039 …Y_0_MEM023_I_ECC_PRTY_E5 (0x1<<3) // Set parity only …
48040 …SWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_PRTY_E5_SHIFT 3
48047 …(0x1<<5) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc …
48068 …ECTED_0_MEM020_I_ECC_CORRECT_BB_K2 (0x1<<3) // Record if a corr…
48069 …SWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM020_I_ECC_CORRECT_BB_K2_SHIFT 3
48076 …a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc …
48082 …ECTED_0_MEM023_I_ECC_CORRECT_E5 (0x1<<3) // Record if a corr…
48083 …SWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_CORRECT_E5_SHIFT 3
48090 …a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc …
48112 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
48113 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
48114 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
48115 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
48121 …:RW DataWidth:0x9 // Debug only: Total number of available PCI read sub-requests. Must be big…
48123 … 0x29d46cUL //Access:RW DataWidth:0x1 // Global ATC enable bit. When reset all ATC…
48124 … 0 - The delivery port continues delivering the next PBF request only if the second delivery port …
48149 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
48150 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
48151 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
48152 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
48164 …IFO_ERR (0x1<<3) // An error in the …
48165 …SWHST2_REG_INT_STS_HST_CPL_FIFO_ERR_SHIFT 3
48169 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
48171 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
48173 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
48175 … (0x1<<3) // This bit masks, when set, the Interrupt …
48176 …SWHST2_REG_INT_MASK_HST_CPL_FIFO_ERR_SHIFT 3
48177 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
48186 …L_FIFO_ERR (0x1<<3) // An error in the …
48187 …SWHST2_REG_INT_STS_WR_HST_CPL_FIFO_ERR_SHIFT 3
48197 …PL_FIFO_ERR (0x1<<3) // An error in the …
48198 …SWHST2_REG_INT_STS_CLR_HST_CPL_FIFO_ERR_SHIFT 3
48202 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
48209 … // Debug only: A bit mask for all PSWHST internal write clients. '1' means this PSWHST is discard…
48210 …:0x1 // Debug only: '1' means this PSWHST is discarding doorbells. This bit should update accor…
48211 …aWidth:0x1 // Debug only: '1' means this PSWHST is discarding p2m. This bit should update accor…
48212 …bit per arbiter-engine indicating if the engine is idle. Idle means the engine is not sending requ…
48213 …- pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 P…
48214 … 0x2a0060UL //Access:R DataWidth:0x1 // 1 - An error request is …
48216 …- RSV [25:18] - byte enable; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM…
48217 … first incorrect access. the format is: [6:0] - length in DWs. The data is written only when the v…
48218 … 0x2a0070UL //Access:R DataWidth:0x1 // 1 - An incorrect access is logged. The valid bi…
48220 … 0x2a0078UL //Access:R DataWidth:0x1 // 1- permission violation data is logged. The valid…
48225 …r of available credits for source in internal write interface: [1:0] usdm; [3:2] xsdm; [5:4] msdm;…
48226 …consumed more than its allowed credits. the format is: [3:0] - client (0 TSDM; 1 MSDM; 2 USDM; 3 X…
48227 … 0x2a0094UL //Access:R DataWidth:0x1 // 1 - A source credit violation is logged. The valid…
48231 …available credits for destination in internal write interface. [1:0] usdm; [3:2] xsdm; [5:4] msdm;…
48233 … 0x2a00acUL //Access:R DataWidth:0x1 // 1 - PSWHST is in drain m…
48235 …- length in DWs; [25:18] - byte enable; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - cli…
48236 … 0x2a00b8UL //Access:R DataWidth:0x1 // 1 - An hst timeout data is logged. The valid bi…
48238 …interface. PSWHST issues an attention if more credits are consumed. Added in BB-B0 due to pipeline.
48254 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
48255 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
48256 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
48257 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
48262 …bit mask for PSWHST source arbiter clients. '1' means this client is waiting for the arbiter. Each…
48271 … (0x1<<3) // An error in write source FIFO 3.
48272 …SWHST_REG_INT_STS_HST_SRC_FIFO3_ERR_SHIFT 3
48302 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
48304 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
48306 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
48308 … (0x1<<3) // This bit masks, when set, the Interrupt …
48309 …SWHST_REG_INT_MASK_HST_SRC_FIFO3_ERR_SHIFT 3
48310 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
48312 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
48314 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
48316 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
48318 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
48320 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
48322 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
48324 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
48326 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
48328 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
48330 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
48332 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
48334 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
48336 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
48345 … (0x1<<3) // An error in write source FIFO 3.
48346 …SWHST_REG_INT_STS_WR_HST_SRC_FIFO3_ERR_SHIFT 3
48382 … (0x1<<3) // An error in write source FIFO 3.
48383 …SWHST_REG_INT_STS_CLR_HST_SRC_FIFO3_ERR_SHIFT 3
48413 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
48416 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
48418 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
48420 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
48422 … (0x1<<3) // This bit masks, when set, the Parity bi…
48423 …SWHST_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT 3
48424 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
48426 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
48428 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
48430 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
48432 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
48434 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
48436 … (0x1<<10) // This bit masks, when set, the Parity bit: PS…
48438 … (0x1<<11) // This bit masks, when set, the Parity bit: PS…
48440 … (0x1<<12) // This bit masks, when set, the Parity bit: PS…
48442 … (0x1<<13) // This bit masks, when set, the Parity bit: PS…
48444 … (0x1<<14) // This bit masks, when set, the Parity bit: PS…
48446 … (0x1<<15) // This bit masks, when set, the Parity bit: PS…
48448 … (0x1<<16) // This bit masks, when set, the Parity bit: PS…
48451 …und interrupts memory. E4 entry structure: [15:0] - CompParams. [23:16] - EventID. [24] - T. [28:2…
48458 …ould make sure the corresponding bit is 1 some time after writing to start_init_inb_int_mem. Bit 0…
48460 …th:0x1 // PTT and GTT initialization is done. MCP should make sure this bit is 1 some time afte…
48462 …should make sure the corresponding bit is 1 some time after writing to start_init_zone_a. Bit 0 is…
48470 …_VIOLATION_ATTN (0x1<<3) // Indicates a VF …
48471 …GLUE_B_REG_INT_STS_VF_LENGTH_VIOLATION_ATTN_SHIFT 3
48490 … (0x1<<13) // Indicates an illegal address event - address smaller than…
48513 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
48515 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
48517 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
48519 … (0x1<<3) // This bit masks, when set, the Interrupt …
48520 …GLUE_B_REG_INT_MASK_VF_LENGTH_VIOLATION_ATTN_SHIFT 3
48521 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
48523 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
48525 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
48527 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
48529 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
48531 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
48533 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
48535 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
48537 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
48539 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
48541 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
48543 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
48545 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
48547 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
48549 … (0x1<<18) // This bit masks, when set, the Interrupt bit: P…
48551 … (0x1<<19) // This bit masks, when set, the Interrupt bit: P…
48553 … (0x1<<20) // This bit masks, when set, the Interrupt bit: P…
48555 … (0x1<<21) // This bit masks, when set, the Interrupt bit: P…
48557 … (0x1<<22) // This bit masks, when set, the Interrupt bit: P…
48559 … (0x1<<23) // This bit masks, when set, the Interrupt bit: P…
48568 …GTH_VIOLATION_ATTN (0x1<<3) // Indicates a VF …
48569 …GLUE_B_REG_INT_STS_WR_VF_LENGTH_VIOLATION_ATTN_SHIFT 3
48588 … (0x1<<13) // Indicates an illegal address event - address smaller than…
48617 …NGTH_VIOLATION_ATTN (0x1<<3) // Indicates a VF …
48618 …GLUE_B_REG_INT_STS_CLR_VF_LENGTH_VIOLATION_ATTN_SHIFT 3
48637 … (0x1<<13) // Indicates an illegal address event - address smaller than…
48660 … (0x1<<0) // This bit masks, when set, the Parity bit: PG…
48663 … (0x1<<0) // This bit masks, when set, the Parity bit: PG…
48665 … (0x1<<4) // This bit masks, when set, the Parity bit: PG…
48667 … (0x1<<1) // This bit masks, when set, the Parity bit: PG…
48669 … (0x1<<2) // This bit masks, when set, the Parity bit: PG…
48671 … (0x1<<3) // This bit masks, when set, the Parity bi…
48672 …GLUE_B_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_SHIFT 3
48673 … (0x1<<5) // This bit masks, when set, the Parity bit: PG…
48675 … (0x1<<4) // This bit masks, when set, the Parity bit: PG…
48677 … (0x1<<5) // This bit masks, when set, the Parity bit: PG…
48679 … (0x1<<6) // This bit masks, when set, the Parity bit: PG…
48681 … (0x1<<7) // This bit masks, when set, the Parity bit: PG…
48683 … (0x1<<8) // This bit masks, when set, the Parity bit: PG…
48685 … (0x1<<10) // This bit masks, when set, the Parity bit: PG…
48687 … (0x1<<9) // This bit masks, when set, the Parity bit: PG…
48689 … (0x1<<11) // This bit masks, when set, the Parity bit: PG…
48691 … (0x1<<10) // This bit masks, when set, the Parity bit: PG…
48693 … (0x1<<6) // This bit masks, when set, the Parity bit: PG…
48695 … (0x1<<11) // This bit masks, when set, the Parity bit: PG…
48697 … (0x1<<12) // This bit masks, when set, the Parity bit: PG…
48699 … (0x1<<13) // This bit masks, when set, the Parity bit: PG…
48701 … (0x1<<7) // This bit masks, when set, the Parity bit: PG…
48703 … (0x1<<14) // This bit masks, when set, the Parity bit: PG…
48705 … (0x1<<8) // This bit masks, when set, the Parity bit: PG…
48707 … (0x1<<15) // This bit masks, when set, the Parity bit: PG…
48709 … (0x1<<9) // This bit masks, when set, the Parity bit: PG…
48711 … (0x1<<16) // This bit masks, when set, the Parity bit: PG…
48713 … (0x1<<0) // This bit masks, when set, the Parity bit: PG…
48715 … (0x1<<17) // This bit masks, when set, the Parity bit: PG…
48717 … (0x1<<18) // This bit masks, when set, the Parity bit: PG…
48719 … (0x1<<19) // This bit masks, when set, the Parity bit: PG…
48721 … (0x1<<20) // This bit masks, when set, the Parity bit: PG…
48723 … (0x1<<21) // This bit masks, when set, the Parity bit: PG…
48725 … (0x1<<22) // This bit masks, when set, the Parity bit: PG…
48727 … (0x1<<1) // This bit masks, when set, the Parity bit: PG…
48729 … (0x1<<23) // This bit masks, when set, the Parity bit: PG…
48731 … (0x1<<12) // This bit masks, when set, the Parity bit: PG…
48733 … (0x1<<24) // This bit masks, when set, the Parity bit: PG…
48735 … (0x1<<13) // This bit masks, when set, the Parity bit: PG…
48737 … (0x1<<25) // This bit masks, when set, the Parity bit: PG…
48739 … (0x1<<14) // This bit masks, when set, the Parity bit: PG…
48741 … (0x1<<26) // This bit masks, when set, the Parity bit: PG…
48743 … (0x1<<15) // This bit masks, when set, the Parity bit: PG…
48745 … (0x1<<27) // This bit masks, when set, the Parity bit: PG…
48747 … (0x1<<16) // This bit masks, when set, the Parity bit: PG…
48749 … (0x1<<28) // This bit masks, when set, the Parity bit: PG…
48751 … (0x1<<17) // This bit masks, when set, the Parity bit: PG…
48753 … (0x1<<29) // This bit masks, when set, the Parity bit: PG…
48755 … (0x1<<18) // This bit masks, when set, the Parity bit: PG…
48757 … (0x1<<30) // This bit masks, when set, the Parity bit: PG…
48759 … (0x1<<19) // This bit masks, when set, the Parity bit: PG…
48761 … (0x1<<20) // This bit masks, when set, the Parity bit: PG…
48763 … (0x1<<21) // This bit masks, when set, the Parity bit: PG…
48766 … (0x1<<0) // This bit masks, when set, the Parity bit: PG…
48768 … (0x1<<1) // This bit masks, when set, the Parity bit: PG…
48770 … (0x1<<2) // This bit masks, when set, the Parity bit: PG…
48775 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
48776 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
48777 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
48778 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
48783 …Bit 0 - for Atomic Op / MRD handling of NPH credits. 0 - Can send both if there is one NPH credit …
48787 … (0x1<<0) // 0 - Debug bus is not output to RBCN_e0. 1 - …
48789 … (0x1<<1) // 0 - Debug bus is not output to RBCN_e1. 1 - …
48804 …E (0x1<<8) // This bit forces a parity err…
48806 … (0x1<<9) // This bit give strict priority to read over write on the P…
48809 …dth:0x2 // Bit 0: This bit indicates that a write request was blocked because of bus_master_en …
48810 …idth:0x2 // Bit 0: This bit indicates that a read request was blocked because of bus_master_en …
48820 …bit indicates a type of legacy error that was received in user RX interface since last reset. Note…
48824 …te) from PGLUE to PCIe core. When disable_two_pending_wr_requests is 0; this bit must be 0 as well.
48828 …n of sending two pending write requests from PGLUE to PCIe core. When this bit is 0; disable_highe…
48835 … Debug only: 0 - PCIe checksum is generated towards PCIe core. 1 - PCIe checksum is not generated …
48836 … 0x2a84d4UL //Access:RW DataWidth:0x20 // A bit per VQ that indicat…
48839 …:0x5 // Pseudo VF target mode configuration that controls the size of each pseudo-VF in the BAR.
48841 … to accesss DORQ via BAR0: 0-disable access; 1-enable access if BAR0 size is 128K; 2-enable acces…
48842 … 0x2a84ecUL //Access:RW DataWidth:0x9 // VSC fields: bit 0 - enable VSC; bits 1-8 - VSC re…
48858 …-PF region. Addresses 0x0 - 0x5c: 12 per-PF PF windows. Each PF window contains two 32-bit values.…
48860 …region. 0x0 - 0x3c8 (0x200 - 0x5c8) - 243 global windows. Each entry is the 12-bit window offset.…
48862 …ister on which config space A attention is generated. Note that this register is in 128-byte units.
48863 …s starting in address cfg_space_a_address generates an attention. If bit N is set - a CSSNOOP cycl…
48864 …ister on which config space B attention is generated. Note that this register is in 128-byte units.
48865 …s starting in address cfg_space_b_address generates an attention. If bit N is set - a CSSNOOP cycl…
48866 …/Access:R DataWidth:0x10 // Config space A attention dirty bits. Each bit indicates that the …
48867 …bit in this register in order to clear the corresponding bit in cfg_space_a_request register. Note…
48868 …/Access:R DataWidth:0x10 // Config space B attention dirty bits. Each bit indicates that the …
48869 …bit in this register in order to clear the corresponding bit in cfg_space_b_request register. Note…
48870 …DataWidth:0x20 // FLR request attention dirty bits for VFs 0 to 31. Each bit indicates that the …
48871 …ataWidth:0x20 // FLR request attention dirty bits for VFs 32 to 63. Each bit indicates that the …
48872 …ataWidth:0x20 // FLR request attention dirty bits for VFs 64 to 95. Each bit indicates that the …
48873 …taWidth:0x20 // FLR request attention dirty bits for VFs 96 to 127. Each bit indicates that the …
48874 …aWidth:0x20 // FLR request attention dirty bits for VFs 128 to 159. Each bit indicates that the …
48875 …aWidth:0x20 // FLR request attention dirty bits for VFs 160 to 191. Each bit indicates that the …
48876 …aWidth:0x20 // FLR request attention dirty bits for VFs 192 to 223. Each bit indicates that the …
48877 …aWidth:0x20 // FLR request attention dirty bits for VFs 224 to 255. Each bit indicates that the …
48878 … DataWidth:0x10 // FLR request attention dirty bits for all PFs. Each bit indicates that the …
48879 …bits clear for VFs 0 to 31. MCP writes 1 to a bit in this register in order to clear the correspon…
48880 …its clear for VFs 32 to 63. MCP writes 1 to a bit in this register in order to clear the correspon…
48881 …its clear for VFs 64 to 95. MCP writes 1 to a bit in this register in order to clear the correspon…
48882 …ts clear for VFs 96 to 127. MCP writes 1 to a bit in this register in order to clear the correspon…
48883 …s clear for VFs 128 to 159. MCP writes 1 to a bit in this register in order to clear the correspon…
48884 …s clear for VFs 160 to 191. MCP writes 1 to a bit in this register in order to clear the correspon…
48885 …s clear for VFs 192 to 223. MCP writes 1 to a bit in this register in order to clear the correspon…
48886 …s clear for VFs 224 to 255. MCP writes 1 to a bit in this register in order to clear the correspon…
48887 …ty bits clear for all PFs. MCP writes 1 to a bit in this register in order to clear the correspon…
48891 …ABLED_REQUEST (0x1<<1) // Debug only: When 1 SR-IOV disbaled request …
48893 …Access:R DataWidth:0x10 // SR IOV disabled attention dirty bits. Each bit indicates that the …
48894 …attention dirty bits clear. MCP writes 1 to a bit in this register in order to clear the correspon…
48895 …/Access:R DataWidth:0x20 // Shadow BME register for VFs 0 to 31. Each bit indicates if the co…
48896 …Access:R DataWidth:0x20 // Shadow BME register for VFs 32 to 63. Each bit indicates if the co…
48897 …Access:R DataWidth:0x20 // Shadow BME register for VFs 64 to 95. Each bit indicates if the co…
48898 …ccess:R DataWidth:0x20 // Shadow BME register for VFs 96 to 127. Each bit indicates if the co…
48899 …cess:R DataWidth:0x20 // Shadow BME register for VFs 128 to 159. Each bit indicates if the co…
48900 …cess:R DataWidth:0x20 // Shadow BME register for VFs 160 to 191. Each bit indicates if the co…
48901 …cess:R DataWidth:0x20 // Shadow BME register for VFs 192 to 223. Each bit indicates if the co…
48902 …cess:R DataWidth:0x20 // Shadow BME register for VFs 224 to 255. Each bit indicates if the co…
48903 …UL //Access:R DataWidth:0x10 // Shadow BME register for all PFs. Each bit indicates if the co…
48904 …bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable,…
48905 …bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable,…
48906 …bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable,…
48907 …bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable,…
48908 …bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable,…
48909 …bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable,…
48910 …bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable,…
48911 …bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable,…
48912 …- Shadow bits clear for PFs 0 to 31. MCP writes 1 to a bit in this register in order to reset the…
48913 …:R DataWidth:0x20 // Shadow ats_enable register for VFs 0 to 31. Each bit indicates if ATS fo…
48914 …R DataWidth:0x20 // Shadow ats_enable register for VFs 32 to 63. Each bit indicates if ATS fo…
48915 …R DataWidth:0x20 // Shadow ats_enable register for VFs 64 to 95. Each bit indicates if ATS fo…
48916 … DataWidth:0x20 // Shadow ats_enable register for VFs 96 to 127. Each bit indicates if ATS fo…
48917 … DataWidth:0x20 // Shadow ats_enable register for VFs 128 to 159. Each bit indicates if ATS fo…
48918 … DataWidth:0x20 // Shadow ats_enable register for VFs 160 to 191. Each bit indicates if ATS fo…
48919 … DataWidth:0x20 // Shadow ats_enable register for VFs 192 to 223. Each bit indicates if ATS fo…
48920 … DataWidth:0x20 // Shadow ats_enable register for VFs 224 to 255. Each bit indicates if ATS fo…
48921 …cess:R DataWidth:0x10 // Shadow ats_enable register for all PFs. Each bit indicates if ATS fo…
48922 … DataWidth:0x10 // Shadow vf_enable register for all PFs. Each bit indicates if SR-IOV for the …
48924 …5. [15:0] : Each bit indicates if IDO_REQ_ENABLE bit for the corresponding PF is set. [31:16] : Ea…
48926 …bit indicates an incorrect behavior in user RX interface. Bit 0 - Reserved. Bit 1 - Reserved. Bit …
48927 …DataWidth:0x20 // Was_error indication dirty bits for VFs 0 to 31. Each bit indicates that ther…
48928 …ataWidth:0x20 // Was_error indication dirty bits for VFs 32 to 63. Each bit indicates that ther…
48929 …ataWidth:0x20 // Was_error indication dirty bits for VFs 64 to 95. Each bit indicates that ther…
48930 …taWidth:0x20 // Was_error indication dirty bits for VFs 96 to 127. Each bit indicates that ther…
48931 …aWidth:0x20 // Was_error indication dirty bits for VFs 128 to 159. Each bit indicates that ther…
48932 …aWidth:0x20 // Was_error indication dirty bits for VFs 160 to 191. Each bit indicates that ther…
48933 …aWidth:0x20 // Was_error indication dirty bits for VFs 192 to 223. Each bit indicates that ther…
48934 …aWidth:0x20 // Was_error indication dirty bits for VFs 224 to 255. Each bit indicates that ther…
48935 … DataWidth:0x10 // Was_error indication dirty bits for PFs 0 to 7. Each bit indicates that ther…
48936 …bits clear for VFs 0 to 31. MCP writes 1 to a bit in this register in order to clear the correspon…
48937 …its clear for VFs 32 to 63. MCP writes 1 to a bit in this register in order to clear the correspon…
48938 …its clear for VFs 64 to 95. MCP writes 1 to a bit in this register in order to clear the correspon…
48939 …ts clear for VFs 96 to 127. MCP writes 1 to a bit in this register in order to clear the correspon…
48940 …s clear for VFs 128 to 159. MCP writes 1 to a bit in this register in order to clear the correspon…
48941 …s clear for VFs 160 to 191. MCP writes 1 to a bit in this register in order to clear the correspon…
48942 …s clear for VFs 192 to 223. MCP writes 1 to a bit in this register in order to clear the correspon…
48943 …s clear for VFs 224 to 255. MCP writes 1 to a bit in this register in order to clear the correspon…
48944 …bits clear for PFs 0 to 7. MCP writes 1 to a bit in this register in order to clear the correspon…
48945 …3:0] - PFID. [4] - VF_VALID. [12:5] - VFID. [14:13] - Error Code - 0 - Indicates Completion Timeou…
48946 …3:0] - PFID. [4] - VF_VALID. [12:5] - VFID. [14:13] - Error Code - 0 - Indicates Completion Timeou…
48949 …ot submitted due to error. [4:0] VQID. [17:5] - Length in bytes. [19] - VF_VALID. [23:20] - PFID. …
48950 …- Error type - [21] - Indicates was_error was set; [22] - Indicates BME was cleared; [23] - Indica…
48953 …QID. [5] TREQ. 1 - Indicates the request is a Translation Request. [18:6] - Length in bytes. [19] …
48954 …- Error type - [21] - Indicates was_error was set; [22] - Indicates BME was cleared; [23] - Indica…
48955 …3:0] - PFID. [11:4] - VFID. [12] - VF_VALID. [17:13] - ITAG Index. [21:18] - Error type - [18] - …
48956 …68UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-VF for master and tar…
48957 …6cUL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for master transac…
48958 …70UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target write t…
48959 …74UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target read tr…
48968 …pfid_enable registers for target flow. Bits [15:0] - internal_pfid_enable_target_write; Bits [31:1…
48969 … global view of internal_pfid_enable registers for master flow. Bits [15:0] - internal_pfid_enable…
49000 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49001 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49002 … interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B re…
49003 … interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B re…
49004 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49005 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49006 … interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B re…
49007 … interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B re…
49008 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49009 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49010 … interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B re…
49011 … interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B re…
49012 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49013 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49014 … interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B re…
49015 … interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B re…
49016 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49017 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49018 … interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B re…
49019 … interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B re…
49020 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49021 …bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it i…
49022 … interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B re…
49023 … interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B re…
49024 … 0x2aa318UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49025 … 0x2aa31cUL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49026 … 0x2aa320UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49027 … 0x2aa324UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49028 … 0x2aa328UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49029 … 0x2aa32cUL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49030 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49031 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49032 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49033 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49034 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49035 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49036 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49037 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49038 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49039 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49040 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49041 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49042 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49043 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49044 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49045 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49046 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49047 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49048 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49049 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49050 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49051 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49052 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49053 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49054 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49055 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49056 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49057 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49058 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49059 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49060 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49061 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49062 …R0. [12:0] Address in DWs (bits [14:2] of byte address). [14:13] BAR. [22:15] VFID. [26:23] - PFID.
49063 …st with length violation (too many DWs) accessing BAR0. [5:0] - Length in DWs. [6] valid - indica…
49064 …ermission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write. [23:16] VFID. [27:24] - PFID. [28…
49065 …bit in this register clears a corresponding error details register and enables logging new error d…
49066 … 0x2aa3c0UL //Access:RW DataWidth:0x20 // Each bit when set indicates that IDO bit tow…
49067 … 0x2aa3c4UL //Access:RW DataWidth:0x1 // Bit 0 - when set indicates that IDO bit t…
49068 … 0x2aa3c8UL //Access:RW DataWidth:0x1 // Bit 0 - when set indicates that IDO bit t…
49069 …Access:RW DataWidth:0x1 // 1 - Do not discard IGU master transactions for PF when the corresp…
49070 …- Accesses to the first 8KB of IGU in BAR0 (MSIX table and PBA) are not allowed. When this value i…
49071 …completion is considered erroneous. [3:0] - PFID. [4] - VF_VALID. [12:5] - VFID. [17:13] - OTB Ent…
49072 …- Unsupported Request or Completer Abort on User RX Interface. 1 - Reception of a poisoned TLP on …
49073 …UL //Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_…
49074 …UL //Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_…
49075 …- Enable the fix for CQ45220. If a Function receives a Translation Completion with a Translation S…
49076 …UL //Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_…
49077 …UL //Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_…
49094 …0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address…
49096 …0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address…
49098 …0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address…
49100 …0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address…
49102 …0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address…
49104 …0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address…
49106 …0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address…
49108 …0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address…
49110 …bit in this read-only register reflects the value of the corresponding 'PF trusted' config bit on …
49113 …- Indicates the request is a Translation Request. [9:6] - PFID. [10] - VF_VALID. [18:11] - VFID. […
49114 …- PGLUE will submit the request with TPH info. PXP will take care of aligning it correctly when se…
49115 … address). [13:10] BE first. [17:14] BE last. [21:18] - PFID. [27:22] - Length in DWs. [28] valid …
49116 …3:0] - original PFID. [7:4] Pretend PFID. [15:8] Pretend VFID. [16] Pretend vf_valid. [20:17] Pret…
49118 …2aa560UL //Access:RW DataWidth:0x1 // 0 - Work with external BAR0 mechanism as defined in E4 …
49125 …57cUL //Access:RW DataWidth:0x1 // FID channel enable configuration per-VF. Controls Target …
49126 …l is enabled for that SDM. One bit per SDM. Bit 0 - TSDM. Bit 1 - MSDM. Bit 2 - USDM. Bit 3 - XSDM…
49127 …3 // Window size for VF to PF channel. 0 - NA; 1 - 8B; 2 - 16B; 3 - 32B; 4 - 64B; 5 - 128B; 6 -…
49130 … (0x1<<0) // Decision bit for PF master requests when BME is cleared: 0 - b…
49132 … (0x1<<1) // Decision bit for PF master requests when fid_enable is cleared: 0…
49134 … (0x1<<2) // Decision bit for PF master requests when was_error is set: 0 - …
49136 … (0x1<<3) // Decision bit for VF master requests when BME is cleare…
49137 …GLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_VF_BME_SHIFT 3
49138 … (0x1<<4) // Decision bit for VF master requests when fid_enable is cleared: 0…
49140 … (0x1<<5) // Decision bit for VF master requests when was_error is set: 0 - …
49143 … PF master requests when BME is cleared: 0 - Always set (and log error details); 1 - never set att…
49145 …er requests when fid_enabled is cleared: 0 - Always set (and log error details); 1 - never set att…
49147 …F master requests when was_error is set: 0 - Always set (and log error details); 1 - never set att…
49149 … VF master requests when BME is cleared: 0 - Always set (and log error details); 1 - never set att…
49151 …er requests when fid_enabled is cleared: 0 - Always set (and log error details); 1 - never set att…
49153 …F master requests when was_error is set: 0 - Always set (and log error details); 1 - never set att…
49155 …en this bit is set and attntion setting configuration is 2 any block or discard event for that fun…
49156 …en this bit is set and attntion setting configuration is 2 any block or discard event for that fun…
49162 … of '1' instructs PGLUE to use the client ID value in the 'tag' field of non-TPH master write pack…
49163 …8UL //Access:RW DataWidth:0x1 // This field is an enable bit for 'detection of out-of-range r…
49165 … of ) the minimal legal address value. It is used in the 'detection of out-of-range requests' debu…
49167 … of ) the maximal legal address value. It is used in the 'detection of out-of-range requests' debu…
49171 …th illegal address. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49172 …- address was smaller than minimal_address_log; 1 - address was bigger than maximal_address_log. …
49175 …th TPH information. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49176 …nt ID. [6:5] PH. [14:7] Steering Tag. [15] - write_n_read: 0 - read; 1 - write. [16] - last SR. […
49177 …x1 // 0 - never pad write sub-requests with zeros. 1 - Pad write sub-requests with zeros and al…
49178 …/Access:RW DataWidth:0x3 // Cache line size for padding. 0 - 32B. 1 - 64B. 2 - 128B. 3 - 256B.
49179 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49180 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49181 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49182 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49183 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49184 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49185 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49186 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49189 …e Teaming. The driver should read BAR1_SIZE from PCIe IP config space (bits 3:0 in PCIE_REG_PCIER_…
49190 …e Teaming. The driver should read BAR2_SIZE from PCIe IP config space (bits 3:0 in PCIE_REG_PCIER_…
49196 …t error indication. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49197 …[15:0] Request ID. [20:16] client ID. [21] - write_n_read: 0 - read; 1 - write. [22] - last SR. […
49198 … DataWidth:0x10 // Atomic Op requester enable register for all PFs. Each bit indicates if Atomic…
49199 …M attention dirty bits. Bit 0 is for engine 0 and bit 1 for engine 1. Set by PXP. Reset by MCP wri…
49200 …y bits clear. Bit 0 is for engine 0 and bit 1 for engine 1. MCP writes 1 to a bit in this register…
49201 … DataWidth:0x10 // MPS attention dirty bit. Set by PXP. Reset by MCP writing 1 to the corresp…
49202 …h:0x10 // MPS attention dirty bit clear. MCP writes 1 to a bit in this register in order to clea…
49203 … DataWidth:0x10 // VPD request attention dirty bits for all PFs. Each bit indicates that the …
49204 …Width:0x10 // This register controls the path_in_d3 output to CPMU. Each bit corresponds to a PF…
49209 … 0x2aaeb0UL //Access:RW DataWidth:0x1 // Chicken bit to disable app_xfer…
49222 …ataWidth:0x1 // Disable master read back 2 back transition IT's checken bit for perfomance impr…
49233 … 0x2aaf10UL //Access:R DataWidth:0x10 // pm_dstate 47-032
49235 … 0x2aaf60UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 31-0
49236 … 0x2aaf64UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 63 -32
49237 … 0x2aaf68UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 95 - 64
49238 … 0x2aaf6cUL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 127 - 96
49239 … 0x2aaf70UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 159-128
49243 …20 // Indicates there was an error in MCTP BIt 21-30 Message code Bit 7-22 Vender ID Bit 3-6 …
49244 …aWidth:0x20 // Indicates there was an error in MCTP Bit 21-30 Length Bit 5-20 PCIE REQ ID Bit 0…
49256 …0x2aafb4UL //Access:RW DataWidth:0x1 // 0 - Don't discard target request with unknown header …
49257 …cess:RW DataWidth:0x1 // 0 - Don't compare the function received in the completion to the ori…
49258 …dth:0x1 // 0 - Enable b2b pop from sync fifos in pgl_pci_core_rx. 1 - Disable b2b pop from sync…
49259 … 0x2aafc0UL //Access:RW DataWidth:0x1 // 0 - Don't discard master request during FLR 1 …
49260 … DataWidth:0x4 // 0 - TXCPL sync fifo push overflow 1 - TXR sync fifo push overflow 2 - TXW hea…
49261 … // 0 - RX target read and config sync fifo pop underflow 1 - RX header sync fifo pop underflow…
49262 …x2aafccUL //Access:R DataWidth:0x12 // 8:0 - RX target read and config sync fifo pop status …
49263 …2aafd0UL //Access:R DataWidth:0x1c // RX data sync fifo pop status (7 bit per each 128b insta…
49271 …_PRE_SCAN_MEM_SELF_INIT_START (0x1<<3) // Reset the pre sc…
49272 …M_REG_MEMORY_SELF_INIT_START_PRE_SCAN_MEM_SELF_INIT_START_SHIFT 3
49273 …Width:0x1 // When set, the self init for the context memory is done. TBD - need to change to re…
49304 …L_FIFO_OV (0x1<<3) // PXP READ CTRL FI…
49305 …M_REG_INT_STS_0_PXP_READ_CTRL_FIFO_OV_SHIFT 3
49350 … (0x1<<26) // INIT command and the logical client valid bit is asserted.
49363 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
49365 … (0x1<<1) // This bit masks, when set, the Interrupt bit: T…
49367 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
49369 … (0x1<<3) // This bit masks, when set, the Interrupt …
49370 …M_REG_INT_MASK_0_PXP_READ_CTRL_FIFO_OV_SHIFT 3
49371 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
49373 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
49375 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
49377 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
49379 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
49381 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
49383 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
49385 … (0x1<<11) // This bit masks, when set, the Interrupt bit: T…
49387 … (0x1<<12) // This bit masks, when set, the Interrupt bit: T…
49389 … (0x1<<13) // This bit masks, when set, the Interrupt bit: T…
49391 … (0x1<<14) // This bit masks, when set, the Interrupt bit: T…
49393 … (0x1<<15) // This bit masks, when set, the Interrupt bit: T…
49395 … (0x1<<16) // This bit masks, when set, the Interrupt bit: T…
49397 … (0x1<<17) // This bit masks, when set, the Interrupt bit: T…
49399 … (0x1<<18) // This bit masks, when set, the Interrupt bit: T…
49401 … (0x1<<19) // This bit masks, when set, the Interrupt bit: T…
49403 … (0x1<<20) // This bit masks, when set, the Interrupt bit: T…
49405 … (0x1<<21) // This bit masks, when set, the Interrupt bit: T…
49407 … (0x1<<22) // This bit masks, when set, the Interrupt bit: T…
49409 … (0x1<<23) // This bit masks, when set, the Interrupt bit: T…
49411 … (0x1<<24) // This bit masks, when set, the Interrupt bit: T…
49413 … (0x1<<25) // This bit masks, when set, the Interrupt bit: T…
49415 … (0x1<<26) // This bit masks, when set, the Interrupt bit: T…
49417 … (0x1<<27) // This bit masks, when set, the Interrupt bit: T…
49419 … (0x1<<28) // This bit masks, when set, the Interrupt bit: T…
49421 … (0x1<<29) // This bit masks, when set, the Interrupt bit: T…
49423 … (0x1<<30) // This bit masks, when set, the Interrupt bit: T…
49425 … (0x1<<31) // This bit masks, when set, the Interrupt bit: T…
49434 …CTRL_FIFO_OV (0x1<<3) // PXP READ CTRL FI…
49435 …M_REG_INT_STS_WR_0_PXP_READ_CTRL_FIFO_OV_SHIFT 3
49480 … (0x1<<26) // INIT command and the logical client valid bit is asserted.
49499 …_CTRL_FIFO_OV (0x1<<3) // PXP READ CTRL FI…
49500 …M_REG_INT_STS_CLR_0_PXP_READ_CTRL_FIFO_OV_SHIFT 3
49545 … (0x1<<26) // INIT command and the logical client valid bit is asserted.
49562 … (0x1<<2) // Context Read with Last indication de-asserted.
49564 … (0x1<<3) // Context Write with Last indication de-…
49565 …M_REG_INT_STS_1_CONTEXT_WR_LAST_SHIFT 3
49581 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
49583 … (0x1<<1) // This bit masks, when set, the Interrupt bit: T…
49585 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
49587 … (0x1<<3) // This bit masks, when set, the Interrupt …
49588 …M_REG_INT_MASK_1_CONTEXT_WR_LAST_SHIFT 3
49589 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
49591 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
49593 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
49595 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
49597 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
49599 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
49601 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
49608 … (0x1<<2) // Context Read with Last indication de-asserted.
49610 … (0x1<<3) // Context Write with Last indication de-…
49611 …M_REG_INT_STS_WR_1_CONTEXT_WR_LAST_SHIFT 3
49631 … (0x1<<2) // Context Read with Last indication de-asserted.
49633 … (0x1<<3) // Context Write with Last indication de-…
49634 …M_REG_INT_STS_CLR_1_CONTEXT_WR_LAST_SHIFT 3
49650 … (0x1<<0) // This bit masks, when set, the Parity bit: TM…
49652 … (0x1<<9) // This bit masks, when set, the Parity bit: TM…
49654 … (0x1<<1) // This bit masks, when set, the Parity bit: TM…
49656 … (0x1<<11) // This bit masks, when set, the Parity bit: TM…
49658 … (0x1<<2) // This bit masks, when set, the Parity bit: TM…
49660 … (0x1<<4) // This bit masks, when set, the Parity bit: TM…
49662 … (0x1<<3) // This bit masks, when set, the Parity bi…
49663 …M_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5_SHIFT 3
49664 … (0x1<<12) // This bit masks, when set, the Parity bit: TM…
49666 … (0x1<<4) // This bit masks, when set, the Parity bit: TM…
49668 … (0x1<<13) // This bit masks, when set, the Parity bit: TM…
49670 … (0x1<<5) // This bit masks, when set, the Parity bit: TM…
49672 … (0x1<<6) // This bit masks, when set, the Parity bit: TM…
49674 … (0x1<<7) // This bit masks, when set, the Parity bit: TM…
49676 … (0x1<<5) // This bit masks, when set, the Parity bit: TM…
49678 … (0x1<<8) // This bit masks, when set, the Parity bit: TM…
49680 … (0x1<<10) // This bit masks, when set, the Parity bit: TM…
49682 … (0x1<<9) // This bit masks, when set, the Parity bit: TM…
49684 … (0x1<<8) // This bit masks, when set, the Parity bit: TM…
49686 … (0x1<<10) // This bit masks, when set, the Parity bit: TM…
49688 … (0x1<<15) // This bit masks, when set, the Parity bit: TM…
49690 … (0x1<<11) // This bit masks, when set, the Parity bit: TM…
49692 … (0x1<<16) // This bit masks, when set, the Parity bit: TM…
49694 … (0x1<<12) // This bit masks, when set, the Parity bit: TM…
49696 … (0x1<<13) // This bit masks, when set, the Parity bit: TM…
49698 … (0x1<<6) // This bit masks, when set, the Parity bit: TM…
49700 … (0x1<<14) // This bit masks, when set, the Parity bit: TM…
49702 … (0x1<<0) // This bit masks, when set, the Parity bit: TM…
49704 … (0x1<<1) // This bit masks, when set, the Parity bit: TM…
49706 … (0x1<<2) // This bit masks, when set, the Parity bit: TM…
49708 … (0x1<<3) // This bit masks, when set, the Parity bi…
49709 …M_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_K2_SHIFT 3
49710 … (0x1<<14) // This bit masks, when set, the Parity bit: TM…
49754 …on is applicable only to scan opeartion. Bit 0: segment 0, bit 1: segment 1, bit 2: segment 2, bit…
49770 …x2 // Number of timers per connection group: 00 - 128 timers, 01 - 64 timers, 10 - 32 timers, 1…
49771 …idth:0x2 // Number of timers per task group: 00 - 128 timers, 01 - 64 timers, 10 - 32 timers, 1…
49772 …- the pre scan feature is disabled, i.e. every scan pulse all the groups are scanned. 01 - each gr…
49773 …- the pre scan feature is disabled, i.e. every scan pulse all the groups are scanned. 01 - each gr…
49776 …lock in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49777 …lock in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49778 …ckss in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49779 …eld for writes; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49780 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49781 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49782 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49783 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49784 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49785 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49786 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49787 …- XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client …
49788 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49789 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49790 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49791 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49792 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49793 …- No threshold; Command to the host is set without checking threshold, 01 - Threshold according to…
49801 …is during the scan process. Bit 0 is for segment 0, bit 1 is for segment 1, bit 2 is for segment 2…
49854 …Bit [0]: if = 1, the following error is enabled: STOP_ALL_TIMERS command and the logical client i…
49858 …the debug_0 registers. The source: 0 - PBF, 1 -TCM, 2- UCM, 3 - XCM, 4 - expiration, 5 - reserved,…
49859 …tes that the debug_0 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49863 …- SET TIMER, 1 - CLEAR TIMER, 2 - STOP ALL TIMERS, 3 - INIT, 4 - FORCE CLEAR TIMER, 5 - reserved,…
49866 …s:R DataWidth:0x1 // The Leader Type field for the errored command: 0 - connection, 1 - task.
49867 …r the errored command. The source: 0 - PBF, 1 -TCM, 2- UCM, 3 - XCM, 4 - expiration, 5 - reserved,…
49868 …Bit 0: logical client 0 valid bit, Bit 1: logical client 0 active bit, Bit 2: logical client 1 val…
49869 …Bit [0]: if = 1, the following error happened: STOP_ALL_TIMERS command and the logical client is …
49870 …tes that the debug_1 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49872 …-0: LCID, Bit 9: scan type (0 - connection, 1 - task), Bits 12-10: type (3 LSbits), Bit 13: Load E…
49873 …tes that the debug_2 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49874 …last indication de-asserted fields: Bits 8-0: LCID, Bit 9: Type (0 - connection, 1 - task), Bit 10…
49875 …tes that the debug_3 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49876 …ion de-asserted fields: Bits 8-0: LCID, Bit 9: Type (0 - connection, 1 - task), Bit 11-10: Qward V…
49877 …-0: cmd_handler. Bit 3: reserved. Bits 7-4: writ…
49878 …tes that the debug_4 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49879 … Bits 8-0: function # (0-239 VFs, 240 and above PFs / segments) . Bit 9: type (0 - connecti…
49881 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
49882 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
49883 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
49884 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
49889 …- number of connections, the value should be multiplies of group_size_resolution_conn register (fo…
49893 …3, row 244 for PF1 segment 0, row 245 for PF1 segment 1, etc. The fields are: bits [15:0] - number…
49897 …r connections, the last 512 rows contain the scan rate fields for tasks. TBD - describe the fields.
49908 … (0x1<<10) // When set link list ram will be initialized - all LCIDs will be lo…
49912 … (0x1<<12) // Setting this bit causes the TID Lock RAM to be initialized. This cannot be set du…
49924 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
49926 … (0x1<<1) // This bit masks, when set, the Interrupt bit: T…
49939 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
49941 … (0x1<<1) // This bit masks, when set, the Parity bit: TC…
49943 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
49945 … (0x1<<2) // This bit masks, when set, the Parity bit: TC…
49947 … (0x1<<1) // This bit masks, when set, the Parity bit: TC…
49949 … (0x1<<3) // This bit masks, when set, the Parity bi…
49950 …CFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_E5_SHIFT 3
49981 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
49982 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
49983 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
49984 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
49989 … 0x2d0548UL //Access:RW DataWidth:0x8 // Eco reserved. bit0: Chicken bit for CQ73536 fix. Wh…
49990 … when the CFC detects an internal error it will set one of these bits. the bit description can be …
49991 …ataWidth:0x11 // Masking for error logging. if a bit in this field is set then the corresponding…
49993 …-- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Requested Regions [04:00] -- Error ID Not…
49994 … DataWidth:0x20 // When the CFC detects an internal error it updates these fields. [31:00] -- CID
49995 …CFC detects an internal error it updates these fields. [24:16] -- Request LCID [08:00] -- Active L…
49996 …an internal error it updates these fields. [23:16] -- Increment Value [15:12] -- Type Field [08:00…
50004 …_ARB (0x1<<3) // When set CFC arb…
50005 …CFC_REG_ARBITERS_REG_SP_MISC_ARB_SHIFT 3
50010 …Width:0x3 // This field allows changing the priorities of the weighted-round-robin arbiter whic…
50014 … (0x1<<0) // This bit disables the inputs…
50016 … (0x1<<1) // This bit disables the output…
50020 … (0xf<<10) // This register is not used in BB-B0. Reduced width to 1 bit to keep…
50048 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50049 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50050 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50055 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
50057 … (0x1<<1) // This bit masks, when set, the Parity bit: TC…
50059 … (0x1<<2) // This bit masks, when set, the Parity bit: TC…
50061 … (0x1<<3) // This bit masks, when set, the Parity bi…
50062 …CFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_MSB_PAR_ERR_SHIFT 3
50063 … (0x1<<4) // This bit masks, when set, the Parity bit: TC…
50065 … (0x1<<5) // This bit masks, when set, the Parity bit: TC…
50078 … 0x2d0700UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cance…
50079 … 0x2d0704UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cance…
50080 …s:RW DataWidth:0x1 // This bit when clear will cause a CFC execution error (weak_enable will …
50081 …s:RW DataWidth:0x1 // This bit when clear will cause a CFC execution error (weak_enable will …
50086 … (0x1<<10) // This field is not used in BB-B0. When set, this configuration bit wi…
50096 … (0x1<<11) // New Load On Error. if this bit is set and there is…
50112 …L //Access:RW DataWidth:0x7 // Set the initial credit for the CDU write-back interface if les…
50127 … //Access:RW DataWidth:0x9 // This is the LCID Threshold for LC CLient 3 (MULD). When the num…
50139 …bit corresponds to one of the state machines [2:0]. Writing the bits to 1'b1 will restart the Time…
50141 … (0x1<<0) // This is the Enable bit for the LCID Limiti…
50143 …his is the Polarity bit for the LCID Limiting Waveform Generator #0. The Waveform will always outp…
50150 … (0x1<<0) // This is the Enable bit for the LCID Limiti…
50152 …his is the Polarity bit for the LCID Limiting Waveform Generator #1. The Waveform will always outp…
50159 … (0x1<<0) // This is the Enable bit for the LCID Limiti…
50161 …his is the Polarity bit for the LCID Limiting Waveform Generator #2. The Waveform will always outp…
50167 …bit in this register matches the corresponding String Type. Bit[0] = TCP Bit[1] = UDP Bit[2] …
50173 …nd Writes to the CID CAM. Setting a bit to 0 will ignore that bit in a search. Setting a bit to 0 …
50174 … 0x2d0a0cUL //Access:RW DataWidth:0x1 // When this bit is set writing to t…
50185 … 0x2d0a38UL //Access:RW DataWidth:0x1 // When this bit is set writing to t…
50186 … 0x2d0a3cUL //Access:R DataWidth:0xa // {HIT;LCID}. HIT - if set then previous…
50187 …- tid is not included in hash calculation (like in A0). 1 - tid is included in hash calculation by…
50188 …- vlan is not included in hash calculation (like in A0). 1 - vlan is included in hash calculation …
50192 … 0x2d0b0cUL //Access:R DataWidth:0x20 // Provides read-only access to the CI…
50196 … 0x2d0b1cUL //Access:R DataWidth:0x20 // Provides read-only access to the ST…
50207 … 0x2db000UL //Access:WB DataWidth:0x21 // CID cam access (Valid - 32;31:0 - Data).
50224 … (0x1<<10) // When set link list ram will be initialized - all LCIDs will be lo…
50228 … (0x1<<12) // Setting this bit causes the TID Lock RAM to be initialized. This cannot be set du…
50233 … 0x2e0010UL //Access:R DataWidth:0x1 // This bit does not exist for …
50240 … (0x1<<0) // This bit masks, when set, the Interrupt bit: C…
50242 … (0x1<<1) // This bit masks, when set, the Interrupt bit: C…
50255 … (0x1<<0) // This bit masks, when set, the Parity bit: CC…
50257 … (0x1<<1) // This bit masks, when set, the Parity bit: CC…
50259 … (0x1<<0) // This bit masks, when set, the Parity bit: CC…
50261 … (0x1<<2) // This bit masks, when set, the Parity bit: CC…
50263 … (0x1<<3) // This bit masks, when set, the Parity bi…
50264 …CFC_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_E5_SHIFT 3
50265 … (0x1<<4) // This bit masks, when set, the Parity bit: CC…
50267 … (0x1<<5) // This bit masks, when set, the Parity bit: CC…
50269 … (0x1<<1) // This bit masks, when set, the Parity bit: CC…
50278 …003_I_ECC_EN_E5 (0x1<<3) // Enable ECC for m…
50279 …CFC_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_E5_SHIFT 3
50291 …0_MEM003_I_ECC_PRTY_E5 (0x1<<3) // Set parity only …
50292 …CFC_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_E5_SHIFT 3
50304 …TED_0_MEM003_I_ECC_CORRECT_E5 (0x1<<3) // Record if a corr…
50305 …CFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_E5_SHIFT 3
50324 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
50325 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
50326 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
50327 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
50332 … 0x2e0548UL //Access:RW DataWidth:0x8 // Eco reserved. bit0: Chicken bit for CQ73536 fix. Wh…
50333 … when the CFC detects an internal error it will set one of these bits. the bit description can be …
50334 …ataWidth:0x11 // Masking for error logging. if a bit in this field is set then the corresponding…
50336 …-- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Requested Regions [04:00] -- Error ID Not…
50337 … DataWidth:0x20 // When the CFC detects an internal error it updates these fields. [31:00] -- CID
50338 …CFC detects an internal error it updates these fields. [24:16] -- Request LCID [08:00] -- Active L…
50339 …an internal error it updates these fields. [23:16] -- Increment Value [15:12] -- Type Field [08:00…
50347 …_ARB (0x1<<3) // When set CFC arb…
50348 …CFC_REG_ARBITERS_REG_SP_MISC_ARB_SHIFT 3
50353 …Width:0x3 // This field allows changing the priorities of the weighted-round-robin arbiter whic…
50357 … (0x1<<0) // This bit disables the inputs…
50359 … (0x1<<1) // This bit disables the output…
50363 … (0xf<<10) // This register is not used in BB-B0. Reduced width to 1 bit to keep…
50391 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50392 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50393 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50398 … (0x1<<0) // This bit masks, when set, the Parity bit: CC…
50400 … (0x1<<1) // This bit masks, when set, the Parity bit: CC…
50402 … (0x1<<2) // This bit masks, when set, the Parity bit: CC…
50404 … (0x1<<3) // This bit masks, when set, the Parity bi…
50405 …CFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_MSB_PAR_ERR_SHIFT 3
50406 … (0x1<<4) // This bit masks, when set, the Parity bit: CC…
50408 … (0x1<<5) // This bit masks, when set, the Parity bit: CC…
50421 … 0x2e0700UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cance…
50422 … 0x2e0704UL //Access:RW DataWidth:0x1 // This bit when clear will cause a load-cance…
50423 …s:RW DataWidth:0x1 // This bit when clear will cause a CFC execution error (weak_enable will …
50424 …s:RW DataWidth:0x1 // This bit when clear will cause a CFC execution error (weak_enable will …
50429 … (0x1<<10) // This field is not used in BB-B0. When set, this configuration bit wi…
50439 … (0x1<<11) // New Load On Error. if this bit is set and there is…
50455 …L //Access:RW DataWidth:0x7 // Set the initial credit for the CDU write-back interface if les…
50470 … //Access:RW DataWidth:0x9 // This is the LCID Threshold for LC CLient 3 (MULD). When the num…
50482 …bit corresponds to one of the state machines [2:0]. Writing the bits to 1'b1 will restart the Time…
50484 … (0x1<<0) // This is the Enable bit for the LCID Limiti…
50486 …his is the Polarity bit for the LCID Limiting Waveform Generator #0. The Waveform will always outp…
50493 … (0x1<<0) // This is the Enable bit for the LCID Limiti…
50495 …his is the Polarity bit for the LCID Limiting Waveform Generator #1. The Waveform will always outp…
50502 … (0x1<<0) // This is the Enable bit for the LCID Limiti…
50504 …his is the Polarity bit for the LCID Limiting Waveform Generator #2. The Waveform will always outp…
50510 …bit in this register matches the corresponding String Type. Bit[0] = TCP Bit[1] = UDP Bit[2] …
50516 …nd Writes to the CID CAM. Setting a bit to 0 will ignore that bit in a search. Setting a bit to 0 …
50517 … 0x2e0a0cUL //Access:RW DataWidth:0x1 // When this bit is set writing to t…
50528 … 0x2e0a38UL //Access:RW DataWidth:0x1 // When this bit is set writing to t…
50529 … 0x2e0a3cUL //Access:R DataWidth:0xa // {HIT;LCID}. HIT - if set then previous…
50530 …- tid is not included in hash calculation (like in A0). 1 - tid is included in hash calculation by…
50531 …- vlan is not included in hash calculation (like in A0). 1 - vlan is included in hash calculation …
50535 … 0x2e0b0cUL //Access:R DataWidth:0x20 // Provides read-only access to the CI…
50539 … 0x2e0b1cUL //Access:R DataWidth:0x20 // Provides read-only access to the ST…
50550 … 0x2eb000UL //Access:WB DataWidth:0x21 // CID cam access (Valid - 32;31:0 - Data).
50570 … (0x1<<3) // Overflow of pf u…
50571 …M_REG_INT_STS_PF_USG_CNT_ERR_SHIFT 3
50609 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Q…
50611 … (0x1<<1) // This bit masks, when set, the Interrupt bit: Q…
50613 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Q…
50615 … (0x1<<3) // This bit masks, when set, the Interrupt …
50616 …M_REG_INT_MASK_PF_USG_CNT_ERR_SHIFT 3
50617 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Q…
50619 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Q…
50621 … (0x1<<6) // This bit masks, when set, the Interrupt bit: Q…
50623 … (0x1<<7) // This bit masks, when set, the Interrupt bit: Q…
50625 … (0x1<<8) // This bit masks, when set, the Interrupt bit: Q…
50627 … (0x1<<9) // This bit masks, when set, the Interrupt bit: Q…
50629 … (0x1<<10) // This bit masks, when set, the Interrupt bit: Q…
50631 … (0x1<<11) // This bit masks, when set, the Interrupt bit: Q…
50633 … (0x1<<12) // This bit masks, when set, the Interrupt bit: Q…
50635 … (0x1<<13) // This bit masks, when set, the Interrupt bit: Q…
50637 … (0x1<<14) // This bit masks, when set, the Interrupt bit: Q…
50639 … (0x1<<15) // This bit masks, when set, the Interrupt bit: Q…
50641 … (0x1<<16) // This bit masks, when set, the Interrupt bit: Q…
50643 … (0x1<<17) // This bit masks, when set, the Interrupt bit: Q…
50645 … (0x1<<18) // This bit masks, when set, the Interrupt bit: Q…
50647 … (0x1<<19) // This bit masks, when set, the Interrupt bit: Q…
50649 … (0x1<<20) // This bit masks, when set, the Interrupt bit: Q…
50651 … (0x1<<21) // This bit masks, when set, the Interrupt bit: Q…
50660 …ERR (0x1<<3) // Overflow of pf u…
50661 …M_REG_INT_STS_WR_PF_USG_CNT_ERR_SHIFT 3
50705 …_ERR (0x1<<3) // Overflow of pf u…
50706 …M_REG_INT_STS_CLR_PF_USG_CNT_ERR_SHIFT 3
50744 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
50746 … (0x1<<1) // This bit masks, when set, the Parity bit: QM…
50748 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
50750 … (0x1<<3) // This bit masks, when set, the Parity bi…
50751 …M_REG_PRTY_MASK_CCM_WRC_FIFO_SHIFT 3
50752 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
50754 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
50756 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
50758 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
50760 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
50762 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
50764 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
50767 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
50769 … (0x1<<1) // This bit masks, when set, the Parity bit: QM…
50771 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
50773 … (0x1<<3) // This bit masks, when set, the Parity bi…
50774 …M_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_E5_SHIFT 3
50775 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
50777 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
50779 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
50781 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
50783 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
50785 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
50787 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
50789 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
50791 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
50793 … (0x1<<11) // This bit masks, when set, the Parity bit: QM…
50795 … (0x1<<12) // This bit masks, when set, the Parity bit: QM…
50797 … (0x1<<13) // This bit masks, when set, the Parity bit: QM…
50799 … (0x1<<11) // This bit masks, when set, the Parity bit: QM…
50801 … (0x1<<14) // This bit masks, when set, the Parity bit: QM…
50803 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
50805 … (0x1<<15) // This bit masks, when set, the Parity bit: QM…
50807 … (0x1<<16) // This bit masks, when set, the Parity bit: QM…
50809 … (0x1<<17) // This bit masks, when set, the Parity bit: QM…
50811 … (0x1<<18) // This bit masks, when set, the Parity bit: QM…
50813 … (0x1<<19) // This bit masks, when set, the Parity bit: QM…
50815 … (0x1<<20) // This bit masks, when set, the Parity bit: QM…
50817 … (0x1<<21) // This bit masks, when set, the Parity bit: QM…
50819 … (0x1<<13) // This bit masks, when set, the Parity bit: QM…
50821 … (0x1<<22) // This bit masks, when set, the Parity bit: QM…
50823 … (0x1<<15) // This bit masks, when set, the Parity bit: QM…
50825 … (0x1<<23) // This bit masks, when set, the Parity bit: QM…
50827 … (0x1<<24) // This bit masks, when set, the Parity bit: QM…
50829 … (0x1<<14) // This bit masks, when set, the Parity bit: QM…
50831 … (0x1<<25) // This bit masks, when set, the Parity bit: QM…
50833 … (0x1<<12) // This bit masks, when set, the Parity bit: QM…
50835 … (0x1<<26) // This bit masks, when set, the Parity bit: QM…
50837 … (0x1<<16) // This bit masks, when set, the Parity bit: QM…
50839 … (0x1<<27) // This bit masks, when set, the Parity bit: QM…
50841 … (0x1<<19) // This bit masks, when set, the Parity bit: QM…
50843 … (0x1<<28) // This bit masks, when set, the Parity bit: QM…
50845 … (0x1<<21) // This bit masks, when set, the Parity bit: QM…
50847 … (0x1<<29) // This bit masks, when set, the Parity bit: QM…
50849 … (0x1<<17) // This bit masks, when set, the Parity bit: QM…
50851 … (0x1<<30) // This bit masks, when set, the Parity bit: QM…
50853 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
50855 … (0x1<<1) // This bit masks, when set, the Parity bit: QM…
50857 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
50859 … (0x1<<3) // This bit masks, when set, the Parity bi…
50860 …M_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_K2_SHIFT 3
50861 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
50863 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
50865 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
50867 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
50869 … (0x1<<18) // This bit masks, when set, the Parity bit: QM…
50871 … (0x1<<20) // This bit masks, when set, the Parity bit: QM…
50873 … (0x1<<22) // This bit masks, when set, the Parity bit: QM…
50875 … (0x1<<23) // This bit masks, when set, the Parity bit: QM…
50877 … (0x1<<24) // This bit masks, when set, the Parity bit: QM…
50879 … (0x1<<25) // This bit masks, when set, the Parity bit: QM…
50881 … (0x1<<26) // This bit masks, when set, the Parity bit: QM…
50883 … (0x1<<27) // This bit masks, when set, the Parity bit: QM…
50885 … (0x1<<28) // This bit masks, when set, the Parity bit: QM…
50887 … (0x1<<29) // This bit masks, when set, the Parity bit: QM…
50889 … (0x1<<30) // This bit masks, when set, the Parity bit: QM…
50892 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
50894 … (0x1<<1) // This bit masks, when set, the Parity bit: QM…
50896 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
50898 … (0x1<<13) // This bit masks, when set, the Parity bit: QM…
50900 … (0x1<<3) // This bit masks, when set, the Parity bi…
50901 …M_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_E5_SHIFT 3
50902 … (0x1<<14) // This bit masks, when set, the Parity bit: QM…
50904 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
50906 … (0x1<<21) // This bit masks, when set, the Parity bit: QM…
50908 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
50910 … (0x1<<20) // This bit masks, when set, the Parity bit: QM…
50912 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
50914 … (0x1<<19) // This bit masks, when set, the Parity bit: QM…
50916 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
50918 … (0x1<<18) // This bit masks, when set, the Parity bit: QM…
50920 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
50922 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
50924 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
50926 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
50928 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
50930 … (0x1<<11) // This bit masks, when set, the Parity bit: QM…
50932 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
50934 … (0x1<<12) // This bit masks, when set, the Parity bit: QM…
50936 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
50938 … (0x1<<13) // This bit masks, when set, the Parity bit: QM…
50940 … (0x1<<14) // This bit masks, when set, the Parity bit: QM…
50942 … (0x1<<1) // This bit masks, when set, the Parity bit: QM…
50944 … (0x1<<15) // This bit masks, when set, the Parity bit: QM…
50946 … (0x1<<16) // This bit masks, when set, the Parity bit: QM…
50948 … (0x1<<17) // This bit masks, when set, the Parity bit: QM…
50950 … (0x1<<18) // This bit masks, when set, the Parity bit: QM…
50952 … (0x1<<19) // This bit masks, when set, the Parity bit: QM…
50954 … (0x1<<20) // This bit masks, when set, the Parity bit: QM…
50956 … (0x1<<21) // This bit masks, when set, the Parity bit: QM…
50958 … (0x1<<22) // This bit masks, when set, the Parity bit: QM…
50960 … (0x1<<23) // This bit masks, when set, the Parity bit: QM…
50962 … (0x1<<24) // This bit masks, when set, the Parity bit: QM…
50964 … (0x1<<25) // This bit masks, when set, the Parity bit: QM…
50966 … (0x1<<26) // This bit masks, when set, the Parity bit: QM…
50968 … (0x1<<12) // This bit masks, when set, the Parity bit: QM…
50970 … (0x1<<27) // This bit masks, when set, the Parity bit: QM…
50972 … (0x1<<15) // This bit masks, when set, the Parity bit: QM…
50974 … (0x1<<28) // This bit masks, when set, the Parity bit: QM…
50976 … (0x1<<29) // This bit masks, when set, the Parity bit: QM…
50978 … (0x1<<30) // This bit masks, when set, the Parity bit: QM…
50980 … (0x1<<3) // This bit masks, when set, the Parity bi…
50981 …M_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_BB_K2_SHIFT 3
50982 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
50984 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
50986 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
50988 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
50990 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
50992 … (0x1<<11) // This bit masks, when set, the Parity bit: QM…
50994 … (0x1<<16) // This bit masks, when set, the Parity bit: QM…
50996 … (0x1<<17) // This bit masks, when set, the Parity bit: QM…
50998 … (0x1<<22) // This bit masks, when set, the Parity bit: QM…
51000 … (0x1<<23) // This bit masks, when set, the Parity bit: QM…
51002 … (0x1<<24) // This bit masks, when set, the Parity bit: QM…
51004 … (0x1<<25) // This bit masks, when set, the Parity bit: QM…
51006 … (0x1<<26) // This bit masks, when set, the Parity bit: QM…
51008 … (0x1<<27) // This bit masks, when set, the Parity bit: QM…
51010 … (0x1<<28) // This bit masks, when set, the Parity bit: QM…
51012 … (0x1<<29) // This bit masks, when set, the Parity bit: QM…
51014 … (0x1<<30) // This bit masks, when set, the Parity bit: QM…
51017 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
51019 … (0x1<<1) // This bit masks, when set, the Parity bit: QM…
51021 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
51023 … (0x1<<3) // This bit masks, when set, the Parity bi…
51024 …M_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_3_E5_SHIFT 3
51025 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
51027 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
51029 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
51031 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
51033 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
51035 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
51037 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
51039 … (0x1<<11) // This bit masks, when set, the Parity bit: QM…
51041 … (0x1<<12) // This bit masks, when set, the Parity bit: QM…
51043 … (0x1<<13) // This bit masks, when set, the Parity bit: QM…
51045 … (0x1<<14) // This bit masks, when set, the Parity bit: QM…
51047 … (0x1<<15) // This bit masks, when set, the Parity bit: QM…
51049 … (0x1<<16) // This bit masks, when set, the Parity bit: QM…
51051 … (0x1<<17) // This bit masks, when set, the Parity bit: QM…
51053 … (0x1<<0) // This bit masks, when set, the Parity bit: QM…
51055 … (0x1<<1) // This bit masks, when set, the Parity bit: QM…
51057 … (0x1<<2) // This bit masks, when set, the Parity bit: QM…
51059 … (0x1<<3) // This bit masks, when set, the Parity bi…
51060 …M_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_6_BB_K2_SHIFT 3
51061 … (0x1<<4) // This bit masks, when set, the Parity bit: QM…
51063 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
51065 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
51067 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
51069 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
51071 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
51073 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
51075 … (0x1<<11) // This bit masks, when set, the Parity bit: QM…
51077 … (0x1<<12) // This bit masks, when set, the Parity bit: QM…
51079 … (0x1<<5) // This bit masks, when set, the Parity bit: QM…
51081 … (0x1<<13) // This bit masks, when set, the Parity bit: QM…
51083 … (0x1<<6) // This bit masks, when set, the Parity bit: QM…
51085 … (0x1<<14) // This bit masks, when set, the Parity bit: QM…
51087 … (0x1<<7) // This bit masks, when set, the Parity bit: QM…
51089 … (0x1<<15) // This bit masks, when set, the Parity bit: QM…
51091 … (0x1<<8) // This bit masks, when set, the Parity bit: QM…
51093 … (0x1<<16) // This bit masks, when set, the Parity bit: QM…
51095 … (0x1<<9) // This bit masks, when set, the Parity bit: QM…
51097 … (0x1<<17) // This bit masks, when set, the Parity bit: QM…
51099 … (0x1<<10) // This bit masks, when set, the Parity bit: QM…
51101 … (0x1<<18) // This bit masks, when set, the Parity bit: QM…
51110 …3_I_ECC_1_EN_E5 (0x1<<3) // Enable ECC for m…
51111 …M_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_1_EN_E5_SHIFT 3
51120 …5_I_ECC_1_EN_BB_K2 (0x1<<3) // Enable ECC for m…
51121 …M_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_BB_K2_SHIFT 3
51131 …MEM003_I_ECC_1_PRTY_E5 (0x1<<3) // Set parity only …
51132 …M_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_1_PRTY_E5_SHIFT 3
51141 …MEM005_I_ECC_1_PRTY_BB_K2 (0x1<<3) // Set parity only …
51142 …M_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_BB_K2_SHIFT 3
51152 …D_0_MEM003_I_ECC_1_CORRECT_E5 (0x1<<3) // Record if a corr…
51153 …M_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_1_CORRECT_E5_SHIFT 3
51162 …D_0_MEM005_I_ECC_1_CORRECT_BB_K2 (0x1<<3) // Record if a corr…
51163 …M_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_BB_K2_SHIFT 3
51167 …aWidth:0x8 // drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); …
51168 …aWidth:0x8 // drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); …
51169 …aWidth:0x8 // drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); …
51170 …aWidth:0x8 // drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); …
51171 …aWidth:0x8 // drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); …
51172 …aWidth:0x8 // drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); …
51173 … Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); …
51174 … Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); …
51175 … Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); …
51176 … Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); …
51177 … Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); …
51178 … Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); …
51179 …0UL //Access:RW DataWidth:0x6 // Enable the write client. Bit: 0 = M; 1 = U; 2 = T; 3 = Y; 4 …
51180 …s to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN
51181 …s to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN
51182 …s to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN
51183 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51184 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51185 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51186 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51187 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51188 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51189 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51190 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51191 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51192 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51193 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51194 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51195 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51196 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51197 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51198 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51199 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51200 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51201 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51202 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51203 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51204 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51205 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51206 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51207 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51208 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51209 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51210 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51211 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51212 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51213 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51214 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51215 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51216 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51217 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51218 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51219 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51220 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51221 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51222 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51223 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51224 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51225 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51226 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51227 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51228 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51229 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51230 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51231 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51232 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51233 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51234 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51235 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51236 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51237 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51238 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51239 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51240 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51241 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51242 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51243 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51244 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51245 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51246 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51254 …r Other queues 63-0; The mapping is as follow: ptrtbl[53:30] read pointer; ptrtbl[29:6] write poin…
51260 … 0x2f1010UL //Access:W DataWidth:0x1 // The mem access cmd (0 - rd; 1 - wr) sent towards…
51264 … 0x2f1030UL //Access:W DataWidth:0x1 // The mem access cmd (0 - rd; 1 - wr) sent towards…
51265 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51266 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51267 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51268 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51269 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51270 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51271 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51272 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51273 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51274 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51275 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51276 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51277 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51278 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51279 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51280 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51281 …rrent Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Queues…
51282 …rrent Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Queues…
51283 …rrent Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Queues…
51284 …rrent Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Queues…
51285 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51286 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51287 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51288 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51289 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51290 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51291 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51292 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51293 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51294 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51295 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51296 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51297 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51298 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51299 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51300 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51301 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51302 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51303 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51304 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51305 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51306 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51307 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51308 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51309 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51310 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51311 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51312 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51313 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51314 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51315 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51316 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51317 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51318 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51319 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51320 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51321 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51322 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51323 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51324 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51325 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51326 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51327 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51328 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51329 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51330 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51331 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51332 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51333 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51334 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51335 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51336 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51337 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51338 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51339 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51340 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51341 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51342 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51343 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51344 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51345 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51346 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51347 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51348 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51349 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51350 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51351 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51352 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51353 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51354 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51355 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51356 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51357 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51358 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51359 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51360 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51361 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51362 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51363 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51364 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskT…
51367 …-b0: rd first bank in page; b3: reserved (zero); b6-b4: wr first bank in page; b7: reserved (zero)…
51368 …al STU within the PXP (there is STU per PF). 0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
51369 …H field used in the PCI request. Per PF value. bits: 8-0 TPH Steering Tag Index; 12-9 reserved; 14…
51375 …- VOQs [0..31] VoqCrdLineFull_msb - VOQs [32..35] Some VOQs are "not used" depending on the…
51376 … to the matched Voq line credit (relevant only for VOQs that are being used - or in other words VO…
51377 …- VOQs [0..31]. VoqCrdByteFull_msb - VOQs [32..35]. Some VOQs are "not used" depending on t…
51378 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51379 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51380 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51381 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51382 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51383 …bit). AFullQmBypThrLineVoqMask (This one) - VOQs [0..31]. AFullQmBypThrLineVoqMask_msb - VO…
51388 …bit per credit resource for the qm bypass. 1 - resource is required to be more than the almost ful…
51391 …ost full threshold for the opportunistic credit flow operation. reset value: -1 x TaskByteCrdCost_3
51392 …ost full threshold for the opportunistic credit flow operation. reset value: -1 x TaskByteCrdCost_4
51395 …bit per credit resource for the opportunistic credit. 1 - resource is required to be more than the…
51398 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51399 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51400 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51401 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51402 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51403 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51404 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51405 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51406 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51407 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51408 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51409 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51410 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51411 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51412 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51413 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51414 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51415 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51416 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51417 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51418 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51419 …eue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 …
51420 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51421 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51422 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51423 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51424 …-s that belong to TxPqMap[WrrWeightGrpRng]==2'b01. NOTE: weight update is allowed only to queues w…
51425 …-s that belong to TxPqMap[WrrWeightGrpRng]==2'b11. NOTE: weight update is allowed only to queues w…
51436 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51437 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51438 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51439 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51440 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51441 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51442 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51443 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51444 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51445 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51446 …bit per CM interface. If this bit is 0 then this interface is masked. i: 0 - MCM sec; 1 - MCM pri…
51447 …bit vector per CM interface which indicates which one of the Other queues are tied to the matched …
51450 … QM EAS section SDM memory map. Required flow: (a) Poll on the SdmCmdReady bit (i.e. SdmCmdReady=1…
51451 … QM EAS section SDM memory map. Required flow: (a) Poll on the SdmCmdReady bit (i.e. SdmCmdReady=1…
51452 … QM EAS section SDM memory map. Required flow: (a) Poll on the SdmCmdReady bit (i.e. SdmCmdReady=1…
51453 … QM EAS section SDM memory map. Required flow: (a) Poll on the SdmCmdReady bit (i.e. SdmCmdReady=1…
51454 … QM EAS section SDM memory map. Required flow: (a) Poll on the SdmCmdReady bit (i.e. SdmCmdReady=1…
51462 …0x2f2800UL //Access:R DataWidth:0x1 // The status of the Other PQ-s: bit0 - PQ paused. Shoul…
51465 … 0x2f2c00UL //Access:RW DataWidth:0x1 // Initialization bit command.
51466 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51467 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51468 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51469 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51470 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51471 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51472 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51473 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51474 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51475 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51476 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51477 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51478 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51479 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51480 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51481 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51482 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51483 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51484 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51485 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51486 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51487 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51488 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51489 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51490 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51491 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51492 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51493 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51494 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51495 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51496 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51497 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51498 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51499 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51500 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51501 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51502 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51503 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51504 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51505 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51506 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51507 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51508 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51509 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51510 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51511 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51512 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51513 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51514 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51515 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51516 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51517 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51518 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51519 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51520 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51521 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51522 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51523 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51524 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51525 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51526 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51527 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51528 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51529 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51530 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51531 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51532 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51533 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51534 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51535 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51536 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51537 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51538 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51539 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51540 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51541 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51542 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51543 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51544 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51545 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51550 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for selecting a line…
51551 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for enabling dwords …
51552 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for circular right s…
51553 … // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - forcing valid.
51554 … // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - forcing frame.
51555 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 lsb data that…
51556 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 msb data that…
51557 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 frame bits tha…
51558 …ebug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 valid bits tha…
51561 …r. The driver can clear this bit (through RBC) based on the functional flows (e.g. FLR). It is als…
51562 … 0x2f2ea4UL //Access:RW DataWidth:0x1 // PF enable vector. Bit per PF. If set the …
51563 … 0x2f2ea8UL //Access:RW DataWidth:0x1 // VF enable vector. Bit per VF. If set the …
51571 …ut period in 25Mhz clock cycles for the global. VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Gl…
51572 …out period in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Gl…
51573 … for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. Upon init should be set with value of …
51574 …od counter in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Gl…
51575 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51576 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51577 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51578 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51579 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51580 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51581 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51582 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51585 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51587 …-init mode. In init mode should be written with the same value of RlGlblUpperBound. Sign: the msb …
51591 …x1 // when 1 - force cam search and update sts_rlglbl_pq_blocked vector even when the rlglblcrd…
51592 …r)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51593 …r)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51594 …o). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51595 …e bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_Rl…
51596 …ataWidth:0x20 // The RL timeout period in 25Mhz clock cycles for the PF RL-s. NOTE: ck25 domain.…
51597 …:0x20 // The RL timeout period counter in 25Mhz clock cycles for the PF RL-s. Upon init should b…
51601 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51604 …-init mode. In init mode should be written with the same value of RlPfUpperBound. Sign: the msb is…
51608 … the PF RL mechanism per VOQ. RlPfVoqEnable (This one) - VOQs [0..31]. RlPfVoqEnable_msb - …
51609 …ter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51610 …ter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51611 …ero). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51612 …ype bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_…
51616 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51619 …- VOQ0..VOQ15. WfqPfCrd_msb - VOQ16..VOQ35. Should be read only access in non-init mode. In init m…
51624 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51625 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51626 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51627 …pe bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_W…
51629 …0x1 // when 1 - force cam search and update sts_wfqvp_pq_blocked vector even when the wfqvpcrd …
51630 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51631 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51632 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51633 …pe bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_W…
51634 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51635 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51636 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51637 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51638 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51639 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51640 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51641 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51642 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51643 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51644 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51645 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51646 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51647 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51648 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51649 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51650 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51651 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51652 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51653 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51654 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51655 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51656 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51657 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51659 …-idle state, trying to start new TX arbitration depends on the GO mode as follows: 0 - start new T…
51662 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51663 …ue. b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51664 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51665 …o). b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51666 …bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_VoqL…
51667 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51668 …ue. b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51669 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51670 …o). b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51671 …bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_VoqB…
51680 …ed. when reset the mem in not initiazlied. There is mask bit per mem, the following are mems 31-0:…
51681 …ed. when reset the mem in not initiazlied. There is mask bit per mem, the following are mems 63-32…
51682 …n reset the mem in initialized with all zeroes. There is bit per mem, the following are mems 31-0:…
51683 …n reset the mem in initialized with all zeroes. There is bit per mem, the following are mems 63-32…
51684 … the mem is currently being initialized. There is status bit per mem, the following are mems 31-0:…
51685 … the mem is currently being initialized. There is status bit per mem, the following are mems 63-32…
51689 … 0x2f5da8UL //Access:R DataWidth:0x16 // Provides read-only access to the BI…
51693 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51694 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51695 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51696 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51697 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51698 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51699 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51700 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51701 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51702 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51703 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51704 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51705 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51706 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51707 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51708 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51709 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51710 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51711 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51712 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51713 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51714 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51715 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51716 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51717 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51718 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51719 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51720 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51721 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51722 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51723 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51724 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51725 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51726 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51727 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51728 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51729 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51730 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51731 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51732 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51733 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51734 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51735 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51736 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51737 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51738 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51739 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51740 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51741 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51742 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51743 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51744 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51745 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51746 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51747 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51748 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51749 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51750 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51751 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51752 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51753 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51754 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51755 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51756 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51757 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51758 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51759 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51760 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51761 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51762 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51763 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51764 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51765 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51766 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51767 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51768 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51769 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51770 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51771 …oad request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51772 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51773 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51774 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51775 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51776 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51777 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51778 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51779 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51780 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51781 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51782 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51783 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51784 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51785 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51786 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51787 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51788 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51789 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51790 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51791 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51792 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51793 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51794 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51795 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51796 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51797 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51798 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51799 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51800 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51801 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51802 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51803 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51804 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51805 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51806 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51807 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51808 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51809 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51810 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51811 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51812 … the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51813 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51814 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51815 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51816 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51817 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51818 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51819 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51820 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51821 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51822 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51823 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51824 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51825 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51826 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51827 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51828 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51829 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51830 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51831 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51832 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51833 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51834 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51835 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51836 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51837 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51838 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51839 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51840 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51841 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51842 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51843 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51844 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51845 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51846 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51847 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51848 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51849 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51850 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51851 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51852 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51853 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51854 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51855 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51856 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51857 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51858 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51859 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51860 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51861 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51862 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51863 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51864 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51865 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51866 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51867 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51868 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51869 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51870 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51871 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51872 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51873 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51874 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51875 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51876 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51877 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51878 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51879 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51880 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51881 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51882 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51883 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51884 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51885 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51886 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51887 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51888 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51889 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51890 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51891 …load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnT…
51892 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51893 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51894 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51895 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51896 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51897 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51898 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51899 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51900 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51901 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51902 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51903 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51904 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51905 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51906 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51907 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51908 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51909 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51910 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51911 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51912 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51913 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51914 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51915 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51916 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51917 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51918 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51919 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51920 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51921 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51922 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51923 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51924 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51925 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51926 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51927 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51928 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51929 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51930 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51931 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51932 …ent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits …
51936 …th:0x4 // The status of the TX PQ-s: bit0 - PQ global VP/QCN RL block; bit1 - PQ active; bit2 -…
51939 …bit 0 - PQ valid; bits 8:1 - RL id; bits 17:9 - VP id (value of all ones is reserved for p…
51945 … the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of…
51948 …-init mode. In init mode should be written with the same value of WfqVpUpperBound. Sign: the msb i…
51951 …: Maps between VP WFQ counter and its resources as follows: bit 5:0 - Voq id; bit 9:6 - Pf i…
51954 …for TX queues 447-0; The mapping is as follow: ptrtbl[53:30] read pointer; ptrtbl[29:6] write poin…
51957 …-init mode. In init mode should be written with the same value of WfqPfUpperBound. Sign: the msb i…
51958 …-init mode. In init mode should be written with the same value of WfqPfUpperBound. Sign: the msb i…
51961 …bit vector per CM interface which indicates which one of the Other queues are tied to the matched …
51962 …bit vector per CM interface which indicates which one of the Other queues are tied to the matched …
51964 … // The actual line credit for each VOQ. Should be read only access in non-init mode. In init mo…
51965 … // The actual line credit for each VOQ. Should be read only access in non-init mode. In init mo…
51969 …it and maximum line credit for each VOQ. The max allowed init value is 2^15-1-2^9. Granularity of …
51970 …it and maximum line credit for each VOQ. The max allowed init value is 2^15-1-2^9. Granularity of …
51974 … // The actual byte credit for each VOQ. Should be read only access in non-init mode. In init mo…
51975 … // The actual byte credit for each VOQ. Should be read only access in non-init mode. In init mo…
51979 …0x18 // The init and maximum byte credit for each VOQ. The max allowed init value is 2^23-1-2^16.
51980 …it and maximum byte credit for each VOQ. The max allowed init value is 2^23-1-2^16. Some VOQs are …
51984 …bit). AFullQmBypThrLineVoqMask - VOQs [0..31]. AFullQmBypThrLineVoqMask_msb (This o…
51985 …F RL mechanism per VOQ. RlPfVoqEnable - VOQs [0..31]. RlPfVoqEnable_msb (This one) …
51986 …- VOQs [0..31]. VoqCrdLineFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending …
51987 …- VOQs [0..31]. VoqCrdByteFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending …
51989 …dth:0x1 // If set and DIF block found error; the DIF block will be stuck - hard reset is needed.
52001 …8 // If bit i is set; the data in the debug_error_info address[5:3] = i is valid. By writing 1 …
52004 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52005 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52007 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52008 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52010 …rved (formerly crc_seed) ; [6:5] protection_type ; [4] set_err_with_eop ; [3] host_guard_is_crc ;…
52013 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52014 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52016 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52017 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52019 …rved (formerly crc_seed) ; [6:5] protection_type ; [4] set_err_with_eop ; [3] host_guard_is_crc ;…
52020 … 0x3000c8UL //Access:R DataWidth:0x1 // Debug: one bit for each protocol I…
52021 … 0x3000ccUL //Access:R DataWidth:0x1 // DEBUG: 0 - no credit; 1 - there is cred…
52022 … 0x3000d0UL //Access:R DataWidth:0x1 // DEBUG: 0 - no message pending; 1 - message …
52023 …G: configuration fatal error. [1:0] host interface; [2] network interface; [3] FWRD ref; [4] FWR a…
52034 … (0x1<<3) // Write to full FI…
52035 …DIF_REG_INT_STS_CMD_FIFO_ERR_SHIFT 3
52047 … (0x1<<0) // This bit masks, when set, the Interrupt bit: R…
52049 … (0x1<<1) // This bit masks, when set, the Interrupt bit: R…
52051 … (0x1<<2) // This bit masks, when set, the Interrupt bit: R…
52053 … (0x1<<3) // This bit masks, when set, the Interrupt …
52054 …DIF_REG_INT_MASK_CMD_FIFO_ERR_SHIFT 3
52055 … (0x1<<4) // This bit masks, when set, the Interrupt bit: R…
52057 … (0x1<<5) // This bit masks, when set, the Interrupt bit: R…
52059 … (0x1<<6) // This bit masks, when set, the Interrupt bit: R…
52061 … (0x1<<7) // This bit masks, when set, the Interrupt bit: R…
52063 … (0x1<<8) // This bit masks, when set, the Interrupt bit: R…
52072 …ERR (0x1<<3) // Write to full FI…
52073 …DIF_REG_INT_STS_WR_CMD_FIFO_ERR_SHIFT 3
52091 …_ERR (0x1<<3) // Write to full FI…
52092 …DIF_REG_INT_STS_CLR_CMD_FIFO_ERR_SHIFT 3
52104 … (0x1<<1) // This bit masks, when set, the Parity bit: RD…
52106 …3] of the address represent the error number (0-7). Do not read from address[3:5]=i if debug_error…
52109 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
52110 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
52111 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
52112 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
52117 …-Initial reference tag Address offset-0 bits [31:0]; Field name-Application tag value Address offs…
52118 …bit). The partition per task context is as follows: In TDIF - Has 8 QWORDs per task allocated (All…
52122 …dth:0x1 // If set and DIF block found error; the DIF block will be stuck - hard reset is needed.
52123 … 0x310044UL //Access:RW DataWidth:0x1 // mask bit for the following c…
52135 …8 // If bit i is set; the data in the debug_error_info address[5:3] = i is valid. By writing 1 …
52138 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52139 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52141 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52142 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52144 …rved (formerly crc_seed) ; [6:5] protection_type ; [4] set_err_with_eop ; [3] host_guard_is_crc ;…
52147 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52148 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52150 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52151 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52153 …rved (formerly crc_seed) ; [6:5] protection_type ; [4] set_err_with_eop ; [3] host_guard_is_crc ;…
52154 … 0x3100c8UL //Access:R DataWidth:0x10 // Debug: one bit for each protocol I…
52155 … 0x3100ccUL //Access:R DataWidth:0x1 // DEBUG: 0 - no credit; 1 - there is cred…
52156 … 0x3100d0UL //Access:R DataWidth:0x1 // DEBUG: 0 - no message pending; 1 - message …
52157 …G: configuration fatal error. [1:0] host interface; [2] network interface; [3] FWRD ref; [4] FWR a…
52158 …dth:0x1b // [3:0] - error type ([0] Write overflow. [1] Read overflow. [2] Read from DIX when DI…
52163 …Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol ID 3.
52184 … (0x1<<3) // Write to full FI…
52185 …DIF_REG_INT_STS_CMD_FIFO_ERR_SHIFT 3
52197 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
52199 … (0x1<<1) // This bit masks, when set, the Interrupt bit: T…
52201 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
52203 … (0x1<<3) // This bit masks, when set, the Interrupt …
52204 …DIF_REG_INT_MASK_CMD_FIFO_ERR_SHIFT 3
52205 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
52207 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
52209 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
52211 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
52213 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
52222 …ERR (0x1<<3) // Write to full FI…
52223 …DIF_REG_INT_STS_WR_CMD_FIFO_ERR_SHIFT 3
52241 …_ERR (0x1<<3) // Write to full FI…
52242 …DIF_REG_INT_STS_CLR_CMD_FIFO_ERR_SHIFT 3
52254 … (0x1<<1) // This bit masks, when set, the Parity bit: TD…
52257 … (0x1<<0) // This bit masks, when set, the Parity bit: TD…
52259 … (0x1<<1) // This bit masks, when set, the Parity bit: TD…
52261 … (0x1<<2) // This bit masks, when set, the Parity bit: TD…
52263 … (0x1<<3) // This bit masks, when set, the Parity bi…
52264 …DIF_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_SHIFT 3
52265 … (0x1<<4) // This bit masks, when set, the Parity bit: TD…
52267 … (0x1<<5) // This bit masks, when set, the Parity bit: TD…
52269 … (0x1<<6) // This bit masks, when set, the Parity bit: TD…
52271 … (0x1<<7) // This bit masks, when set, the Parity bit: TD…
52273 … (0x1<<8) // This bit masks, when set, the Parity bit: TD…
52275 … (0x1<<9) // This bit masks, when set, the Parity bit: TD…
52277 … (0x1<<10) // This bit masks, when set, the Parity bit: TD…
52279 … (0x1<<10) // This bit masks, when set, the Parity bit: TD…
52281 … (0x1<<11) // This bit masks, when set, the Parity bit: TD…
52290 …011_I_ECC_EN (0x1<<3) // Enable ECC for m…
52291 …DIF_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_EN_SHIFT 3
52299 …0_MEM011_I_ECC_PRTY (0x1<<3) // Set parity only …
52300 …DIF_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_PRTY_SHIFT 3
52308 …TED_0_MEM011_I_ECC_CORRECT (0x1<<3) // Record if a corr…
52309 …DIF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_CORRECT_SHIFT 3
52311 …3] of the address represent the error number (0-7). Do not read from address[3:5]=i if debug_error…
52314 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
52315 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
52316 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
52317 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
52322 …bit). The partition per task context is as follows: In TDIF - Has 8 QWORDs per task allocated (All…
52326 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
52327 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
52328 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
52329 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
52338 … (0x1<<0) // This bit masks, when set, the Interrupt bit: R…
52348 … (0x1<<0) // This bit masks, when set, the Parity bit: RG…
52350 … (0x1<<1) // This bit masks, when set, the Parity bit: RG…
52373 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_…
52374 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_…
52389 …- SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; …
52398 … 0x320480UL //Access:RC DataWidth:0x20 // Number of SRC commands which hit with HOP=3 or more
52400 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
52401 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
52402 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
52403 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
52412 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
52422 … (0x1<<0) // This bit masks, when set, the Parity bit: TG…
52424 … (0x1<<1) // This bit masks, when set, the Parity bit: TG…
52447 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_…
52448 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_…
52463 …- SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; …
52472 … 0x322480UL //Access:RC DataWidth:0x20 // Number of SRC commands which hit with HOP=3 or more
52473 … // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en re…
52474 … // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en re…
52475 …bit should be set when initialization of all BRTB registers and memories is finished. BRTB will fi…
52483 …_ERROR (0x1<<3) // Read packet clie…
52484 …RB_REG_INT_STS_0_RC_PKT0_LEN_ERROR_SHIFT 3
52485 … (0x1<<4) // Read packet client PRM error when SOP bit is set in the packe…
52495 … (0x1<<9) // Read packet client MSDM error when SOP bit is set in the packe…
52505 … (0x1<<14) // Read packet client TSDM error when SOP bit is set in the packe…
52515 … (0x1<<19) // Read packet client parser error when SOP bit is set in the packe…
52525 … (0x1<<24) // Warning! Check this bit connection for E4 A…
52527 … (0x1<<25) // Warning! Check this bit connection for E4 A…
52529 …/ Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have…
52542 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
52544 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
52546 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
52548 … (0x1<<3) // This bit masks, when set, the Interrupt …
52549 …RB_REG_INT_MASK_0_RC_PKT0_LEN_ERROR_SHIFT 3
52550 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
52552 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
52554 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
52556 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
52558 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
52560 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
52562 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
52564 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
52566 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
52568 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
52570 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
52572 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
52574 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
52576 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
52578 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
52580 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
52582 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
52584 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
52586 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
52588 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
52590 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
52592 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
52594 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
52596 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
52598 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
52600 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
52602 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
52604 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
52613 …LEN_ERROR (0x1<<3) // Read packet clie…
52614 …RB_REG_INT_STS_WR_0_RC_PKT0_LEN_ERROR_SHIFT 3
52615 … (0x1<<4) // Read packet client PRM error when SOP bit is set in the packe…
52625 … (0x1<<9) // Read packet client MSDM error when SOP bit is set in the packe…
52635 … (0x1<<14) // Read packet client TSDM error when SOP bit is set in the packe…
52645 … (0x1<<19) // Read packet client parser error when SOP bit is set in the packe…
52655 … (0x1<<24) // Warning! Check this bit connection for E4 A…
52657 … (0x1<<25) // Warning! Check this bit connection for E4 A…
52659 …/ Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have…
52678 …_LEN_ERROR (0x1<<3) // Read packet clie…
52679 …RB_REG_INT_STS_CLR_0_RC_PKT0_LEN_ERROR_SHIFT 3
52680 … (0x1<<4) // Read packet client PRM error when SOP bit is set in the packe…
52690 … (0x1<<9) // Read packet client MSDM error when SOP bit is set in the packe…
52700 … (0x1<<14) // Read packet client TSDM error when SOP bit is set in the packe…
52710 … (0x1<<19) // Read packet client parser error when SOP bit is set in the packe…
52720 … (0x1<<24) // Warning! Check this bit connection for E4 A…
52722 … (0x1<<25) // Warning! Check this bit connection for E4 A…
52724 …/ Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have…
52741 …O_ERROR (0x1<<3) // Input FIFO error…
52742 …RB_REG_INT_STS_1_WC0_INP_FIFO_ERROR_SHIFT 3
52769 … (0x1<<18) // Warning! Check this bit connection for E4 A…
52771 … (0x1<<19) // Warning! Check this bit connection for E4 A…
52773 … (0x1<<20) // Warning! Check this bit connection for E4 A…
52775 … (0x1<<21) // Warning! Check this bit connection for E4 A…
52777 … (0x1<<22) // Warning! Check this bit connection for E4 A…
52779 … (0x1<<23) // Warning! Check this bit connection for E4 A…
52781 … (0x1<<24) // Warning! Check this bit connection for E4 A…
52783 … (0x1<<25) // Warning! Check this bit connection for E4 A…
52785 … (0x1<<26) // Warning! Check this bit connection for E4 A…
52787 … (0x1<<27) // Warning! Check this bit connection for E4 A…
52789 … (0x1<<28) // Warning! Check this bit connection for E4 A…
52791 … (0x1<<29) // Warning! Check this bit connection for E4 A…
52793 … (0x1<<30) // Warning! Check this bit connection for E4 A…
52795 … (0x1<<31) // Warning! Check this bit connection for E4 A…
52798 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
52800 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
52802 … (0x1<<3) // This bit masks, when set, the Interrupt …
52803 …RB_REG_INT_MASK_1_WC0_INP_FIFO_ERROR_SHIFT 3
52804 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
52806 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
52808 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
52810 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
52812 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
52814 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
52816 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
52818 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
52820 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
52822 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
52824 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
52826 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
52828 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
52830 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
52832 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
52834 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
52836 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
52838 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
52840 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
52842 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
52844 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
52846 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
52848 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
52850 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
52852 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
52854 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
52856 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
52863 …FIFO_ERROR (0x1<<3) // Input FIFO error…
52864 …RB_REG_INT_STS_WR_1_WC0_INP_FIFO_ERROR_SHIFT 3
52891 … (0x1<<18) // Warning! Check this bit connection for E4 A…
52893 … (0x1<<19) // Warning! Check this bit connection for E4 A…
52895 … (0x1<<20) // Warning! Check this bit connection for E4 A…
52897 … (0x1<<21) // Warning! Check this bit connection for E4 A…
52899 … (0x1<<22) // Warning! Check this bit connection for E4 A…
52901 … (0x1<<23) // Warning! Check this bit connection for E4 A…
52903 … (0x1<<24) // Warning! Check this bit connection for E4 A…
52905 … (0x1<<25) // Warning! Check this bit connection for E4 A…
52907 … (0x1<<26) // Warning! Check this bit connection for E4 A…
52909 … (0x1<<27) // Warning! Check this bit connection for E4 A…
52911 … (0x1<<28) // Warning! Check this bit connection for E4 A…
52913 … (0x1<<29) // Warning! Check this bit connection for E4 A…
52915 … (0x1<<30) // Warning! Check this bit connection for E4 A…
52917 … (0x1<<31) // Warning! Check this bit connection for E4 A…
52924 …_FIFO_ERROR (0x1<<3) // Input FIFO error…
52925 …RB_REG_INT_STS_CLR_1_WC0_INP_FIFO_ERROR_SHIFT 3
52952 … (0x1<<18) // Warning! Check this bit connection for E4 A…
52954 … (0x1<<19) // Warning! Check this bit connection for E4 A…
52956 … (0x1<<20) // Warning! Check this bit connection for E4 A…
52958 … (0x1<<21) // Warning! Check this bit connection for E4 A…
52960 … (0x1<<22) // Warning! Check this bit connection for E4 A…
52962 … (0x1<<23) // Warning! Check this bit connection for E4 A…
52964 … (0x1<<24) // Warning! Check this bit connection for E4 A…
52966 … (0x1<<25) // Warning! Check this bit connection for E4 A…
52968 … (0x1<<26) // Warning! Check this bit connection for E4 A…
52970 … (0x1<<27) // Warning! Check this bit connection for E4 A…
52972 … (0x1<<28) // Warning! Check this bit connection for E4 A…
52974 … (0x1<<29) // Warning! Check this bit connection for E4 A…
52976 … (0x1<<30) // Warning! Check this bit connection for E4 A…
52978 … (0x1<<31) // Warning! Check this bit connection for E4 A…
52981 … (0x1<<0) // Warning! Check this bit connection for E4 A…
52983 … (0x1<<1) // Warning! Check this bit connection for E4 A…
52985 … (0x1<<2) // Warning! Check this bit connection for E4 A…
52987 … (0x1<<3) // Warning! Check this bit connec…
52988 …RB_REG_INT_STS_2_WC2_QUEUE_FIFO_ERROR_SHIFT 3
52989 … (0x1<<4) // Warning! Check this bit connection for E4 A…
52991 … (0x1<<5) // Warning! Check this bit connection for E4 A…
52993 … (0x1<<6) // Warning! Check this bit connection for E4 A…
52995 … (0x1<<7) // Warning! Check this bit connection for E4 A…
52997 … (0x1<<8) // Warning! Check this bit connection for E4 A…
52999 … (0x1<<9) // Warning! Check this bit connection for E4 A…
53001 … (0x1<<10) // Warning! Check this bit connection for E4 A…
53003 … (0x1<<11) // Warning! Check this bit connection for E4 A…
53005 … (0x1<<12) // Warning! Check this bit connection for E4 A…
53007 … (0x1<<13) // Warning! Check this bit connection for E4 A…
53009 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in wr…
53011 … (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in wri…
53013 … (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in wri…
53015 … (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in wr…
53017 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in…
53019 … (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in…
53021 … (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in wr…
53023 … (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error…
53025 … (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error …
53027 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in…
53029 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in wr…
53031 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in writ…
53033 …ng! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for…
53035 …k this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for request…
53038 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
53040 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
53042 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
53044 … (0x1<<3) // This bit masks, when set, the Interrupt …
53045 …RB_REG_INT_MASK_2_WC2_QUEUE_FIFO_ERROR_SHIFT 3
53046 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
53048 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
53050 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
53052 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
53054 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
53056 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
53058 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
53060 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
53062 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
53064 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
53066 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
53068 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
53070 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
53072 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
53074 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
53076 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
53078 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
53080 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
53082 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
53084 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
53086 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
53088 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
53090 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
53092 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
53095 … (0x1<<0) // Warning! Check this bit connection for E4 A…
53097 … (0x1<<1) // Warning! Check this bit connection for E4 A…
53099 … (0x1<<2) // Warning! Check this bit connection for E4 A…
53101 … (0x1<<3) // Warning! Check this bit connec…
53102 …RB_REG_INT_STS_WR_2_WC2_QUEUE_FIFO_ERROR_SHIFT 3
53103 … (0x1<<4) // Warning! Check this bit connection for E4 A…
53105 … (0x1<<5) // Warning! Check this bit connection for E4 A…
53107 … (0x1<<6) // Warning! Check this bit connection for E4 A…
53109 … (0x1<<7) // Warning! Check this bit connection for E4 A…
53111 … (0x1<<8) // Warning! Check this bit connection for E4 A…
53113 … (0x1<<9) // Warning! Check this bit connection for E4 A…
53115 … (0x1<<10) // Warning! Check this bit connection for E4 A…
53117 … (0x1<<11) // Warning! Check this bit connection for E4 A…
53119 … (0x1<<12) // Warning! Check this bit connection for E4 A…
53121 … (0x1<<13) // Warning! Check this bit connection for E4 A…
53123 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in wr…
53125 … (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in wri…
53127 … (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in wri…
53129 … (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in wr…
53131 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in…
53133 … (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in…
53135 … (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in wr…
53137 … (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error…
53139 … (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error …
53141 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in…
53143 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in wr…
53145 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in writ…
53147 …ng! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for…
53149 …k this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for request…
53152 … (0x1<<0) // Warning! Check this bit connection for E4 A…
53154 … (0x1<<1) // Warning! Check this bit connection for E4 A…
53156 … (0x1<<2) // Warning! Check this bit connection for E4 A…
53158 … (0x1<<3) // Warning! Check this bit connec…
53159 …RB_REG_INT_STS_CLR_2_WC2_QUEUE_FIFO_ERROR_SHIFT 3
53160 … (0x1<<4) // Warning! Check this bit connection for E4 A…
53162 … (0x1<<5) // Warning! Check this bit connection for E4 A…
53164 … (0x1<<6) // Warning! Check this bit connection for E4 A…
53166 … (0x1<<7) // Warning! Check this bit connection for E4 A…
53168 … (0x1<<8) // Warning! Check this bit connection for E4 A…
53170 … (0x1<<9) // Warning! Check this bit connection for E4 A…
53172 … (0x1<<10) // Warning! Check this bit connection for E4 A…
53174 … (0x1<<11) // Warning! Check this bit connection for E4 A…
53176 … (0x1<<12) // Warning! Check this bit connection for E4 A…
53178 … (0x1<<13) // Warning! Check this bit connection for E4 A…
53180 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in wr…
53182 … (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in wri…
53184 … (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in wri…
53186 … (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in wr…
53188 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in…
53190 … (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in…
53192 … (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in wr…
53194 … (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error…
53196 … (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error …
53198 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in…
53200 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in wr…
53202 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in writ…
53204 …ng! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for…
53206 …k this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for request…
53213 …_FIFO_ERROR (0x1<<3) // Read packet clie…
53214 …RB_REG_INT_STS_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT 3
53272 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
53274 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
53276 … (0x1<<3) // This bit masks, when set, the Interrupt …
53277 …RB_REG_INT_MASK_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT 3
53278 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
53280 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
53282 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
53284 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
53286 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
53288 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
53290 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
53292 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
53294 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
53296 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
53298 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
53300 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
53302 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
53304 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
53306 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
53308 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
53310 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
53312 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
53314 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
53316 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
53318 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
53320 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
53322 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
53324 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
53326 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
53328 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
53330 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
53332 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
53339 …BLK_FIFO_ERROR (0x1<<3) // Read packet clie…
53340 …RB_REG_INT_STS_WR_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT 3
53402 …_BLK_FIFO_ERROR (0x1<<3) // Read packet clie…
53403 …RB_REG_INT_STS_CLR_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT 3
53467 …_FIFO_ERROR (0x1<<3) // Read SOP client …
53468 …RB_REG_INT_STS_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT 3
53495 … (0x1<<22) // Read packet client parser error when SOP bit is set in the packe…
53516 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
53518 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
53520 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
53522 … (0x1<<3) // This bit masks, when set, the Interrupt …
53523 …RB_REG_INT_MASK_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT 3
53524 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
53526 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
53528 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
53530 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
53532 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
53534 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
53536 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
53538 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
53540 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
53542 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
53544 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
53546 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
53548 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
53550 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
53552 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
53554 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
53556 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
53558 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
53560 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
53562 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
53564 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
53566 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
53568 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
53577 …SCR_FIFO_ERROR (0x1<<3) // Read SOP client …
53578 …RB_REG_INT_STS_WR_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT 3
53605 … (0x1<<22) // Read packet client parser error when SOP bit is set in the packe…
53632 …DSCR_FIFO_ERROR (0x1<<3) // Read SOP client …
53633 …RB_REG_INT_STS_CLR_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT 3
53660 … (0x1<<22) // Read packet client parser error when SOP bit is set in the packe…
53684 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
53695 … (0x1<<23) // Warning! Check this bit connection for E4 A…
53697 … (0x1<<24) // Warning! Check this bit connection for E4 A…
53699 … (0x1<<25) // Warning! Check this bit connection for E4 A…
53701 … (0x1<<26) // Warning! Check this bit connection for E4 A…
53703 … (0x1<<29) // Warning! Check this bit connection for E4 A…
53705 … (0x1<<30) // Warning! Check this bit connection for E4 A…
53707 … (0x1<<31) // Warning! Check this bit connection for E4 A…
53710 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
53712 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
53714 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
53716 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
53718 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
53720 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
53722 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
53724 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
53729 … (0x1<<23) // Warning! Check this bit connection for E4 A…
53731 … (0x1<<24) // Warning! Check this bit connection for E4 A…
53733 … (0x1<<25) // Warning! Check this bit connection for E4 A…
53735 … (0x1<<26) // Warning! Check this bit connection for E4 A…
53737 … (0x1<<29) // Warning! Check this bit connection for E4 A…
53739 … (0x1<<30) // Warning! Check this bit connection for E4 A…
53741 … (0x1<<31) // Warning! Check this bit connection for E4 A…
53746 … (0x1<<23) // Warning! Check this bit connection for E4 A…
53748 … (0x1<<24) // Warning! Check this bit connection for E4 A…
53750 … (0x1<<25) // Warning! Check this bit connection for E4 A…
53752 … (0x1<<26) // Warning! Check this bit connection for E4 A…
53754 … (0x1<<29) // Warning! Check this bit connection for E4 A…
53756 … (0x1<<30) // Warning! Check this bit connection for E4 A…
53758 … (0x1<<31) // Warning! Check this bit connection for E4 A…
53761 … (0x1<<0) // Warning! Check this bit connection for E4 A…
53763 … (0x1<<1) // Warning! Check this bit connection for E4 A…
53765 … (0x1<<2) // Warning! Check this bit connection for E4 A…
53767 …R (0x1<<3) // Warning! Check this bit connec…
53768 …RB_REG_INT_STS_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT 3
53769 … (0x1<<4) // Warning! Check this bit connection for E4 A…
53771 … (0x1<<5) // Warning! Check this bit connection for E4 A…
53773 … (0x1<<6) // Warning! Check this bit connection for E4 A…
53775 … (0x1<<7) // Warning! Check this bit connection for E4 A…
53777 … (0x1<<8) // Warning! Check this bit connection for E4 A…
53779 … (0x1<<9) // Warning! Check this bit connection for E4 A…
53781 … (0x1<<10) // Warning! Check this bit connection for E4 A…
53783 … (0x1<<11) // Warning! Check this bit connection for E4 A…
53785 … (0x1<<12) // Warning! Check this bit connection for E4 A…
53787 … (0x1<<13) // Warning! Check this bit connection for E4 A…
53789 … (0x1<<14) // Warning! Check this bit connection for E4 A…
53791 … (0x1<<15) // Warning! Check this bit connection for E4 A…
53793 … (0x1<<16) // Warning! Check this bit connection for E4 A…
53795 … (0x1<<17) // Warning! Check this bit connection for E4 A…
53797 … (0x1<<18) // Warning! Check this bit connection for E4 A…
53801 … (0x1<<20) // Warning! Check this bit connection for E4 A…
53803 … (0x1<<21) // Warning! Check this bit connection for E4 A…
53805 … (0x1<<22) // Warning! Check this bit connection for E4 A…
53807 … (0x1<<23) // Warning! Check this bit connection for E4 A…
53809 … (0x1<<24) // Warning! Check this bit connection for E4 A…
53811 … (0x1<<25) // Warning! Check this bit connection for E4 A…
53813 … (0x1<<26) // Warning! Check this bit connection for E4 A…
53815 … (0x1<<27) // Warning! Check this bit connection for E4 A…
53817 … (0x1<<28) // Warning! Check this bit connection for E4 A…
53819 … (0x1<<29) // Warning! Check this bit connection for E4 A…
53821 … (0x1<<30) // Warning! Check this bit connection for E4 A…
53823 … (0x1<<31) // Warning! Check this bit connection for E4 A…
53826 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
53828 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
53830 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
53832 … (0x1<<3) // This bit masks, when set, the Interrupt …
53833 …RB_REG_INT_MASK_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT 3
53834 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
53836 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
53838 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
53840 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
53842 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
53844 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
53846 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
53848 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
53850 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
53852 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
53854 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
53856 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
53858 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
53860 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
53862 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
53864 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
53866 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
53868 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
53870 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
53872 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
53874 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
53876 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
53878 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
53880 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
53882 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
53884 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
53886 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
53888 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
53891 … (0x1<<0) // Warning! Check this bit connection for E4 A…
53893 … (0x1<<1) // Warning! Check this bit connection for E4 A…
53895 … (0x1<<2) // Warning! Check this bit connection for E4 A…
53897 …RROR (0x1<<3) // Warning! Check this bit connec…
53898 …RB_REG_INT_STS_WR_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT 3
53899 … (0x1<<4) // Warning! Check this bit connection for E4 A…
53901 … (0x1<<5) // Warning! Check this bit connection for E4 A…
53903 … (0x1<<6) // Warning! Check this bit connection for E4 A…
53905 … (0x1<<7) // Warning! Check this bit connection for E4 A…
53907 … (0x1<<8) // Warning! Check this bit connection for E4 A…
53909 … (0x1<<9) // Warning! Check this bit connection for E4 A…
53911 … (0x1<<10) // Warning! Check this bit connection for E4 A…
53913 … (0x1<<11) // Warning! Check this bit connection for E4 A…
53915 … (0x1<<12) // Warning! Check this bit connection for E4 A…
53917 … (0x1<<13) // Warning! Check this bit connection for E4 A…
53919 … (0x1<<14) // Warning! Check this bit connection for E4 A…
53921 … (0x1<<15) // Warning! Check this bit connection for E4 A…
53923 … (0x1<<16) // Warning! Check this bit connection for E4 A…
53925 … (0x1<<17) // Warning! Check this bit connection for E4 A…
53927 … (0x1<<18) // Warning! Check this bit connection for E4 A…
53931 … (0x1<<20) // Warning! Check this bit connection for E4 A…
53933 … (0x1<<21) // Warning! Check this bit connection for E4 A…
53935 … (0x1<<22) // Warning! Check this bit connection for E4 A…
53937 … (0x1<<23) // Warning! Check this bit connection for E4 A…
53939 … (0x1<<24) // Warning! Check this bit connection for E4 A…
53941 … (0x1<<25) // Warning! Check this bit connection for E4 A…
53943 … (0x1<<26) // Warning! Check this bit connection for E4 A…
53945 … (0x1<<27) // Warning! Check this bit connection for E4 A…
53947 … (0x1<<28) // Warning! Check this bit connection for E4 A…
53949 … (0x1<<29) // Warning! Check this bit connection for E4 A…
53951 … (0x1<<30) // Warning! Check this bit connection for E4 A…
53953 … (0x1<<31) // Warning! Check this bit connection for E4 A…
53956 … (0x1<<0) // Warning! Check this bit connection for E4 A…
53958 … (0x1<<1) // Warning! Check this bit connection for E4 A…
53960 … (0x1<<2) // Warning! Check this bit connection for E4 A…
53962 …ERROR (0x1<<3) // Warning! Check this bit connec…
53963 …RB_REG_INT_STS_CLR_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT 3
53964 … (0x1<<4) // Warning! Check this bit connection for E4 A…
53966 … (0x1<<5) // Warning! Check this bit connection for E4 A…
53968 … (0x1<<6) // Warning! Check this bit connection for E4 A…
53970 … (0x1<<7) // Warning! Check this bit connection for E4 A…
53972 … (0x1<<8) // Warning! Check this bit connection for E4 A…
53974 … (0x1<<9) // Warning! Check this bit connection for E4 A…
53976 … (0x1<<10) // Warning! Check this bit connection for E4 A…
53978 … (0x1<<11) // Warning! Check this bit connection for E4 A…
53980 … (0x1<<12) // Warning! Check this bit connection for E4 A…
53982 … (0x1<<13) // Warning! Check this bit connection for E4 A…
53984 … (0x1<<14) // Warning! Check this bit connection for E4 A…
53986 … (0x1<<15) // Warning! Check this bit connection for E4 A…
53988 … (0x1<<16) // Warning! Check this bit connection for E4 A…
53990 … (0x1<<17) // Warning! Check this bit connection for E4 A…
53992 … (0x1<<18) // Warning! Check this bit connection for E4 A…
53996 … (0x1<<20) // Warning! Check this bit connection for E4 A…
53998 … (0x1<<21) // Warning! Check this bit connection for E4 A…
54000 … (0x1<<22) // Warning! Check this bit connection for E4 A…
54002 … (0x1<<23) // Warning! Check this bit connection for E4 A…
54004 … (0x1<<24) // Warning! Check this bit connection for E4 A…
54006 … (0x1<<25) // Warning! Check this bit connection for E4 A…
54008 … (0x1<<26) // Warning! Check this bit connection for E4 A…
54010 … (0x1<<27) // Warning! Check this bit connection for E4 A…
54012 … (0x1<<28) // Warning! Check this bit connection for E4 A…
54014 … (0x1<<29) // Warning! Check this bit connection for E4 A…
54016 … (0x1<<30) // Warning! Check this bit connection for E4 A…
54018 … (0x1<<31) // Warning! Check this bit connection for E4 A…
54021 … (0x1<<0) // Warning! Check this bit connection for E4 A…
54023 … (0x1<<1) // Warning! Check this bit connection for E4 A…
54025 … (0x1<<2) // Warning! Check this bit connection for E4 A…
54027 … (0x1<<3) // Warning! Check this bit connec…
54028 …RB_REG_INT_STS_8_WC6_BB_PA_CNT_ERROR_SHIFT 3
54029 … (0x1<<4) // Warning! Check this bit connection for E4 A…
54031 … (0x1<<5) // Warning! Check this bit connection for E4 A…
54033 … (0x1<<6) // Warning! Check this bit connection for E4 A…
54035 … (0x1<<7) // Warning! Check this bit connection for E4 A…
54037 … (0x1<<8) // Warning! Check this bit connection for E4 A…
54039 … (0x1<<9) // Warning! Check this bit connection for E4 A…
54041 … (0x1<<10) // Warning! Check this bit connection for E4 A…
54043 … (0x1<<11) // Warning! Check this bit connection for E4 A…
54045 … (0x1<<12) // Warning! Check this bit connection for E4 A…
54047 … (0x1<<13) // Warning! Check this bit connection for E4 A…
54049 … (0x1<<14) // Warning! Check this bit connection for E4 A…
54051 … (0x1<<15) // Warning! Check this bit connection for E4 A…
54053 … (0x1<<16) // Warning! Check this bit connection for E4 A…
54056 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
54058 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
54060 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
54062 … (0x1<<3) // This bit masks, when set, the Interrupt …
54063 …RB_REG_INT_MASK_8_WC6_BB_PA_CNT_ERROR_SHIFT 3
54064 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
54066 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
54068 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
54070 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
54072 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
54074 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
54076 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
54078 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
54080 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
54082 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
54084 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
54086 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
54088 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
54091 … (0x1<<0) // Warning! Check this bit connection for E4 A…
54093 … (0x1<<1) // Warning! Check this bit connection for E4 A…
54095 … (0x1<<2) // Warning! Check this bit connection for E4 A…
54097 … (0x1<<3) // Warning! Check this bit connec…
54098 …RB_REG_INT_STS_WR_8_WC6_BB_PA_CNT_ERROR_SHIFT 3
54099 … (0x1<<4) // Warning! Check this bit connection for E4 A…
54101 … (0x1<<5) // Warning! Check this bit connection for E4 A…
54103 … (0x1<<6) // Warning! Check this bit connection for E4 A…
54105 … (0x1<<7) // Warning! Check this bit connection for E4 A…
54107 … (0x1<<8) // Warning! Check this bit connection for E4 A…
54109 … (0x1<<9) // Warning! Check this bit connection for E4 A…
54111 … (0x1<<10) // Warning! Check this bit connection for E4 A…
54113 … (0x1<<11) // Warning! Check this bit connection for E4 A…
54115 … (0x1<<12) // Warning! Check this bit connection for E4 A…
54117 … (0x1<<13) // Warning! Check this bit connection for E4 A…
54119 … (0x1<<14) // Warning! Check this bit connection for E4 A…
54121 … (0x1<<15) // Warning! Check this bit connection for E4 A…
54123 … (0x1<<16) // Warning! Check this bit connection for E4 A…
54126 … (0x1<<0) // Warning! Check this bit connection for E4 A…
54128 … (0x1<<1) // Warning! Check this bit connection for E4 A…
54130 … (0x1<<2) // Warning! Check this bit connection for E4 A…
54132 … (0x1<<3) // Warning! Check this bit connec…
54133 …RB_REG_INT_STS_CLR_8_WC6_BB_PA_CNT_ERROR_SHIFT 3
54134 … (0x1<<4) // Warning! Check this bit connection for E4 A…
54136 … (0x1<<5) // Warning! Check this bit connection for E4 A…
54138 … (0x1<<6) // Warning! Check this bit connection for E4 A…
54140 … (0x1<<7) // Warning! Check this bit connection for E4 A…
54142 … (0x1<<8) // Warning! Check this bit connection for E4 A…
54144 … (0x1<<9) // Warning! Check this bit connection for E4 A…
54146 … (0x1<<10) // Warning! Check this bit connection for E4 A…
54148 … (0x1<<11) // Warning! Check this bit connection for E4 A…
54150 … (0x1<<12) // Warning! Check this bit connection for E4 A…
54152 … (0x1<<13) // Warning! Check this bit connection for E4 A…
54154 … (0x1<<14) // Warning! Check this bit connection for E4 A…
54156 … (0x1<<15) // Warning! Check this bit connection for E4 A…
54158 … (0x1<<16) // Warning! Check this bit connection for E4 A…
54161 … (0x1<<0) // Warning! Check this bit connection for E4 A…
54164 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
54167 … (0x1<<0) // Warning! Check this bit connection for E4 A…
54170 … (0x1<<0) // Warning! Check this bit connection for E4 A…
54177 …NC_FIFO_PUSH_ERROR (0x1<<3) // Packet RC input …
54178 …RB_REG_INT_STS_10_RC1_INP_SYNC_FIFO_PUSH_ERROR_SHIFT 3
54210 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
54212 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
54214 … (0x1<<3) // This bit masks, when set, the Interrupt …
54215 …RB_REG_INT_MASK_10_RC1_INP_SYNC_FIFO_PUSH_ERROR_SHIFT 3
54216 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
54218 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
54220 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
54222 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
54224 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
54226 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
54228 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
54230 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
54232 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
54234 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
54236 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
54238 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
54240 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
54242 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
54244 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
54251 …_SYNC_FIFO_PUSH_ERROR (0x1<<3) // Packet RC input …
54252 …RB_REG_INT_STS_WR_10_RC1_INP_SYNC_FIFO_PUSH_ERROR_SHIFT 3
54288 …P_SYNC_FIFO_PUSH_ERROR (0x1<<3) // Packet RC input …
54289 …RB_REG_INT_STS_CLR_10_RC1_INP_SYNC_FIFO_PUSH_ERROR_SHIFT 3
54327 … (0x1<<13) // Free shared area calculation error for MAC port 3 When unified_shared_…
54329 … (0x1<<14) // Warning! Check this bit connection for E4 A…
54331 … (0x1<<15) // Warning! Check this bit connection for E4 A…
54333 … (0x1<<16) // Warning! Check this bit connection for E4 A…
54335 … (0x1<<17) // Warning! Check this bit connection for E4 A…
54338 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
54340 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
54342 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
54344 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
54346 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
54348 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
54350 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
54352 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
54361 … (0x1<<13) // Free shared area calculation error for MAC port 3 When unified_shared_…
54363 … (0x1<<14) // Warning! Check this bit connection for E4 A…
54365 … (0x1<<15) // Warning! Check this bit connection for E4 A…
54367 … (0x1<<16) // Warning! Check this bit connection for E4 A…
54369 … (0x1<<17) // Warning! Check this bit connection for E4 A…
54378 … (0x1<<13) // Free shared area calculation error for MAC port 3 When unified_shared_…
54380 … (0x1<<14) // Warning! Check this bit connection for E4 A…
54382 … (0x1<<15) // Warning! Check this bit connection for E4 A…
54384 … (0x1<<16) // Warning! Check this bit connection for E4 A…
54386 … (0x1<<17) // Warning! Check this bit connection for E4 A…
54389 … (0x1<<0) // This bit masks, when set, the Parity bit: BR…
54391 … (0x1<<1) // This bit masks, when set, the Parity bit: BR…
54393 … (0x1<<2) // This bit masks, when set, the Parity bit: BR…
54395 … (0x1<<3) // This bit masks, when set, the Parity bi…
54396 …RB_REG_PRTY_MASK_LL_BANK3_MEM_PRTY_SHIFT 3
54397 … (0x1<<4) // This bit masks, when set, the Parity bit: BR…
54400 … (0x1<<0) // This bit masks, when set, the Parity bit: BR…
54402 … (0x1<<1) // This bit masks, when set, the Parity bit: BR…
54404 … (0x1<<2) // This bit masks, when set, the Parity bit: BR…
54406 … (0x1<<3) // This bit masks, when set, the Parity bi…
54407 …RB_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_SHIFT 3
54408 … (0x1<<4) // This bit masks, when set, the Parity bit: BR…
54410 … (0x1<<5) // This bit masks, when set, the Parity bit: BR…
54412 … (0x1<<6) // This bit masks, when set, the Parity bit: BR…
54414 … (0x1<<7) // This bit masks, when set, the Parity bit: BR…
54416 … (0x1<<8) // This bit masks, when set, the Parity bit: BR…
54418 … (0x1<<9) // This bit masks, when set, the Parity bit: BR…
54420 … (0x1<<10) // This bit masks, when set, the Parity bit: BR…
54422 … (0x1<<11) // This bit masks, when set, the Parity bit: BR…
54424 … (0x1<<12) // This bit masks, when set, the Parity bit: BR…
54426 … (0x1<<13) // This bit masks, when set, the Parity bit: BR…
54428 … (0x1<<14) // This bit masks, when set, the Parity bit: BR…
54430 … (0x1<<15) // This bit masks, when set, the Parity bit: BR…
54432 … (0x1<<16) // This bit masks, when set, the Parity bit: BR…
54434 … (0x1<<17) // This bit masks, when set, the Parity bit: BR…
54436 … (0x1<<18) // This bit masks, when set, the Parity bit: BR…
54438 … (0x1<<19) // This bit masks, when set, the Parity bit: BR…
54440 … (0x1<<20) // This bit masks, when set, the Parity bit: BR…
54442 … (0x1<<21) // This bit masks, when set, the Parity bit: BR…
54444 … (0x1<<22) // This bit masks, when set, the Parity bit: BR…
54446 … (0x1<<23) // This bit masks, when set, the Parity bit: BR…
54448 … (0x1<<29) // This bit masks, when set, the Parity bit: BR…
54450 … (0x1<<24) // This bit masks, when set, the Parity bit: BR…
54452 … (0x1<<28) // This bit masks, when set, the Parity bit: BR…
54454 … (0x1<<25) // This bit masks, when set, the Parity bit: BR…
54456 … (0x1<<20) // This bit masks, when set, the Parity bit: BR…
54458 … (0x1<<26) // This bit masks, when set, the Parity bit: BR…
54460 … (0x1<<21) // This bit masks, when set, the Parity bit: BR…
54462 … (0x1<<27) // This bit masks, when set, the Parity bit: BR…
54464 … (0x1<<22) // This bit masks, when set, the Parity bit: BR…
54466 … (0x1<<28) // This bit masks, when set, the Parity bit: BR…
54468 … (0x1<<23) // This bit masks, when set, the Parity bit: BR…
54470 … (0x1<<29) // This bit masks, when set, the Parity bit: BR…
54472 … (0x1<<24) // This bit masks, when set, the Parity bit: BR…
54474 … (0x1<<30) // This bit masks, when set, the Parity bit: BR…
54476 … (0x1<<16) // This bit masks, when set, the Parity bit: BR…
54478 … (0x1<<17) // This bit masks, when set, the Parity bit: BR…
54480 … (0x1<<17) // This bit masks, when set, the Parity bit: BR…
54482 … (0x1<<18) // This bit masks, when set, the Parity bit: BR…
54484 … (0x1<<16) // This bit masks, when set, the Parity bit: BR…
54486 … (0x1<<19) // This bit masks, when set, the Parity bit: BR…
54488 … (0x1<<20) // This bit masks, when set, the Parity bit: BR…
54490 … (0x1<<21) // This bit masks, when set, the Parity bit: BR…
54492 … (0x1<<22) // This bit masks, when set, the Parity bit: BR…
54494 … (0x1<<23) // This bit masks, when set, the Parity bit: BR…
54496 … (0x1<<24) // This bit masks, when set, the Parity bit: BR…
54498 … (0x1<<25) // This bit masks, when set, the Parity bit: BR…
54500 … (0x1<<26) // This bit masks, when set, the Parity bit: BR…
54502 … (0x1<<27) // This bit masks, when set, the Parity bit: BR…
54504 … (0x1<<30) // This bit masks, when set, the Parity bit: BR…
54506 … (0x1<<18) // This bit masks, when set, the Parity bit: BR…
54508 … (0x1<<19) // This bit masks, when set, the Parity bit: BR…
54510 … (0x1<<25) // This bit masks, when set, the Parity bit: BR…
54512 … (0x1<<26) // This bit masks, when set, the Parity bit: BR…
54514 … (0x1<<27) // This bit masks, when set, the Parity bit: BR…
54516 … (0x1<<28) // This bit masks, when set, the Parity bit: BR…
54518 … (0x1<<29) // This bit masks, when set, the Parity bit: BR…
54520 … (0x1<<30) // This bit masks, when set, the Parity bit: BR…
54523 … (0x1<<10) // This bit masks, when set, the Parity bit: BR…
54525 … (0x1<<0) // This bit masks, when set, the Parity bit: BR…
54527 … (0x1<<1) // This bit masks, when set, the Parity bit: BR…
54529 … (0x1<<2) // This bit masks, when set, the Parity bit: BR…
54531 … (0x1<<3) // This bit masks, when set, the Parity bi…
54532 …RB_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_E5_SHIFT 3
54533 … (0x1<<4) // This bit masks, when set, the Parity bit: BR…
54535 … (0x1<<5) // This bit masks, when set, the Parity bit: BR…
54537 … (0x1<<6) // This bit masks, when set, the Parity bit: BR…
54539 … (0x1<<7) // This bit masks, when set, the Parity bit: BR…
54541 … (0x1<<8) // This bit masks, when set, the Parity bit: BR…
54543 … (0x1<<9) // This bit masks, when set, the Parity bit: BR…
54545 … (0x1<<10) // This bit masks, when set, the Parity bit: BR…
54547 … (0x1<<11) // This bit masks, when set, the Parity bit: BR…
54549 … (0x1<<12) // This bit masks, when set, the Parity bit: BR…
54551 … (0x1<<13) // This bit masks, when set, the Parity bit: BR…
54553 … (0x1<<14) // This bit masks, when set, the Parity bit: BR…
54555 … (0x1<<15) // This bit masks, when set, the Parity bit: BR…
54557 … (0x1<<11) // This bit masks, when set, the Parity bit: BR…
54559 … (0x1<<16) // This bit masks, when set, the Parity bit: BR…
54561 … (0x1<<3) // This bit masks, when set, the Parity bi…
54562 …RB_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_K2_SHIFT 3
54563 … (0x1<<17) // This bit masks, when set, the Parity bit: BR…
54565 … (0x1<<4) // This bit masks, when set, the Parity bit: BR…
54567 … (0x1<<18) // This bit masks, when set, the Parity bit: BR…
54569 … (0x1<<17) // This bit masks, when set, the Parity bit: BR…
54571 … (0x1<<19) // This bit masks, when set, the Parity bit: BR…
54573 … (0x1<<28) // This bit masks, when set, the Parity bit: BR…
54575 … (0x1<<20) // This bit masks, when set, the Parity bit: BR…
54577 … (0x1<<13) // This bit masks, when set, the Parity bit: BR…
54579 … (0x1<<21) // This bit masks, when set, the Parity bit: BR…
54581 … (0x1<<0) // This bit masks, when set, the Parity bit: BR…
54583 … (0x1<<22) // This bit masks, when set, the Parity bit: BR…
54585 … (0x1<<1) // This bit masks, when set, the Parity bit: BR…
54587 … (0x1<<23) // This bit masks, when set, the Parity bit: BR…
54589 … (0x1<<8) // This bit masks, when set, the Parity bit: BR…
54591 … (0x1<<14) // This bit masks, when set, the Parity bit: BR…
54593 … (0x1<<24) // This bit masks, when set, the Parity bit: BR…
54595 … (0x1<<7) // This bit masks, when set, the Parity bit: BR…
54597 … (0x1<<13) // This bit masks, when set, the Parity bit: BR…
54599 … (0x1<<25) // This bit masks, when set, the Parity bit: BR…
54601 … (0x1<<2) // This bit masks, when set, the Parity bit: BR…
54603 … (0x1<<26) // This bit masks, when set, the Parity bit: BR…
54605 … (0x1<<3) // This bit masks, when set, the Parity bi…
54606 …RB_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_BB_SHIFT 3
54607 … (0x1<<29) // This bit masks, when set, the Parity bit: BR…
54609 … (0x1<<27) // This bit masks, when set, the Parity bit: BR…
54611 … (0x1<<6) // This bit masks, when set, the Parity bit: BR…
54613 … (0x1<<12) // This bit masks, when set, the Parity bit: BR…
54615 … (0x1<<28) // This bit masks, when set, the Parity bit: BR…
54617 … (0x1<<9) // This bit masks, when set, the Parity bit: BR…
54619 … (0x1<<21) // This bit masks, when set, the Parity bit: BR…
54621 … (0x1<<29) // This bit masks, when set, the Parity bit: BR…
54623 … (0x1<<10) // This bit masks, when set, the Parity bit: BR…
54625 … (0x1<<22) // This bit masks, when set, the Parity bit: BR…
54627 … (0x1<<30) // This bit masks, when set, the Parity bit: BR…
54629 … (0x1<<0) // This bit masks, when set, the Parity bit: BR…
54631 … (0x1<<1) // This bit masks, when set, the Parity bit: BR…
54633 … (0x1<<2) // This bit masks, when set, the Parity bit: BR…
54635 … (0x1<<5) // This bit masks, when set, the Parity bit: BR…
54637 … (0x1<<6) // This bit masks, when set, the Parity bit: BR…
54639 … (0x1<<7) // This bit masks, when set, the Parity bit: BR…
54641 … (0x1<<8) // This bit masks, when set, the Parity bit: BR…
54643 … (0x1<<9) // This bit masks, when set, the Parity bit: BR…
54645 … (0x1<<4) // This bit masks, when set, the Parity bit: BR…
54647 … (0x1<<15) // This bit masks, when set, the Parity bit: BR…
54649 … (0x1<<16) // This bit masks, when set, the Parity bit: BR…
54651 … (0x1<<5) // This bit masks, when set, the Parity bit: BR…
54653 … (0x1<<18) // This bit masks, when set, the Parity bit: BR…
54655 … (0x1<<19) // This bit masks, when set, the Parity bit: BR…
54657 … (0x1<<20) // This bit masks, when set, the Parity bit: BR…
54659 … (0x1<<11) // This bit masks, when set, the Parity bit: BR…
54661 … (0x1<<23) // This bit masks, when set, the Parity bit: BR…
54663 … (0x1<<12) // This bit masks, when set, the Parity bit: BR…
54665 … (0x1<<24) // This bit masks, when set, the Parity bit: BR…
54667 … (0x1<<25) // This bit masks, when set, the Parity bit: BR…
54669 … (0x1<<26) // This bit masks, when set, the Parity bit: BR…
54671 … (0x1<<27) // This bit masks, when set, the Parity bit: BR…
54673 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54675 … (0x1<<0) // This bit masks, when set, the Parity bit: BR…
54677 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54678 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54679 …3].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of ea…
54689 … (0x1<<3) // Enable ECC for memory ecc instance brb.BB_BANK_K…
54690 …RB_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN_SHIFT 3
54727 … (0x1<<22) // Enable ECC for memory ecc instance brb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i…
54729 … (0x1<<23) // Enable ECC for memory ecc instance brb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i…
54731 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54741 … (0x1<<3) // Set parity only for memory ecc instance brb.BB_BANK…
54742 …RB_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY_SHIFT 3
54779 …(0x1<<22) // Set parity only for memory ecc instance brb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i…
54781 …(0x1<<23) // Set parity only for memory ecc instance brb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i…
54783 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54793 … (0x1<<3) // Record if a correctable error occurred on memory ecc instance …
54794 …RB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT_SHIFT 3
54831 … a correctable error occurred on memory ecc instance brb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i…
54833 … a correctable error occurred on memory ecc instance brb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i…
54835 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54839 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54840 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54841 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54842 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54843 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54844 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54845 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54846 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54847 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
54848 … to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_…
54849 …04UL //Access:RW DataWidth:0xa // Number of valid bytes in header in 16-bytes resolution. Aft…
54857 … 0x340844UL //Access:RW DataWidth:0x5 // There is bit for each PACKET read client. When bit …
54858 … shared and headroom areas. This register should be equal to total_mac_size - SUM(tc_guarantied) R…
54920 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54921 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54922 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54923 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54924 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54925 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54926 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54927 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54928 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54929 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54930 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54931 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54932 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54933 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54934 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54935 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54936 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54937 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54938 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54939 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54940 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54941 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54942 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54943 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54944 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54945 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54946 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54947 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54948 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54949 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54950 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54951 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54952 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54953 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54954 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54955 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54956 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54957 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54958 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54959 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54960 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54961 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54962 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54963 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54964 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54965 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54966 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54967 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54968 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54969 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54970 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54971 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54972 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54973 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54974 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54975 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54976 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54977 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54978 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54979 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54980 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54981 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54982 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54983 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54984 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54985 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54986 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54987 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54988 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54989 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54990 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54991 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54992 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54993 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54994 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54995 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54996 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54997 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54998 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54999 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55000 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55001 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55002 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55003 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55004 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55005 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55006 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55007 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55008 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55009 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55010 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55011 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55012 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55013 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55014 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55015 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55016 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55017 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55018 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55019 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55020 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55021 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55022 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55023 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55024 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55025 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55026 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55027 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55028 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55029 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55030 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55031 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55032 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55033 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55034 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55035 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55036 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55037 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55038 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55039 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55040 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55041 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55042 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55043 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55044 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55045 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55046 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55047 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55048 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55049 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55050 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55051 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55052 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55053 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55054 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55055 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55056 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55057 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55058 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55059 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55060 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55061 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55062 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55063 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55065 …rted when number of allocated blocks in TC bigger lossless_threshold, if 0 - then full to that TC…
55070 …bit for each PACKET read client. Bit 0 suits to client 0 and so on. If bit is set then packet will…
55072 …ty then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s…
55074 …ty then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s…
55076 …ty then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s…
55078 …ty then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s…
55080 …priority then selection between them is done with RR. Possible values are 1-3. Priority 7 is highe…
55082 …bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then packet wil…
55083 …bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then highest pr…
55084 …riority for SOP read client to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/…
55085 …s is priority for EOP read client to BIG RAM arbiters. Possible values are 0-7. Priority 7 is high…
55086 …quest of write client group to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/…
55087 …ple clients of identical priority is supported. Possible values are 1-3. Priority 3 is highest::s/…
55107 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
55108 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
55109 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
55110 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
55116 …bit per each read client interface: B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser. When bit is set then …
55118 …bit per each EOP read client interface: B0 - IF0, B1- IF1. When bit is set then appropriate interf…
55120 … (0x1<<14) // There is bit per SOP read client interface. When bit is set then appropriate int…
55122 …bit per write client interface: B0 - NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - …
55125 …bit per each read client interface: B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser. When bit is set then …
55127 …bit per each EOP read client interface: B0 - IF0, B1- IF1. When bit is set then appropriate interf…
55129 … (0x1<<14) // There is bit per SOP read client interface. When bit is set then appropriate int…
55131 …bit for all pause interfaces per each MAC port. When bit is set then pause interface is enabled. W…
55133 …bit for empty interfaces per each MAC port. When bit is set then empty interface is enabled. When …
55135 …bit for packet avalable interfaces. When bit is set then packet avalable interface is enabled. Whe…
55137 …bit for stop parsing interfaces. When bit is set then stop parsing interface is enabled. When bit …
55139 …bit for power management interfaces. When bit is set then power management interface is enabled. …
55141 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55142 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55143 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55144 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55145 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55146 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55147 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55148 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55149 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55150 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55151 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55152 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55153 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55154 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55155 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55156 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55159 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
55160 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
55161 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
55162 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
55163 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
55164 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
55165 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
55166 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
55167 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
55168 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
55169 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
55170 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
55171 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
55172 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
55173 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
55174 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
55175 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
55176 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
55179 …f input FIFO for EOP client 0[2:0]; status of input FIFO for EOP client 1[6:3]::s/RC_EOP_STAT_WDTH…
55236 …/ Debug register. The number of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Ar…
55237 …/ Debug register. The number of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Ar…
55238 …/ Debug register. The number of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Ar…
55239 …/ Debug register. The number of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Ar…
55240 …/ Debug register. The number of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Ar…
55291 …ter for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - qu…
55294 …ister for each erad packet client interface: 0-PRM; 1-MSDM ; 2-TSDM; 3-TMLD; 4-PRS. Message spelli…
55296 …t client interface: 0-PRM; 1-MSDM ; 2-TSDM; 3-TMLD; 4-PRS. Message spelling (MSB->LSB): opaque[9:0…
55298 …-port per-TC counters. In BigBear, entries 0-7 are port 0 (main 0) TCs 0-7. Entries 8-16 are port …
55301 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55303 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55305 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55307 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55309 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55311 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55313 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55315 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55323 …ccess:RW DataWidth:0x1 // When this bit is set, then the shared area is common for all ports.…
55326 … 0x344014UL //Access:RW DataWidth:0x10 // Bit enable per each main TC. When the bit …
55327 … 0x344018UL //Access:RW DataWidth:0x14 // Bit enable per each LB TC. When the bit i…
55328 … 0x34401cUL //Access:RW DataWidth:0x10 // Bit enable per each main TC. When the bit …
55329 … 0x344020UL //Access:RW DataWidth:0x14 // Bit enable per each LB TC. When the bit i…
55330 …Access:RW DataWidth:0xe // Link list dual port memory that contains per-block descriptor::s/B…
55331 …Access:RW DataWidth:0xf // Link list dual port memory that contains per-block descriptor::s/B…
55335 … 0x4c0000UL //Access:RW DataWidth:0x4 // Each bit indicates if the cu…
55338 …s:RW DataWidth:0x3 // Number of slots at the PCI read response buffer: 3=4/8 slots of 512 byt…
55353 …c0050UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 3
55358 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 3
55365 …0x20 // Logging in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_minica…
55366 …0x20 // Logging in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_minica…
55367 … // Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_c…
55368 … // Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_t…
55369 …th:0x4 // Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags com…
55370 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55371 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55372 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55373 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55374 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55375 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55376 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55377 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55378 …0x4c00b4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55379 …0x4c00b8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55380 …0x4c00bcUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55381 …0x4c00c0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55383 …th:0x8 // Logging register for segment message error: bits 3:0 - header len; bits 7:4 - number …
55384 … DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 31:0 of the seg…
55385 … DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 63:32 of the se…
55386 … DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 95:64 of the se…
55392 …bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message wi…
55393 …Access:R DataWidth:0x20 // Logging register for long message error: bit 0:3 Segment message h…
55401 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55403 … (0x1<<3) // Mini cache error - meaning t…
55404 …YLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR_SHIFT 3
55405 … (0x1<<4) // Mini cache error - meaning that A load …
55410 … (0x1<<0) // This bit masks, when set, the Interrupt bit: X…
55412 … (0x1<<1) // This bit masks, when set, the Interrupt bit: X…
55414 … (0x1<<2) // This bit masks, when set, the Interrupt bit: X…
55416 … (0x1<<3) // This bit masks, when set, the Interrupt …
55417 …YLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR_SHIFT 3
55418 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
55420 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
55427 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55429 … (0x1<<3) // Mini cache error - meaning t…
55430 …YLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR_SHIFT 3
55431 … (0x1<<4) // Mini cache error - meaning that A load …
55440 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55442 …R (0x1<<3) // Mini cache error - meaning t…
55443 …YLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR_SHIFT 3
55444 … (0x1<<4) // Mini cache error - meaning that A load …
55449 … (0x1<<0) // This bit masks, when set, the Parity bit: XY…
55451 … (0x1<<1) // This bit masks, when set, the Parity bit: XY…
55453 … (0x1<<2) // This bit masks, when set, the Parity bit: XY…
55455 … (0x1<<3) // This bit masks, when set, the Parity bi…
55456 …YLD_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT 3
55457 … (0x1<<4) // This bit masks, when set, the Parity bit: XY…
55459 … (0x1<<5) // This bit masks, when set, the Parity bit: XY…
55461 … (0x1<<7) // This bit masks, when set, the Parity bit: XY…
55463 … (0x1<<6) // This bit masks, when set, the Parity bit: XY…
55465 … (0x1<<7) // This bit masks, when set, the Parity bit: XY…
55467 … (0x1<<8) // This bit masks, when set, the Parity bit: XY…
55469 … (0x1<<6) // This bit masks, when set, the Parity bit: XY…
55471 … (0x1<<9) // This bit masks, when set, the Parity bit: XY…
55473 … (0x1<<10) // This bit masks, when set, the Parity bit: XY…
55475 … (0x1<<5) // This bit masks, when set, the Parity bit: XY…
55477 … (0x1<<11) // This bit masks, when set, the Parity bit: XY…
55479 … (0x1<<4) // This bit masks, when set, the Parity bit: XY…
55481 … (0x1<<12) // This bit masks, when set, the Parity bit: XY…
55483 … (0x1<<8) // This bit masks, when set, the Parity bit: XY…
55485 … (0x1<<13) // This bit masks, when set, the Parity bit: XY…
55487 … (0x1<<14) // This bit masks, when set, the Parity bit: XY…
55489 … (0x1<<0) // This bit masks, when set, the Parity bit: XY…
55491 … (0x1<<1) // This bit masks, when set, the Parity bit: XY…
55521 … 0x4c0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
55523 … 0x4c0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
55530 … (0x1<<2) // defines that only back-to-back aggregation is …
55532 …OBAL_INC_SN_E5 (0x1<<3) // When this flag i…
55533 …YLD_REG_L2MA_AGGR_CONFIG1_GLOBAL_INC_SN_E5_SHIFT 3
55549 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
55551 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
55553 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
55555 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
55558 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
55560 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
55562 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
55564 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
55567 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
55569 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
55571 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
55573 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
55576 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
55578 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
55580 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
55582 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
55618 … 0x4c0924UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55619 … 0x4c0928UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55620 … 0x4c092cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55621 … 0x4c0930UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55622 … 0x4c0934UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55623 … 0x4c0938UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55624 … 0x4c093cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55625 … 0x4c0940UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55626 … 0x4c0944UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55627 … 0x4c0948UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55628 … 0x4c094cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55629 … 0x4c0950UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55630 … 0x4c0954UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55631 … 0x4c0958UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55632 … 0x4c095cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55633 … 0x4c0960UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55634 … 0x4c0964UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55635 … 0x4c0968UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55636 … 0x4c096cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55637 … 0x4c0970UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55638 … 0x4c0974UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55639 … 0x4c0978UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55640 … 0x4c097cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55641 … 0x4c0980UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
55642 … 0x4c0984UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
55643 … 0x4c0988UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
55644 … 0x4c098cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
55645 … 0x4c0990UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
55646 … 0x4c0994UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
55647 … 0x4c0998UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
55648 … 0x4c099cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
55649 … 0x4c09a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
55651 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
55653 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
55655 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
55657 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
55660 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
55662 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
55664 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
55666 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
55669 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
55671 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
55673 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
55675 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
55678 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
55680 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
55682 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
55684 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
55723 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
55725 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
55727 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
55729 … (0x1<<3) // indication if to include the flow-ID in the stream…
55730 …YLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3_E5_SHIFT 3
55731 … (0x1f<<4) // offset of the flow-ID, in 32b units, from the beginning of the message. Should b…
55733 … (0x1f<<9) // offset of the flow-ID, in 32b units, from the beginning of the message. Should b…
55735 … (0x1f<<14) // offset of the flow-ID, in 32b units, from the beginning of the message. Should b…
55737 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
55746 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 3.
55755 … (0xf<<12) // the maximal number of children in a specific aggregation. for set 3.
55758 … (0xff<<0) // The value by which to increment the event-ID in case of success…
55760 … (0xff<<8) // The value by which to increment the event-ID in case of success…
55762 … (0xff<<16) // The value by which to increment the event-ID in case of success…
55764 …ff<<24) // The value by which to increment the event-ID in case of successful aggregation. for set…
55766 … 0x4c09d4UL //Access:RW DataWidth:0xc // maximum loader size in 256 bit words
55767 …Width:0x2 // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_st…
55768 …Width:0x2 // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_st…
55769 …Width:0x2 // The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_st…
55770 …Width:0x2 // The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_st…
55771 …Width:0x2 // The weight of queue 2 at the WRR arbiteration, in case its bit is reset at scbd_st…
55772 … //Access:RW DataWidth:0x2 // The weight of queue 3 at the WRR arbiteration, in case its bit …
55774 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
55775 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
55776 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
55777 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
55786 … 0x4c8000UL //Access:RW DataWidth:0x4 // Each bit indicates if the cu…
55787 …Width:0x2 // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_st…
55788 …Width:0x2 // The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_st…
55802 …c8040UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 3
55807 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 3
55811 …0x20 // Logging in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_minica…
55812 …0x20 // Logging in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_minica…
55813 … // Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_c…
55814 … // Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_t…
55815 …th:0x4 // Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags com…
55816 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55817 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55818 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55819 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55820 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55821 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55822 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55823 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55824 …0x4c8098UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55825 …0x4c809cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55826 …0x4c80a0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55827 …0x4c80a4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55832 …bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message wi…
55833 …Access:R DataWidth:0x20 // Logging register for long message error: bit 0:3 Segment message h…
55841 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55843 …_K2 (0x1<<3) // Mini cache error - meaning t…
55844 …ULD_REG_INT_STS_LD_TID_MINI_CACHE_ERR_BB_K2_SHIFT 3
55845 … (0x1<<4) // Mini cache error - meaning that A load …
55850 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
55852 … (0x1<<1) // This bit masks, when set, the Interrupt bit: Y…
55854 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Y…
55856 … (0x1<<3) // This bit masks, when set, the Interrupt …
55857 …ULD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR_BB_K2_SHIFT 3
55858 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
55860 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
55867 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55869 …_BB_K2 (0x1<<3) // Mini cache error - meaning t…
55870 …ULD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR_BB_K2_SHIFT 3
55871 … (0x1<<4) // Mini cache error - meaning that A load …
55880 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55882 …R_BB_K2 (0x1<<3) // Mini cache error - meaning t…
55883 …ULD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR_BB_K2_SHIFT 3
55884 … (0x1<<4) // Mini cache error - meaning that A load …
55889 … (0x1<<0) // This bit masks, when set, the Parity bit: YU…
55891 … (0x1<<1) // This bit masks, when set, the Parity bit: YU…
55893 … (0x1<<2) // This bit masks, when set, the Parity bit: YU…
55895 … (0x1<<3) // This bit masks, when set, the Parity bi…
55896 …ULD_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT 3
55897 … (0x1<<4) // This bit masks, when set, the Parity bit: YU…
55899 … (0x1<<5) // This bit masks, when set, the Parity bit: YU…
55902 … 0x4c8400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
55904 … 0x4c8800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
55907 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
55908 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
55909 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
55910 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
55919 … 0x4d0000UL //Access:RW DataWidth:0x4 // Each bit indicates if the cu…
55925 …the BRB read response buffer. The slot size would be the BRB-response-buffer-size/number-of-slots.…
55928 …data returning from the BRB is swapped. meaning that bytes 0-3 is swapped with bytes 4-7 in …
55929 …30UL //Access:RW DataWidth:0x3 // Max credit number for the BRB request-resonse interface::/M…
55936 …d004cUL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 3
55941 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 3
55947 …0x20 // Logging in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_minica…
55948 …0x20 // Logging in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_minica…
55949 … // Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_c…
55950 … // Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_t…
55951 …th:0x4 // Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags com…
55952 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55953 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55954 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55955 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55956 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55957 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55958 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55959 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55960 …0x4d00acUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55961 …0x4d00b0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55962 …0x4d00b4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55963 …0x4d00b8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55968 …bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message wi…
55969 …Access:R DataWidth:0x20 // Logging register for long message error: bit 0:3 Segment message h…
55977 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
55979 … (0x1<<3) // Mini cache error - meaning t…
55980 …MLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR_SHIFT 3
55981 … (0x1<<4) // Mini cache error - meaning that A load …
55986 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
55988 … (0x1<<1) // This bit masks, when set, the Interrupt bit: T…
55990 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
55992 … (0x1<<3) // This bit masks, when set, the Interrupt …
55993 …MLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR_SHIFT 3
55994 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
55996 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
56003 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56005 … (0x1<<3) // Mini cache error - meaning t…
56006 …MLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR_SHIFT 3
56007 … (0x1<<4) // Mini cache error - meaning that A load …
56016 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56018 …R (0x1<<3) // Mini cache error - meaning t…
56019 …MLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR_SHIFT 3
56020 … (0x1<<4) // Mini cache error - meaning that A load …
56025 … (0x1<<0) // This bit masks, when set, the Parity bit: TM…
56027 … (0x1<<1) // This bit masks, when set, the Parity bit: TM…
56029 … (0x1<<2) // This bit masks, when set, the Parity bit: TM…
56031 … (0x1<<3) // This bit masks, when set, the Parity bi…
56032 …MLD_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT 3
56033 … (0x1<<4) // This bit masks, when set, the Parity bit: TM…
56035 … (0x1<<5) // This bit masks, when set, the Parity bit: TM…
56037 … (0x1<<4) // This bit masks, when set, the Parity bit: TM…
56039 … (0x1<<6) // This bit masks, when set, the Parity bit: TM…
56041 … (0x1<<7) // This bit masks, when set, the Parity bit: TM…
56043 … (0x1<<6) // This bit masks, when set, the Parity bit: TM…
56045 … (0x1<<8) // This bit masks, when set, the Parity bit: TM…
56047 … (0x1<<9) // This bit masks, when set, the Parity bit: TM…
56049 … (0x1<<10) // This bit masks, when set, the Parity bit: TM…
56051 … (0x1<<11) // This bit masks, when set, the Parity bit: TM…
56053 … (0x1<<12) // This bit masks, when set, the Parity bit: TM…
56055 … (0x1<<5) // This bit masks, when set, the Parity bit: TM…
56057 … (0x1<<13) // This bit masks, when set, the Parity bit: TM…
56059 … (0x1<<0) // This bit masks, when set, the Parity bit: TM…
56083 … 0x4d0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
56085 … 0x4d0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
56092 … (0x1<<2) // defines that only back-to-back aggregation is …
56094 …OBAL_INC_SN_E5 (0x1<<3) // When this flag i…
56095 …MLD_REG_L2MA_AGGR_CONFIG1_GLOBAL_INC_SN_E5_SHIFT 3
56111 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
56113 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
56115 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
56117 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
56120 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
56122 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
56124 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
56126 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
56129 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
56131 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
56133 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
56135 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
56138 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
56140 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
56142 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
56144 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
56180 … 0x4d0924UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56181 … 0x4d0928UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56182 … 0x4d092cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56183 … 0x4d0930UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56184 … 0x4d0934UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56185 … 0x4d0938UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56186 … 0x4d093cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56187 … 0x4d0940UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56188 … 0x4d0944UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56189 … 0x4d0948UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56190 … 0x4d094cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56191 … 0x4d0950UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56192 … 0x4d0954UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56193 … 0x4d0958UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56194 … 0x4d095cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56195 … 0x4d0960UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56196 … 0x4d0964UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56197 … 0x4d0968UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56198 … 0x4d096cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56199 … 0x4d0970UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56200 … 0x4d0974UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56201 … 0x4d0978UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56202 … 0x4d097cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56203 … 0x4d0980UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56204 … 0x4d0984UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
56205 … 0x4d0988UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
56206 … 0x4d098cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
56207 … 0x4d0990UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
56208 … 0x4d0994UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
56209 … 0x4d0998UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
56210 … 0x4d099cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
56211 … 0x4d09a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
56213 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
56215 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
56217 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
56219 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
56222 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
56224 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
56226 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
56228 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
56231 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
56233 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
56235 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
56237 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
56240 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
56242 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
56244 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
56246 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
56285 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
56287 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
56289 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
56291 … (0x1<<3) // indication if to include the flow-ID in the stream…
56292 …MLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3_E5_SHIFT 3
56293 … (0x1f<<4) // offset of the flow-ID, in 32b units, from the beginning of the message. Should b…
56295 … (0x1f<<9) // offset of the flow-ID, in 32b units, from the beginning of the message. Should b…
56297 … (0x1f<<14) // offset of the flow-ID, in 32b units, from the beginning of the message. Should b…
56299 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56308 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 3.
56317 … (0xf<<12) // the maximal number of children in a specific aggregation. for set 3.
56320 … (0xff<<0) // The value by which to increment the event-ID in case of success…
56322 … (0xff<<8) // The value by which to increment the event-ID in case of success…
56324 … (0xff<<16) // The value by which to increment the event-ID in case of success…
56326 …ff<<24) // The value by which to increment the event-ID in case of successful aggregation. for set…
56328 … 0x4d09d4UL //Access:RW DataWidth:0xc // maximum loader size in 256 bit words
56329 …Width:0x2 // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_st…
56330 …Width:0x2 // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_st…
56331 …Width:0x2 // The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_st…
56332 …Width:0x2 // The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_st…
56333 …Width:0x2 // The weight of queue 2 at the WRR arbiteration, in case its bit is reset at scbd_st…
56334 … //Access:RW DataWidth:0x2 // The weight of queue 3 at the WRR arbiteration, in case its bit …
56336 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
56337 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
56338 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
56339 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
56348 … 0x4e0000UL //Access:RW DataWidth:0x4 // Each bit indicates if the cu…
56349 …Width:0x2 // The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_st…
56350 …Width:0x2 // The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_st…
56351 …Width:0x2 // The weight of queue 2 at the WRR arbiteration, in case its bit is reset at scbd_st…
56352 … //Access:RW DataWidth:0x2 // The weight of queue 3 at the WRR arbiteration, in case its bit …
56353 …//Access:RW DataWidth:0x4 // Log 2 of the BD size in bytes - 2:BD size is 4bytes; 3:BD size i…
56355 …/Access:RW DataWidth:0x4 // Log 2 of the SGE size in bytes - 2:SGE size is 4bytes; 3:SGE size…
56359 …s:RW DataWidth:0x3 // Number of slots at the PCI read response buffer: 3=4/8 slots of 512 byt…
56373 …e0064UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 3
56378 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 3
56387 …0x20 // Logging in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_minica…
56388 …0x20 // Logging in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_minica…
56389 … // Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_c…
56390 … // Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_t…
56391 …th:0x4 // Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags com…
56392 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56393 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56394 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56395 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56396 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56397 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56398 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56399 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56400 …0x4e00d0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56401 …0x4e00d4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56402 …0x4e00d8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56403 …0x4e00dcUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56408 …bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message wi…
56409 …Access:R DataWidth:0x20 // Logging register for long message error: bit 0:3 Segment message h…
56417 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56419 … (0x1<<3) // Mini cache error - meaning t…
56420 …ULD_REG_INT_STS_LD_TID_MINI_CACHE_ERR_SHIFT 3
56421 … (0x1<<4) // Mini cache error - meaning that A load …
56426 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
56428 … (0x1<<1) // This bit masks, when set, the Interrupt bit: M…
56430 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
56432 … (0x1<<3) // This bit masks, when set, the Interrupt …
56433 …ULD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR_SHIFT 3
56434 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
56436 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
56443 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56445 … (0x1<<3) // Mini cache error - meaning t…
56446 …ULD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR_SHIFT 3
56447 … (0x1<<4) // Mini cache error - meaning that A load …
56456 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
56458 …R (0x1<<3) // Mini cache error - meaning t…
56459 …ULD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR_SHIFT 3
56460 … (0x1<<4) // Mini cache error - meaning that A load …
56465 … (0x1<<0) // This bit masks, when set, the Parity bit: MU…
56467 … (0x1<<1) // This bit masks, when set, the Parity bit: MU…
56469 … (0x1<<2) // This bit masks, when set, the Parity bit: MU…
56471 … (0x1<<3) // This bit masks, when set, the Parity bi…
56472 …ULD_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_E5_SHIFT 3
56473 … (0x1<<4) // This bit masks, when set, the Parity bit: MU…
56475 … (0x1<<5) // This bit masks, when set, the Parity bit: MU…
56477 … (0x1<<6) // This bit masks, when set, the Parity bit: MU…
56479 … (0x1<<7) // This bit masks, when set, the Parity bit: MU…
56481 … (0x1<<9) // This bit masks, when set, the Parity bit: MU…
56483 … (0x1<<8) // This bit masks, when set, the Parity bit: MU…
56485 … (0x1<<9) // This bit masks, when set, the Parity bit: MU…
56487 … (0x1<<8) // This bit masks, when set, the Parity bit: MU…
56489 … (0x1<<10) // This bit masks, when set, the Parity bit: MU…
56491 … (0x1<<11) // This bit masks, when set, the Parity bit: MU…
56493 … (0x1<<7) // This bit masks, when set, the Parity bit: MU…
56495 … (0x1<<12) // This bit masks, when set, the Parity bit: MU…
56497 … (0x1<<6) // This bit masks, when set, the Parity bit: MU…
56499 … (0x1<<13) // This bit masks, when set, the Parity bit: MU…
56501 … (0x1<<14) // This bit masks, when set, the Parity bit: MU…
56503 … (0x1<<15) // This bit masks, when set, the Parity bit: MU…
56505 … (0x1<<0) // This bit masks, when set, the Parity bit: MU…
56507 … (0x1<<2) // This bit masks, when set, the Parity bit: MU…
56509 … (0x1<<3) // This bit masks, when set, the Parity bi…
56510 …ULD_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_BB_K2_SHIFT 3
56518 …013_I_ECC_EN_E5 (0x1<<3) // Enable ECC for m…
56519 …ULD_REG_MEM_ECC_ENABLE_0_MEM013_I_ECC_EN_E5_SHIFT 3
56524 …007_I_ECC_EN_BB_K2 (0x1<<3) // Enable ECC for m…
56525 …ULD_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN_BB_K2_SHIFT 3
56533 …0_MEM013_I_ECC_PRTY_E5 (0x1<<3) // Set parity only …
56534 …ULD_REG_MEM_ECC_PARITY_ONLY_0_MEM013_I_ECC_PRTY_E5_SHIFT 3
56539 …0_MEM007_I_ECC_PRTY_BB_K2 (0x1<<3) // Set parity only …
56540 …ULD_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY_BB_K2_SHIFT 3
56548 …TED_0_MEM013_I_ECC_CORRECT_E5 (0x1<<3) // Record if a corr…
56549 …ULD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM013_I_ECC_CORRECT_E5_SHIFT 3
56554 …TED_0_MEM007_I_ECC_CORRECT_BB_K2 (0x1<<3) // Record if a corr…
56555 …ULD_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT_BB_K2_SHIFT 3
56557 … 0x4e0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
56559 … 0x4e0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
56561 … 0x4e0c00UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue2 - Debug access::/TMLD_…
56563 … 0x4e1000UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue3 - Debug access::/TMLD_…
56570 … (0x1<<2) // defines that only back-to-back aggregation is …
56572 …OBAL_INC_SN_E5 (0x1<<3) // When this flag i…
56573 …ULD_REG_L2MA_AGGR_CONFIG1_GLOBAL_INC_SN_E5_SHIFT 3
56589 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
56591 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
56593 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
56595 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
56598 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
56600 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
56602 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
56604 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
56607 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
56609 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
56611 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
56613 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
56616 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
56618 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
56620 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
56622 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
56658 … 0x4e1424UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56659 … 0x4e1428UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56660 … 0x4e142cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56661 … 0x4e1430UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56662 … 0x4e1434UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56663 … 0x4e1438UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56664 … 0x4e143cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56665 … 0x4e1440UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56666 … 0x4e1444UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56667 … 0x4e1448UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56668 … 0x4e144cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56669 … 0x4e1450UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56670 … 0x4e1454UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56671 … 0x4e1458UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56672 … 0x4e145cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56673 … 0x4e1460UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56674 … 0x4e1464UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56675 … 0x4e1468UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56676 … 0x4e146cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56677 … 0x4e1470UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56678 … 0x4e1474UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56679 … 0x4e1478UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56680 … 0x4e147cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56681 … 0x4e1480UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
56682 … 0x4e1484UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
56683 … 0x4e1488UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
56684 … 0x4e148cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
56685 … 0x4e1490UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
56686 … 0x4e1494UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
56687 … 0x4e1498UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
56688 … 0x4e149cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
56689 … 0x4e14a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
56691 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
56693 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
56695 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
56697 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
56700 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
56702 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
56704 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
56706 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
56709 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
56711 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
56713 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
56715 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
56718 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
56720 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
56722 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
56724 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
56763 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
56765 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
56767 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
56769 … (0x1<<3) // indication if to include the flow-ID in the stream…
56770 …ULD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3_E5_SHIFT 3
56771 … (0x1f<<4) // offset of the flow-ID, in 32b units, from the beginning of the message. Should b…
56773 … (0x1f<<9) // offset of the flow-ID, in 32b units, from the beginning of the message. Should b…
56775 … (0x1f<<14) // offset of the flow-ID, in 32b units, from the beginning of the message. Should b…
56777 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
56786 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 3.
56795 … (0xf<<12) // the maximal number of children in a specific aggregation. for set 3.
56798 … (0xff<<0) // The value by which to increment the event-ID in case of success…
56800 … (0xff<<8) // The value by which to increment the event-ID in case of success…
56802 … (0xff<<16) // The value by which to increment the event-ID in case of success…
56804 …ff<<24) // The value by which to increment the event-ID in case of successful aggregation. for set…
56806 … 0x4e14d4UL //Access:RW DataWidth:0xc // maximum loader size in 256 bit words
56809 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
56810 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
56811 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
56812 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
56819 …- Fields order[Link page]: [180] Next address valid; [179:178] Endianity bits; [177] No snoop flag…
56823 …- Fields order[Link page]: [180] Next address valid; [179:178] Endianity bits; [177] No snoop flag…
56836 …O_ERROR_WR (0x1<<3) // FIFO error in de…
56837 …IG_REG_INT_STS_0_DBG_SYNCFIFO_ERROR_WR_SHIFT 3
56859 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
56861 … (0x1<<1) // This bit masks, when set, the Interrupt bit: N…
56863 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
56865 … (0x1<<3) // This bit masks, when set, the Interrupt …
56866 …IG_REG_INT_MASK_0_DBG_SYNCFIFO_ERROR_WR_SHIFT 3
56867 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
56869 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
56871 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
56873 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
56875 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
56877 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
56879 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
56881 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
56883 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
56885 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
56894 …FIFO_ERROR_WR (0x1<<3) // FIFO error in de…
56895 …IG_REG_INT_STS_WR_0_DBG_SYNCFIFO_ERROR_WR_SHIFT 3
56923 …CFIFO_ERROR_WR (0x1<<3) // FIFO error in de…
56924 …IG_REG_INT_STS_CLR_0_DBG_SYNCFIFO_ERROR_WR_SHIFT 3
56952 …ROR (0x1<<3) // Error in the TX …
56953 …IG_REG_INT_STS_1_TX_SOPQ3_ERROR_SHIFT 3
57011 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
57013 … (0x1<<1) // This bit masks, when set, the Interrupt bit: N…
57015 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
57017 … (0x1<<3) // This bit masks, when set, the Interrupt …
57018 …IG_REG_INT_MASK_1_TX_SOPQ3_ERROR_SHIFT 3
57019 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
57021 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
57023 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
57025 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
57027 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
57029 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
57031 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
57033 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
57035 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
57037 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
57039 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
57041 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
57043 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
57045 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
57047 … (0x1<<18) // This bit masks, when set, the Interrupt bit: N…
57049 … (0x1<<19) // This bit masks, when set, the Interrupt bit: N…
57051 … (0x1<<20) // This bit masks, when set, the Interrupt bit: N…
57053 … (0x1<<21) // This bit masks, when set, the Interrupt bit: N…
57055 … (0x1<<22) // This bit masks, when set, the Interrupt bit: N…
57057 … (0x1<<23) // This bit masks, when set, the Interrupt bit: N…
57059 … (0x1<<24) // This bit masks, when set, the Interrupt bit: N…
57061 … (0x1<<25) // This bit masks, when set, the Interrupt bit: N…
57063 … (0x1<<26) // This bit masks, when set, the Interrupt bit: N…
57065 … (0x1<<27) // This bit masks, when set, the Interrupt bit: N…
57067 … (0x1<<28) // This bit masks, when set, the Interrupt bit: N…
57069 … (0x1<<29) // This bit masks, when set, the Interrupt bit: N…
57071 … (0x1<<30) // This bit masks, when set, the Interrupt bit: N…
57073 … (0x1<<31) // This bit masks, when set, the Interrupt bit: N…
57082 …_ERROR (0x1<<3) // Error in the TX …
57083 …IG_REG_INT_STS_WR_1_TX_SOPQ3_ERROR_SHIFT 3
57147 …3_ERROR (0x1<<3) // Error in the TX …
57148 …IG_REG_INT_STS_CLR_1_TX_SOPQ3_ERROR_SHIFT 3
57206 … (0x1<<0) // Error in the pure-loopback SOPQ.
57212 …IFO_ERROR (0x1<<3) // FIFO error in TX…
57213 …IG_REG_INT_STS_2_P0_TX_BMB_FIFO_ERROR_SHIFT 3
57251 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
57253 … (0x1<<1) // This bit masks, when set, the Interrupt bit: N…
57255 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
57257 … (0x1<<3) // This bit masks, when set, the Interrupt …
57258 …IG_REG_INT_MASK_2_P0_TX_BMB_FIFO_ERROR_SHIFT 3
57259 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
57261 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
57263 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
57265 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
57267 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
57269 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
57271 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
57273 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
57275 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
57277 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
57279 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
57281 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
57283 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
57285 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
57287 … (0x1<<18) // This bit masks, when set, the Interrupt bit: N…
57289 … (0x1<<19) // This bit masks, when set, the Interrupt bit: N…
57291 … (0x1<<20) // This bit masks, when set, the Interrupt bit: N…
57293 … (0x1<<21) // This bit masks, when set, the Interrupt bit: N…
57296 … (0x1<<0) // Error in the pure-loopback SOPQ.
57302 …B_FIFO_ERROR (0x1<<3) // FIFO error in TX…
57303 …IG_REG_INT_STS_WR_2_P0_TX_BMB_FIFO_ERROR_SHIFT 3
57341 … (0x1<<0) // Error in the pure-loopback SOPQ.
57347 …MB_FIFO_ERROR (0x1<<3) // FIFO error in TX…
57348 …IG_REG_INT_STS_CLR_2_P0_TX_BMB_FIFO_ERROR_SHIFT 3
57392 …E_TOO_LONG_INT (0x1<<3) // Triggered by TC …
57393 …IG_REG_INT_STS_3_P0_TC2_PAUSE_TOO_LONG_INT_SHIFT 3
57423 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
57425 … (0x1<<1) // This bit masks, when set, the Interrupt bit: N…
57427 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
57429 … (0x1<<3) // This bit masks, when set, the Interrupt …
57430 …IG_REG_INT_MASK_3_P0_TC2_PAUSE_TOO_LONG_INT_SHIFT 3
57431 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
57433 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
57435 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
57437 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
57439 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
57441 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
57443 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
57445 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
57447 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
57449 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
57451 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
57453 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
57455 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
57457 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
57466 …AUSE_TOO_LONG_INT (0x1<<3) // Triggered by TC …
57467 …IG_REG_INT_STS_WR_3_P0_TC2_PAUSE_TOO_LONG_INT_SHIFT 3
57503 …PAUSE_TOO_LONG_INT (0x1<<3) // Triggered by TC …
57504 …IG_REG_INT_STS_CLR_3_P0_TC2_PAUSE_TOO_LONG_INT_SHIFT 3
57534 … (0x1<<0) // Error in the pure-loopback SOPQ.
57540 …IFO_ERROR (0x1<<3) // FIFO error in TX…
57541 …IG_REG_INT_STS_4_P1_TX_BMB_FIFO_ERROR_SHIFT 3
57579 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
57581 … (0x1<<1) // This bit masks, when set, the Interrupt bit: N…
57583 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
57585 … (0x1<<3) // This bit masks, when set, the Interrupt …
57586 …IG_REG_INT_MASK_4_P1_TX_BMB_FIFO_ERROR_SHIFT 3
57587 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
57589 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
57591 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
57593 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
57595 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
57597 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
57599 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
57601 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
57603 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
57605 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
57607 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
57609 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
57611 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
57613 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
57615 … (0x1<<18) // This bit masks, when set, the Interrupt bit: N…
57617 … (0x1<<19) // This bit masks, when set, the Interrupt bit: N…
57619 … (0x1<<20) // This bit masks, when set, the Interrupt bit: N…
57621 … (0x1<<21) // This bit masks, when set, the Interrupt bit: N…
57624 … (0x1<<0) // Error in the pure-loopback SOPQ.
57630 …B_FIFO_ERROR (0x1<<3) // FIFO error in TX…
57631 …IG_REG_INT_STS_WR_4_P1_TX_BMB_FIFO_ERROR_SHIFT 3
57669 … (0x1<<0) // Error in the pure-loopback SOPQ.
57675 …MB_FIFO_ERROR (0x1<<3) // FIFO error in TX…
57676 …IG_REG_INT_STS_CLR_4_P1_TX_BMB_FIFO_ERROR_SHIFT 3
57720 …E_TOO_LONG_INT (0x1<<3) // Triggered by TC …
57721 …IG_REG_INT_STS_5_P1_TC2_PAUSE_TOO_LONG_INT_SHIFT 3
57751 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
57753 … (0x1<<1) // This bit masks, when set, the Interrupt bit: N…
57755 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
57757 … (0x1<<3) // This bit masks, when set, the Interrupt …
57758 …IG_REG_INT_MASK_5_P1_TC2_PAUSE_TOO_LONG_INT_SHIFT 3
57759 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
57761 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
57763 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
57765 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
57767 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
57769 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
57771 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
57773 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
57775 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
57777 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
57779 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
57781 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
57783 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
57785 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
57794 …AUSE_TOO_LONG_INT (0x1<<3) // Triggered by TC …
57795 …IG_REG_INT_STS_WR_5_P1_TC2_PAUSE_TOO_LONG_INT_SHIFT 3
57831 …PAUSE_TOO_LONG_INT (0x1<<3) // Triggered by TC …
57832 …IG_REG_INT_STS_CLR_5_P1_TC2_PAUSE_TOO_LONG_INT_SHIFT 3
57862 … (0x1<<0) // Error in the pure-loopback SOPQ.
57868 …IFO_ERROR_K2_E5 (0x1<<3) // FIFO error in TX…
57869 …IG_REG_INT_STS_6_P2_TX_BMB_FIFO_ERROR_K2_E5_SHIFT 3
57907 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
57909 … (0x1<<1) // This bit masks, when set, the Interrupt bit: N…
57911 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
57913 … (0x1<<3) // This bit masks, when set, the Interrupt …
57914 …IG_REG_INT_MASK_6_P2_TX_BMB_FIFO_ERROR_K2_E5_SHIFT 3
57915 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
57917 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
57919 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
57921 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
57923 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
57925 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
57927 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
57929 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
57931 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
57933 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
57935 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
57937 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
57939 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
57941 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
57943 … (0x1<<18) // This bit masks, when set, the Interrupt bit: N…
57945 … (0x1<<19) // This bit masks, when set, the Interrupt bit: N…
57947 … (0x1<<20) // This bit masks, when set, the Interrupt bit: N…
57949 … (0x1<<21) // This bit masks, when set, the Interrupt bit: N…
57952 …_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
57958 …B_FIFO_ERROR_K2_E5 (0x1<<3) // FIFO error in TX…
57959 …IG_REG_INT_STS_WR_6_P2_TX_BMB_FIFO_ERROR_K2_E5_SHIFT 3
57997 …2_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
58003 …MB_FIFO_ERROR_K2_E5 (0x1<<3) // FIFO error in TX…
58004 …IG_REG_INT_STS_CLR_6_P2_TX_BMB_FIFO_ERROR_K2_E5_SHIFT 3
58048 …E_TOO_LONG_INT_K2_E5 (0x1<<3) // Triggered by TC …
58049 …IG_REG_INT_STS_7_P2_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 3
58079 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
58081 … (0x1<<1) // This bit masks, when set, the Interrupt bit: N…
58083 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
58085 … (0x1<<3) // This bit masks, when set, the Interrupt …
58086 …IG_REG_INT_MASK_7_P2_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 3
58087 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
58089 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
58091 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
58093 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
58095 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
58097 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
58099 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
58101 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
58103 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
58105 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
58107 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
58109 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
58111 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
58113 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
58122 …AUSE_TOO_LONG_INT_K2_E5 (0x1<<3) // Triggered by TC …
58123 …IG_REG_INT_STS_WR_7_P2_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 3
58159 …PAUSE_TOO_LONG_INT_K2_E5 (0x1<<3) // Triggered by TC …
58160 …IG_REG_INT_STS_CLR_7_P2_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 3
58190 … (0x1<<0) // Error in the pure-loopback SOPQ.
58196 …IFO_ERROR_K2_E5 (0x1<<3) // FIFO error in TX…
58197 …IG_REG_INT_STS_8_P3_TX_BMB_FIFO_ERROR_K2_E5_SHIFT 3
58235 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
58237 … (0x1<<1) // This bit masks, when set, the Interrupt bit: N…
58239 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
58241 … (0x1<<3) // This bit masks, when set, the Interrupt …
58242 …IG_REG_INT_MASK_8_P3_TX_BMB_FIFO_ERROR_K2_E5_SHIFT 3
58243 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
58245 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
58247 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
58249 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
58251 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
58253 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
58255 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
58257 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
58259 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
58261 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
58263 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
58265 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
58267 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
58269 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
58271 … (0x1<<18) // This bit masks, when set, the Interrupt bit: N…
58273 … (0x1<<19) // This bit masks, when set, the Interrupt bit: N…
58275 … (0x1<<20) // This bit masks, when set, the Interrupt bit: N…
58277 … (0x1<<21) // This bit masks, when set, the Interrupt bit: N…
58280 …_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
58286 …B_FIFO_ERROR_K2_E5 (0x1<<3) // FIFO error in TX…
58287 …IG_REG_INT_STS_WR_8_P3_TX_BMB_FIFO_ERROR_K2_E5_SHIFT 3
58325 …2_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
58331 …MB_FIFO_ERROR_K2_E5 (0x1<<3) // FIFO error in TX…
58332 …IG_REG_INT_STS_CLR_8_P3_TX_BMB_FIFO_ERROR_K2_E5_SHIFT 3
58376 …E_TOO_LONG_INT_K2_E5 (0x1<<3) // Triggered by TC …
58377 …IG_REG_INT_STS_9_P3_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 3
58407 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
58409 … (0x1<<1) // This bit masks, when set, the Interrupt bit: N…
58411 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
58413 … (0x1<<3) // This bit masks, when set, the Interrupt …
58414 …IG_REG_INT_MASK_9_P3_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 3
58415 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
58417 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
58419 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
58421 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
58423 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
58425 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
58427 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
58429 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
58431 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
58433 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
58435 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
58437 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
58439 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
58441 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
58450 …AUSE_TOO_LONG_INT_K2_E5 (0x1<<3) // Triggered by TC …
58451 …IG_REG_INT_STS_WR_9_P3_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 3
58487 …PAUSE_TOO_LONG_INT_K2_E5 (0x1<<3) // Triggered by TC …
58488 …IG_REG_INT_STS_CLR_9_P3_TC2_PAUSE_TOO_LONG_INT_K2_E5_SHIFT 3
58519 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58528 …ERROR_E5 (0x1<<3) // Error in the TX …
58529 …IG_REG_INT_STS_10_TX_SOPQ19_ERROR_E5_SHIFT 3
58555 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
58557 … (0x1<<1) // This bit masks, when set, the Interrupt bit: N…
58559 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
58561 … (0x1<<3) // This bit masks, when set, the Interrupt …
58562 …IG_REG_INT_MASK_10_TX_SOPQ19_ERROR_E5_SHIFT 3
58563 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
58565 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
58567 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
58569 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
58571 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
58573 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
58575 … (0x1<<10) // This bit masks, when set, the Interrupt bit: N…
58577 … (0x1<<11) // This bit masks, when set, the Interrupt bit: N…
58579 … (0x1<<12) // This bit masks, when set, the Interrupt bit: N…
58581 … (0x1<<13) // This bit masks, when set, the Interrupt bit: N…
58583 … (0x1<<14) // This bit masks, when set, the Interrupt bit: N…
58585 … (0x1<<15) // This bit masks, when set, the Interrupt bit: N…
58594 …19_ERROR_E5 (0x1<<3) // Error in the TX …
58595 …IG_REG_INT_STS_WR_10_TX_SOPQ19_ERROR_E5_SHIFT 3
58627 …Q19_ERROR_E5 (0x1<<3) // Error in the TX …
58628 …IG_REG_INT_STS_CLR_10_TX_SOPQ19_ERROR_E5_SHIFT 3
58654 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58656 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
58658 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
58660 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
58662 … (0x1<<3) // This bit masks, when set, the Parity bi…
58663 …IG_REG_PRTY_MASK_H_0_MEM083_I_MEM_PRTY_E5_SHIFT 3
58664 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
58666 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
58668 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
58670 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
58672 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
58674 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
58676 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
58678 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
58680 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
58682 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
58684 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
58686 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
58688 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
58690 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
58692 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
58694 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
58696 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
58698 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
58700 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
58702 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
58704 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
58706 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
58708 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
58710 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
58712 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
58714 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
58716 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
58718 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
58720 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
58722 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
58724 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
58726 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
58728 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
58730 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
58732 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
58734 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
58736 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
58738 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
58740 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
58742 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
58744 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
58746 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
58748 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
58750 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
58752 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
58754 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
58756 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
58758 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
58760 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
58762 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58764 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
58766 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
58768 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
58770 … (0x1<<3) // This bit masks, when set, the Parity bi…
58771 …IG_REG_PRTY_MASK_H_0_MEM105_I_MEM_PRTY_K2_SHIFT 3
58772 … (0x1<<3) // This bit masks, when set, the Parity bi…
58773 …IG_REG_PRTY_MASK_H_0_MEM106_I_MEM_PRTY_BB_SHIFT 3
58774 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
58776 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
58778 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
58780 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
58782 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
58784 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
58786 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
58788 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
58790 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
58792 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
58794 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
58796 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58798 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
58800 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
58802 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
58804 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
58806 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
58808 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
58810 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
58812 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
58814 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
58816 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
58818 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
58820 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
58822 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
58824 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
58826 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
58828 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
58830 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
58832 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
58834 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
58836 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
58838 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
58841 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
58843 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58845 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
58847 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
58849 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
58851 … (0x1<<3) // This bit masks, when set, the Parity bi…
58852 …IG_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_E5_SHIFT 3
58853 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
58855 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
58857 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
58859 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
58861 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
58863 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
58865 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
58867 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
58869 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
58871 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
58873 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
58875 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
58877 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
58879 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
58881 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
58883 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
58885 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
58887 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
58889 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
58891 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
58893 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
58895 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
58897 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
58899 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
58901 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
58903 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
58905 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
58907 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
58909 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
58911 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
58913 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
58915 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
58917 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
58919 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
58921 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
58923 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
58925 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
58927 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
58929 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
58931 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
58933 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
58935 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58937 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
58939 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
58941 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
58943 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
58945 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
58947 … (0x1<<3) // This bit masks, when set, the Parity bi…
58948 …IG_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_K2_SHIFT 3
58949 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
58951 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
58953 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
58955 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
58957 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
58959 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
58961 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
58963 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
58965 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
58967 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
58969 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
58971 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
58973 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
58975 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
58977 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
58979 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
58981 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
58983 … (0x1<<3) // This bit masks, when set, the Parity bi…
58984 …IG_REG_PRTY_MASK_H_1_MEM087_I_MEM_PRTY_BB_SHIFT 3
58985 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
58987 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
58989 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
58991 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
58993 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
58995 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
58997 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
58999 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59001 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
59003 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
59005 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
59007 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
59009 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
59011 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
59013 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
59015 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
59017 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
59019 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
59021 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
59023 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
59025 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
59028 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59030 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
59032 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
59034 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
59036 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
59038 … (0x1<<3) // This bit masks, when set, the Parity bi…
59039 …IG_REG_PRTY_MASK_H_2_MEM106_I_MEM_PRTY_E5_SHIFT 3
59040 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
59042 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
59044 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
59046 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
59048 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
59050 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
59052 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
59054 … (0x1<<3) // This bit masks, when set, the Parity bi…
59055 …IG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_BB_SHIFT 3
59056 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
59058 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
59060 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
59062 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
59064 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
59066 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
59068 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
59070 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
59072 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
59074 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59076 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
59078 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
59080 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
59082 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
59084 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
59086 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
59088 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
59090 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
59092 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
59094 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
59096 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
59098 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
59100 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
59102 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
59104 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
59106 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
59108 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
59110 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
59112 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
59114 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
59116 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
59118 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
59120 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
59122 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
59124 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
59126 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
59128 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
59130 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
59132 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
59134 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
59136 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
59138 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
59140 … (0x1<<3) // This bit masks, when set, the Parity bi…
59141 …IG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_K2_SHIFT 3
59142 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
59144 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
59146 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
59148 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
59150 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
59152 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
59154 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
59156 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
59158 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
59160 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
59162 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59164 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
59166 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
59168 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
59170 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
59172 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
59174 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
59176 … (0x1<<23) // This bit masks, when set, the Parity bit: NI…
59178 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
59180 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
59182 … (0x1<<26) // This bit masks, when set, the Parity bit: NI…
59184 … (0x1<<27) // This bit masks, when set, the Parity bit: NI…
59186 … (0x1<<28) // This bit masks, when set, the Parity bit: NI…
59188 … (0x1<<29) // This bit masks, when set, the Parity bit: NI…
59190 … (0x1<<30) // This bit masks, when set, the Parity bit: NI…
59192 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
59194 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
59196 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
59198 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
59200 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
59202 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
59204 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
59206 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
59208 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
59210 … (0x1<<24) // This bit masks, when set, the Parity bit: NI…
59212 … (0x1<<25) // This bit masks, when set, the Parity bit: NI…
59215 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
59217 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
59219 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
59221 … (0x1<<3) // This bit masks, when set, the Parity bi…
59222 …IG_REG_PRTY_MASK_H_3_MEM097_I_MEM_PRTY_E5_SHIFT 3
59223 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
59225 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
59227 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
59229 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
59231 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
59233 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
59235 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
59237 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59239 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
59241 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
59243 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
59245 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
59247 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
59249 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59251 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
59253 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
59255 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
59257 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
59259 … (0x1<<17) // This bit masks, when set, the Parity bit: NI…
59261 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
59263 … (0x1<<18) // This bit masks, when set, the Parity bit: NI…
59265 … (0x1<<19) // This bit masks, when set, the Parity bit: NI…
59267 … (0x1<<20) // This bit masks, when set, the Parity bit: NI…
59269 … (0x1<<4) // This bit masks, when set, the Parity bit: NI…
59271 … (0x1<<21) // This bit masks, when set, the Parity bit: NI…
59273 … (0x1<<5) // This bit masks, when set, the Parity bit: NI…
59275 … (0x1<<22) // This bit masks, when set, the Parity bit: NI…
59277 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
59279 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
59281 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
59283 … (0x1<<3) // This bit masks, when set, the Parity bi…
59284 …IG_REG_PRTY_MASK_H_3_MEM014_I_MEM_PRTY_K2_SHIFT 3
59285 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
59287 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
59289 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
59291 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
59293 … (0x1<<0) // This bit masks, when set, the Parity bit: NI…
59295 … (0x1<<1) // This bit masks, when set, the Parity bit: NI…
59297 … (0x1<<2) // This bit masks, when set, the Parity bit: NI…
59299 … (0x1<<3) // This bit masks, when set, the Parity bi…
59300 …IG_REG_PRTY_MASK_H_3_MEM018_I_MEM_PRTY_BB_SHIFT 3
59301 … (0x1<<6) // This bit masks, when set, the Parity bit: NI…
59303 … (0x1<<7) // This bit masks, when set, the Parity bit: NI…
59305 … (0x1<<8) // This bit masks, when set, the Parity bit: NI…
59307 … (0x1<<9) // This bit masks, when set, the Parity bit: NI…
59309 … (0x1<<10) // This bit masks, when set, the Parity bit: NI…
59311 … (0x1<<11) // This bit masks, when set, the Parity bit: NI…
59313 … (0x1<<12) // This bit masks, when set, the Parity bit: NI…
59315 … (0x1<<13) // This bit masks, when set, the Parity bit: NI…
59317 … (0x1<<14) // This bit masks, when set, the Parity bit: NI…
59319 … (0x1<<15) // This bit masks, when set, the Parity bit: NI…
59321 … (0x1<<16) // This bit masks, when set, the Parity bit: NI…
59324 …0x1 // Close-gate function disable bit: 0 - egress drain mode is enabled when close-gate input…
59328 … 0x500810UL //Access:RW DataWidth:0x10 // The Ethernet type value for L2 tag 3.
59331 … 0x50081cUL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
59332 … 0x500820UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
59333 … 0x500824UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
59334 … 0x500828UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
59335 … 0x50082cUL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
59336 … 0x500830UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
59338 …bit for choosing between XSTORM and YSTORM for forwarding RX packets. 0 is for XSTORM; 1 is for Y…
59339 …get the current credit count on the interface. This configuration should be static during run-time.
59343 … (0x1<<8) // T-bit to be used in CM he…
59349 …-PF drop and per-VPORT drop packets or forward the packet to the destination with the error bit se…
59350 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59351 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59352 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59353 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59354 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59355 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59356 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59357 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59358 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59359 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59360 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59361 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59362 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59363 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59364 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59365 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59366 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59367 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59368 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59369 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59370 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59371 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59372 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59373 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59374 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59375 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59376 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59377 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59378 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59379 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59380 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59381 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59382 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59383 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59384 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59385 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59386 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59387 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59388 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59389 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59390 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59391 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59392 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59393 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59394 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59395 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59396 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59397 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59398 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59399 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59400 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59401 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59402 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59403 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59404 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59405 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59406 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59407 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59408 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59409 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59410 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59411 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59412 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59413 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59414 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59415 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59416 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59417 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59418 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59419 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59420 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59421 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59422 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59423 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59424 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59425 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59426 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59427 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59428 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59429 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59430 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59431 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59432 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59433 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59434 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59435 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59436 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59437 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59438 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59439 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59440 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59441 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59442 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59443 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59444 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59445 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59446 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59447 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59448 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59449 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59450 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59451 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59452 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59453 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59454 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59455 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59456 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59457 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59458 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59459 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59460 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59461 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59462 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59463 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59464 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59465 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59466 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59467 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59468 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59469 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59470 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59471 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59472 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59473 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59474 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59475 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59476 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59477 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59478 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59479 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59480 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59481 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59482 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59483 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59484 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59485 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59486 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59487 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59488 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59489 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59490 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59491 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59492 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59493 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59494 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59495 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59496 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59497 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59498 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59499 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59500 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59501 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59502 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59503 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59504 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59505 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59506 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59507 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59508 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59509 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59510 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59511 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59512 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59513 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59514 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59515 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59516 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59517 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59518 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59519 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59520 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59521 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59522 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59523 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59524 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59525 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59526 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59527 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59528 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59529 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59530 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59531 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59532 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59533 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59534 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59535 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59536 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59537 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59538 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59539 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59540 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59541 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59542 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59543 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59544 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59545 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59546 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59547 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59548 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59549 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59550 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59551 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59552 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59553 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59554 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59555 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59556 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59557 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
59558 …ccess:RW DataWidth:0x1 // Per-PF drop configuration to be used for main and LB traffic of all…
59561 …0cUL //Access:R DataWidth:0x18 // TX SOP descriptor queue empty status - for main traffic que…
59562 …c10UL //Access:R DataWidth:0x18 // TX SOP descriptor queue full status - for main traffic que…
59563 … DataWidth:0x40 // Addresses for TimeSync related registers in the timesync generator sub-module.
59567 …1 // Output enable for the STORM interface. This configuration should be static during run-time.
59580 …UL //Access:RW DataWidth:0x4 // Size of the proprietary header, in 32-bit words, that is pres…
59582 …//Access:RW DataWidth:0x1 // Packet has Ethernet FCS field. Set this bit to indicate that th…
59586 …Bit-map indicating which L2 hdrs may appear after the basic Ethernet header. Bit 0-tag0 (outer ta…
59587 … 0x50101cUL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59588 … 0x501020UL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59589 … 0x501024UL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59590 … 0x501028UL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59591 … 0x50102cUL //Access:RW DataWidth:0x8 // Bit-map indicating which L2 hdrs may appear after L…
59592 … 0x501030UL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59593 … 0x501034UL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59594 …Bit-map indicating which L2 hdrs may appear after the basic Ethernet header. Bit 0-tag0 (outer ta…
59595 … 0x50103cUL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59596 … 0x501040UL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59597 … 0x501044UL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59598 … 0x501048UL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59599 … 0x50104cUL //Access:RW DataWidth:0x8 // Bit-map indicating which L2 hdrs may appear after L…
59600 … 0x501050UL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59601 … 0x501054UL //Access:RW DataWidth:0x8 // Bit-map indicating which…
59603 … (0x1<<0) // Enable bit for Ethernet-over-GRE (L2 GRE…
59605 … (0x1<<1) // Enable bit for IP-over-GRE (IP GRE) e…
59607 … (0x1<<2) // Enable bit for VXLAN encapsula…
59612 … 0x501068UL //Access:RW DataWidth:0x10 // FCOE Ethertype - default is 0x8906.
59617 … 0x50107cUL //Access:RW DataWidth:0x8 // IPv4 protocol field for ICMPv4 - defaults to 0x01.
59618 … 0x501080UL //Access:RW DataWidth:0x8 // IPv6 next header field for ICMPv6 - defaults to 0x3A.
59624 … 0x501098UL //Access:RW DataWidth:0x20 // Destination MAC address 3;The LLH will look fo…
59625 … 0x50109cUL //Access:RW DataWidth:0x10 // Destination MAC address 3;The LLH will look fo…
59626 … 0x5010a0UL //Access:RW DataWidth:0x20 // Destination MAC address 3. LLH will look for …
59627 … 0x5010a4UL //Access:RW DataWidth:0x10 // Destination MAC address 3. LLH will look for …
59647 … 0x5010f4UL //Access:RW DataWidth:0x20 // Destination IP address 3;The LLH will look fo…
59648 … 0x5010f8UL //Access:RW DataWidth:0x20 // Destination IP address 3;The LLH will look fo…
59649 … 0x5010fcUL //Access:RW DataWidth:0x20 // Destination IP address 3;The LLH will look fo…
59650 … 0x501100UL //Access:RW DataWidth:0x20 // Destination IP address 3;The LLH will look fo…
59651 …s:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_0: 0 - IPv6; 1-IPv4.
59652 …s:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_1: 0 - IPv6; 1-IPv4.
59653 …s:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_2: 0 - IPv6; 1-IPv4.
59656 … 0x501118UL //Access:RW DataWidth:0x10 // Destination TCP address 3. The LLH will look f…
59659 … 0x501124UL //Access:RW DataWidth:0x10 // Destination UDP address 3 The LLH will look f…
59661 … (0x1<<0) // Mask bit for forwarding broa…
59663 … (0x1<<1) // Mask bit for forwarding mult…
59667 …CST (0x1<<3) // Mask bit for forwarding…
59668 …IG_REG_RX_LLH_NCSI_MCP_MASK_IPV6_MLCST_SHIFT 3
59669 … (0x1<<4) // Mask bit for forwarding unic…
59671 … (0x1<<5) // Mask bit for forwarding pack…
59673 … (0x1<<6) // Mask bit for forwarding pack…
59675 … (0x1<<7) // Mask bit for forwarding pack…
59677 … (0x1<<8) // Mask bit for forwarding pack…
59679 … (0x1<<9) // Mask bit for forwarding pack…
59681 … (0x1<<10) // Mask bit for forwarding pack…
59683 … (0x1<<11) // Mask bit for forwarding pack…
59685 … (0x1<<12) // Mask bit for forwarding pack…
59687 … (0x1<<13) // Mask bit for forwarding pack…
59689 … (0x1<<14) // Mask bit for forwarding pack…
59691 … (0x1<<15) // Mask bit for forwarding pack…
59693 … (0x1<<16) // Mask bit for forwarding pack…
59695 … (0x1<<17) // Mask bit for forwarding pack…
59697 … (0x1<<18) // Mask bit for forwarding pack…
59699 … (0x1<<19) // Mask bit for forwarding pack…
59705 … (0x1<<22) // Mask bit for forwarding pack…
59707 … (0x1<<23) // Mask bit for forwarding pack…
59709 … (0x1<<24) // Mask bit for forwarding pack…
59711 … (0x1<<25) // Mask bit for forwarding pack…
59713 … (0x1<<26) // Mask bit for forwarding pack…
59719 … (0x1<<29) // Mask bit for forwarding ICMP…
59721 … (0x1<<30) // Mask bit for forwarding ICMP…
59723 … (0x1<<31) // Mask bit for forwarding ICMP…
59726 … (0x1<<0) // Mask bit for forwarding pack…
59728 … (0x1<<1) // Mask bit for forwarding pack…
59730 … (0x1<<2) // Mask bit for forwarding pack…
59732 …D1 (0x1<<3) // Mask bit for forwarding…
59733 …IG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ID1_SHIFT 3
59734 … (0x1<<4) // Mask bit for forwarding pack…
59737 … (0x1<<0) // Mask bit for forwarding pack…
59739 … (0x1<<1) // Mask bit for forwarding pack…
59741 … (0x1<<2) // Mask bit for forwarding pack…
59743 … (0x1<<3) // Mask bit for forwarding…
59744 …IG_REG_RX_LLH_NCSI_MCP_MASK_OTAG1_SHIFT 3
59745 … (0x1<<4) // Mask bit for forwarding pack…
59748 … (0x1<<0) // Mask bit for forwarding pack…
59750 … (0x1<<1) // Mask bit for forwarding IPv4…
59752 … (0x1<<2) // Mask bit for forwarding IPv6…
59754 …ER (0x1<<3) // Mask bit for forwarding…
59755 …IG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV4_ER_SHIFT 3
59756 … (0x1<<4) // Mask bit for forwarding ICMP…
59758 … (0x1<<5) // Mask bit for forwarding ICMP…
59760 … 0x501138UL //Access:RW DataWidth:0x1 // Enable bit for forwarding pack…
59761 …s:RW DataWidth:0x1 // Enable bit for forwarding packets for each PF to MCP in multifunction m…
59763 … (0x1<<0) // Mask bit for not forwarding …
59765 …CST (0x1<<1) // Mask bit for not forwarding …
59769 …IPV6_MLCST (0x1<<3) // Mask bit for not forwar…
59770 …IG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV6_MLCST_SHIFT 3
59771 … (0x1<<4) // Mask bit for not forwarding …
59773 … (0x1<<5) // Mask bit for not forwarding …
59775 … (0x1<<6) // Mask bit for not forwarding …
59777 … (0x1<<7) // Mask bit for not forwarding …
59779 … (0x1<<8) // Mask bit for not forwarding …
59781 … (0x1<<9) // Mask bit for not forwarding …
59783 … (0x1<<10) // Mask bit for not forwarding …
59785 …YPE0 (0x1<<11) // Mask bit for not forwarding …
59787 …YPE1 (0x1<<12) // Mask bit for not forwarding …
59789 … (0x1<<13) // Mask bit for not forwarding …
59791 … (0x1<<14) // Mask bit for not forwarding …
59793 … (0x1<<15) // Mask bit for not forwarding …
59795 … (0x1<<16) // Mask bit for not forwarding …
59797 … (0x1<<17) // Mask bit for not forwarding …
59799 … (0x1<<18) // Mask bit for not forwarding …
59801 … (0x1<<19) // Mask bit for not forwarding …
59807 … (0x1<<22) // Mask bit for not forwarding …
59809 … (0x1<<23) // Mask bit for not forwarding …
59811 … (0x1<<24) // Mask bit for not forwarding …
59813 … (0x1<<25) // Mask bit for not forwarding …
59815 …_DST (0x1<<26) // Mask bit for not forwarding …
59821 …_NA (0x1<<29) // Mask bit for not forwarding …
59823 …_RA (0x1<<30) // Mask bit for not forwarding …
59825 … (0x1<<31) // Mask bit for not forwarding …
59828 …_ANY (0x1<<0) // Mask bit for not forwarding …
59830 …_NONE (0x1<<1) // Mask bit for not forwarding …
59832 …_ID0 (0x1<<2) // Mask bit for not forwarding …
59834 …IVLAN_ID1 (0x1<<3) // Mask bit for not forwar…
59835 …IG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ID1_SHIFT 3
59836 …_ID2 (0x1<<4) // Mask bit for not forwarding …
59839 …ANY (0x1<<0) // Mask bit for not forwarding …
59841 …NONE (0x1<<1) // Mask bit for not forwarding …
59843 … (0x1<<2) // Mask bit for not forwarding …
59845 …OTAG1 (0x1<<3) // Mask bit for not forwar…
59846 …IG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG1_SHIFT 3
59847 …PF (0x1<<4) // Mask bit for not forwarding …
59850 … (0x1<<0) // Mask bit for not forwarding …
59852 …4 (0x1<<1) // Mask bit for not forwarding …
59854 …6 (0x1<<2) // Mask bit for not forwarding …
59856 …ICMPV4_ER (0x1<<3) // Mask bit for not forwar…
59857 …IG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV4_ER_SHIFT 3
59858 …6_ER (0x1<<4) // Mask bit for not forwarding …
59860 …6_NS (0x1<<5) // Mask bit for not forwarding …
59862 … 0x501150UL //Access:RW DataWidth:0x1 // Enable bit for not forwarding …
59863 … DataWidth:0x1 // Enable bit for not forwarding packets for the PF to the host in multifuncti…
59885 … (0x1<<0) // L2 filter rule enable. Set this bit to enable this rule.
59889 …for comparison. A value of 7 selects the MAC address range 01-80-C2-00-00-00 to 01-80-C2-00-00-0F.
60005 …1<<0) // L2 filter (for not forwarding to the host) rule enable. Set this bit to enable this rule.
60009 … for comparison. A value of 7 selects the MAC address range 01-80-C2-00-00-00 to 01-80-C2-00-00-0F.
60124 …ataWidth:0x1 // Disable bit for forwarding packets to the host for this port. No packet is for…
60125 …:RW DataWidth:0x1 // Disable bit for forwarding packets to the host. No packet is forwarded …
60126 …e bit for forwarding packets that failed PF classification to the host. No packet with classifica…
60127 …-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that …
60133 … (0x1<<0) // Mask bit for filtering packe…
60135 … (0x1<<1) // Mask bit for filtering packe…
60137 … (0x1<<2) // Mask bit for filtering packe…
60139 … (0x1<<3) // Mask bit for filtering …
60140 …IG_REG_RX_LLH_STORM_MASK_ETHERTYPE3_SHIFT 3
60147 …Bit 0 - message FIFO empty. Bit 1 - descriptor FIFO empty. Bit 2 - message FIFO has more than 32 e…
60148 …-to-send data remaining below which ETS arbiter for the LB path should start selecting the next pa…
60149 …//Access:RW DataWidth:0x1 // Packet has Ethernet FCS field. Set this bit to indicate that th…
60150 …ataWidth:0x1 // Zero-padding enable for LB packets. Set this bit to enable the padding of shor…
60152 …T_EN (0x1<<0) // Enable bit for the BRB interfa…
60156 … DataWidth:0x20 // Increment PERIOD for the BRB interface rate limiter - in term of 25MHz clo…
60157 …W DataWidth:0x20 // Increment VALUE for the BRB interface rate limiter - in term of bytes, cy…
60158 … DataWidth:0x20 // Upper bound VALUE for the BRB interface rate limiter - in term of bytes, cy…
60161 … (0x1<<0) // Enable bit for the per-TC rate limite…
60163 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60166 … (0x1<<0) // Enable bit for the per-TC rate limite…
60168 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60171 … (0x1<<0) // Enable bit for the per-TC rate limite…
60173 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60176 … (0x1<<0) // Enable bit for the per-TC rate limite…
60178 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60181 … (0x1<<0) // Enable bit for the per-TC rate limite…
60183 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60186 … (0x1<<0) // Enable bit for the per-TC rate limite…
60188 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60191 … (0x1<<0) // Enable bit for the per-TC rate limite…
60193 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60196 … (0x1<<0) // Enable bit for the per-TC rate limite…
60198 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60200 …40UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60201 …44UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60202 …48UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60203 …4cUL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60204 …50UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60205 …54UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60206 …58UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60207 …5cUL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60208 …560UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60209 …564UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60210 …568UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60211 …56cUL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60212 …570UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60213 …574UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60214 …578UL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60215 …57cUL //Access:RW DataWidth:0x20 // Increment VALUE for the per-TC rate limiter - in term of …
60216 …0UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60217 …4UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60218 …8UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60219 …cUL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60220 …0UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60221 …4UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60222 …8UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60223 …cUL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60232 …lient): 0-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6…
60233 …lient): 0-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6…
60234 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
60235 …3:0] are for priority 0 client; bits [39:36] are for priority 9 client. The clients are assigned …
60237 …-robin arbiter stays on the winning input instead of moving to the next one. Bit 0 is for the mai…
60239 … 0x5015e0UL //Access:RW DataWidth:0x1 // Enable bit for the pseudo-random arbit…
60243 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 3 is allowed to reach.
60253 …idth:0x20 // Specify the weight (in bytes) to be added to credit register 3 when it is time to i…
60260 …501634UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
60261 …501638UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
60262 …50163cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
60263 …R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter credit register 3.
60264 …501644UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
60265 …501648UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
60266 …50164cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
60267 …501650UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
60268 …501654UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
60269 …501658UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbiter…
60270 …:RW DataWidth:0x1 // Disable bit for forwarding packets to the host. No packet is forwarded …
60271 …e bit for forwarding packets that failed PF classification to the host. No packet with classifica…
60272 …-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that …
60289 …r TimeSync feature. Bit 0 enables TimeSync on RX side. Bit 1 enables V1 frame format in timesync…
60290 …r TimeSync feature. Bit 0 enables TimeSync on TX side. Bit 1 enables V1 frame format in timesync…
60293 …-specified packet timestamp mode. NIG will capture the timestamp value of the packet that SW indi…
60297 …bit to 1 to mask out the particular parameter. 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0…
60298 …bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 1-{IPv4 DA 0; UDP DP 1} . 2…
60299 …bit to 1 to mask out the particular parameter. 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0…
60300 …bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 1-{IPv4 DA 0; UDP DP 1} . 2…
60301 …-deep FIFOs for the host. Bits [15:0] return the sequence ID of the packet. Bit 16 indicates the…
60302 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
60303 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
60304 … 1-deep FIFOs for MCP. Bits [15:0] return the sequence ID of the packet. Bit 16 indicates the va…
60305 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. …
60306 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. …
60307 …-deep FIFOs for TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16 indicates the…
60308 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFO for the TX …
60309 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFO for the TX …
60310 …-bit time for the 64-bit timestamp value. Error occurs when bits [31:30] of the MAC timestamp val…
60311 …-bit time for the 64-bit timestamp value. Error occurs when bits [31:30] of the MAC timestamp val…
60312 …bit to perform PF classification before sending the packet to the BRB and performing WOL detection…
60313 …n based on tag/VLAN/MAC matching. 2: classification based on protocol. 3: dual-stage classificati…
60314 …-stage classification mode; value of 0: AND the hit vectors; value of 1: OR the hit vectors; value…
60315 …Default per-port value to be used when protocol-based classification fails. This is the per-port …
60316 …lt per-port value to be used when outer-tag/inner VLAN/MAC classification fails. This is the per…
60317 …3-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally r…
60318 …3-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally r…
60319 …3-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally r…
60320 …3-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally r…
60321 …3-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally r…
60322 …3-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally r…
60323 …3-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally r…
60324 …3-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally r…
60325 …-bit field immediately following the Ethertype to be used for each of the outer tag value bit. The…
60326 …23:18] of this register specify the index for bit 7. Bits [5:0] of this register specify the inde…
60327 …3:18] of this register specify the index for bit 11. Bits [5:0] of this register specify the inde…
60328 …3:18] of this register specify the index for bit 15. Bits [5:0] of this register specify the inde…
60329 …:RW DataWidth:0x10 // Outer tag value mask. Set a bit to 0 to mask out the corresponding bit …
60330 …-port per-PF register. This register selects the classification type for the tag/VLAN/MAC mode. …
60331 … 0x5019b0UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60333 …9c0UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function select b…
60335 … 0x5019d0UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. Per-function…
60337 …1 // This is a per-port per-PF register. Per-function no outer tag/inner VLAN configuration fo…
60338 …er-port per-PF register. Per-function MAC addresses to be matched with for MAC-address-based clas…
60340 … 0x501a80UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60342 …-port per-PF register. Per-function mode select bit to indicate whether the filter is to be used …
60344 …-port per-PF register. Per-function select bits for the different protocol types to be evaluated …
60346 …b40UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function select b…
60348 …e. 0 selects connection-based classification. 1 selects the PF-based classification. This regist…
60349 …-tuple search for TCP packets. Set this bit to use the TCP 4-tuple (TCP source and destination po…
60350 …-tuple search for UDP packets. Set this bit to use the UDP 4-tuple (UDP source and destination po…
60351 …ed to hash the data string in connection-based engine classification. This register is used only …
60352 …-entry Engine ID lookup table, with 1 bit per entry. Set the bit to 1 to have packets associated …
60354 …bit select. This configuration selects one of the 24-bit destination QP bits to be used as the en…
60355 …-global-PF engine ID to be used in PF-based engine classification. Set the bit to 1 to have packe…
60356 …ss:RW DataWidth:0x3 // Flow control mode. 0 - disable; 1 - PFC; 2 - LLFC; 3 - PPP; 4 - PAUSE…
60357 …dth:0x20 // Eight 4-bit configurations for specifying which TC (0-15 for future expansion) each …
60359 …ting the packet priority information. Valid values are 2-5 for selecting one of the L2 tags 2-5. …
60361 …3) // Bit offset in the outer tag starting from which to extract the 3-bit packet priority informa…
60362 …IG_REG_PKT_PRIORITY_TAG_PKT_PRIORITY_OTAG_BITOFFSET_SHIFT 3
60363 …Bit offset in the selected tag starting from which to extract the 3-bit packet priority informatio…
60365 …bit per TC and the same configuration is applicable to both RX and LB interfaces to the BRB of the…
60366 …. There is one bit per TC and the same configuration is applicable to both RX and LB interfaces t…
60367 …cess:RW DataWidth:0x8 // Per-TC flow control enable for received XOFF requests to pause trans…
60368 …b8UL //Access:RW DataWidth:0x8 // Per-TC flow control enable for XOFF messages sent to the MA…
60369 …/Access:RW DataWidth:0x9 // Per-TC flow control enable for received XOFF requests to pause LB…
60370 …W DataWidth:0x1 // Enable bit for the no-drop-hdr-ind field of the LB-only-header. When set,…
60371 …-drop of LB packets with the no-drop-hdr-ind bit set due to per-TC full backpressure from the BRB.…
60372 …cifies the number of 256-bit cycles, starting from the SOP cycle, of the packet not to be dropped …
60373 … // Flow control priorities used for each TC. This register is bit-mapped with one bit for each …
60374 … // Flow control priorities used for each TC. This register is bit-mapped with one bit for each …
60375 … // Flow control priorities used for each TC. This register is bit-mapped with one bit for each …
60376 … // Flow control priorities used for each TC. This register is bit-mapped with one bit for each …
60377 … // Flow control priorities used for each TC. This register is bit-mapped with one bit for each …
60378 … // Flow control priorities used for each TC. This register is bit-mapped with one bit for each …
60379 … // Flow control priorities used for each TC. This register is bit-mapped with one bit for each …
60380 … // Flow control priorities used for each TC. This register is bit-mapped with one bit for each …
60381 …Bit-map indicating which received SAFC/PFC priorities to map to the TC. A priority is mapped to t…
60382 … Bit-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC wh…
60383 … Bit-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC wh…
60384 … Bit-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC wh…
60385 …Bit-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC whe…
60386 …Bit-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC whe…
60387 …Bit-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC whe…
60388 …Bit-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC whe…
60393 …enable. Set this bit to enable drain mode. Drain mode starts immediately upon assertion and stops…
60394 …affic. Set this bit to enable drain mode. Drain mode starts immediately upon assertion and stops…
60395 …Bit 0 is for TC0 flow. Bit 7 is for TC7 flow. When enabled -- draining of the corrresponding TC …
60396 …Bit 0 is for TC0 flow. Bit 8 is for TC8 flow. When enabled -- draining of the corrresponding TC …
60406 … 0x501c50UL //Access:RW DataWidth:0x1 // Set this bit to clear the curren…
60436 … // Statistics for the number of single-cycle packets dropped. This is an RF generated RC statist…
60454 …dropped due to buffer full. This is an RF generated RC statistics register - reading this registe…
60455 …uncated due to buffer full. This is an RF generated RC statistics register - reading this registe…
60497 … // Statistics for the number of single-cycle packets dropped. This is an RF generated RC statist…
60498 …ll of the TX packets dropped, due to the drop bit, the per-PF drop, the per-VPORT drop, and the M…
60499 …// Statistic register for the number of TX packets that have the per-PF drop or per-VPORT drop con…
60500 … all of the LB packets dropped, due to the drop bit, the per-PF drop, the per-VPORT drop, and the…
60501 …-PF drop or per-VPORT drop configuration set while the no-drop-hdr-ind in the packet is cleared. T…
60568 …ets from BMB to be forwarded to the host that got truncated due to BRB LB per-TC full backpressure.
60569 …ckets from BMB to be forwarded to the host that got dropped due to BRB LB per-TC full backpressure.
60570 … 0x501f08UL //Access:RW DataWidth:0x1 // Zero-padding enable for TX packets. Set this bi…
60574 … (0xff<<1) // TC enable for EDPM. There is one bit per TC. This is us…
60576 …-to-transmit data remaining below which ETS arbiter for the transmit path should start selecting …
60580 …TELIMIT_EN (0x1<<0) // Enable bit for the global rate…
60584 …ccess:RW DataWidth:0x20 // Increment PERIOD for the global rate limiter - in term of 25MHz clo…
60585 …Access:RW DataWidth:0x20 // Increment VALUE for the global rate limiter - in term of bytes, cy…
60586 …cess:RW DataWidth:0x20 // Upper bound VALUE for the global rate limiter - in term of bytes, cy…
60589 …-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffi…
60590 …-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffi…
60591 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
60592 …3:0] are for priority 0 client; bits [47:44] are for priority 11 client. The clients are assigned…
60594 …-robin arbiter stays on the winning input instead of moving to the next one. Bit 0 is for the mai…
60596 … 0x501f50UL //Access:RW DataWidth:0x1 // Enable bit for the pseudo-random arbit…
60597 … 0x501f54UL //Access:RW DataWidth:0x1 // Set this bit to disable debug tr…
60601 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 3 is allowed to reach.
60613 …idth:0x20 // Specify the weight (in bytes) to be added to credit register 3 when it is time to i…
60622 …501fb8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60623 …501fbcUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60624 …501fc0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60625 …R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter credit register 3.
60626 …501fc8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60627 …501fccUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60628 …501fd0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60629 …501fd4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60630 …501fd8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60631 …501fdcUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60632 …501fe0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60633 …501fe4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbiter…
60635 … (0x1<<0) // Mask bit for forwarding broa…
60637 … (0x1<<1) // Mask bit for forwarding mult…
60641 …CST (0x1<<3) // Mask bit for forwarding…
60642 …IG_REG_TX_LLH_NCSI_MCP_MASK_IPV6_MLCST_SHIFT 3
60643 … (0x1<<4) // Mask bit for forwarding unic…
60645 … (0x1<<5) // Mask bit for forwarding pack…
60647 … (0x1<<6) // Mask bit for forwarding pack…
60649 … (0x1<<7) // Mask bit for forwarding pack…
60651 … (0x1<<8) // Mask bit for forwarding pack…
60653 … (0x1<<9) // Mask bit for forwarding pack…
60655 … (0x1<<10) // Mask bit for forwarding pack…
60657 … (0x1<<11) // Mask bit for forwarding pack…
60659 … (0x1<<12) // Mask bit for forwarding pack…
60661 … (0x1<<13) // Mask bit for forwarding pack…
60663 … (0x1<<14) // Mask bit for forwarding pack…
60665 … (0x1<<15) // Mask bit for forwarding pack…
60667 … (0x1<<16) // Mask bit for forwarding pack…
60669 … (0x1<<17) // Mask bit for forwarding pack…
60671 … (0x1<<18) // Mask bit for forwarding pack…
60673 … (0x1<<19) // Mask bit for forwarding pack…
60679 … (0x1<<22) // Mask bit for forwarding pack…
60681 … (0x1<<23) // Mask bit for forwarding pack…
60683 … (0x1<<24) // Mask bit for forwarding pack…
60685 … (0x1<<25) // Mask bit for forwarding pack…
60687 … (0x1<<26) // Mask bit for forwarding pack…
60693 … (0x1<<29) // Mask bit for forwarding ICMP…
60695 … (0x1<<30) // Mask bit for forwarding ICMP…
60697 … (0x1<<31) // Mask bit for forwarding ICMP…
60700 … (0x1<<0) // Mask bit for forwarding pack…
60702 … (0x1<<1) // Mask bit for forwarding pack…
60704 … (0x1<<2) // Mask bit for forwarding pack…
60706 …D1 (0x1<<3) // Mask bit for forwarding…
60707 …IG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ID1_SHIFT 3
60708 … (0x1<<4) // Mask bit for forwarding pack…
60711 …T (0x1<<0) // Mask bit for not forwarding …
60713 …LCST (0x1<<1) // Mask bit for not forwarding …
60717 …_IPV6_MLCST (0x1<<3) // Mask bit for not forwar…
60718 …IG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_MLCST_SHIFT 3
60719 …T (0x1<<4) // Mask bit for not forwarding …
60721 … (0x1<<5) // Mask bit for not forwarding …
60723 … (0x1<<6) // Mask bit for not forwarding …
60725 … (0x1<<7) // Mask bit for not forwarding …
60727 … (0x1<<8) // Mask bit for not forwarding …
60729 … (0x1<<9) // Mask bit for not forwarding …
60731 … (0x1<<10) // Mask bit for not forwarding …
60733 …TYPE0 (0x1<<11) // Mask bit for not forwarding …
60735 …TYPE1 (0x1<<12) // Mask bit for not forwarding …
60737 … (0x1<<13) // Mask bit for not forwarding …
60739 … (0x1<<14) // Mask bit for not forwarding …
60741 … (0x1<<15) // Mask bit for not forwarding …
60743 … (0x1<<16) // Mask bit for not forwarding …
60745 … (0x1<<17) // Mask bit for not forwarding …
60747 … (0x1<<18) // Mask bit for not forwarding …
60749 … (0x1<<19) // Mask bit for not forwarding …
60755 … (0x1<<22) // Mask bit for not forwarding …
60757 … (0x1<<23) // Mask bit for not forwarding …
60759 … (0x1<<24) // Mask bit for not forwarding …
60761 … (0x1<<25) // Mask bit for not forwarding …
60763 …U_DST (0x1<<26) // Mask bit for not forwarding …
60769 …6_NA (0x1<<29) // Mask bit for not forwarding …
60771 …6_RA (0x1<<30) // Mask bit for not forwarding …
60773 …6 (0x1<<31) // Mask bit for not forwarding …
60776 … (0x1<<0) // Mask bit for forwarding broa…
60778 … (0x1<<1) // Mask bit for forwarding mult…
60782 …LCST (0x1<<3) // Mask bit for forwarding…
60783 …IG_REG_TX_LLH_NCSI_NTWK_MASK_IPV6_MLCST_SHIFT 3
60784 … (0x1<<4) // Mask bit for forwarding unic…
60786 … (0x1<<5) // Mask bit for forwarding pack…
60788 … (0x1<<6) // Mask bit for forwarding pack…
60790 … (0x1<<7) // Mask bit for forwarding pack…
60792 … (0x1<<8) // Mask bit for forwarding pack…
60794 … (0x1<<9) // Mask bit for forwarding pack…
60796 … (0x1<<10) // Mask bit for forwarding pack…
60798 … (0x1<<11) // Mask bit for forwarding pack…
60800 … (0x1<<12) // Mask bit for forwarding pack…
60802 … (0x1<<13) // Mask bit for forwarding pack…
60804 … (0x1<<14) // Mask bit for forwarding pack…
60806 … (0x1<<15) // Mask bit for forwarding pack…
60808 … (0x1<<16) // Mask bit for forwarding pack…
60810 … (0x1<<17) // Mask bit for forwarding pack…
60812 … (0x1<<18) // Mask bit for forwarding pack…
60814 … (0x1<<19) // Mask bit for forwarding pack…
60820 … (0x1<<22) // Mask bit for forwarding pack…
60822 … (0x1<<23) // Mask bit for forwarding pack…
60824 … (0x1<<24) // Mask bit for forwarding pack…
60826 … (0x1<<25) // Mask bit for forwarding pack…
60828 … (0x1<<26) // Mask bit for forwarding pack…
60834 … (0x1<<29) // Mask bit for forwarding ICMP…
60836 … (0x1<<30) // Mask bit for forwarding ICMP…
60838 … (0x1<<31) // Mask bit for forwarding ICMP…
60841 … (0x1<<0) // Mask bit for forwarding pack…
60843 … (0x1<<1) // Mask bit for forwarding pack…
60845 … (0x1<<2) // Mask bit for forwarding pack…
60847 …ID1 (0x1<<3) // Mask bit for forwarding…
60848 …IG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ID1_SHIFT 3
60849 … (0x1<<4) // Mask bit for forwarding pack…
60871 …rride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bit…
60872 …rride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bit…
60889 …n the BMC-to-host path to BRB. This is also used in the TX management path (when enabled by *tx_m…
60890 …able the use of TC to control the flow of TX management traffic. Set this bit to 1 to enable the …
60891 …-to-MCP path enable. Set this bit to enable the routing of management packets from PBF interface …
60895 … 0x5020acUL //Access:RW DataWidth:0x6 // Almost-full threshold for BM…
60900 … 0x5020c0UL //Access:RW DataWidth:0x7 // Almost-full threshold for DO…
60904 …- send debug traffic through port 0. 1 - send debug traffic through port 1. 2 - send debug traffi…
60907 … 0x5020dcUL //Access:RW DataWidth:0x8 // Almost-full threshold for de…
60910 …- the number of valid bytes in the last cycle (0=all bytes are valid); [261]eop - active on the la…
60913 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
60914 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
60915 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
60916 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
60922 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
60923 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
60924 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
60925 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
60927 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
60928 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
60929 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
60930 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
60932 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
60933 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
60934 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
60935 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
60937 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
60938 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
60939 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
60940 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
60942 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
60943 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
60944 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
60945 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
60947 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
60948 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
60949 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
60950 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
60953 …-port per-PF register. L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0: 5 - L…
60954 … per-port per-PF register. Proprietary header removal configuration for ACPI. Set this bit to 1 …
60955 …taWidth:0x1 // Set this bit to enable ACPI pattern matching and TCP SYN matching in multi-funct…
60956 …ataWidth:0x1 // Set this bit to enable ACPI and TCP SYN matching even when the packet is forwar…
60957 … 0x508080UL //Access:WB DataWidth:0x100 // This is a per-port per-PF register. Byt…
60959 …Width:0x1 // This is a per-port per-PF register. When this bit is set ACPI packet recognition…
60960 … 0x508104UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60961 … 0x508108UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60962 … 0x50810cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60963 … 0x508110UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60964 … 0x508114UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60965 … 0x508118UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60966 …811cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC32C for pattern 3.
60967 … 0x508120UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60968 … 0x508124UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60969 … 0x508128UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60970 … 0x50812cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60971 … 0x508130UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60972 … 0x508134UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60973 … 0x508138UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60974 … 0x50813cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60975 … 0x508140UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60976 …s:RW DataWidth:0x2 // This is a per-port per-PF register. Set bit 0 to enable wake on IPv4 T…
60977 …-port per-PF register. Enable bits for fields to be compared if IPv6 is present in the packet. B…
60978 …-port per-PF register. Enable bits for fields to be compared if IPv4 is present in the packet. B…
60979 … 0x508150UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. IPv…
60980 … 0x508154UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. TCP…
60981 … 0x508158UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. IPv…
60982 … 0x50815cUL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. TCP…
60983 … 0x508160UL //Access:WB DataWidth:0x80 // This is a per-port per-PF register. IPv…
60985 … 0x508170UL //Access:WB DataWidth:0x80 // This is a per-port per-PF register. IPv…
60987 … 0x508180UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. IPv…
60988 … 0x508184UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. IPv…
60989 …idth:0x1 // This is a per-port per-PF register. When this bit is set Magic Packet recognition…
60990 … 0x508190UL //Access:WB DataWidth:0x30 // This is a per-port per-PF register. MAC…
60992 …/Access:RW DataWidth:0x1 // This is a per-port per-PF register. A low-to-high transition of …
60993 … 0x5081a0UL //Access:WB_R DataWidth:0x100 // Read-only data from the Wa…
60995 …- a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details regist…
60996 …- all fields are sticky. Bits 15:0 - PF Vector: The bit-mapped vector indicating which of the gl…
60997 … 0x5081c8UL //Access:R DataWidth:0xe // Wake packet length - the actual length of…
60998 …- all fields are sticky. Bits 7:0 - ACPI MATCH: Per-function bit-mapped result from ACPI patte…
60999 …s:WB_R DataWidth:0x50 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
61001 …s:WB_R DataWidth:0x50 // Packet TimeSync information that is buffered in 1-deep FIFO for the TX …
61011 … classification mask bits bit 0: mask_dstMac bit 1: mask_srcMac bit 2: mask_dstIPv4 bit 3: mask_sr…
61012 … classification mask bits bit 0: mask_dstMac bit 1: mask_srcMac bit 2: mask_dstIPv4 bit 3: mask_sr…
61013 …ion rules bit 0: MAC address enable bit 1: IPV4 + UDP enable bit 2: Ethernet type enable bit 3: IP…
61014 …ion rules bit 0: MAC address enable bit 1: IPV4 + UDP enable bit 2: Ethernet type enable bit 3: IP…
61015 …aWidth:0x1 // This bit defines whether to add offset and jitter of the timestamp to the returne…
61019 …cksum 3: TRAILER � insert timestamp to packet trailer 4: IPv4_STANDARD � insert timestamp using st…
61022 …RW DataWidth:0x5 // Global timestamp shift for the free running counter. Legal values are 0-16
61026 …-deep FIFOs. Bits [15:0] return the sequence ID of the packet which is set by free running counte…
61027 …ataWidth:0x40 // RX user protocol Packet information that is buffered in 1-deep FIFO. Timestamp …
61029 …ataWidth:0x30 // RX user protocol packet information that is buffered in 1-deep FIFO. Source add…
61031 …-deep FIFOs. Bits [15:0] return the sequence ID of the packet which is set by free running counte…
61032 …ataWidth:0x40 // TX user protocol Packet information that is buffered in 1-deep FIFO. Timestamp …
61034 …ataWidth:0x30 // RX user protocol packet information that is buffered in 1-deep FIFO. Destinatio…
61036 …0x5088a8UL //Access:RW DataWidth:0x20 // This register contains the 32 bit LSB of the configur…
61037 …0x5088acUL //Access:RW DataWidth:0x20 // This register contains the 32 bit MSB of the configur…
61038 …0x5088b0UL //Access:RW DataWidth:0x20 // This register contains the 32 bit LSB of the offset v…
61039 …0x5088b4UL //Access:RW DataWidth:0x20 // This register contains the 32 bit MSB of the offset v…
61040 …0x5088b8UL //Access:R DataWidth:0x20 // This register contains the 32 bit LSB of the free run…
61041 …0x5088bcUL //Access:R DataWidth:0x20 // This register contains the 32 bit MSB of the free run…
61042 …0x5088c0UL //Access:R DataWidth:0x20 // This register contains the 32 bit LSB of the synchron…
61043 …0x5088c4UL //Access:R DataWidth:0x20 // This register contains the 32 bit MSB of the synchron…
61044 …, high period and low period are all configurable, and when asserting this bit the PPS starts to t…
61049 …ubtract from the TSGEN_OFFSET_T0 register when making a Drift adjustment. Bit 31 controls whether…
61050 …e0UL //Access:RW DataWidth:0x4 // Bits 3:0 are the active-low output enables for the TSIO Out…
61051 … 0x5088e4UL //Access:R DataWidth:0x4 // Bits 3:0 reflect pulse value for the TSIO Output pin…
61052 …FO data bytes occupancy is higher than this threshold nig_dorq_edpm_en is de-asserted. The value i…
61054 …bit 0 marks that packet should be duplicated to host and Storm when BTH opcode equals bth_hdr_flow…
61055 …D in case that PF classification fails: 0: Use engine 0. 1: Use engine 1. 2/3: Use connection base…
61057 …decision for ROCE/RROCE packets. Bits [3:2] define decision for other packets 0: use engine 0 1: u…
61059 …6 // This field maps (ipv4_tos >> 2) 6 bits to 6 bits: bits 5:3 - priority bits 2:0 - TC This c…
61065 …-port register L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0: 5 - L2 tags 0…
61066 …s a per-port register. Proprietary header removal configuration for ACPI. Set this bit to 1 to e…
61067 … 0x508b18UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61068 … 0x508b1cUL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61069 … 0x508b20UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61070 … 0x508b24UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61071 … 0x508b28UL //Access:RW DataWidth:0x1 // This is a per-port register. Enabl…
61072 … 0x508b2cUL //Access:RW DataWidth:0x1 // This is a per-port register. Enable…
61073 … 0x508b30UL //Access:RW DataWidth:0x1 // This is a per-port register. Perfo…
61074 … 0x508b34UL //Access:RW DataWidth:0x10 // This is a per-port register. Next …
61075 … 0x508b38UL //Access:RW DataWidth:0x10 // This is a per-port register. Destin…
61076 … // This is a per-port register which defines mapping of TC from the received TC to the TC sent …
61080 …I_MCP_MASK_IPV6_MLD (0x1<<0) // Mask bit for forwarding IPV6…
61082 …I_MCP_MASK_IPV6_NEI_SOLICI (0x1<<1) // Mask bit for forwarding IPv6…
61084 …I_MCP_MASK_DHCP_V6_SERVER (0x1<<2) // Mask bit for forwarding IPv6…
61086 …H_NCSI_MCP_MASK_DHCP_V4_CLIENT (0x1<<3) // Mask bit for forwarding…
61087 …IG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_DHCP_V4_CLIENT_SHIFT 3
61088 …I_MCP_MASK_DHCP_V4_SERVER (0x1<<4) // Mask bit for forwarding DHCP…
61090 …I_MCP_MASK_MAC6_K2_E5 (0x1<<5) // Mask bit for forwarding pack…
61092 …I_MCP_MASK_MAC7_K2_E5 (0x1<<6) // Mask bit for forwarding pack…
61094 …I_MCP_MASK_DHCP_V6_CLI_E5 (0x1<<7) // Mask bit for forwarding IPv6…
61097 …I_MCP_MASK_IPV6_MLD (0x1<<0) // Mask bit for forwarding unic…
61099 …I_MCP_MASK_IPV6_NEI_SOLICI (0x1<<1) // Mask bit for forwarding IPv6…
61101 …I_MCP_MASK_DHCP_V6_SERVER (0x1<<2) // Mask bit for forwarding DHCP…
61103 …H_NCSI_MCP_MASK_DHCP_V4_CLIENT (0x1<<3) // Mask bit for forwarding…
61104 …IG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_DHCP_V4_CLIENT_SHIFT 3
61105 …I_MCP_MASK_DHCP_V4_SERVER (0x1<<4) // Mask bit for forwarding DHCP…
61107 …I_MCP_MASK_DHCP_V6_CLI_E5 (0x1<<7) // Mask bit for forwarding DHCP…
61110 …LLH_NCSI_BRB_DNTFWD_MASK_IPV6_MLD (0x1<<0) // Mask bit for not forwarding …
61112 …LLH_NCSI_BRB_DNTFWD_MASK_IPV6_NEI_SOLICI (0x1<<1) // Mask bit for not forwarding …
61114 …LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V6_SERVER (0x1<<2) // Mask bit for not forwarding …
61116 …2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V4_CLIENT (0x1<<3) // Mask bit for not forwar…
61117 …IG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V4_CLIENT_SHIFT 3
61118 …LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V4_SERVER (0x1<<4) // Mask bit for not forwarding …
61120 …LLH_NCSI_BRB_DNTFWD_MASK_MAC6_K2_E5 (0x1<<5) // Mask bit for not forwarding …
61122 …LLH_NCSI_BRB_DNTFWD_MASK_MAC7_K2_E5 (0x1<<6) // Mask bit for not forwarding …
61124 …LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V6_CLI_E5 (0x1<<7) // Mask bit for not forwarding …
61127 …_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_MLD (0x1<<0) // Mask bit for not forwarding …
61129 …_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_NEI_SOLICI (0x1<<1) // Mask bit for not forwarding …
61131 …_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V6_SERVER (0x1<<2) // Mask bit for not forwarding …
61133 …_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V4_CLIENT (0x1<<3) // Mask bit for not forwar…
61134 …IG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V4_CLIENT_SHIFT 3
61135 …_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V4_SERVER (0x1<<4) // Mask bit for not forwarding …
61137 …_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V6_CLI_E5 (0x1<<7) // Mask bit for not forwarding …
61140 …SI_NTWK_MASK_IPV6_MLD (0x1<<0) // Mask bit for forwarding IPv6…
61142 …SI_NTWK_MASK_IPV6_NEI_SOLICI (0x1<<1) // Mask bit for forwarding IPv6…
61144 …SI_NTWK_MASK_DHCP_V6_SERVER (0x1<<2) // Mask bit for forwarding DHCP…
61146 …LH_NCSI_NTWK_MASK_DHCP_V4_CLIENT (0x1<<3) // Mask bit for forwarding…
61147 …IG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V4_CLIENT_SHIFT 3
61148 …SI_NTWK_MASK_DHCP_V4_SERVER (0x1<<4) // Mask bit for forwarding DHCP…
61150 …SI_NTWK_MASK_DHCP_V6_CLI_E5 (0x1<<7) // Mask bit for forwarding DHCP…
61152 …UL //Access:RW DataWidth:0x1 // This is a Global register. When this bit is enabled, instead…
61159 … 0x508b78UL //Access:RW DataWidth:0x1 // When this bit is set and there is…
61161 …nables credit sharing with one of the BTB TCs. 0: DORQ. 1: MNG. 2: Debug. 3: N/A. 4-11: BTB per TC.
61162 …nables credit sharing with one of the BTB TCs. 0: DORQ. 1: MNG. 2: Debug. 3: N/A. 4-11: BTB per TC.
61163 …t reisters. This enables credit sharing with one of the BTB TCs. 0: MNG. 1-8: BTB per TC. 9: B…
61164 … 0x508b8cUL //Access:RW DataWidth:0x1 // This bit inhibits sending mo…
61165 … 0x508b90UL //Access:RW DataWidth:0x1 // This bit inhibits sending mo…
61166 … 0x509000UL //Access:RW DataWidth:0x1 // When this bit is configured to 1,…
61167 … 0x509004UL //Access:RW DataWidth:0x1 // When this bit is configured to 1,…
61168 …o this register: Bit 0: resets the value of the free running counter. Bit 1: pauses the auto incre…
61182 … 0x509040UL //Access:RW DataWidth:0x1 // This bit enables time stamp …
61183 …cess:RW DataWidth:0x1 // This bit enables time stamp latching for one step PTP packets with R…
61184 …ss:RW DataWidth:0x1 // This bit enables correction field update for one step PTP packets with…
61192 …RW DataWidth:0x1 // This bit selects whether to use the MPA CRC calculation on one fully cont…
61193 …MAC addresses to be matched with for MAC-address-based classification. This register is also used…
61197 …ter is to be used for MAC-addresss based classification or protocol-based classification. Set thi…
61199 …-based classification mode: bit 0: compare the Ethertype; bit 1: compare the TCP source port; bit …
61203 …n. This filed allows using dynamic number of filters for every PPF. bits [4:3] are the port ID, bi…
61207 …cess:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of a…
61209 … 0x50d800UL //Access:RW DataWidth:0x6 // Almost-full threshold for BM…
61253 … // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en re…
61254 … // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en re…
61255 …bit should be set when initialization of all BRTB registers and memories is finished. BRTB will fi…
61279 … (0x1<<24) // Warning! Check this bit connection for E4 A…
61281 … (0x1<<25) // Warning! Check this bit connection for E4 A…
61283 …/ Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have…
61290 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
61292 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
61294 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
61296 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
61298 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
61300 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
61302 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
61304 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
61306 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
61308 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
61310 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
61312 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
61314 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
61316 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
61318 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
61320 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
61345 … (0x1<<24) // Warning! Check this bit connection for E4 A…
61347 … (0x1<<25) // Warning! Check this bit connection for E4 A…
61349 …/ Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have…
61378 … (0x1<<24) // Warning! Check this bit connection for E4 A…
61380 … (0x1<<25) // Warning! Check this bit connection for E4 A…
61382 …/ Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have…
61391 …O_ERROR (0x1<<3) // Input FIFO error…
61392 …MB_REG_INT_STS_1_WC0_INP_FIFO_ERROR_SHIFT 3
61419 … (0x1<<18) // Warning! Check this bit connection for E4 A…
61421 … (0x1<<19) // Warning! Check this bit connection for E4 A…
61423 … (0x1<<21) // Warning! Check this bit connection for E4 A…
61425 … (0x1<<22) // Warning! Check this bit connection for E4 A…
61427 … (0x1<<23) // Warning! Check this bit connection for E4 A…
61429 … (0x1<<24) // Warning! Check this bit connection for E4 A…
61431 … (0x1<<25) // Warning! Check this bit connection for E4 A…
61433 … (0x1<<26) // Warning! Check this bit connection for E4 A…
61435 … (0x1<<27) // Warning! Check this bit connection for E4 A…
61437 … (0x1<<28) // Warning! Check this bit connection for E4 A…
61439 … (0x1<<29) // Warning! Check this bit connection for E4 A…
61441 … (0x1<<30) // Warning! Check this bit connection for E4 A…
61443 … (0x1<<31) // Warning! Check this bit connection for E4 A…
61446 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
61448 … (0x1<<3) // This bit masks, when set, the Interrupt …
61449 …MB_REG_INT_MASK_1_WC0_INP_FIFO_ERROR_SHIFT 3
61450 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
61452 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
61454 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
61456 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
61458 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
61460 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
61462 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
61464 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
61466 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
61468 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
61470 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
61472 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
61474 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
61476 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
61478 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
61480 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
61482 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
61484 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
61486 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
61488 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
61490 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
61492 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
61494 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
61496 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
61498 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
61500 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
61505 …FIFO_ERROR (0x1<<3) // Input FIFO error…
61506 …MB_REG_INT_STS_WR_1_WC0_INP_FIFO_ERROR_SHIFT 3
61533 … (0x1<<18) // Warning! Check this bit connection for E4 A…
61535 … (0x1<<19) // Warning! Check this bit connection for E4 A…
61537 … (0x1<<21) // Warning! Check this bit connection for E4 A…
61539 … (0x1<<22) // Warning! Check this bit connection for E4 A…
61541 … (0x1<<23) // Warning! Check this bit connection for E4 A…
61543 … (0x1<<24) // Warning! Check this bit connection for E4 A…
61545 … (0x1<<25) // Warning! Check this bit connection for E4 A…
61547 … (0x1<<26) // Warning! Check this bit connection for E4 A…
61549 … (0x1<<27) // Warning! Check this bit connection for E4 A…
61551 … (0x1<<28) // Warning! Check this bit connection for E4 A…
61553 … (0x1<<29) // Warning! Check this bit connection for E4 A…
61555 … (0x1<<30) // Warning! Check this bit connection for E4 A…
61557 … (0x1<<31) // Warning! Check this bit connection for E4 A…
61562 …_FIFO_ERROR (0x1<<3) // Input FIFO error…
61563 …MB_REG_INT_STS_CLR_1_WC0_INP_FIFO_ERROR_SHIFT 3
61590 … (0x1<<18) // Warning! Check this bit connection for E4 A…
61592 … (0x1<<19) // Warning! Check this bit connection for E4 A…
61594 … (0x1<<21) // Warning! Check this bit connection for E4 A…
61596 … (0x1<<22) // Warning! Check this bit connection for E4 A…
61598 … (0x1<<23) // Warning! Check this bit connection for E4 A…
61600 … (0x1<<24) // Warning! Check this bit connection for E4 A…
61602 … (0x1<<25) // Warning! Check this bit connection for E4 A…
61604 … (0x1<<26) // Warning! Check this bit connection for E4 A…
61606 … (0x1<<27) // Warning! Check this bit connection for E4 A…
61608 … (0x1<<28) // Warning! Check this bit connection for E4 A…
61610 … (0x1<<29) // Warning! Check this bit connection for E4 A…
61612 … (0x1<<30) // Warning! Check this bit connection for E4 A…
61614 … (0x1<<31) // Warning! Check this bit connection for E4 A…
61617 … (0x1<<0) // Warning! Check this bit connection for E4 A…
61619 … (0x1<<1) // Warning! Check this bit connection for E4 A…
61621 … (0x1<<3) // Warning! Check this bit connec…
61622 …MB_REG_INT_STS_2_WC2_QUEUE_FIFO_ERROR_SHIFT 3
61623 … (0x1<<4) // Warning! Check this bit connection for E4 A…
61625 … (0x1<<5) // Warning! Check this bit connection for E4 A…
61627 … (0x1<<6) // Warning! Check this bit connection for E4 A…
61629 … (0x1<<7) // Warning! Check this bit connection for E4 A…
61631 … (0x1<<8) // Warning! Check this bit connection for E4 A…
61633 … (0x1<<9) // Warning! Check this bit connection for E4 A…
61635 … (0x1<<10) // Warning! Check this bit connection for E4 A…
61637 … (0x1<<11) // Warning! Check this bit connection for E4 A…
61639 … (0x1<<12) // Warning! Check this bit connection for E4 A…
61641 … (0x1<<13) // Warning! Check this bit connection for E4 A…
61643 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in wr…
61645 … (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in wri…
61647 … (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in wr…
61649 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in…
61651 … (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in…
61653 … (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in wr…
61655 … (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error…
61657 … (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error …
61659 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in…
61661 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in wr…
61663 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in writ…
61665 …ng! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for…
61667 …k this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for request…
61670 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
61672 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
61674 … (0x1<<3) // This bit masks, when set, the Interrupt …
61675 …MB_REG_INT_MASK_2_WC2_QUEUE_FIFO_ERROR_SHIFT 3
61676 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
61678 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
61680 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
61682 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
61684 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
61686 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
61688 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
61690 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
61692 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
61694 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
61696 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
61698 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
61700 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
61702 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
61704 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
61706 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
61708 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
61710 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
61712 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
61714 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
61716 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
61718 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
61720 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
61723 … (0x1<<0) // Warning! Check this bit connection for E4 A…
61725 … (0x1<<1) // Warning! Check this bit connection for E4 A…
61727 … (0x1<<3) // Warning! Check this bit connec…
61728 …MB_REG_INT_STS_WR_2_WC2_QUEUE_FIFO_ERROR_SHIFT 3
61729 … (0x1<<4) // Warning! Check this bit connection for E4 A…
61731 … (0x1<<5) // Warning! Check this bit connection for E4 A…
61733 … (0x1<<6) // Warning! Check this bit connection for E4 A…
61735 … (0x1<<7) // Warning! Check this bit connection for E4 A…
61737 … (0x1<<8) // Warning! Check this bit connection for E4 A…
61739 … (0x1<<9) // Warning! Check this bit connection for E4 A…
61741 … (0x1<<10) // Warning! Check this bit connection for E4 A…
61743 … (0x1<<11) // Warning! Check this bit connection for E4 A…
61745 … (0x1<<12) // Warning! Check this bit connection for E4 A…
61747 … (0x1<<13) // Warning! Check this bit connection for E4 A…
61749 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in wr…
61751 … (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in wri…
61753 … (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in wr…
61755 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in…
61757 … (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in…
61759 … (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in wr…
61761 … (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error…
61763 … (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error …
61765 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in…
61767 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in wr…
61769 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in writ…
61771 …ng! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for…
61773 …k this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for request…
61776 … (0x1<<0) // Warning! Check this bit connection for E4 A…
61778 … (0x1<<1) // Warning! Check this bit connection for E4 A…
61780 … (0x1<<3) // Warning! Check this bit connec…
61781 …MB_REG_INT_STS_CLR_2_WC2_QUEUE_FIFO_ERROR_SHIFT 3
61782 … (0x1<<4) // Warning! Check this bit connection for E4 A…
61784 … (0x1<<5) // Warning! Check this bit connection for E4 A…
61786 … (0x1<<6) // Warning! Check this bit connection for E4 A…
61788 … (0x1<<7) // Warning! Check this bit connection for E4 A…
61790 … (0x1<<8) // Warning! Check this bit connection for E4 A…
61792 … (0x1<<9) // Warning! Check this bit connection for E4 A…
61794 … (0x1<<10) // Warning! Check this bit connection for E4 A…
61796 … (0x1<<11) // Warning! Check this bit connection for E4 A…
61798 … (0x1<<12) // Warning! Check this bit connection for E4 A…
61800 … (0x1<<13) // Warning! Check this bit connection for E4 A…
61802 … (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in wr…
61804 … (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in wri…
61806 … (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in wr…
61808 … (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in…
61810 … (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in…
61812 … (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in wr…
61814 … (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error…
61816 … (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error …
61818 … (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in…
61820 … (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in wr…
61822 … (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in writ…
61824 …ng! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for…
61826 …k this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for request…
61833 …_FIFO_ERROR (0x1<<3) // Read packet clie…
61834 …MB_REG_INT_STS_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT 3
61892 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
61894 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
61896 … (0x1<<3) // This bit masks, when set, the Interrupt …
61897 …MB_REG_INT_MASK_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT 3
61898 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
61900 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
61902 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
61904 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
61906 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
61908 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
61910 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
61912 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
61914 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
61916 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
61918 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
61920 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
61922 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
61924 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
61926 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
61928 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
61930 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
61932 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
61934 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
61936 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
61938 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
61940 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
61942 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
61944 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
61946 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
61948 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
61950 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
61952 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
61959 …BLK_FIFO_ERROR (0x1<<3) // Read packet clie…
61960 …MB_REG_INT_STS_WR_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT 3
62022 …_BLK_FIFO_ERROR (0x1<<3) // Read packet clie…
62023 …MB_REG_INT_STS_CLR_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT 3
62087 …_FIFO_ERROR (0x1<<3) // Read SOP client …
62088 …MB_REG_INT_STS_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT 3
62136 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
62138 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
62140 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
62142 … (0x1<<3) // This bit masks, when set, the Interrupt …
62143 …MB_REG_INT_MASK_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT 3
62144 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
62146 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
62148 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
62150 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
62152 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
62154 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
62156 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
62158 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
62160 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
62162 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
62164 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
62166 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
62168 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
62170 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
62172 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
62174 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
62176 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
62178 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
62180 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
62182 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
62184 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
62186 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
62188 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
62197 …SCR_FIFO_ERROR (0x1<<3) // Read SOP client …
62198 …MB_REG_INT_STS_WR_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT 3
62252 …DSCR_FIFO_ERROR (0x1<<3) // Read SOP client …
62253 …MB_REG_INT_STS_CLR_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT 3
62305 …E_FIFO_ERROR (0x1<<3) // Read packet clie…
62306 …MB_REG_INT_STS_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT 3
62360 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
62362 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
62364 … (0x1<<3) // This bit masks, when set, the Interrupt …
62365 …MB_REG_INT_MASK_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT 3
62366 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
62368 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
62370 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
62372 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
62374 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
62376 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
62378 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
62380 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
62382 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
62384 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
62386 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
62388 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
62390 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
62392 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
62394 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
62396 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
62398 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
62400 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
62402 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
62404 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
62406 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
62408 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
62410 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
62412 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
62414 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
62416 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
62423 …SIDE_FIFO_ERROR (0x1<<3) // Read packet clie…
62424 …MB_REG_INT_STS_WR_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT 3
62482 …_SIDE_FIFO_ERROR (0x1<<3) // Read packet clie…
62483 …MB_REG_INT_STS_CLR_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT 3
62541 …TOCOL_ERROR (0x1<<3) // Read packet clie…
62542 …MB_REG_INT_STS_6_RC_PKT8_PROTOCOL_ERROR_SHIFT 3
62579 … (0x1<<23) // Warning! Check this bit connection for E4 A…
62581 … (0x1<<24) // Warning! Check this bit connection for E4 A…
62583 … (0x1<<25) // Warning! Check this bit connection for E4 A…
62585 … (0x1<<26) // Warning! Check this bit connection for E4 A…
62587 … (0x1<<27) // Warning! Check this bit connection for E4 A…
62589 … (0x1<<28) // Warning! Check this bit connection for E4 A…
62591 … (0x1<<29) // Warning! Check this bit connection for E4 A…
62593 … (0x1<<30) // Warning! Check this bit connection for E4 A…
62595 … (0x1<<31) // Warning! Check this bit connection for E4 A…
62598 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
62600 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
62602 … (0x1<<3) // This bit masks, when set, the Interrupt …
62603 …MB_REG_INT_MASK_6_RC_PKT8_PROTOCOL_ERROR_SHIFT 3
62604 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
62606 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
62608 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
62610 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
62612 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
62614 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
62616 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
62618 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
62620 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
62622 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
62624 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
62626 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
62628 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
62630 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
62632 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
62634 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
62636 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
62638 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
62640 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
62642 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
62644 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
62646 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
62648 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
62650 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
62652 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
62654 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
62656 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
62663 …PROTOCOL_ERROR (0x1<<3) // Read packet clie…
62664 …MB_REG_INT_STS_WR_6_RC_PKT8_PROTOCOL_ERROR_SHIFT 3
62701 … (0x1<<23) // Warning! Check this bit connection for E4 A…
62703 … (0x1<<24) // Warning! Check this bit connection for E4 A…
62705 … (0x1<<25) // Warning! Check this bit connection for E4 A…
62707 … (0x1<<26) // Warning! Check this bit connection for E4 A…
62709 … (0x1<<27) // Warning! Check this bit connection for E4 A…
62711 … (0x1<<28) // Warning! Check this bit connection for E4 A…
62713 … (0x1<<29) // Warning! Check this bit connection for E4 A…
62715 … (0x1<<30) // Warning! Check this bit connection for E4 A…
62717 … (0x1<<31) // Warning! Check this bit connection for E4 A…
62724 …_PROTOCOL_ERROR (0x1<<3) // Read packet clie…
62725 …MB_REG_INT_STS_CLR_6_RC_PKT8_PROTOCOL_ERROR_SHIFT 3
62762 … (0x1<<23) // Warning! Check this bit connection for E4 A…
62764 … (0x1<<24) // Warning! Check this bit connection for E4 A…
62766 … (0x1<<25) // Warning! Check this bit connection for E4 A…
62768 … (0x1<<26) // Warning! Check this bit connection for E4 A…
62770 … (0x1<<27) // Warning! Check this bit connection for E4 A…
62772 … (0x1<<28) // Warning! Check this bit connection for E4 A…
62774 … (0x1<<29) // Warning! Check this bit connection for E4 A…
62776 … (0x1<<30) // Warning! Check this bit connection for E4 A…
62778 … (0x1<<31) // Warning! Check this bit connection for E4 A…
62781 … (0x1<<0) // Warning! Check this bit connection for E4 A…
62783 … (0x1<<1) // Warning! Check this bit connection for E4 A…
62785 … (0x1<<2) // Warning! Check this bit connection for E4 A…
62787 …R (0x1<<3) // Warning! Check this bit connec…
62788 …MB_REG_INT_STS_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT 3
62789 … (0x1<<4) // Warning! Check this bit connection for E4 A…
62791 … (0x1<<5) // Warning! Check this bit connection for E4 A…
62793 … (0x1<<6) // Warning! Check this bit connection for E4 A…
62795 … (0x1<<7) // Warning! Check this bit connection for E4 A…
62797 … (0x1<<8) // Warning! Check this bit connection for E4 A…
62799 … (0x1<<9) // Warning! Check this bit connection for E4 A…
62801 … (0x1<<10) // Warning! Check this bit connection for E4 A…
62803 … (0x1<<11) // Warning! Check this bit connection for E4 A…
62805 … (0x1<<12) // Warning! Check this bit connection for E4 A…
62807 … (0x1<<13) // Warning! Check this bit connection for E4 A…
62809 … (0x1<<14) // Warning! Check this bit connection for E4 A…
62811 … (0x1<<15) // Warning! Check this bit connection for E4 A…
62813 … (0x1<<16) // Warning! Check this bit connection for E4 A…
62815 … (0x1<<17) // Warning! Check this bit connection for E4 A…
62817 … (0x1<<18) // Warning! Check this bit connection for E4 A…
62821 … (0x1<<20) // Warning! Check this bit connection for E4 A…
62823 … (0x1<<21) // Warning! Check this bit connection for E4 A…
62825 … (0x1<<22) // Warning! Check this bit connection for E4 A…
62827 … (0x1<<23) // Warning! Check this bit connection for E4 A…
62829 … (0x1<<24) // Warning! Check this bit connection for E4 A…
62831 … (0x1<<25) // Warning! Check this bit connection for E4 A…
62833 … (0x1<<26) // Warning! Check this bit connection for E4 A…
62835 … (0x1<<27) // Warning! Check this bit connection for E4 A…
62837 … (0x1<<28) // Warning! Check this bit connection for E4 A…
62839 … (0x1<<29) // Warning! Check this bit connection for E4 A…
62841 … (0x1<<30) // Warning! Check this bit connection for E4 A…
62843 … (0x1<<31) // Warning! Check this bit connection for E4 A…
62846 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
62848 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
62850 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
62852 … (0x1<<3) // This bit masks, when set, the Interrupt …
62853 …MB_REG_INT_MASK_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT 3
62854 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
62856 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
62858 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
62860 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
62862 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
62864 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
62866 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
62868 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
62870 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
62872 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
62874 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
62876 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
62878 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
62880 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
62882 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
62884 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
62886 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
62888 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
62890 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
62892 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
62894 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
62896 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
62898 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
62900 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
62902 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
62904 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
62906 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
62908 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
62911 … (0x1<<0) // Warning! Check this bit connection for E4 A…
62913 … (0x1<<1) // Warning! Check this bit connection for E4 A…
62915 … (0x1<<2) // Warning! Check this bit connection for E4 A…
62917 …RROR (0x1<<3) // Warning! Check this bit connec…
62918 …MB_REG_INT_STS_WR_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT 3
62919 … (0x1<<4) // Warning! Check this bit connection for E4 A…
62921 … (0x1<<5) // Warning! Check this bit connection for E4 A…
62923 … (0x1<<6) // Warning! Check this bit connection for E4 A…
62925 … (0x1<<7) // Warning! Check this bit connection for E4 A…
62927 … (0x1<<8) // Warning! Check this bit connection for E4 A…
62929 … (0x1<<9) // Warning! Check this bit connection for E4 A…
62931 … (0x1<<10) // Warning! Check this bit connection for E4 A…
62933 … (0x1<<11) // Warning! Check this bit connection for E4 A…
62935 … (0x1<<12) // Warning! Check this bit connection for E4 A…
62937 … (0x1<<13) // Warning! Check this bit connection for E4 A…
62939 … (0x1<<14) // Warning! Check this bit connection for E4 A…
62941 … (0x1<<15) // Warning! Check this bit connection for E4 A…
62943 … (0x1<<16) // Warning! Check this bit connection for E4 A…
62945 … (0x1<<17) // Warning! Check this bit connection for E4 A…
62947 … (0x1<<18) // Warning! Check this bit connection for E4 A…
62951 … (0x1<<20) // Warning! Check this bit connection for E4 A…
62953 … (0x1<<21) // Warning! Check this bit connection for E4 A…
62955 … (0x1<<22) // Warning! Check this bit connection for E4 A…
62957 … (0x1<<23) // Warning! Check this bit connection for E4 A…
62959 … (0x1<<24) // Warning! Check this bit connection for E4 A…
62961 … (0x1<<25) // Warning! Check this bit connection for E4 A…
62963 … (0x1<<26) // Warning! Check this bit connection for E4 A…
62965 … (0x1<<27) // Warning! Check this bit connection for E4 A…
62967 … (0x1<<28) // Warning! Check this bit connection for E4 A…
62969 … (0x1<<29) // Warning! Check this bit connection for E4 A…
62971 … (0x1<<30) // Warning! Check this bit connection for E4 A…
62973 … (0x1<<31) // Warning! Check this bit connection for E4 A…
62976 … (0x1<<0) // Warning! Check this bit connection for E4 A…
62978 … (0x1<<1) // Warning! Check this bit connection for E4 A…
62980 … (0x1<<2) // Warning! Check this bit connection for E4 A…
62982 …ERROR (0x1<<3) // Warning! Check this bit connec…
62983 …MB_REG_INT_STS_CLR_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT 3
62984 … (0x1<<4) // Warning! Check this bit connection for E4 A…
62986 … (0x1<<5) // Warning! Check this bit connection for E4 A…
62988 … (0x1<<6) // Warning! Check this bit connection for E4 A…
62990 … (0x1<<7) // Warning! Check this bit connection for E4 A…
62992 … (0x1<<8) // Warning! Check this bit connection for E4 A…
62994 … (0x1<<9) // Warning! Check this bit connection for E4 A…
62996 … (0x1<<10) // Warning! Check this bit connection for E4 A…
62998 … (0x1<<11) // Warning! Check this bit connection for E4 A…
63000 … (0x1<<12) // Warning! Check this bit connection for E4 A…
63002 … (0x1<<13) // Warning! Check this bit connection for E4 A…
63004 … (0x1<<14) // Warning! Check this bit connection for E4 A…
63006 … (0x1<<15) // Warning! Check this bit connection for E4 A…
63008 … (0x1<<16) // Warning! Check this bit connection for E4 A…
63010 … (0x1<<17) // Warning! Check this bit connection for E4 A…
63012 … (0x1<<18) // Warning! Check this bit connection for E4 A…
63016 … (0x1<<20) // Warning! Check this bit connection for E4 A…
63018 … (0x1<<21) // Warning! Check this bit connection for E4 A…
63020 … (0x1<<22) // Warning! Check this bit connection for E4 A…
63022 … (0x1<<23) // Warning! Check this bit connection for E4 A…
63024 … (0x1<<24) // Warning! Check this bit connection for E4 A…
63026 … (0x1<<25) // Warning! Check this bit connection for E4 A…
63028 … (0x1<<26) // Warning! Check this bit connection for E4 A…
63030 … (0x1<<27) // Warning! Check this bit connection for E4 A…
63032 … (0x1<<28) // Warning! Check this bit connection for E4 A…
63034 … (0x1<<29) // Warning! Check this bit connection for E4 A…
63036 … (0x1<<30) // Warning! Check this bit connection for E4 A…
63038 … (0x1<<31) // Warning! Check this bit connection for E4 A…
63041 … (0x1<<0) // Warning! Check this bit connection for E4 A…
63043 … (0x1<<1) // Warning! Check this bit connection for E4 A…
63045 … (0x1<<2) // Warning! Check this bit connection for E4 A…
63047 … (0x1<<3) // Warning! Check this bit connec…
63048 …MB_REG_INT_STS_8_WC6_BB_PA_CNT_ERROR_SHIFT 3
63049 … (0x1<<4) // Warning! Check this bit connection for E4 A…
63051 … (0x1<<5) // Warning! Check this bit connection for E4 A…
63053 … (0x1<<6) // Warning! Check this bit connection for E4 A…
63055 … (0x1<<7) // Warning! Check this bit connection for E4 A…
63057 … (0x1<<8) // Warning! Check this bit connection for E4 A…
63059 … (0x1<<9) // Warning! Check this bit connection for E4 A…
63061 … (0x1<<10) // Warning! Check this bit connection for E4 A…
63063 … (0x1<<11) // Warning! Check this bit connection for E4 A…
63065 … (0x1<<12) // Warning! Check this bit connection for E4 A…
63067 … (0x1<<13) // Warning! Check this bit connection for E4 A…
63069 … (0x1<<14) // Warning! Check this bit connection for E4 A…
63071 … (0x1<<15) // Warning! Check this bit connection for E4 A…
63073 … (0x1<<16) // Warning! Check this bit connection for E4 A…
63075 … (0x1<<17) // Warning! Check this bit connection for E4 A…
63077 … (0x1<<18) // Warning! Check this bit connection for E4 A…
63079 … (0x1<<19) // Warning! Check this bit connection for E4 A…
63081 … (0x1<<20) // Warning! Check this bit connection for E4 A…
63083 … (0x1<<21) // Warning! Check this bit connection for E4 A…
63085 … (0x1<<22) // Warning! Check this bit connection for E4 A…
63087 … (0x1<<23) // Warning! Check this bit connection for E4 A…
63089 … (0x1<<24) // Warning! Check this bit connection for E4 A…
63091 … (0x1<<25) // Warning! Check this bit connection for E4 A…
63093 … (0x1<<26) // Warning! Check this bit connection for E4 A…
63095 … (0x1<<27) // Warning! Check this bit connection for E4 A…
63097 … (0x1<<28) // Warning! Check this bit connection for E4 A…
63099 … (0x1<<29) // Warning! Check this bit connection for E4 A…
63101 … (0x1<<30) // Warning! Check this bit connection for E4 A…
63103 … (0x1<<31) // Warning! Check this bit connection for E4 A…
63106 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
63108 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
63110 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
63112 … (0x1<<3) // This bit masks, when set, the Interrupt …
63113 …MB_REG_INT_MASK_8_WC6_BB_PA_CNT_ERROR_SHIFT 3
63114 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
63116 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
63118 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
63120 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
63122 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
63124 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
63126 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
63128 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
63130 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
63132 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
63134 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
63136 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
63138 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
63140 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
63142 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
63144 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
63146 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
63148 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
63150 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
63152 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
63154 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
63156 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
63158 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
63160 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
63162 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
63164 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
63166 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
63168 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
63171 … (0x1<<0) // Warning! Check this bit connection for E4 A…
63173 … (0x1<<1) // Warning! Check this bit connection for E4 A…
63175 … (0x1<<2) // Warning! Check this bit connection for E4 A…
63177 … (0x1<<3) // Warning! Check this bit connec…
63178 …MB_REG_INT_STS_WR_8_WC6_BB_PA_CNT_ERROR_SHIFT 3
63179 … (0x1<<4) // Warning! Check this bit connection for E4 A…
63181 … (0x1<<5) // Warning! Check this bit connection for E4 A…
63183 … (0x1<<6) // Warning! Check this bit connection for E4 A…
63185 … (0x1<<7) // Warning! Check this bit connection for E4 A…
63187 … (0x1<<8) // Warning! Check this bit connection for E4 A…
63189 … (0x1<<9) // Warning! Check this bit connection for E4 A…
63191 … (0x1<<10) // Warning! Check this bit connection for E4 A…
63193 … (0x1<<11) // Warning! Check this bit connection for E4 A…
63195 … (0x1<<12) // Warning! Check this bit connection for E4 A…
63197 … (0x1<<13) // Warning! Check this bit connection for E4 A…
63199 … (0x1<<14) // Warning! Check this bit connection for E4 A…
63201 … (0x1<<15) // Warning! Check this bit connection for E4 A…
63203 … (0x1<<16) // Warning! Check this bit connection for E4 A…
63205 … (0x1<<17) // Warning! Check this bit connection for E4 A…
63207 … (0x1<<18) // Warning! Check this bit connection for E4 A…
63209 … (0x1<<19) // Warning! Check this bit connection for E4 A…
63211 … (0x1<<20) // Warning! Check this bit connection for E4 A…
63213 … (0x1<<21) // Warning! Check this bit connection for E4 A…
63215 … (0x1<<22) // Warning! Check this bit connection for E4 A…
63217 … (0x1<<23) // Warning! Check this bit connection for E4 A…
63219 … (0x1<<24) // Warning! Check this bit connection for E4 A…
63221 … (0x1<<25) // Warning! Check this bit connection for E4 A…
63223 … (0x1<<26) // Warning! Check this bit connection for E4 A…
63225 … (0x1<<27) // Warning! Check this bit connection for E4 A…
63227 … (0x1<<28) // Warning! Check this bit connection for E4 A…
63229 … (0x1<<29) // Warning! Check this bit connection for E4 A…
63231 … (0x1<<30) // Warning! Check this bit connection for E4 A…
63233 … (0x1<<31) // Warning! Check this bit connection for E4 A…
63236 … (0x1<<0) // Warning! Check this bit connection for E4 A…
63238 … (0x1<<1) // Warning! Check this bit connection for E4 A…
63240 … (0x1<<2) // Warning! Check this bit connection for E4 A…
63242 … (0x1<<3) // Warning! Check this bit connec…
63243 …MB_REG_INT_STS_CLR_8_WC6_BB_PA_CNT_ERROR_SHIFT 3
63244 … (0x1<<4) // Warning! Check this bit connection for E4 A…
63246 … (0x1<<5) // Warning! Check this bit connection for E4 A…
63248 … (0x1<<6) // Warning! Check this bit connection for E4 A…
63250 … (0x1<<7) // Warning! Check this bit connection for E4 A…
63252 … (0x1<<8) // Warning! Check this bit connection for E4 A…
63254 … (0x1<<9) // Warning! Check this bit connection for E4 A…
63256 … (0x1<<10) // Warning! Check this bit connection for E4 A…
63258 … (0x1<<11) // Warning! Check this bit connection for E4 A…
63260 … (0x1<<12) // Warning! Check this bit connection for E4 A…
63262 … (0x1<<13) // Warning! Check this bit connection for E4 A…
63264 … (0x1<<14) // Warning! Check this bit connection for E4 A…
63266 … (0x1<<15) // Warning! Check this bit connection for E4 A…
63268 … (0x1<<16) // Warning! Check this bit connection for E4 A…
63270 … (0x1<<17) // Warning! Check this bit connection for E4 A…
63272 … (0x1<<18) // Warning! Check this bit connection for E4 A…
63274 … (0x1<<19) // Warning! Check this bit connection for E4 A…
63276 … (0x1<<20) // Warning! Check this bit connection for E4 A…
63278 … (0x1<<21) // Warning! Check this bit connection for E4 A…
63280 … (0x1<<22) // Warning! Check this bit connection for E4 A…
63282 … (0x1<<23) // Warning! Check this bit connection for E4 A…
63284 … (0x1<<24) // Warning! Check this bit connection for E4 A…
63286 … (0x1<<25) // Warning! Check this bit connection for E4 A…
63288 … (0x1<<26) // Warning! Check this bit connection for E4 A…
63290 … (0x1<<27) // Warning! Check this bit connection for E4 A…
63292 … (0x1<<28) // Warning! Check this bit connection for E4 A…
63294 … (0x1<<29) // Warning! Check this bit connection for E4 A…
63296 … (0x1<<30) // Warning! Check this bit connection for E4 A…
63298 … (0x1<<31) // Warning! Check this bit connection for E4 A…
63301 … (0x1<<0) // Warning! Check this bit connection for E4 A…
63303 … (0x1<<1) // Warning! Check this bit connection for E4 A…
63305 … (0x1<<2) // Warning! Check this bit connection for E4 A…
63307 … (0x1<<3) // Warning! Check this bit connec…
63308 …MB_REG_INT_STS_9_WC9_STRT_FIFO_ERROR_SHIFT 3
63309 … (0x1<<4) // Warning! Check this bit connection for E4 A…
63311 … (0x1<<5) // Warning! Check this bit connection for E4 A…
63313 … (0x1<<6) // Warning! Check this bit connection for E4 A…
63315 … (0x1<<7) // Warning! Check this bit connection for E4 A…
63317 … (0x1<<8) // Warning! Check this bit connection for E4 A…
63319 … (0x1<<9) // Warning! Check this bit connection for E4 A…
63321 … (0x1<<10) // Warning! Check this bit connection for E4 A…
63376 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
63378 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
63380 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
63382 … (0x1<<3) // This bit masks, when set, the Interrupt …
63383 …MB_REG_INT_MASK_9_WC9_STRT_FIFO_ERROR_SHIFT 3
63384 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
63386 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
63388 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
63390 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
63392 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
63394 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
63396 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
63398 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
63400 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
63402 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
63404 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
63406 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
63408 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
63410 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
63412 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
63414 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
63416 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
63418 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
63420 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
63422 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
63424 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
63426 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
63428 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
63430 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
63432 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
63434 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
63436 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
63438 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
63440 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
63442 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
63444 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
63446 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
63448 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
63451 … (0x1<<0) // Warning! Check this bit connection for E4 A…
63453 … (0x1<<1) // Warning! Check this bit connection for E4 A…
63455 … (0x1<<2) // Warning! Check this bit connection for E4 A…
63457 … (0x1<<3) // Warning! Check this bit connec…
63458 …MB_REG_INT_STS_WR_9_WC9_STRT_FIFO_ERROR_SHIFT 3
63459 … (0x1<<4) // Warning! Check this bit connection for E4 A…
63461 … (0x1<<5) // Warning! Check this bit connection for E4 A…
63463 … (0x1<<6) // Warning! Check this bit connection for E4 A…
63465 … (0x1<<7) // Warning! Check this bit connection for E4 A…
63467 … (0x1<<8) // Warning! Check this bit connection for E4 A…
63469 … (0x1<<9) // Warning! Check this bit connection for E4 A…
63471 … (0x1<<10) // Warning! Check this bit connection for E4 A…
63526 … (0x1<<0) // Warning! Check this bit connection for E4 A…
63528 … (0x1<<1) // Warning! Check this bit connection for E4 A…
63530 … (0x1<<2) // Warning! Check this bit connection for E4 A…
63532 … (0x1<<3) // Warning! Check this bit connec…
63533 …MB_REG_INT_STS_CLR_9_WC9_STRT_FIFO_ERROR_SHIFT 3
63534 … (0x1<<4) // Warning! Check this bit connection for E4 A…
63536 … (0x1<<5) // Warning! Check this bit connection for E4 A…
63538 … (0x1<<6) // Warning! Check this bit connection for E4 A…
63540 … (0x1<<7) // Warning! Check this bit connection for E4 A…
63542 … (0x1<<8) // Warning! Check this bit connection for E4 A…
63544 … (0x1<<9) // Warning! Check this bit connection for E4 A…
63546 … (0x1<<10) // Warning! Check this bit connection for E4 A…
63612 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
63614 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
63616 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
63618 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
63620 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
63645 … (0x1<<6) // Warning! Check this bit connection for E4 A…
63647 … (0x1<<7) // Warning! Check this bit connection for E4 A…
63656 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
63658 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
63660 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
63662 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
63664 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
63667 … (0x1<<6) // Warning! Check this bit connection for E4 A…
63669 … (0x1<<7) // Warning! Check this bit connection for E4 A…
63678 … (0x1<<6) // Warning! Check this bit connection for E4 A…
63680 … (0x1<<7) // Warning! Check this bit connection for E4 A…
63689 … (0x1<<0) // This bit masks, when set, the Parity bit: BM…
63691 … (0x1<<1) // This bit masks, when set, the Parity bit: BM…
63693 … (0x1<<2) // This bit masks, when set, the Parity bit: BM…
63695 … (0x1<<3) // This bit masks, when set, the Parity bi…
63696 …MB_REG_PRTY_MASK_LL_BANK3_MEM_PRTY_SHIFT 3
63697 … (0x1<<4) // This bit masks, when set, the Parity bit: BM…
63700 … (0x1<<0) // This bit masks, when set, the Parity bit: BM…
63702 … (0x1<<1) // This bit masks, when set, the Parity bit: BM…
63704 … (0x1<<2) // This bit masks, when set, the Parity bit: BM…
63706 … (0x1<<3) // This bit masks, when set, the Parity bi…
63707 …MB_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_SHIFT 3
63708 … (0x1<<4) // This bit masks, when set, the Parity bit: BM…
63710 … (0x1<<5) // This bit masks, when set, the Parity bit: BM…
63712 … (0x1<<6) // This bit masks, when set, the Parity bit: BM…
63714 … (0x1<<7) // This bit masks, when set, the Parity bit: BM…
63716 … (0x1<<8) // This bit masks, when set, the Parity bit: BM…
63718 … (0x1<<9) // This bit masks, when set, the Parity bit: BM…
63720 … (0x1<<10) // This bit masks, when set, the Parity bit: BM…
63722 … (0x1<<11) // This bit masks, when set, the Parity bit: BM…
63724 … (0x1<<12) // This bit masks, when set, the Parity bit: BM…
63726 … (0x1<<13) // This bit masks, when set, the Parity bit: BM…
63728 … (0x1<<14) // This bit masks, when set, the Parity bit: BM…
63730 … (0x1<<15) // This bit masks, when set, the Parity bit: BM…
63732 … (0x1<<16) // This bit masks, when set, the Parity bit: BM…
63734 … (0x1<<17) // This bit masks, when set, the Parity bit: BM…
63736 … (0x1<<18) // This bit masks, when set, the Parity bit: BM…
63738 … (0x1<<19) // This bit masks, when set, the Parity bit: BM…
63740 … (0x1<<20) // This bit masks, when set, the Parity bit: BM…
63742 … (0x1<<21) // This bit masks, when set, the Parity bit: BM…
63744 … (0x1<<22) // This bit masks, when set, the Parity bit: BM…
63746 … (0x1<<23) // This bit masks, when set, the Parity bit: BM…
63748 … (0x1<<24) // This bit masks, when set, the Parity bit: BM…
63750 … (0x1<<25) // This bit masks, when set, the Parity bit: BM…
63752 … (0x1<<26) // This bit masks, when set, the Parity bit: BM…
63754 … (0x1<<27) // This bit masks, when set, the Parity bit: BM…
63756 … (0x1<<28) // This bit masks, when set, the Parity bit: BM…
63758 … (0x1<<29) // This bit masks, when set, the Parity bit: BM…
63760 … (0x1<<30) // This bit masks, when set, the Parity bit: BM…
63762 … (0x1<<16) // This bit masks, when set, the Parity bit: BM…
63764 … (0x1<<17) // This bit masks, when set, the Parity bit: BM…
63766 … (0x1<<18) // This bit masks, when set, the Parity bit: BM…
63768 … (0x1<<19) // This bit masks, when set, the Parity bit: BM…
63770 … (0x1<<20) // This bit masks, when set, the Parity bit: BM…
63772 … (0x1<<21) // This bit masks, when set, the Parity bit: BM…
63774 … (0x1<<22) // This bit masks, when set, the Parity bit: BM…
63776 … (0x1<<23) // This bit masks, when set, the Parity bit: BM…
63778 … (0x1<<24) // This bit masks, when set, the Parity bit: BM…
63780 … (0x1<<25) // This bit masks, when set, the Parity bit: BM…
63782 … (0x1<<26) // This bit masks, when set, the Parity bit: BM…
63784 … (0x1<<27) // This bit masks, when set, the Parity bit: BM…
63786 … (0x1<<28) // This bit masks, when set, the Parity bit: BM…
63788 … (0x1<<29) // This bit masks, when set, the Parity bit: BM…
63790 … (0x1<<30) // This bit masks, when set, the Parity bit: BM…
63793 … (0x1<<11) // This bit masks, when set, the Parity bit: BM…
63795 … (0x1<<0) // This bit masks, when set, the Parity bit: BM…
63797 … (0x1<<12) // This bit masks, when set, the Parity bit: BM…
63799 … (0x1<<1) // This bit masks, when set, the Parity bit: BM…
63801 … (0x1<<2) // This bit masks, when set, the Parity bit: BM…
63803 … (0x1<<3) // This bit masks, when set, the Parity bi…
63804 …MB_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY_E5_SHIFT 3
63805 … (0x1<<4) // This bit masks, when set, the Parity bit: BM…
63807 … (0x1<<5) // This bit masks, when set, the Parity bit: BM…
63809 … (0x1<<6) // This bit masks, when set, the Parity bit: BM…
63811 … (0x1<<7) // This bit masks, when set, the Parity bit: BM…
63813 … (0x1<<8) // This bit masks, when set, the Parity bit: BM…
63815 … (0x1<<9) // This bit masks, when set, the Parity bit: BM…
63817 … (0x1<<10) // This bit masks, when set, the Parity bit: BM…
63819 … (0x1<<11) // This bit masks, when set, the Parity bit: BM…
63821 … (0x1<<12) // This bit masks, when set, the Parity bit: BM…
63823 … (0x1<<13) // This bit masks, when set, the Parity bit: BM…
63825 … (0x1<<14) // This bit masks, when set, the Parity bit: BM…
63827 … (0x1<<0) // This bit masks, when set, the Parity bit: BM…
63829 … (0x1<<15) // This bit masks, when set, the Parity bit: BM…
63831 … (0x1<<1) // This bit masks, when set, the Parity bit: BM…
63833 … (0x1<<16) // This bit masks, when set, the Parity bit: BM…
63835 … (0x1<<17) // This bit masks, when set, the Parity bit: BM…
63837 … (0x1<<18) // This bit masks, when set, the Parity bit: BM…
63839 … (0x1<<19) // This bit masks, when set, the Parity bit: BM…
63841 … (0x1<<20) // This bit masks, when set, the Parity bit: BM…
63843 … (0x1<<13) // This bit masks, when set, the Parity bit: BM…
63845 … (0x1<<21) // This bit masks, when set, the Parity bit: BM…
63847 … (0x1<<14) // This bit masks, when set, the Parity bit: BM…
63849 … (0x1<<22) // This bit masks, when set, the Parity bit: BM…
63851 … (0x1<<2) // This bit masks, when set, the Parity bit: BM…
63853 … (0x1<<3) // This bit masks, when set, the Parity bi…
63854 …MB_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_BB_K2_SHIFT 3
63855 … (0x1<<4) // This bit masks, when set, the Parity bit: BM…
63857 … (0x1<<5) // This bit masks, when set, the Parity bit: BM…
63859 … (0x1<<6) // This bit masks, when set, the Parity bit: BM…
63861 … (0x1<<7) // This bit masks, when set, the Parity bit: BM…
63863 … (0x1<<8) // This bit masks, when set, the Parity bit: BM…
63865 … (0x1<<9) // This bit masks, when set, the Parity bit: BM…
63867 … (0x1<<10) // This bit masks, when set, the Parity bit: BM…
63869 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63870 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63871 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63872 …OR[3].i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an e…
63873 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63874 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63875 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63876 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63877 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63878 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63879 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63880 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63881 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63882 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63883 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63884 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
63892 … (0x1<<3) // Enable ECC for memory ecc instance bmb.BB_BANK_…
63893 …MB_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN_SHIFT 3
63925 … (0x1<<3) // Set parity only for memory ecc instance bmb.BB_BA…
63926 …MB_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY_SHIFT 3
63958 … (0x1<<3) // Record if a correctable error occurred on memory ecc instanc…
63959 …MB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT_SHIFT 3
63985 … to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_…
63986 …04UL //Access:RW DataWidth:0xa // Number of valid bytes in header in 16-bytes resolution. Aft…
63994 … 0x540844UL //Access:RW DataWidth:0x3 // There is bit for each PACKET read client. When bit …
63995 … shared and headroom areas. This register should be equal to total_mac_size - SUM(tc_guarantied) R…
64009 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64010 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64011 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64012 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64013 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64014 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64015 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64016 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64017 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64018 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64019 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64020 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64021 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64022 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64023 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64024 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64025 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64026 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64027 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64028 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64029 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64030 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64031 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64032 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64033 …bit for each PACKET read client. Bit 0 suits to client 0 and so on. If bit is set then packet will…
64035 …ty then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s…
64037 …ty then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s…
64039 …ty then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s…
64041 …ty then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s…
64043 …ty then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s…
64045 …ty then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s…
64047 …ty then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s…
64049 …ty then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s…
64051 …riority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest
64053 …riority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest
64055 …cess:RW DataWidth:0xa // There is bit for each PACKET write client. Bit 0 suits to client 0 a…
64056 …cess:RW DataWidth:0xa // There is bit for each PACKET write client. Bit 0 suits to client 0 a…
64057 …riority for SOP read client to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/…
64058 …quest of write client group to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/…
64059 …ple clients of identical priority is supported. Possible values are 1-3. Priority 3 is highest::s/…
64080 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
64081 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
64082 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
64083 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
64089 …bit per each read client interface: TBD. When bit is set then appropriate interface is enabled. Wh…
64091 … (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate int…
64093 …bit per write client interface: B0 - NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - …
64096 …bit per each read client interface: TBD. When bit is set then appropriate interface is enabled. Wh…
64098 … (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate int…
64100 …bit for all pause interfaces per each MAC port. When bit is set then pause interface is enabled. W…
64102 …bit for packet avalable interfaces. When bit is set then packet avalable interface is enabled. Whe…
64104 …bit for power management interfaces. When bit is set then power management interface is enabled. …
64106 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64107 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64108 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64109 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64110 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64111 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64112 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64113 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64114 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64115 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64128 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
64129 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
64130 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
64131 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
64132 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
64133 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
64134 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
64135 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
64136 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
64137 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
64138 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
64139 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
64140 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
64141 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
64142 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
64143 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
64144 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
64145 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
64146 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
64147 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
64148 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64149 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64150 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64151 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64152 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64153 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64154 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64155 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64156 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64157 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
64158 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
64159 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
64160 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
64252 …ter for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - qu…
64254 …s register for each erad packet client interface: TBD. Message spelling (MSB->LSB): rest_size_erro…
64257 …acket client interface: TBD. Message spelling (MSB->LSB): opaque[1:0]; rls_to_do[15:0]; queue_numb…
64260 … strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
64262 … strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
64264 … strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
64266 … strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
64268 … strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
64270 … strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
64272 … strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
64274 … strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
64276 … strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
64278 … strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
64280 …Access:RW DataWidth:0xc // Link list dual port memory that contains per-block descriptor::s/B…
64284 … DataWidth:0x1 // When this bit is enabled, then BMC is connected and BMB WC9/RC2 is connected…
64285 … 0x560000UL //Access:RW DataWidth:0x1 // Initiate the ATC array - reset all the valid …
64287 …taWidth:0x20 // Logging register for reuse miss on transpend entry [31:0] - TID of the problemat…
64288 …taWidth:0x1c // Logging register for reuse miss on transpend entry [27:0] - ATC page index of th…
64289 …gister for reuse miss on transpend entry [11:0] - Reuse count of the problematic lookuprequest [23…
64290 …ster for the case of invalidation halt (lkpres of invalidated range) [31:0] - TID of the problemat…
64291 …ster for the case of invalidation halt (lkpres of invalidated range) [27:0] - ATC page index of th…
64292 …ster for the case of invalidation halt (lkpres of invalidated range) [11:0] - Reuse count of the p…
64294 …s of the PXP read requests issued by the PTU logic. [0:8] - ST index; [10:9] - ST hint; [11] - ST …
64301 … 0x560078UL //Access:RW DataWidth:0x20 // TID of the invalidated range - register per PF.
64302 … 0x56007cUL //Access:RW DataWidth:0x20 // Bit mask for the invali…
64303 …Bit per PF.Indicates that the data in inv_tid and inv_tid_mask is valid and invalidation should ta…
64304 … 0x560084UL //Access:RW DataWidth:0x1 // Bit per PF. Indicates that the marked invalidation i…
64305 … 0x560088UL //Access:RW DataWidth:0x1 // Bit per PF. If set, the…
64306 … 0x56008cUL //Access:RW DataWidth:0x1 // When set - the block will halt …
64307 … 0x560090UL //Access:RW DataWidth:0x3 // Max credits of the PBF->PXP interface.
64308 … 0x560094UL //Access:RW DataWidth:0x3 // Max credits of the PRM->PXP interface.
64309 … 0x560098UL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64310 … 0x56009cUL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64311 … 0x5600a0UL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64320 …00c4UL //Access:RW DataWidth:0x1 // Replacement mode for the ATC. If de-asserted then low pri…
64326 … 0x5600dcUL //Access:RW DataWidth:0x1 // Chicken bit for the atc otb ove…
64328 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
64329 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
64330 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
64331 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
64339 … (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
64343 …MPTY_CNT (0x1<<3) // RCPL arrives to …
64344 …TU_REG_INT_STS_ATC_RCPL_TO_EMPTY_CNT_SHIFT 3
64354 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
64356 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
64358 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
64360 … (0x1<<3) // This bit masks, when set, the Interrupt …
64361 …TU_REG_INT_MASK_ATC_RCPL_TO_EMPTY_CNT_SHIFT 3
64362 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
64364 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
64366 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
64368 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
64373 … (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
64377 …O_EMPTY_CNT (0x1<<3) // RCPL arrives to …
64378 …TU_REG_INT_STS_WR_ATC_RCPL_TO_EMPTY_CNT_SHIFT 3
64390 … (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
64394 …TO_EMPTY_CNT (0x1<<3) // RCPL arrives to …
64395 …TU_REG_INT_STS_CLR_ATC_RCPL_TO_EMPTY_CNT_SHIFT 3
64405 … (0x1<<0) // This bit masks, when set, the Parity bit: PT…
64407 … (0x1<<1) // This bit masks, when set, the Parity bit: PT…
64409 … (0x1<<3) // This bit masks, when set, the Parity bi…
64410 …TU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT 3
64411 … (0x1<<2) // This bit masks, when set, the Parity bit: PT…
64413 … (0x1<<4) // This bit masks, when set, the Parity bit: PT…
64415 … (0x1<<3) // This bit masks, when set, the Parity bi…
64416 …TU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_E5_SHIFT 3
64417 … (0x1<<5) // This bit masks, when set, the Parity bit: PT…
64419 … (0x1<<4) // This bit masks, when set, the Parity bit: PT…
64421 … (0x1<<6) // This bit masks, when set, the Parity bit: PT…
64423 … (0x1<<5) // This bit masks, when set, the Parity bit: PT…
64425 … (0x1<<7) // This bit masks, when set, the Parity bit: PT…
64427 … (0x1<<6) // This bit masks, when set, the Parity bit: PT…
64429 … (0x1<<17) // This bit masks, when set, the Parity bit: PT…
64431 … (0x1<<7) // This bit masks, when set, the Parity bit: PT…
64433 … (0x1<<8) // This bit masks, when set, the Parity bit: PT…
64435 … (0x1<<12) // This bit masks, when set, the Parity bit: PT…
64437 … (0x1<<9) // This bit masks, when set, the Parity bit: PT…
64439 … (0x1<<2) // This bit masks, when set, the Parity bit: PT…
64441 … (0x1<<10) // This bit masks, when set, the Parity bit: PT…
64443 … (0x1<<15) // This bit masks, when set, the Parity bit: PT…
64445 … (0x1<<11) // This bit masks, when set, the Parity bit: PT…
64447 … (0x1<<14) // This bit masks, when set, the Parity bit: PT…
64449 … (0x1<<12) // This bit masks, when set, the Parity bit: PT…
64451 … (0x1<<16) // This bit masks, when set, the Parity bit: PT…
64453 … (0x1<<13) // This bit masks, when set, the Parity bit: PT…
64455 … (0x1<<13) // This bit masks, when set, the Parity bit: PT…
64457 … (0x1<<14) // This bit masks, when set, the Parity bit: PT…
64459 … (0x1<<9) // This bit masks, when set, the Parity bit: PT…
64461 … (0x1<<15) // This bit masks, when set, the Parity bit: PT…
64463 … (0x1<<11) // This bit masks, when set, the Parity bit: PT…
64465 … (0x1<<16) // This bit masks, when set, the Parity bit: PT…
64467 … (0x1<<0) // This bit masks, when set, the Parity bit: PT…
64469 … (0x1<<1) // This bit masks, when set, the Parity bit: PT…
64471 … (0x1<<10) // This bit masks, when set, the Parity bit: PT…
64477 …00UL //Access:RW DataWidth:0x2 // Defines the number of sets - 3 - 512 ;2- 256; 1- 128; 0- 64.
64479 …ne FIFO full bit; RCPL FIFO full bit; TCPL FIFO full bit; IREQ full bit; PLKP FIFO full bit; MLKP …
64480 …IFO empty bit; RCPL FIFO empty bit; TCPL FIFO empty bit; IREQ empty bit; PLKP FIFO empty bit; MLKP…
64481 … 0x560410UL //Access:RW DataWidth:0x1 // WaitIfMiss configuration bit.
64482 … 0x560414UL //Access:RW DataWidth:0x1 // WaitTransPending cofiguration bit.
64483 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64484 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64485 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64486 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64487 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64488 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64489 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64490 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64491 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64492 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64493 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64494 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
64509 … 0x560480UL //Access:RW DataWidth:0x1 // CheckTags configuration bit - when set the avail…
64510 … 0x560484UL //Access:RW DataWidth:0x8 // TAG threshold - for the checkTags fe…
64522 … 0x5604b4UL //Access:RW DataWidth:0x1 // Disable bit for the scrubbing e…
64523 … 0x5604b8UL //Access:RC DataWidth:0x20 // Number of hits for Main-lookups in the ATC.
64525 … 0x5604c0UL //Access:RC DataWidth:0x20 // Number of treqs issued due to pre-lookup.
64569 …rted request [1]; Completer abort/completion timeout [2]; Both R & W bits are reset [3]; Other [4].
64570 …rted request [1]; Completer abort/completion timeout [2]; Both R & W bits are reset [3]; Other [4].
64571 …erroneous TCPL: [12:0] Func (VF_Valid;VFID;PFID);[13] U bit; [14] W bit; [15] R bit; [16] NS bit; …
64572 … //Access:R DataWidth:0x20 // Data belongs to an erroneous TCPL: [31:0]-bits [31:0] of the ad…
64573 … //Access:R DataWidth:0x14 // Data belongs to an erroneous TCPL: [19:0]-bits [51:32] of the a…
64578 … 0x560594UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 31-0.
64579 … 0x560598UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 63-32.
64580 … 0x56059cUL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 95-64.
64581 … 0x5605a0UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 127-96.
64582 … 0x5605a4UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 159-128.
64583 … 0x5605a8UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 191-160.
64584 … 0x5605acUL //Access:R DataWidth:0x10 // Indicates the end of FLI flow for PF 15-0.
64585 …b0UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 31-0 accordingly.
64586 …b4UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 63-32 accordingly.
64587 …8UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 95-64 accordingly.
64588 …cUL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 127-96 accordingly.
64589 …L //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 159-128 accordingly.
64590 …UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 191-160 accordingly.
64591 …c8UL //Access:RW DataWidth:0x10 // Clears the FLI done indication for PF bits 15-0 accordingly.
64610 …605e4UL //Access:RW DataWidth:0x8 // Resource Type of the invalidated range - register per PF.
64611 … 0x5605e8UL //Access:RW DataWidth:0x8 // Bit mask for the invali…
64612 …er for the case of invalidation halt (lkpres of invalidated range) [7:0] - Resource type of the…
64614 …x8 // Logging register for reuse miss on transpend entry bits [35:28] - of the problematic r…
64615 …Width:0x8 // Logging register for reuse miss on transpend entry [7:0] - Resource type of the…
64617 … 0x560600UL //Access:RW DataWidth:0x20 // TID of the invalidated range - register per Strom.
64619 … 0x560620UL //Access:RW DataWidth:0x20 // Bit mask for the invali…
64621 … 0x560640UL //Access:RW DataWidth:0x8 // TID of the invalidated range - register per Storm.
64623 … 0x560660UL //Access:RW DataWidth:0x8 // Bit mask for the invali…
64625 …Bit per Storm. Indicates that the data in inv_tid and inv_tid_mask is valid and invalidation shoul…
64627 …0x5606a0UL //Access:RW DataWidth:0x1 // Bit per Storm. Indicates that the marked invalidation…
64629 … 0x5606c0UL //Access:RW DataWidth:0x1 // Bit per PF. If set, the…
64631 …x40 // Access the GPA table way 0; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64633 …x40 // Access the GPA table way 1; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64635 …x40 // Access the GPA table way 2; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64639 …h:0x40 // Access the GPA table way3; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID-…
64641 …- {par - [51]; NS bit - [50]; W bit - [49]; R bit - [48]; U bit - [47]; Priority bit - [46]; PLRU …
64643 … // Access the GPA table way 0; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64645 … // Access the GPA table way 1; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64647 … // Access the GPA table way 2; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64649 … // Access the GPA table way3; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64651 …- { Priority bit - [23]; PLRU - [22]; Err bit - [21]; invpend bit [20]; transpend bit - [19]; vali…
64658 … (0x1<<1) // Enables CDU Inputs -- Must be set for norm…
64660 … (0x1<<2) // Enables CDU Outputs -- Must be set for nor…
64662 … (0x1<<3) // Sets the L1TT Ar…
64663 …DU_REG_CONTROL0_L1TT_SP_SHIFT 3
64668 … (0x1<<6) // Masks all PCIE Errors for Load transactions. NOTE -- This is not connecte…
64677 …M_ERROR (0x1<<3) // Number of L1s wi…
64678 …DU_REG_INT_STS_CCFC_WB_L1_NUM_ERROR_SHIFT 3
64685 …face. All transactions should be either 8 or 16 bytes, so pxp_bvalid[2:0] should always be 3'b000.
64694 …1_NUM_ERROR (0x1<<3) // Number of L1s wi…
64695 …DU_REG_INT_STS_CLR_CCFC_WB_L1_NUM_ERROR_SHIFT 3
64702 …face. All transactions should be either 8 or 16 bytes, so pxp_bvalid[2:0] should always be 3'b000.
64711 …_NUM_ERROR (0x1<<3) // Number of L1s wi…
64712 …DU_REG_INT_STS_WR_CCFC_WB_L1_NUM_ERROR_SHIFT 3
64719 …face. All transactions should be either 8 or 16 bytes, so pxp_bvalid[2:0] should always be 3'b000.
64722 … (0x1<<0) // This bit masks, when set, the Interrupt bit: C…
64724 … (0x1<<1) // This bit masks, when set, the Interrupt bit: C…
64726 … (0x1<<2) // This bit masks, when set, the Interrupt bit: C…
64728 … (0x1<<3) // This bit masks, when set, the Interrupt …
64729 …DU_REG_INT_MASK_CCFC_WB_L1_NUM_ERROR_SHIFT 3
64730 … (0x1<<4) // This bit masks, when set, the Interrupt bit: C…
64732 … (0x1<<5) // This bit masks, when set, the Interrupt bit: C…
64734 … (0x1<<6) // This bit masks, when set, the Interrupt bit: C…
64736 … (0x1<<7) // This bit masks, when set, the Interrupt bit: C…
64739 … (0x1<<0) // This bit masks, when set, the Parity bit: CD…
64741 … (0x1<<4) // This bit masks, when set, the Parity bit: CD…
64743 … (0x1<<1) // This bit masks, when set, the Parity bit: CD…
64745 … (0x1<<2) // This bit masks, when set, the Parity bit: CD…
64747 … (0x1<<1) // This bit masks, when set, the Parity bit: CD…
64749 … (0x1<<3) // This bit masks, when set, the Parity bi…
64750 …DU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_E5_SHIFT 3
64751 … (0x1<<3) // This bit masks, when set, the Parity bi…
64752 …DU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT 3
64755 …n for Region0 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64757 …n for Region1 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64759 …n for Region2 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64761 …n for Region3 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64764 …n for Region4 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64766 …n for Region5 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64768 …n for Region6 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64770 …n for Region7 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64773 …n for Region0 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64775 …n for Region1 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64777 …n for Region2 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64779 …n for Region3 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64782 …n for Region4 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64784 …n for Region5 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64786 …n for Region6 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64788 …n for Region7 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64790 …rols the Full signal to PXP. This register must never be set higher than 8 -- doing so will result…
64791 …ories when past this limit. This register must never be set higher than 13 -- doing so will result…
64795 …GS_LD (0x7<<3) // ATC Flags Field …
64796 …DU_REG_CCFC_PXP_CCFC_ATC_FLAGS_LD_SHIFT 3
64799 … (0x1<<16) // TPH Valid bit for CCFC PXP Reques…
64801 … (0x1<<17) // Relaxed ordering bit for CCFC PXP rd_req.
64803 … (0x1<<18) // Relaxed ordering bit for CCFC PXP wr_req.
64805 … (0x1<<19) // No snoop bit for CCFC PXP rd_req.
64807 … (0x1<<20) // No snoop bit for CCFC PXP wr_req.
64812 …GS_LD (0x7<<3) // ATC Flags Field …
64813 …DU_REG_TCFC_PXP_TCFC_ATC_FLAGS_LD_SHIFT 3
64816 … (0x1<<16) // TPH Valid bit for TCFC PXP Reques…
64818 … (0x1<<17) // Relaxed ordering bit for TCFC working me…
64820 … (0x1<<18) // Relaxed ordering bit for TCFC init memor…
64822 … (0x1<<19) // Relaxed ordering bit for TCFC working me…
64824 … (0x1<<20) // No snoop bit for TCFC working me…
64826 … (0x1<<21) // No snoop bit for TCFC init memor…
64828 … (0x1<<22) // No snoop bit for TCFC working me…
64850 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
64851 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
64852 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
64853 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
64872 … (0xfff<<12) // Block waste within a page. this number equals to PageSize-NCIB*ContextSize.
64904 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64910 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64911 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64921 …th:0x4 // Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags com…
64922 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64923 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64924 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64925 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64926 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64927 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64928 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64929 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64930 …0x5a0030UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64931 …0x5a0034UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64932 …0x5a0038UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64933 …0x5a003cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64936 …bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message wi…
64937 …Access:R DataWidth:0x20 // Logging register for long message error: bit 0:3 Segment message h…
64945 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
64947 … (0x1<<3) // Mini cache error - meaning t…
64948 …TLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR_E5_SHIFT 3
64949 … (0x1<<4) // Mini cache error - meaning that A load …
64954 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
64956 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
64958 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
64960 … (0x1<<3) // This bit masks, when set, the Interrupt …
64961 …TLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR_E5_SHIFT 3
64962 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
64964 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
64971 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
64973 …_E5 (0x1<<3) // Mini cache error - meaning t…
64974 …TLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR_E5_SHIFT 3
64975 … (0x1<<4) // Mini cache error - meaning that A load …
64984 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
64986 …R_E5 (0x1<<3) // Mini cache error - meaning t…
64987 …TLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR_E5_SHIFT 3
64988 … (0x1<<4) // Mini cache error - meaning that A load …
64993 … (0x1<<0) // This bit masks, when set, the Parity bit: PT…
64995 … (0x1<<1) // This bit masks, when set, the Parity bit: PT…
64997 … (0x1<<2) // This bit masks, when set, the Parity bit: PT…
64999 … (0x1<<3) // This bit masks, when set, the Parity bi…
65000 …TLD_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_E5_SHIFT 3
65001 … (0x1<<4) // This bit masks, when set, the Parity bit: PT…
65003 … (0x1<<5) // This bit masks, when set, the Parity bit: PT…
65005 … (0x1<<6) // This bit masks, when set, the Parity bit: PT…
65007 … (0x1<<7) // This bit masks, when set, the Parity bit: PT…
65013 … 0x5a0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
65020 … (0x1<<2) // defines that only back-to-back aggregation is …
65022 …OBAL_INC_SN_E5 (0x1<<3) // When this flag i…
65023 …TLD_REG_L2MA_AGGR_CONFIG1_GLOBAL_INC_SN_E5_SHIFT 3
65039 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
65041 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
65043 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
65045 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
65048 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
65050 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
65052 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
65054 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
65057 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
65059 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
65061 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
65063 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
65066 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
65068 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
65070 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
65072 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
65108 … 0x5a0824UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65109 … 0x5a0828UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65110 … 0x5a082cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65111 … 0x5a0830UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65112 … 0x5a0834UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65113 … 0x5a0838UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65114 … 0x5a083cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65115 … 0x5a0840UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65116 … 0x5a0844UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65117 … 0x5a0848UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65118 … 0x5a084cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65119 … 0x5a0850UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65120 … 0x5a0854UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65121 … 0x5a0858UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65122 … 0x5a085cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65123 … 0x5a0860UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65124 … 0x5a0864UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65125 … 0x5a0868UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65126 … 0x5a086cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65127 … 0x5a0870UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65128 … 0x5a0874UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65129 … 0x5a0878UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65130 … 0x5a087cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65131 … 0x5a0880UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65132 … 0x5a0884UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
65133 … 0x5a0888UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
65134 … 0x5a088cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
65135 … 0x5a0890UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
65136 … 0x5a0894UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
65137 … 0x5a0898UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
65138 … 0x5a089cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
65139 … 0x5a08a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
65141 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
65143 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
65145 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
65147 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
65150 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
65152 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
65154 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
65156 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
65159 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
65161 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
65163 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
65165 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
65168 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
65170 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
65172 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
65174 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
65213 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
65215 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
65217 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
65219 … (0x1<<3) // indication if to include the flow-ID in the stream…
65220 …TLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3_E5_SHIFT 3
65221 … (0x1f<<4) // offset of the flow-ID, in 32b units, from the beginning of the message. Should b…
65223 … (0x1f<<9) // offset of the flow-ID, in 32b units, from the beginning of the message. Should b…
65225 … (0x1f<<14) // offset of the flow-ID, in 32b units, from the beginning of the message. Should b…
65227 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65236 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 3.
65245 … (0xf<<12) // the maximal number of children in a specific aggregation. for set 3.
65248 … (0xff<<0) // The value by which to increment the event-ID in case of success…
65250 … (0xff<<8) // The value by which to increment the event-ID in case of success…
65252 … (0xff<<16) // The value by which to increment the event-ID in case of success…
65254 …ff<<24) // The value by which to increment the event-ID in case of successful aggregation. for set…
65256 … 0x5a08d4UL //Access:RW DataWidth:0xc // maximum loader size in 256 bit words
65258 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
65259 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
65260 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
65261 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
65273 …th:0x4 // Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags com…
65274 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65275 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65276 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65277 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65278 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65279 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65280 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65281 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65282 …0x5c0030UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65283 …0x5c0034UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65284 …0x5c0038UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65285 …0x5c003cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65288 …bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message wi…
65289 …Access:R DataWidth:0x20 // Logging register for long message error: bit 0:3 Segment message h…
65297 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
65299 … (0x1<<3) // Mini cache error - meaning t…
65300 …PLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR_E5_SHIFT 3
65301 … (0x1<<4) // Mini cache error - meaning that A load …
65306 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
65308 … (0x1<<1) // This bit masks, when set, the Interrupt bit: Y…
65310 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Y…
65312 … (0x1<<3) // This bit masks, when set, the Interrupt …
65313 …PLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR_E5_SHIFT 3
65314 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
65316 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
65323 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
65325 …_E5 (0x1<<3) // Mini cache error - meaning t…
65326 …PLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR_E5_SHIFT 3
65327 … (0x1<<4) // Mini cache error - meaning that A load …
65336 … (0x1<<2) // Issuese related to the seg message fields - the sum of the seg m…
65338 …R_E5 (0x1<<3) // Mini cache error - meaning t…
65339 …PLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR_E5_SHIFT 3
65340 … (0x1<<4) // Mini cache error - meaning that A load …
65345 … (0x1<<0) // This bit masks, when set, the Parity bit: YP…
65347 … (0x1<<1) // This bit masks, when set, the Parity bit: YP…
65349 … (0x1<<2) // This bit masks, when set, the Parity bit: YP…
65351 … (0x1<<3) // This bit masks, when set, the Parity bi…
65352 …PLD_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_E5_SHIFT 3
65353 … (0x1<<4) // This bit masks, when set, the Parity bit: YP…
65355 … (0x1<<5) // This bit masks, when set, the Parity bit: YP…
65357 … (0x1<<6) // This bit masks, when set, the Parity bit: YP…
65359 … (0x1<<7) // This bit masks, when set, the Parity bit: YP…
65365 … 0x5c0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
65372 … (0x1<<2) // defines that only back-to-back aggregation is …
65374 …OBAL_INC_SN_E5 (0x1<<3) // When this flag i…
65375 …PLD_REG_L2MA_AGGR_CONFIG1_GLOBAL_INC_SN_E5_SHIFT 3
65391 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0.
65393 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0.
65395 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 0.
65397 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0.
65400 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1.
65402 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1.
65404 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 1.
65406 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1.
65409 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2.
65411 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2.
65413 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 2.
65415 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2.
65418 …/ Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3.
65420 …/ Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3.
65422 …/ Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set 3.
65424 …/ Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3.
65460 … 0x5c0824UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65461 … 0x5c0828UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65462 … 0x5c082cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65463 … 0x5c0830UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65464 … 0x5c0834UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65465 … 0x5c0838UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65466 … 0x5c083cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65467 … 0x5c0840UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65468 … 0x5c0844UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65469 … 0x5c0848UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65470 … 0x5c084cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65471 … 0x5c0850UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65472 … 0x5c0854UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65473 … 0x5c0858UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65474 … 0x5c085cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65475 … 0x5c0860UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65476 … 0x5c0864UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65477 … 0x5c0868UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65478 … 0x5c086cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65479 … 0x5c0870UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65480 … 0x5c0874UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65481 … 0x5c0878UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65482 … 0x5c087cUL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65483 … 0x5c0880UL //Access:RW DataWidth:0x20 // bit-mask on the selected…
65484 … 0x5c0884UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
65485 … 0x5c0888UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
65486 … 0x5c088cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
65487 … 0x5c0890UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
65488 … 0x5c0894UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
65489 … 0x5c0898UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
65490 … 0x5c089cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
65491 … 0x5c08a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 par…
65493 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0.
65495 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0.
65497 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 0.
65499 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0.
65502 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1.
65504 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1.
65506 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 1.
65508 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1.
65511 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2.
65513 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2.
65515 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 2.
65517 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2.
65520 …// Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3.
65522 …// Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3.
65524 …// Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set 3.
65526 …// Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3.
65565 … (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0.
65567 … (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1.
65569 … (0x1<<2) // indication if to include the flow-ID in the stream-ID for set 2.
65571 … (0x1<<3) // indication if to include the flow-ID in the stream…
65572 …PLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_3_E5_SHIFT 3
65573 … (0x1f<<4) // offset of the flow-ID, in 32b units, from the beginning of the message. Should b…
65575 … (0x1f<<9) // offset of the flow-ID, in 32b units, from the beginning of the message. Should b…
65577 … (0x1f<<14) // offset of the flow-ID, in 32b units, from the beginning of the message. Should b…
65579 …-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of t…
65588 …erial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 3.
65597 … (0xf<<12) // the maximal number of children in a specific aggregation. for set 3.
65600 … (0xff<<0) // The value by which to increment the event-ID in case of success…
65602 … (0xff<<8) // The value by which to increment the event-ID in case of success…
65604 … (0xff<<16) // The value by which to increment the event-ID in case of success…
65606 …ff<<24) // The value by which to increment the event-ID in case of successful aggregation. for set…
65608 … 0x5c08d4UL //Access:RW DataWidth:0xc // maximum loader size in 256 bit words
65610 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
65611 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
65612 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
65613 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
65626 … (0x1<<0) // This bit masks, when set, the Interrupt bit: W…
65635 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
65636 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
65637 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
65638 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
65644 … (0x1<<0) // This bit masks, when set, the Parity bit: WO…
65646 … (0x1<<1) // This bit masks, when set, the Parity bit: WO…
65648 … (0x1<<2) // This bit masks, when set, the Parity bit: WO…
65650 … (0x1<<3) // This bit masks, when set, the Parity bi…
65651 …OL_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_E5_SHIFT 3
65652 … (0x1<<4) // This bit masks, when set, the Parity bit: WO…
65654 … (0x1<<5) // This bit masks, when set, the Parity bit: WO…
65656 … (0x1<<6) // This bit masks, when set, the Parity bit: WO…
65658 … (0x1<<7) // This bit masks, when set, the Parity bit: WO…
65660 … (0x1<<8) // This bit masks, when set, the Parity bit: WO…
65662 … (0x1<<9) // This bit masks, when set, the Parity bit: WO…
65664 … (0x1<<10) // This bit masks, when set, the Parity bit: WO…
65666 … (0x1<<11) // This bit masks, when set, the Parity bit: WO…
65668 … (0x1<<12) // This bit masks, when set, the Parity bit: WO…
65670 … (0x1<<13) // This bit masks, when set, the Parity bit: WO…
65672 … (0x1<<14) // This bit masks, when set, the Parity bit: WO…
65674 … (0x1<<15) // This bit masks, when set, the Parity bit: WO…
65676 … (0x1<<16) // This bit masks, when set, the Parity bit: WO…
65678 … (0x1<<17) // This bit masks, when set, the Parity bit: WO…
65680 … (0x1<<18) // This bit masks, when set, the Parity bit: WO…
65682 … (0x1<<19) // This bit masks, when set, the Parity bit: WO…
65684 … (0x1<<20) // This bit masks, when set, the Parity bit: WO…
65686 … (0x1<<21) // This bit masks, when set, the Parity bit: WO…
65688 … (0x1<<22) // This bit masks, when set, the Parity bit: WO…
65690 … (0x1<<23) // This bit masks, when set, the Parity bit: WO…
65693 …-port per-PF register. L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0: 5 - L…
65694 …ataWidth:0x1 // Set this bit to enable ACPI and TCP SYN matching even when the packet is forwar…
65695 … 0x608080UL //Access:WB DataWidth:0x100 // This is a per-port per-PF register. Byt…
65697 …ataWidth:0x1 // This is a per-port register. When this bit is set ACPI packet recognition wil…
65698 … 0x608104UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65699 … 0x608108UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65700 … 0x60810cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65701 … 0x608110UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65702 … 0x608114UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65703 … 0x608118UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65704 …811cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC32C for pattern 3.
65705 … 0x608120UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65706 … 0x608124UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65707 … 0x608128UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65708 … 0x60812cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65709 … 0x608130UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65710 … 0x608134UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65711 … 0x608138UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65712 … 0x60813cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65713 … 0x608140UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65714 …idth:0x1 // This is a per-port per-PF register. When this bit is set Magic Packet recognition…
65715 … 0x608148UL //Access:WB DataWidth:0x30 // This is a per-port per-PF register. MAC…
65717 …/Access:RW DataWidth:0x1 // This is a per-port per-PF register. A low-to-high transition of …
65718 … 0x608160UL //Access:WB_R DataWidth:0x100 // Read-only data from the Wa…
65720 …- a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details regist…
65721 …- all fields are sticky. Bits 15:0 - PF Vector: The bit-mapped vector indicating which of the gl…
65722 … 0x608188UL //Access:R DataWidth:0xe // Wake packet length - the actual length of…
65723 …- all fields are sticky. Bits 7:0 - ACPI MATCH: Per-function bit-mapped result from ACPI patte…
65724 … 0x608190UL //Access:RW DataWidth:0x3 // This bit selects the default…
65725 …- acpi_default_pf_sel. 2: Select the first of each: 2 ports (quad_port_mode is 0) - use one of eac…
65726 …ccess:RW DataWidth:0x2 // This is a per-PF register. Set bit 0 to enable wake on IPv4 TCP SY…
65727 … 0x60819cUL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65728 … 0x6081a0UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65729 … 0x6081a4UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65730 … 0x6081a8UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65731 … 0x6081acUL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65732 … 0x6081b0UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65743 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
65752 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
65753 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
65754 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
65755 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
65764 …rride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bit…
65765 …rride for management packets. This field consists of {3-bit priority, 1-bit drop eligible, 12-bit…
65766 … 0x6101f8UL //Access:RW DataWidth:0x3 // The length, in 2-byte granularity, of …
65780 …_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_QFWD_L_I_K2_E5 (0x1<<3) //
65781 …HY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_QFWD_L_I_K2_E5_SHIFT 3
65805 …_PHY_REFCLK_CONTROL_PHY1_CMU_PD_I_K2_E5 (0x1<<3) //
65806 …HY_PCIE_REG_PHY_REFCLK_CONTROL_PHY1_CMU_PD_I_K2_E5_SHIFT 3
65821 … (0xff<<0) // Firmware must set this bit to 1 after finished…
65823 … (0x1<<8) // Firmware must set this bit to 1 after finished…
65832 …_PHY_STATUS_PHY1_REFCLK_GATE_ACK_O_K2_E5 (0x1<<3) //
65833 …HY_PCIE_REG_PHY_STATUS_PHY1_REFCLK_GATE_ACK_O_K2_E5_SHIFT 3
65836 … 0x628018UL //Access:RW DataWidth:0x10 // Bit masks to be ANDed w…
65877 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
65878 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
65879 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
65880 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
65882 …set signal into the SerDes. This should be 0 (Reset value) write 1 to this bit to allow the SerDes…
65886 …d on CMU0 in multiple CMU PHYs if there are any active lanes. Signal is over-riden by por_n_i so h…
65888 …Q_I_K2_E5 (0x1<<3) // Turn off CMU mas…
65889 …S_REG_COMMON_CONTROL_CMU_IDDQ_I_K2_E5_SHIFT 3
65907 …5 (0x1<<3) // Lane IDDQ mode e…
65908 …S_REG_LN1_CNTL_LN1_IDDQ_K2_E5_SHIFT 3
65911 …- rxsig_det_mask_i 16 - rxeii_exit_type_i 15 - rxei_infer_i 14 - bslip_req_i 13 - data_width_i - 0…
65915 …pcs_sdet 0 - ln1_stat_o[2] (RX Locked indicator) 1 - ln1_astat_o[5] (Raw signal detext indicator)…
65923 …- not used 12 - ln1_ok_o 11 - ln1_runlen_err_o 10:4 - not used 3:2 - ln1_rx_locked_o - bit 3 =rxda…
65925 …(0x3f<<14) // 19 - Raw signal detect - Bit Slip Ack 18 - ln1_bitslip_ack_o - Bit Slip Ack 17 - not…
65930 …K_SEL_I_K2_E5 (0x1<<3) // Assert to provid…
65931 …S_REG_CLOCK_SELECT_CMU_REFCLK_SEL_I_K2_E5_SHIFT 3
65945 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
65958 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
65959 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
65960 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
65961 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
65968 …-0x1ff. Reserved = 0x200-0x3ff. LANE1 registers = 0x400-0x5ff. Reserved = 0x600-0x7f…
65977 …3) // Register subst selection driven by core signals. This bus, when HW control gate is enabled, …
65978 …VS_WRAP_REG_AVS_CONTROL_SETSEL_K2_SHIFT 3
65979 …orresponding bit in the AVSC_FLOW_CTRL is enabled. Bit [0] : corresponds to FLOW 1 Bit [1] : corre…
65984 … (0x3<<1) // It replicates the mode-sel value when voltag…
65986 … (0x7<<3) // It replicates the set-sel valu…
65987 …VS_WRAP_REG_AVS_INDICATION_CORE_SETACK_K2_SHIFT 3
65996 … (0x1<<0) // This bit masks, when set, the Interrupt bit: A…
65998 … (0x1<<2) // This bit masks, when set, the Interrupt bit: A…
66011 … (0x1<<0) // This bit masks, when set, the Parity bit: AV…
66013 … (0x1<<1) // This bit masks, when set, the Parity bit: AV…
66015 … (0x1<<2) // This bit masks, when set, the Parity bit: AV…
66027 …re control of the Traffic LED. The Traffic LED will then be controlled via bit LED_CONTROL_TRAFFIC…
66029 …ng with the LED_CONTROL_OVERRIDE_TRAFFIC bit turns on the Traffic LED. If the LED_CONTROL_BLINK_TR…
66031 …<<8) // If set along with the LED_CONTROL_OVERRIDE_TRAFFIC bit and LED_CONTROL_TRAFFIC LED bit; th…
66033 … (0x1<<12) // This bit is set to enable the use of the LED_CONTROL_BLINK_RATE field de…
66035 … (0x1<<13) // This bit is set to enable th…
66039 …-> MAC; 1-2 -> PHY1; 3 -> PHY3; 4 -> MAC2; 5-6 -> PHY4; 7 -> PHY6; 8 -> MAC3; …
66040 …ss:RW DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G A '1'…
66041 …ss:RW DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G A '1'…
66042 …ss:RW DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G A '1'…
66043 …-> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G This register allows the MAC (Driver/FW) to set …
66045 … corresponding Physical function. 0 -> NW0 connects to PF0 1 -> NW0 connects to PF1 2 -> NW0 co…
66047 … corresponding Physical function. 0 -> NW1 connects to PF0 1 -> NW1 connects to PF1 2 -> NW1 co…
66049 … corresponding Physical function. 0 -> NW2 connects to PF0 1 -> NW2 connects to PF1 2 -> NW2 co…
66051 … corresponding Physical function. 0 -> NW3 connects to PF0 1 -> NW3 connects to PF1 2 -> NW3 co…
66053 …1cUL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66054 …20UL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66055 …24UL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66056 …28UL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66057 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
66062 … (0x1<<0) // This bit masks, when set, the Interrupt bit: L…
66073 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66075 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66077 …SS0RECCALA_E5 (0x1<<3) // Unknown signal, …
66078 …WS_REG_HSS0_CONTROL_COMMON_HSS0RECCALA_E5_SHIFT 3
66081 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66084 …<0) // 0x0 - Select reference clock from Bump 0x1 - Select inter-macro refrence clock from the lef…
66086 … (0x3<<2) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro ref…
66088 … (0x3<<4) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro re…
66090 …l is used for nws_nwm_sd_energy_detect. 0 - use ~lnX_stat_los_o 1 - use ~lnX_stat_los_deglitch_o (…
66094 … holds the SerDes in Reset. Once the memory is configured, write 1 to this bit to allow the SerDes…
66096 …is should be 0 (Reset value) This holds the cmu0 in Reset. write 1 to this bit to allow the SerDes…
66098 …is should be 0 (Reset value) This holds the cmu0 in Reset. write 1 to this bit to allow the SerDes…
66108 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66110 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66112 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66114 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66116 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66118 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66121 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66128 … (0x1f<<0) // Sets phy_ctrl_refclk_i used for CMU0 0x09 - refclk is 257.8125Mhz
66130 … Sets phy_ctrl_rate1_i used for CMU0 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125…
66132 … Sets phy_ctrl_rate1_i used for CMU1 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125…
66141 …WNPLLA_E5 (0x1<<3) // HS PLLp Power Do…
66142 …WS_REG_HSS0_CONTROL1A_HSS0PDWNPLLA_E5_SHIFT 3
66148 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66150 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66152 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66154 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66157 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66164 … (0x1<<0) // 0x0 - No error 0x1 - Phy has inter…
66166 … (0x1<<1) // 0x1 - Indicates CMU0 PLL h…
66168 … (0x1<<2) // 0x1 - Indicates CMU1 PLL h…
66170 … (0x1<<3) // 0x0 - PHY is not ready to respond to cm0_rst_n_i and cm0_pd_i[1:0]. The s…
66171 …WS_REG_COMMON_STATUS_CM0_RST_PD_READY_O_K2_SHIFT 3
66172 … (0x1<<4) // 0x0 - PHY is not ready to respond to cm1_rst_n_i and cm1_pd_i[1:0]. The signal…
66174 … (0x1<<5) // 0x0 - PHY is not ready to respond to ln0_rst_n_i and ln0_pd_i[1:0]. The signal…
66176 … (0x1<<6) // 0x0 - PHY is not ready to respond to ln1_rst_n_i and ln1_pd_i[1:0]. The signal…
66178 … (0x1<<7) // 0x0 - PHY is not ready to respond to ln2_rst_n_i and ln2_pd_i[1:0]. The signal…
66180 … (0x1<<8) // 0x0 - PHY is not ready to respond to ln3_rst_n_i and ln3_pd_i[1:0]. The signal…
66189 …WNPLLB_E5 (0x1<<3) // HS PLLp Power Do…
66190 …WS_REG_HSS0_CONTROL1B_HSS0PDWNPLLB_E5_SHIFT 3
66196 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66198 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 …
66199 …WS_REG_LN0_CNTL_LN0_CTRL_RXPOLARITY_K2_SHIFT 3
66200 … 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS…
66204 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66207 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66209 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66211 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66213 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (…
66214 …WS_REG_HSS0_STATUS_HSS0PRTREADYB_E5_SHIFT 3
66215 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66218 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66220 … (0x1<<1) // 0x0 - data on ln0_rxdata_o is invalid. 0x1 - d…
66222 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66224 …3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assiste…
66225 …WS_REG_LN0_STATUS_LN0_STAT_LOS_K2_SHIFT 3
66226 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. …
66231 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66233 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66235 …SS1RECCALA_E5 (0x1<<3) // Unknown signal, …
66236 …WS_REG_HSS1_CONTROL_COMMON_HSS1RECCALA_E5_SHIFT 3
66239 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66248 …0_LINK_STATUS_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the …
66249 …WS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_40G_KR4_I_K2_SHIFT 3
66261 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66268 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66270 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66272 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66274 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66276 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66278 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66280 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66282 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66284 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66288 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66292 …bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are sub…
66294 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66296 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66307 …WNPLLA_E5 (0x1<<3) // HS PLLp Power Do…
66308 …WS_REG_HSS1_CONTROL1A_HSS1PDWNPLLA_E5_SHIFT 3
66314 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66316 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 …
66317 …WS_REG_LN1_CNTL_LN1_CTRL_RXPOLARITY_K2_SHIFT 3
66318 … 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS…
66322 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66325 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66332 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66334 … (0x1<<1) // 0x0 - data on ln1_rxdata_o is invalid. 0x1 - d…
66336 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66338 …3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assiste…
66339 …WS_REG_LN1_STATUS_LN1_STAT_LOS_K2_SHIFT 3
66340 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. …
66349 …WNPLLB_E5 (0x1<<3) // HS PLLp Power Do…
66350 …WS_REG_HSS1_CONTROL1B_HSS1PDWNPLLB_E5_SHIFT 3
66362 …1_LINK_STATUS_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the …
66363 …WS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_40G_KR4_I_K2_SHIFT 3
66375 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66377 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66379 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66381 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (…
66382 …WS_REG_HSS1_STATUS_HSS1PRTREADYB_E5_SHIFT 3
66383 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66386 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66388 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66390 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66392 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66394 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66396 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66398 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66400 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66402 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66406 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66410 …bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are sub…
66412 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66414 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66421 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66423 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66425 …SS2RECCALA_E5 (0x1<<3) // Unknown signal, …
66426 …WS_REG_HSS2_CONTROL_COMMON_HSS2RECCALA_E5_SHIFT 3
66429 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66432 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66434 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 …
66435 …WS_REG_LN2_CNTL_LN2_CTRL_RXPOLARITY_K2_SHIFT 3
66436 … 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS…
66440 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66443 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66450 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66452 … (0x1<<1) // 0x0 - data on ln2_rxdata_o is invalid. 0x1 - d…
66454 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66456 …3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assiste…
66457 …WS_REG_LN2_STATUS_LN2_STAT_LOS_K2_SHIFT 3
66458 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. …
66467 …WNPLLA_E5 (0x1<<3) // HS PLLp Power Do…
66468 …WS_REG_HSS2_CONTROL1A_HSS2PDWNPLLA_E5_SHIFT 3
66480 …2_LINK_STATUS_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the …
66481 …WS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_40G_KR4_I_K2_SHIFT 3
66493 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66500 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66502 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66504 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66506 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66508 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66510 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66512 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66514 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66516 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66520 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66524 …bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are sub…
66526 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66528 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66539 …WNPLLB_E5 (0x1<<3) // HS PLLp Power Do…
66540 …WS_REG_HSS2_CONTROL1B_HSS2PDWNPLLB_E5_SHIFT 3
66546 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66548 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 …
66549 …WS_REG_LN3_CNTL_LN3_CTRL_RXPOLARITY_K2_SHIFT 3
66550 … 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS…
66554 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66557 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66559 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66561 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66563 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (…
66564 …WS_REG_HSS2_STATUS_HSS2PRTREADYB_E5_SHIFT 3
66565 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66568 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0…
66570 … (0x1<<1) // 0x0 - data on ln3_rxdata_o is invalid. 0x1 - d…
66572 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66574 …3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assiste…
66575 …WS_REG_LN3_STATUS_LN3_STAT_LOS_K2_SHIFT 3
66576 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. …
66581 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66583 …5 (0x1<<2) // Power-On-Reset Power Enable. …
66585 …SS3RECCALA_E5 (0x1<<3) // Unknown signal, …
66586 …WS_REG_HSS3_CONTROL_COMMON_HSS3RECCALA_E5_SHIFT 3
66589 …Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pll…
66598 …3_LINK_STATUS_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the …
66599 …WS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_40G_KR4_I_K2_SHIFT 3
66611 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66618 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66620 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66622 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66624 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66626 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66628 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66630 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66632 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66634 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66638 …-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high,…
66642 …bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are sub…
66644 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66646 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66657 …WNPLLA_E5 (0x1<<3) // HS PLLp Power Do…
66658 …WS_REG_HSS3_CONTROL1A_HSS3PDWNPLLA_E5_SHIFT 3
66664 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66677 …WNPLLB_E5 (0x1<<3) // HS PLLp Power Do…
66678 …WS_REG_HSS3_CONTROL1B_HSS3PDWNPLLB_E5_SHIFT 3
66684 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66686 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66688 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66690 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (…
66691 …WS_REG_HSS3_STATUS_HSS3PRTREADYB_E5_SHIFT 3
66692 … (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX lin…
66695 …bit 10 of Receiver Configuration Mode Register is set to �1�. Otherwise, these pins are ignored. 0…
66697 …bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustment.…
66699 …3) // Early Input. External EARLY input to internal rotator control logic. Based on the setting of…
66700 …WS_REG_RX0_CONTROL_RX0EARLYIN_E5_SHIFT 3
66701 …l Early/Late Selection Control in Receiver Phase Rotator Control Register, bit 4, each rising edge…
66707 …on). 1 Enabled (external control of phase rotators). Note: Do not set this bit to �1� until the co…
66710 …bit 10 of Receiver Configuration Mode Register is set to �1�. Otherwise, these pins are ignored. 0…
66712 …bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustment.…
66714 …3) // Early Input. External EARLY input to internal rotator control logic. Based on the setting of…
66715 …WS_REG_RX1_CONTROL_RX1EARLYIN_E5_SHIFT 3
66716 …l Early/Late Selection Control in Receiver Phase Rotator Control Register, bit 4, each rising edge…
66722 …on). 1 Enabled (external control of phase rotators). Note: Do not set this bit to �1� until the co…
66725 …bit 10 of Receiver Configuration Mode Register is set to �1�. Otherwise, these pins are ignored. 0…
66727 …bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustment.…
66729 …3) // Early Input. External EARLY input to internal rotator control logic. Based on the setting of…
66730 …WS_REG_RX2_CONTROL_RX2EARLYIN_E5_SHIFT 3
66731 …l Early/Late Selection Control in Receiver Phase Rotator Control Register, bit 4, each rising edge…
66737 …on). 1 Enabled (external control of phase rotators). Note: Do not set this bit to �1� until the co…
66740 …bit 10 of Receiver Configuration Mode Register is set to �1�. Otherwise, these pins are ignored. 0…
66742 …bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustment.…
66744 …3) // Early Input. External EARLY input to internal rotator control logic. Based on the setting of…
66745 …WS_REG_RX3_CONTROL_RX3EARLYIN_E5_SHIFT 3
66746 …l Early/Late Selection Control in Receiver Phase Rotator Control Register, bit 4, each rising edge…
66752 …on). 1 Enabled (external control of phase rotators). Note: Do not set this bit to �1� until the co…
66755 …bit 10 of the Transmitter Configuration Mode Register is set to �1�. Otherwise, these pins are ign…
66757 …Bit 13. Coefficient preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second …
66771 …-impedance state.) 1 Normal operation. Notes: 1. This pin is ignored if HSSJTAGCE = �1� and the tr…
66777 …-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Reserved. Bits 5:4. Post-cursor c…
66779 …bit 10 of the Transmitter Configuration Mode Register is set to �1�. Otherwise, these pins are ign…
66781 …Bit 13. Coefficient preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second …
66795 …-impedance state.) 1 Normal operation. Notes: 1. This pin is ignored if HSSJTAGCE = �1� and the tr…
66801 …-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Reserved. Bits 5:4. Post-cursor c…
66803 …bit 10 of the Transmitter Configuration Mode Register is set to �1�. Otherwise, these pins are ign…
66805 …Bit 13. Coefficient preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second …
66819 …-impedance state.) 1 Normal operation. Notes: 1. This pin is ignored if HSSJTAGCE = �1� and the tr…
66825 …-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Reserved. Bits 5:4. Post-cursor c…
66827 …bit 10 of the Transmitter Configuration Mode Register is set to �1�. Otherwise, these pins are ign…
66829 …Bit 13. Coefficient preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second …
66843 …-impedance state.) 1 Normal operation. Notes: 1. This pin is ignored if HSSJTAGCE = �1� and the tr…
66849 …-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Reserved. Bits 5:4. Post-cursor c…
66858 …T_EXTERNAL_SIGDET_P3_K2_E5 (0x1<<3) // Used to detect t…
66859 …WS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P3_K2_E5_SHIFT 3
66868 …TATUS_EXTERNAL_PHY_LASI_B_P3_K2_E5 (0x1<<3) // Link Alarm Statu…
66869 …WS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P3_K2_E5_SHIFT 3
66877 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
66878 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
66879 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
66880 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
66894 …LVE_40G_CR4_K2 (0x1<<3) // Autonegotiation …
66895 …WS_REG_INT_STS_0_LN0_AN_RESOLVE_40G_CR4_K2_SHIFT 3
66909 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
66911 … (0x1<<1) // This bit masks, when set, the Interrupt bit: N…
66913 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
66915 … (0x1<<3) // This bit masks, when set, the Interrupt …
66916 …WS_REG_INT_MASK_0_LN0_AN_RESOLVE_40G_CR4_K2_SHIFT 3
66917 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
66919 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
66921 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
66923 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
66925 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
66927 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
66936 …ESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation …
66937 …WS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_40G_CR4_K2_SHIFT 3
66957 …RESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation …
66958 …WS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_40G_CR4_K2_SHIFT 3
66976 …LVE_40G_CR4_K2 (0x1<<3) // Autonegotiation …
66977 …WS_REG_INT_STS_1_LN1_AN_RESOLVE_40G_CR4_K2_SHIFT 3
66991 … (0x1<<1) // This bit masks, when set, the Interrupt bit: N…
66993 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
66995 … (0x1<<3) // This bit masks, when set, the Interrupt …
66996 …WS_REG_INT_MASK_1_LN1_AN_RESOLVE_40G_CR4_K2_SHIFT 3
66997 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
66999 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
67001 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
67003 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
67005 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
67007 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
67014 …ESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation …
67015 …WS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_40G_CR4_K2_SHIFT 3
67033 …RESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation …
67034 …WS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_40G_CR4_K2_SHIFT 3
67052 …LVE_40G_CR4_K2 (0x1<<3) // Autonegotiation …
67053 …WS_REG_INT_STS_2_LN2_AN_RESOLVE_40G_CR4_K2_SHIFT 3
67067 … (0x1<<1) // This bit masks, when set, the Interrupt bit: N…
67069 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
67071 … (0x1<<3) // This bit masks, when set, the Interrupt …
67072 …WS_REG_INT_MASK_2_LN2_AN_RESOLVE_40G_CR4_K2_SHIFT 3
67073 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
67075 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
67077 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
67079 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
67081 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
67083 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
67090 …ESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation …
67091 …WS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_40G_CR4_K2_SHIFT 3
67109 …RESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation …
67110 …WS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_40G_CR4_K2_SHIFT 3
67128 …LVE_40G_CR4_K2 (0x1<<3) // Autonegotiation …
67129 …WS_REG_INT_STS_3_LN3_AN_RESOLVE_40G_CR4_K2_SHIFT 3
67143 … (0x1<<1) // This bit masks, when set, the Interrupt bit: N…
67145 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
67147 … (0x1<<3) // This bit masks, when set, the Interrupt …
67148 …WS_REG_INT_MASK_3_LN3_AN_RESOLVE_40G_CR4_K2_SHIFT 3
67149 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
67151 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
67153 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
67155 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
67157 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
67159 … (0x1<<9) // This bit masks, when set, the Interrupt bit: N…
67166 …ESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation …
67167 …WS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_40G_CR4_K2_SHIFT 3
67185 …RESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation …
67186 …WS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_40G_CR4_K2_SHIFT 3
67200 … (0x1<<1) // This bit masks, when set, the Parity bit: NW…
67202 … (0x1<<0) // This bit masks, when set, the Parity bit: NW…
67204 … (0x1<<0) // This bit masks, when set, the Parity bit: NW…
67206 … (0x1<<2) // This bit masks, when set, the Parity bit: NW…
67208 … (0x1<<3) // This bit masks, when set, the Parity bi…
67209 …WS_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_SHIFT 3
67211 …10 // PHY instance0 = 0x000-0x1fff. PHY instance1 = 0x2000-0x3fff. PHY instance2 = 0x4000-0x5fff…
67213 …-0x7ff. CMU0 registers = 0x0800-0x0bff. CMU1 registers = 0x0c00-0x0fff. Reserved = …
67215 …[1] bits[15:8] = ram address [2] bits[7:0] = ram address [3] register 0 = ram location [3:0] re…
67217 …[1] bits[15:8] = ram address [2] bits[7:0] = ram address [3] register 0 = ram location [3:0] re…
67226 …1_K2_E5 (0x1<<3) // TX fifo overflow
67227 …WM_REG_INT_STS_TX_OVERFLOW_1_K2_E5_SHIFT 3
67250 … (0x1<<22) // Lane 3 Resolved to 10Mb rate
67252 … (0x1<<23) // Lane 3 Resolved to 100Mb ra…
67255 … (0x1<<0) // This bit masks, when set, the Interrupt bit: N…
67257 … (0x1<<1) // This bit masks, when set, the Interrupt bit: N…
67259 … (0x1<<2) // This bit masks, when set, the Interrupt bit: N…
67261 … (0x1<<3) // This bit masks, when set, the Interrupt …
67262 …WM_REG_INT_MASK_TX_OVERFLOW_1_K2_E5_SHIFT 3
67263 … (0x1<<4) // This bit masks, when set, the Interrupt bit: N…
67265 … (0x1<<5) // This bit masks, when set, the Interrupt bit: N…
67267 … (0x1<<6) // This bit masks, when set, the Interrupt bit: N…
67269 … (0x1<<7) // This bit masks, when set, the Interrupt bit: N…
67271 … (0x1<<8) // This bit masks, when set, the Interrupt bit: N…
67273 … (0x1<<16) // This bit masks, when set, the Interrupt bit: N…
67275 … (0x1<<17) // This bit masks, when set, the Interrupt bit: N…
67277 … (0x1<<18) // This bit masks, when set, the Interrupt bit: N…
67279 … (0x1<<19) // This bit masks, when set, the Interrupt bit: N…
67281 … (0x1<<20) // This bit masks, when set, the Interrupt bit: N…
67283 … (0x1<<21) // This bit masks, when set, the Interrupt bit: N…
67285 … (0x1<<22) // This bit masks, when set, the Interrupt bit: N…
67287 … (0x1<<23) // This bit masks, when set, the Interrupt bit: N…
67296 …OW_1_K2_E5 (0x1<<3) // TX fifo overflow
67297 …WM_REG_INT_STS_WR_TX_OVERFLOW_1_K2_E5_SHIFT 3
67320 … (0x1<<22) // Lane 3 Resolved to 10Mb rate
67322 … (0x1<<23) // Lane 3 Resolved to 100Mb ra…
67331 …LOW_1_K2_E5 (0x1<<3) // TX fifo overflow
67332 …WM_REG_INT_STS_CLR_TX_OVERFLOW_1_K2_E5_SHIFT 3
67355 … (0x1<<22) // Lane 3 Resolved to 10Mb rate
67357 … (0x1<<23) // Lane 3 Resolved to 100Mb ra…
67359 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67360 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67361 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67362 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67364 …bit 9 - LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bi…
67380 …bit 9 - LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bi…
67396 …bit 9 - LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bi…
67412 …bit 9 - LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bi…
67435 …_E5 (0x1<<3) // SGMII PCS Enable…
67436 …WM_REG_PCS_SELECT_SG3_ENA_K2_E5_SHIFT 3
67440 … (0x1<<1) // Auto-Negotiation status. Set to '1' when the Auto…
67444 … (0x1<<3) // Auto-Negotiation status. Set to '1' when the…
67445 …WM_REG_SGMII_PCS_STATUS_SG1_AN_DONE_K2_E5_SHIFT 3
67448 … (0x1<<5) // Auto-Negotiation status. Set to '1' when the Auto…
67452 … (0x1<<7) // Auto-Negotiation status. Set to '1' when the Auto…
67470 … 0x800058UL //Access:RW DataWidth:0x1 // Controls the fast-wake mode for the LPI…
67522 … (0x1<<3) // Indication that the remote has disabled its transmitter and the local Se…
67523 …WM_REG_PORT0_SG_EEE_STATUS_SG0_PMA_RXMODE_QUIET_K2_E5_SHIFT 3
67531 … (0x1<<3) // Indication that the remote has disabled its transmitter and the local Se…
67532 …WM_REG_PORT1_SG_EEE_STATUS_SG1_PMA_RXMODE_QUIET_K2_E5_SHIFT 3
67540 … (0x1<<3) // Indication that the remote has disabled its transmitter and the local Se…
67541 …WM_REG_PORT2_SG_EEE_STATUS_SG2_PMA_RXMODE_QUIET_K2_E5_SHIFT 3
67549 … (0x1<<3) // Indication that the remote has disabled its transmitter and the local Se…
67550 …WM_REG_PORT3_SG_EEE_STATUS_SG3_PMA_RXMODE_QUIET_K2_E5_SHIFT 3
67554 …) the block synchronization state machines could successfully lock onto 66-bit block boundaries on…
67556 …Bit Error Rate indication for all lanes. Depending on mode, when asserted, at least 97 invalid syn…
67558 …-lock or align-done status, depending on current mode, and a cleared hi-ber status. The signal sta…
67561 …e XLGMII reconciliation layer detects the remote sequences received on the link. One bit per port.
67563 …GMII reconciliation layer detects the local fault sequences received on the link. One bit per port.
67565 …ation layer detects the Link Interruption (fault) sequences received on the link. One bit per port.
67568 … the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send …
67570 … the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send …
67572 …s the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send …
67574 …3) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly …
67575 …WM_REG_TX_FAULT_MAC1_TX_LOC_FAULT_K2_E5_SHIFT 3
67576 … the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send …
67578 …s the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send …
67580 … the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send …
67582 … the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send …
67584 …s the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send …
67586 … the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send …
67588 … the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send …
67590 …s the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send …
67603 …rrors in a block. count of the number of times fec_cerr asserted for virtual lane 3. Clear on Read.
67611 …rors in a block. count of the number of times fec_ncerr asserted for virtual lane 3. Clear on Read.
67618 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
67619 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
67620 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
67621 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
67627 … (0x1<<0) // This bit masks, when set, the Parity bit: NW…
67629 … (0x1<<1) // This bit masks, when set, the Parity bit: NW…
67631 … (0x1<<2) // This bit masks, when set, the Parity bit: NW…
67633 … (0x1<<3) // This bit masks, when set, the Parity bi…
67634 …WM_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY_K2_E5_SHIFT 3
67635 … (0x1<<4) // This bit masks, when set, the Parity bit: NW…
67637 … (0x1<<5) // This bit masks, when set, the Parity bit: NW…
67639 … (0x1<<6) // This bit masks, when set, the Parity bit: NW…
67641 … (0x1<<7) // This bit masks, when set, the Parity bit: NW…
67643 … (0x1<<8) // This bit masks, when set, the Parity bit: NW…
67645 … (0x1<<9) // This bit masks, when set, the Parity bit: NW…
67647 … (0x1<<10) // This bit masks, when set, the Parity bit: NW…
67649 … (0x1<<11) // This bit masks, when set, the Parity bit: NW…
67651 … (0x1<<12) // This bit masks, when set, the Parity bit: NW…
67653 … (0x1<<13) // This bit masks, when set, the Parity bit: NW…
67655 … (0x1<<14) // This bit masks, when set, the Parity bit: NW…
67657 … (0x1<<15) // This bit masks, when set, the Parity bit: NW…
67659 … (0x1<<16) // This bit masks, when set, the Parity bit: NW…
67661 … (0x1<<17) // This bit masks, when set, the Parity bit: NW…
67663 … (0x1<<18) // This bit masks, when set, the Parity bit: NW…
67665 … (0x1<<19) // This bit masks, when set, the Parity bit: NW…
67667 … (0x1<<20) // This bit masks, when set, the Parity bit: NW…
67669 … (0x1<<21) // This bit masks, when set, the Parity bit: NW…
67671 … (0x1<<22) // This bit masks, when set, the Parity bit: NW…
67673 … (0x1<<23) // This bit masks, when set, the Parity bit: NW…
67675 … (0x1<<24) // This bit masks, when set, the Parity bit: NW…
67677 … (0x1<<25) // This bit masks, when set, the Parity bit: NW…
67679 … (0x1<<26) // This bit masks, when set, the Parity bit: NW…
67681 … (0x1<<27) // This bit masks, when set, the Parity bit: NW…
67683 … (0x1<<28) // This bit masks, when set, the Parity bit: NW…
67685 … (0x1<<29) // This bit masks, when set, the Parity bit: NW…
67687 … (0x1<<30) // This bit masks, when set, the Parity bit: NW…
67690 … (0x1<<0) // This bit masks, when set, the Parity bit: NW…
67692 … (0x1<<1) // This bit masks, when set, the Parity bit: NW…
67694 … (0x1<<2) // This bit masks, when set, the Parity bit: NW…
67696 … (0x1<<3) // This bit masks, when set, the Parity bi…
67697 …WM_REG_PRTY_MASK_H_1_MEM061_I_MEM_PRTY_K2_E5_SHIFT 3
67698 … (0x1<<4) // This bit masks, when set, the Parity bit: NW…
67700 … (0x1<<5) // This bit masks, when set, the Parity bit: NW…
67702 … (0x1<<6) // This bit masks, when set, the Parity bit: NW…
67704 … (0x1<<7) // This bit masks, when set, the Parity bit: NW…
67706 … (0x1<<8) // This bit masks, when set, the Parity bit: NW…
67708 … (0x1<<9) // This bit masks, when set, the Parity bit: NW…
67710 … (0x1<<10) // This bit masks, when set, the Parity bit: NW…
67712 … (0x1<<11) // This bit masks, when set, the Parity bit: NW…
67714 … (0x1<<12) // This bit masks, when set, the Parity bit: NW…
67716 … (0x1<<13) // This bit masks, when set, the Parity bit: NW…
67718 … (0x1<<14) // This bit masks, when set, the Parity bit: NW…
67720 … (0x1<<15) // This bit masks, when set, the Parity bit: NW…
67722 … (0x1<<16) // This bit masks, when set, the Parity bit: NW…
67724 … (0x1<<17) // This bit masks, when set, the Parity bit: NW…
67726 … (0x1<<18) // This bit masks, when set, the Parity bit: NW…
67728 … (0x1<<19) // This bit masks, when set, the Parity bit: NW…
67730 … (0x1<<20) // This bit masks, when set, the Parity bit: NW…
67732 … (0x1<<21) // This bit masks, when set, the Parity bit: NW…
67734 … (0x1<<22) // This bit masks, when set, the Parity bit: NW…
67736 … (0x1<<23) // This bit masks, when set, the Parity bit: NW…
67738 … (0x1<<24) // This bit masks, when set, the Parity bit: NW…
67740 … (0x1<<25) // This bit masks, when set, the Parity bit: NW…
67742 … (0x1<<26) // This bit masks, when set, the Parity bit: NW…
67744 … (0x1<<27) // This bit masks, when set, the Parity bit: NW…
67746 … (0x1<<28) // This bit masks, when set, the Parity bit: NW…
67748 … (0x1<<29) // This bit masks, when set, the Parity bit: NW…
67750 … (0x1<<30) // This bit masks, when set, the Parity bit: NW…
67753 … (0x1<<0) // This bit masks, when set, the Parity bit: NW…
67755 … (0x1<<1) // This bit masks, when set, the Parity bit: NW…
67757 … (0x1<<2) // This bit masks, when set, the Parity bit: NW…
67759 … (0x1<<3) // This bit masks, when set, the Parity bi…
67760 …WM_REG_PRTY_MASK_H_2_MEM068_I_MEM_PRTY_K2_E5_SHIFT 3
67761 … (0x1<<4) // This bit masks, when set, the Parity bit: NW…
67763 … (0x1<<5) // This bit masks, when set, the Parity bit: NW…
67765 … (0x1<<6) // This bit masks, when set, the Parity bit: NW…
67767 … (0x1<<7) // This bit masks, when set, the Parity bit: NW…
67769 … (0x1<<8) // This bit masks, when set, the Parity bit: NW…
67771 … (0x1<<9) // This bit masks, when set, the Parity bit: NW…
67780 … 0x801000UL //Access:RW DataWidth:0x20 // Register space for MAC port 3. Registers defined i…
67788 …//Access:RW DataWidth:0x10 // Register space for 10/25G PCS RS FEC port 3. Registers defined i…
67796 …0x802580UL //Access:RW DataWidth:0x10 // Register space for 1G PCS port 3. Registers defined i…
67804 …0000UL //Access:RW DataWidth:0x10 // Register space for 10/25G PCS port 3. Registers defined i…
67806 … 0xd80000UL //Access:RW DataWidth:0x1 // Init bit. When set the initi…
67854 …ENABLE_BB_K2 (0x1<<3) // Enables the pcm …
67855 …BF_REG_IF_ENABLE_REG_PCM_IF_ENABLE_BB_K2_SHIFT 3
67857 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
67858 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
67859 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
67860 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
67866 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
67867 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
67869 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
67870 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
67873 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
67874 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
67877 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
67878 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
67891 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
67900 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
67903 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
67905 … (0x1<<1) // This bit masks, when set, the Parity bit: PB…
67907 … (0x1<<2) // This bit masks, when set, the Parity bit: PB…
67909 … (0x1<<3) // This bit masks, when set, the Parity bi…
67910 …BF_REG_PRTY_MASK_H_0_MEM040_I_ECC_RF_INT_E5_SHIFT 3
67911 … (0x1<<3) // This bit masks, when set, the Parity bi…
67912 …BF_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_K2_SHIFT 3
67913 … (0x1<<4) // This bit masks, when set, the Parity bit: PB…
67915 … (0x1<<5) // This bit masks, when set, the Parity bit: PB…
67917 … (0x1<<6) // This bit masks, when set, the Parity bit: PB…
67919 … (0x1<<7) // This bit masks, when set, the Parity bit: PB…
67921 … (0x1<<8) // This bit masks, when set, the Parity bit: PB…
67923 … (0x1<<9) // This bit masks, when set, the Parity bit: PB…
67925 … (0x1<<10) // This bit masks, when set, the Parity bit: PB…
67927 … (0x1<<11) // This bit masks, when set, the Parity bit: PB…
67929 … (0x1<<12) // This bit masks, when set, the Parity bit: PB…
67931 … (0x1<<13) // This bit masks, when set, the Parity bit: PB…
67933 … (0x1<<14) // This bit masks, when set, the Parity bit: PB…
67935 … (0x1<<15) // This bit masks, when set, the Parity bit: PB…
67937 … (0x1<<16) // This bit masks, when set, the Parity bit: PB…
67939 … (0x1<<17) // This bit masks, when set, the Parity bit: PB…
67941 … (0x1<<18) // This bit masks, when set, the Parity bit: PB…
67943 … (0x1<<19) // This bit masks, when set, the Parity bit: PB…
67945 … (0x1<<20) // This bit masks, when set, the Parity bit: PB…
67947 … (0x1<<21) // This bit masks, when set, the Parity bit: PB…
67949 … (0x1<<22) // This bit masks, when set, the Parity bit: PB…
67951 … (0x1<<23) // This bit masks, when set, the Parity bit: PB…
67953 … (0x1<<24) // This bit masks, when set, the Parity bit: PB…
67955 … (0x1<<25) // This bit masks, when set, the Parity bit: PB…
67957 … (0x1<<26) // This bit masks, when set, the Parity bit: PB…
67959 … (0x1<<27) // This bit masks, when set, the Parity bit: PB…
67961 … (0x1<<24) // This bit masks, when set, the Parity bit: PB…
67963 … (0x1<<28) // This bit masks, when set, the Parity bit: PB…
67965 … (0x1<<25) // This bit masks, when set, the Parity bit: PB…
67967 … (0x1<<29) // This bit masks, when set, the Parity bit: PB…
67969 … (0x1<<30) // This bit masks, when set, the Parity bit: PB…
67971 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
67973 … (0x1<<1) // This bit masks, when set, the Parity bit: PB…
67975 … (0x1<<2) // This bit masks, when set, the Parity bit: PB…
67977 … (0x1<<4) // This bit masks, when set, the Parity bit: PB…
67979 … (0x1<<5) // This bit masks, when set, the Parity bit: PB…
67981 … (0x1<<6) // This bit masks, when set, the Parity bit: PB…
67983 … (0x1<<7) // This bit masks, when set, the Parity bit: PB…
67985 … (0x1<<8) // This bit masks, when set, the Parity bit: PB…
67987 … (0x1<<9) // This bit masks, when set, the Parity bit: PB…
67989 … (0x1<<10) // This bit masks, when set, the Parity bit: PB…
67991 … (0x1<<11) // This bit masks, when set, the Parity bit: PB…
67993 … (0x1<<12) // This bit masks, when set, the Parity bit: PB…
67995 … (0x1<<13) // This bit masks, when set, the Parity bit: PB…
67997 … (0x1<<14) // This bit masks, when set, the Parity bit: PB…
67999 … (0x1<<15) // This bit masks, when set, the Parity bit: PB…
68001 … (0x1<<16) // This bit masks, when set, the Parity bit: PB…
68003 … (0x1<<17) // This bit masks, when set, the Parity bit: PB…
68005 … (0x1<<18) // This bit masks, when set, the Parity bit: PB…
68007 … (0x1<<19) // This bit masks, when set, the Parity bit: PB…
68009 … (0x1<<20) // This bit masks, when set, the Parity bit: PB…
68011 … (0x1<<21) // This bit masks, when set, the Parity bit: PB…
68013 … (0x1<<22) // This bit masks, when set, the Parity bit: PB…
68015 … (0x1<<23) // This bit masks, when set, the Parity bit: PB…
68017 … (0x1<<26) // This bit masks, when set, the Parity bit: PB…
68019 … (0x1<<27) // This bit masks, when set, the Parity bit: PB…
68021 … (0x1<<28) // This bit masks, when set, the Parity bit: PB…
68023 … (0x1<<29) // This bit masks, when set, the Parity bit: PB…
68025 … (0x1<<30) // This bit masks, when set, the Parity bit: PB…
68028 … (0x1<<21) // This bit masks, when set, the Parity bit: PB…
68030 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
68032 … (0x1<<23) // This bit masks, when set, the Parity bit: PB…
68034 … (0x1<<1) // This bit masks, when set, the Parity bit: PB…
68036 … (0x1<<10) // This bit masks, when set, the Parity bit: PB…
68038 … (0x1<<2) // This bit masks, when set, the Parity bit: PB…
68040 … (0x1<<3) // This bit masks, when set, the Parity bi…
68041 …BF_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_E5_SHIFT 3
68042 … (0x1<<12) // This bit masks, when set, the Parity bit: PB…
68044 … (0x1<<4) // This bit masks, when set, the Parity bit: PB…
68046 … (0x1<<11) // This bit masks, when set, the Parity bit: PB…
68048 … (0x1<<5) // This bit masks, when set, the Parity bit: PB…
68050 … (0x1<<19) // This bit masks, when set, the Parity bit: PB…
68052 … (0x1<<6) // This bit masks, when set, the Parity bit: PB…
68054 … (0x1<<20) // This bit masks, when set, the Parity bit: PB…
68056 … (0x1<<7) // This bit masks, when set, the Parity bit: PB…
68058 … (0x1<<5) // This bit masks, when set, the Parity bit: PB…
68060 … (0x1<<8) // This bit masks, when set, the Parity bit: PB…
68062 … (0x1<<4) // This bit masks, when set, the Parity bit: PB…
68064 … (0x1<<9) // This bit masks, when set, the Parity bit: PB…
68066 … (0x1<<10) // This bit masks, when set, the Parity bit: PB…
68068 … (0x1<<16) // This bit masks, when set, the Parity bit: PB…
68070 … (0x1<<11) // This bit masks, when set, the Parity bit: PB…
68072 … (0x1<<9) // This bit masks, when set, the Parity bit: PB…
68074 … (0x1<<12) // This bit masks, when set, the Parity bit: PB…
68076 … (0x1<<8) // This bit masks, when set, the Parity bit: PB…
68078 … (0x1<<13) // This bit masks, when set, the Parity bit: PB…
68080 … (0x1<<6) // This bit masks, when set, the Parity bit: PB…
68082 … (0x1<<14) // This bit masks, when set, the Parity bit: PB…
68084 … (0x1<<7) // This bit masks, when set, the Parity bit: PB…
68086 … (0x1<<15) // This bit masks, when set, the Parity bit: PB…
68088 … (0x1<<16) // This bit masks, when set, the Parity bit: PB…
68090 … (0x1<<17) // This bit masks, when set, the Parity bit: PB…
68092 … (0x1<<18) // This bit masks, when set, the Parity bit: PB…
68094 … (0x1<<1) // This bit masks, when set, the Parity bit: PB…
68096 … (0x1<<19) // This bit masks, when set, the Parity bit: PB…
68098 … (0x1<<3) // This bit masks, when set, the Parity bi…
68099 …BF_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_K2_SHIFT 3
68100 … (0x1<<20) // This bit masks, when set, the Parity bit: PB…
68102 … (0x1<<2) // This bit masks, when set, the Parity bit: PB…
68104 … (0x1<<21) // This bit masks, when set, the Parity bit: PB…
68106 … (0x1<<18) // This bit masks, when set, the Parity bit: PB…
68108 … (0x1<<22) // This bit masks, when set, the Parity bit: PB…
68110 … (0x1<<23) // This bit masks, when set, the Parity bit: PB…
68112 … (0x1<<26) // This bit masks, when set, the Parity bit: PB…
68114 … (0x1<<24) // This bit masks, when set, the Parity bit: PB…
68116 … (0x1<<24) // This bit masks, when set, the Parity bit: PB…
68118 … (0x1<<25) // This bit masks, when set, the Parity bit: PB…
68120 … (0x1<<25) // This bit masks, when set, the Parity bit: PB…
68122 … (0x1<<26) // This bit masks, when set, the Parity bit: PB…
68124 … (0x1<<27) // This bit masks, when set, the Parity bit: PB…
68126 … (0x1<<28) // This bit masks, when set, the Parity bit: PB…
68128 … (0x1<<29) // This bit masks, when set, the Parity bit: PB…
68130 … (0x1<<30) // This bit masks, when set, the Parity bit: PB…
68132 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
68134 … (0x1<<13) // This bit masks, when set, the Parity bit: PB…
68136 … (0x1<<14) // This bit masks, when set, the Parity bit: PB…
68138 … (0x1<<15) // This bit masks, when set, the Parity bit: PB…
68140 … (0x1<<17) // This bit masks, when set, the Parity bit: PB…
68142 … (0x1<<22) // This bit masks, when set, the Parity bit: PB…
68144 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
68146 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
68148 … (0x1<<1) // This bit masks, when set, the Parity bit: PB…
68150 … (0x1<<2) // This bit masks, when set, the Parity bit: PB…
68152 … (0x1<<3) // This bit masks, when set, the Parity bi…
68153 …BF_REG_PRTY_MASK_H_2_MEM017_I_MEM_PRTY_E5_SHIFT 3
68154 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
68155 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
68156 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
68157 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
68166 …40_I_ECC_EN_E5 (0x1<<3) // Enable ECC for m…
68167 …BF_REG_MEM_ECC_ENABLE_0_MEM040_I_ECC_EN_E5_SHIFT 3
68168 …03_I_ECC_EN_BB_K2 (0x1<<3) // Enable ECC for m…
68169 …BF_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_BB_K2_SHIFT 3
68262 …_MEM040_I_ECC_PRTY_E5 (0x1<<3) // Set parity only …
68263 …BF_REG_MEM_ECC_PARITY_ONLY_0_MEM040_I_ECC_PRTY_E5_SHIFT 3
68264 …_MEM003_I_ECC_PRTY_BB_K2 (0x1<<3) // Set parity only …
68265 …BF_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_BB_K2_SHIFT 3
68358 …ED_0_MEM040_I_ECC_CORRECT_E5 (0x1<<3) // Record if a corr…
68359 …BF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM040_I_ECC_CORRECT_E5_SHIFT 3
68360 …ED_0_MEM003_I_ECC_CORRECT_BB_K2 (0x1<<3) // Record if a corr…
68361 …BF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_BB_K2_SHIFT 3
68448 …0400UL //Access:RW DataWidth:0x3 // PXP read request interface initial credit - transoriented.
68449 … 0xd80404UL //Access:RW DataWidth:0x6 // TDIF pass-through command inter…
68450 … 0xd80408UL //Access:RW DataWidth:0x6 // TDIF non_pass-through command inter…
68452 …10UL //Access:RW DataWidth:0x2 // PXP internal write interface initial credit - transoriented.
68453 … 0xd80414UL //Access:RW DataWidth:0x3 // TM interface initial credit - transoriented.
68473 … 0xd8048cUL //Access:RW DataWidth:0x10 // The Ethernet type value for L2 tag 3.
68479 …L //Access:RW DataWidth:0x3 // The length of the info field for L2 tag 3. The length is betw…
68482 …-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port. …
68483 …-port: Bit-map indicating which L2 hdrs may appear after the LLC header on this port. This applie…
68484 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port. This applies to …
68485 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port. This applies to …
68486 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port. This applies to …
68487 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port. This applies to …
68488 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port. This applies to …
68489 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port. This applies to …
68490 …-port: Bit-map indicating which headers must appear in the packet on this port. This applies to t…
68491 … 0xd804d4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68492 … 0xd804d8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68493 … 0xd804dcUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68494 … 0xd804e0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68495 … 0xd804e4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68496 … 0xd804e8UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68497 … 0xd804ecUL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68498 … 0xd804f0UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68499 … 0xd804f4UL //Access:RW DataWidth:0x8 // Per-port: Bit-map indicating w…
68511 … 0xd80524UL //Access:RW DataWidth:0x1 // Per-port: Flag to compar…
68519 …AL_FIRSTMAC_EN_E5 (0x1<<3) // Enables inclusio…
68520 …BF_REG_SAME_AS_LAST_CONFIG_SAL_FIRSTMAC_EN_E5_SHIFT 3
68529 … (0x1<<9) // Enables inclusion of Tenant ID Exist bit in lookup tuple. If…
68538 …LD_CONFIG_SAL_FLEX_UPPER_BYTE_OFFSET_E5 (0xf<<3) // Byte offset (wit…
68539 …BF_REG_SAME_AS_LAST_FLEX_FIELD_CONFIG_SAL_FLEX_UPPER_BYTE_OFFSET_E5_SHIFT 3
68542 …TGFS message. 0: Basic Parsing Info; 1: Raw L3/L4; 2: Extended Tunnel Info; 3: Extracted Header 4:…
68544 …used only if sal_flex_upper_bytes is not 0, and number of bytes selected = 8 - sal_flex_upper_bytes
68548 …TGFS message. 0: Basic Parsing Info; 1: Raw L3/L4; 2: Extended Tunnel Info; 3: Extracted Header 4:…
68550 …ataWidth:0x20 // Masks 64 bit Flexible field used for Same-as-last lookup. A 0 in each bit masks…
68551 …ataWidth:0x20 // Masks 64 bit Flexible field used for Same-as-last lookup. A 0 in each bit masks…
68571 …R_TYPE_3_E5 (0xff<<24) // ipv6 extension uniform header type 3
68605 …N_BIT_E5 (0x1<<4) // Chicken bit to use single fc en…
68614 …IDS_IPV6_EXT_UNIFORM_HDR_TYPE_3_VALID_E5 (0x1<<3) // If set, validate…
68615 …BF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_3_VALID_E5_SHIFT 3
68641 …rder. Reset value is in the order from left to right: tag0; tag1; tag2; tag3; tag4; tag5; llc-snap.
68642 …//Access:RW DataWidth:0x4 // Per-Port: Specifies the flexible L2 tag to be used for T-tag. T…
68645 …alue. A zero in this register will cause the corresponding bit to not be included …
68646 …alue. A zero in this register will cause the corresponding bit to not be included …
68651 …ic. Setting to 1 selects or unmasks the condition. Bit 0 of this mask corresponds to Parsing Error…
68655 …vent ID modification logic. Setting to 1 selects or unmasks the condition. Bit 0 of this mask corr…
68658 … Setting to 1 selects or unmasks the condition. Bit 0 of this mask corresponds to First L2 Tag Exi…
68660 … Setting to 1 selects or unmasks the condition. Bit 0 of this mask corresponds to Inner L2 Tag Exi…
68663 …DataWidth:0xb // Number of shared BTB 256 byte blocks which can be used by all TC-s in the port.
68666 …nibble to MS nibble holds the TC number of the corresponding priority. bits 3:0 hold the TC number…
68667 …-priority w/ anti-starvation arbiter is a RR arbiter. A value of all ones means no RR slots; i.e. …
68668 …W DataWidth:0x8 // L2 EDPM threshold in 256 byte blocks. Only if all TC-s have allocated bloc…
68669 …ld in 256 byte blocks. Only if all TC-s in port N have allocated blocks above this threshold, the …
68670 … DataWidth:0xb // RDMA EDPM threshold in 256 byte blocks. Only if all TC-s have allocated bloc…
68671 … 0xd80600UL //Access:RW DataWidth:0x10 // 1st bit mask used to contro…
68672 … 0xd80604UL //Access:RW DataWidth:0x10 // 2nd bit mask used to contro…
68673 … 0xd80608UL //Access:RW DataWidth:0x10 // 3rd bit mask used to cont…
68674 … 0xd8060cUL //Access:RW DataWidth:0x10 // 4th bit mask used to contro…
68759 …Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 3.
68760 … 0xd80764UL //Access:RW DataWidth:0x5 // Almost full threshold for VOQ 3 in the YSTORM comman…
68761 …ess:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 3 (after ending the c…
68762 … 0xd8076cUL //Access:RC DataWidth:0x20 // Number of commands received on VOQ 3 from YSTORM.
68763 … 0xd80770UL //Access:R DataWidth:0xa // Number of commands in the Y command queue of VOQ 3.
68764 …yclic counter for number of 16 byte lines freed from the Y command queue of VOQ 3. Reset upon init.
68765 …/Access:R DataWidth:0xd // Number of 16 bytes lines occupied in the Y command queue of VOQ 3.
68766 …0xd8077cUL //Access:RW DataWidth:0xb // The number of BTB 256 byte blocks guaranteed for VOQ 3
68768 …0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 3
68774 …cess:R DataWidth:0xc // Number of blocks allocated in the BTB for VOQ 3 in both guaranteed a…
68775 …idth:0x20 // Cyclic counter for number of blocks allocated (producer) for VOQ 3. Reset upon init.
68776 …Width:0x20 // Cyclic counter for number of blocks released (consumer) for VOQ 3. Reset upon init.
69362 …OR (0x1<<3) // Parameter FIFO e…
69363 …BF_PB1_REG_INT_STS_PFIFO_ERROR_SHIFT 3
69375 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
69377 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
69379 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
69381 … (0x1<<3) // This bit masks, when set, the Interrupt …
69382 …BF_PB1_REG_INT_MASK_PFIFO_ERROR_SHIFT 3
69383 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
69385 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
69387 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
69389 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
69391 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
69400 …ERROR (0x1<<3) // Parameter FIFO e…
69401 …BF_PB1_REG_INT_STS_WR_PFIFO_ERROR_SHIFT 3
69419 …_ERROR (0x1<<3) // Parameter FIFO e…
69420 …BF_PB1_REG_INT_STS_CLR_PFIFO_ERROR_SHIFT 3
69432 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
69441 …_DISABLE (0x1<<3) // Disables EOP che…
69442 …BF_PB1_REG_CONTROL_EOP_CHECK_DISABLE_SHIFT 3
69453 …ived on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
69455 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69456 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69457 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69458 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69459 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69460 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69461 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69462 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69463 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69464 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69465 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69466 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69477 …bit of this register. Bits 31:29 provide additional information about the instruction. Bit 31 in…
69479 …er being executed at the time EOP error is detected. The task passthrough bit is not kept and is …
69487 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
69488 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
69489 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
69490 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
69491 … 0xda2000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
69502 …OR (0x1<<3) // Parameter FIFO e…
69503 …BF_PB2_REG_INT_STS_PFIFO_ERROR_SHIFT 3
69515 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
69517 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
69519 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
69521 … (0x1<<3) // This bit masks, when set, the Interrupt …
69522 …BF_PB2_REG_INT_MASK_PFIFO_ERROR_SHIFT 3
69523 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
69525 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
69527 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
69529 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
69531 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
69540 …ERROR (0x1<<3) // Parameter FIFO e…
69541 …BF_PB2_REG_INT_STS_WR_PFIFO_ERROR_SHIFT 3
69559 …_ERROR (0x1<<3) // Parameter FIFO e…
69560 …BF_PB2_REG_INT_STS_CLR_PFIFO_ERROR_SHIFT 3
69572 … (0x1<<0) // This bit masks, when set, the Parity bit: PB…
69581 …_DISABLE (0x1<<3) // Disables EOP che…
69582 …BF_PB2_REG_CONTROL_EOP_CHECK_DISABLE_SHIFT 3
69593 …ived on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
69595 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69596 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69597 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69598 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69599 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69600 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69601 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69602 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69603 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69604 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69605 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69606 … bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits…
69617 …bit of this register. Bits 31:29 provide additional information about the instruction. Bit 31 in…
69619 …er being executed at the time EOP error is detected. The task passthrough bit is not kept and is …
69627 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
69628 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
69629 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
69630 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
69631 … 0xda6000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
69635 … // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en re…
69636 … // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en re…
69637 …bit should be set when initialization of all BRTB registers and memories is finished. BRTB will fi…
69643 …_ERROR (0x1<<3) // Read packet clie…
69644 …TB_REG_INT_STS_0_RC_PKT0_LEN_ERROR_SHIFT 3
69672 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
69674 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
69676 … (0x1<<3) // This bit masks, when set, the Interrupt …
69677 …TB_REG_INT_MASK_0_RC_PKT0_LEN_ERROR_SHIFT 3
69678 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
69680 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
69682 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
69684 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
69686 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
69688 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
69690 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
69692 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
69694 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
69696 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
69698 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
69700 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
69702 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
69709 …LEN_ERROR (0x1<<3) // Read packet clie…
69710 …TB_REG_INT_STS_WR_0_RC_PKT0_LEN_ERROR_SHIFT 3
69742 …_LEN_ERROR (0x1<<3) // Read packet clie…
69743 …TB_REG_INT_STS_CLR_0_RC_PKT0_LEN_ERROR_SHIFT 3
69775 …O_ERROR (0x1<<3) // Input FIFO error…
69776 …TB_REG_INT_STS_1_WC0_INP_FIFO_ERROR_SHIFT 3
69804 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
69806 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
69808 … (0x1<<3) // This bit masks, when set, the Interrupt …
69809 …TB_REG_INT_MASK_1_WC0_INP_FIFO_ERROR_SHIFT 3
69810 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
69812 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
69814 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
69816 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
69818 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
69820 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
69822 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
69824 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
69826 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
69828 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
69830 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
69832 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
69834 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
69841 …FIFO_ERROR (0x1<<3) // Input FIFO error…
69842 …TB_REG_INT_STS_WR_1_WC0_INP_FIFO_ERROR_SHIFT 3
69874 …_FIFO_ERROR (0x1<<3) // Input FIFO error…
69875 …TB_REG_INT_STS_CLR_1_WC0_INP_FIFO_ERROR_SHIFT 3
69912 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
69914 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
69916 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
69918 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
69945 …_FIFO_ERROR (0x1<<3) // Read packet clie…
69946 …TB_REG_INT_STS_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT 3
70004 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
70006 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
70008 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
70010 … (0x1<<3) // This bit masks, when set, the Interrupt …
70011 …TB_REG_INT_MASK_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT 3
70012 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
70014 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
70016 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
70018 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
70020 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
70022 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
70024 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
70026 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
70028 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
70030 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
70032 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
70034 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
70036 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
70038 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
70040 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
70042 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
70044 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
70046 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
70048 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
70050 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
70052 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
70054 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
70056 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
70058 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
70060 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
70062 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
70064 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
70066 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
70075 …BLK_FIFO_ERROR (0x1<<3) // Read packet clie…
70076 …TB_REG_INT_STS_WR_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT 3
70140 …_BLK_FIFO_ERROR (0x1<<3) // Read packet clie…
70141 …TB_REG_INT_STS_CLR_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT 3
70246 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
70248 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
70250 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
70252 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
70254 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
70256 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
70258 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
70260 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
70262 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
70264 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
70266 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
70268 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
70270 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
70272 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
70274 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
70276 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
70278 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
70280 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
70282 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
70284 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
70286 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
70288 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
70290 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
70393 …E_FIFO_ERROR (0x1<<3) // Read packet clie…
70394 …TB_REG_INT_STS_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT 3
70452 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
70454 … (0x1<<1) // This bit masks, when set, the Interrupt bit: B…
70456 … (0x1<<2) // This bit masks, when set, the Interrupt bit: B…
70458 … (0x1<<3) // This bit masks, when set, the Interrupt …
70459 …TB_REG_INT_MASK_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT 3
70460 … (0x1<<4) // This bit masks, when set, the Interrupt bit: B…
70462 … (0x1<<5) // This bit masks, when set, the Interrupt bit: B…
70464 … (0x1<<6) // This bit masks, when set, the Interrupt bit: B…
70466 … (0x1<<7) // This bit masks, when set, the Interrupt bit: B…
70468 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
70470 … (0x1<<9) // This bit masks, when set, the Interrupt bit: B…
70472 … (0x1<<10) // This bit masks, when set, the Interrupt bit: B…
70474 … (0x1<<11) // This bit masks, when set, the Interrupt bit: B…
70476 … (0x1<<12) // This bit masks, when set, the Interrupt bit: B…
70478 … (0x1<<13) // This bit masks, when set, the Interrupt bit: B…
70480 … (0x1<<14) // This bit masks, when set, the Interrupt bit: B…
70482 … (0x1<<15) // This bit masks, when set, the Interrupt bit: B…
70484 … (0x1<<16) // This bit masks, when set, the Interrupt bit: B…
70486 … (0x1<<17) // This bit masks, when set, the Interrupt bit: B…
70488 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
70490 … (0x1<<19) // This bit masks, when set, the Interrupt bit: B…
70492 … (0x1<<20) // This bit masks, when set, the Interrupt bit: B…
70494 … (0x1<<21) // This bit masks, when set, the Interrupt bit: B…
70496 … (0x1<<22) // This bit masks, when set, the Interrupt bit: B…
70498 … (0x1<<23) // This bit masks, when set, the Interrupt bit: B…
70500 … (0x1<<24) // This bit masks, when set, the Interrupt bit: B…
70502 … (0x1<<25) // This bit masks, when set, the Interrupt bit: B…
70504 … (0x1<<26) // This bit masks, when set, the Interrupt bit: B…
70506 … (0x1<<27) // This bit masks, when set, the Interrupt bit: B…
70508 … (0x1<<28) // This bit masks, when set, the Interrupt bit: B…
70510 … (0x1<<29) // This bit masks, when set, the Interrupt bit: B…
70512 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
70514 … (0x1<<31) // This bit masks, when set, the Interrupt bit: B…
70523 …SIDE_FIFO_ERROR (0x1<<3) // Read packet clie…
70524 …TB_REG_INT_STS_WR_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT 3
70588 …_SIDE_FIFO_ERROR (0x1<<3) // Read packet clie…
70589 …TB_REG_INT_STS_CLR_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT 3
70650 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
70659 … (0x1<<0) // Warning! Check this bit connection for E4 A…
70662 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
70665 … (0x1<<0) // Warning! Check this bit connection for E4 A…
70668 … (0x1<<0) // Warning! Check this bit connection for E4 A…
70671 … (0x1<<0) // Warning! Check this bit connection for E4 A…
70674 … (0x1<<0) // This bit masks, when set, the Interrupt bit: B…
70677 … (0x1<<0) // Warning! Check this bit connection for E4 A…
70680 … (0x1<<0) // Warning! Check this bit connection for E4 A…
70686 … (0x1<<30) // This bit masks, when set, the Interrupt bit: B…
70700 … (0x1<<8) // This bit masks, when set, the Interrupt bit: B…
70702 … (0x1<<18) // This bit masks, when set, the Interrupt bit: B…
70715 … (0x1<<0) // This bit masks, when set, the Parity bit: BT…
70717 … (0x1<<1) // This bit masks, when set, the Parity bit: BT…
70719 … (0x1<<2) // This bit masks, when set, the Parity bit: BT…
70721 … (0x1<<3) // This bit masks, when set, the Parity bi…
70722 …TB_REG_PRTY_MASK_LL_BANK3_MEM_PRTY_SHIFT 3
70723 … (0x1<<4) // This bit masks, when set, the Parity bit: BT…
70726 … (0x1<<0) // This bit masks, when set, the Parity bit: BT…
70728 … (0x1<<1) // This bit masks, when set, the Parity bit: BT…
70730 … (0x1<<2) // This bit masks, when set, the Parity bit: BT…
70732 … (0x1<<3) // This bit masks, when set, the Parity bi…
70733 …TB_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_SHIFT 3
70734 … (0x1<<4) // This bit masks, when set, the Parity bit: BT…
70736 … (0x1<<5) // This bit masks, when set, the Parity bit: BT…
70738 … (0x1<<6) // This bit masks, when set, the Parity bit: BT…
70740 … (0x1<<7) // This bit masks, when set, the Parity bit: BT…
70742 … (0x1<<8) // This bit masks, when set, the Parity bit: BT…
70744 … (0x1<<9) // This bit masks, when set, the Parity bit: BT…
70746 … (0x1<<10) // This bit masks, when set, the Parity bit: BT…
70748 … (0x1<<11) // This bit masks, when set, the Parity bit: BT…
70750 … (0x1<<12) // This bit masks, when set, the Parity bit: BT…
70752 … (0x1<<13) // This bit masks, when set, the Parity bit: BT…
70754 … (0x1<<14) // This bit masks, when set, the Parity bit: BT…
70756 … (0x1<<15) // This bit masks, when set, the Parity bit: BT…
70758 … (0x1<<16) // This bit masks, when set, the Parity bit: BT…
70760 … (0x1<<17) // This bit masks, when set, the Parity bit: BT…
70762 … (0x1<<18) // This bit masks, when set, the Parity bit: BT…
70764 … (0x1<<19) // This bit masks, when set, the Parity bit: BT…
70766 … (0x1<<20) // This bit masks, when set, the Parity bit: BT…
70768 … (0x1<<21) // This bit masks, when set, the Parity bit: BT…
70770 … (0x1<<22) // This bit masks, when set, the Parity bit: BT…
70772 … (0x1<<23) // This bit masks, when set, the Parity bit: BT…
70774 … (0x1<<16) // This bit masks, when set, the Parity bit: BT…
70776 … (0x1<<24) // This bit masks, when set, the Parity bit: BT…
70778 … (0x1<<17) // This bit masks, when set, the Parity bit: BT…
70780 … (0x1<<25) // This bit masks, when set, the Parity bit: BT…
70782 … (0x1<<18) // This bit masks, when set, the Parity bit: BT…
70784 … (0x1<<26) // This bit masks, when set, the Parity bit: BT…
70786 … (0x1<<19) // This bit masks, when set, the Parity bit: BT…
70788 … (0x1<<27) // This bit masks, when set, the Parity bit: BT…
70790 … (0x1<<17) // This bit masks, when set, the Parity bit: BT…
70792 … (0x1<<20) // This bit masks, when set, the Parity bit: BT…
70794 … (0x1<<28) // This bit masks, when set, the Parity bit: BT…
70796 … (0x1<<21) // This bit masks, when set, the Parity bit: BT…
70798 … (0x1<<29) // This bit masks, when set, the Parity bit: BT…
70800 … (0x1<<22) // This bit masks, when set, the Parity bit: BT…
70802 … (0x1<<30) // This bit masks, when set, the Parity bit: BT…
70804 … (0x1<<23) // This bit masks, when set, the Parity bit: BT…
70806 … (0x1<<24) // This bit masks, when set, the Parity bit: BT…
70808 … (0x1<<22) // This bit masks, when set, the Parity bit: BT…
70810 … (0x1<<25) // This bit masks, when set, the Parity bit: BT…
70812 … (0x1<<21) // This bit masks, when set, the Parity bit: BT…
70814 … (0x1<<26) // This bit masks, when set, the Parity bit: BT…
70816 … (0x1<<20) // This bit masks, when set, the Parity bit: BT…
70818 … (0x1<<27) // This bit masks, when set, the Parity bit: BT…
70820 … (0x1<<19) // This bit masks, when set, the Parity bit: BT…
70822 … (0x1<<28) // This bit masks, when set, the Parity bit: BT…
70824 … (0x1<<18) // This bit masks, when set, the Parity bit: BT…
70826 … (0x1<<29) // This bit masks, when set, the Parity bit: BT…
70828 … (0x1<<16) // This bit masks, when set, the Parity bit: BT…
70830 … (0x1<<30) // This bit masks, when set, the Parity bit: BT…
70832 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
70834 … (0x1<<0) // This bit masks, when set, the Parity bit: BT…
70836 … (0x1<<1) // This bit masks, when set, the Parity bit: BT…
70838 … (0x1<<2) // This bit masks, when set, the Parity bit: BT…
70840 … (0x1<<3) // This bit masks, when set, the Parity bi…
70841 …TB_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_E5_SHIFT 3
70842 … (0x1<<4) // This bit masks, when set, the Parity bit: BT…
70844 … (0x1<<5) // This bit masks, when set, the Parity bit: BT…
70846 … (0x1<<6) // This bit masks, when set, the Parity bit: BT…
70848 … (0x1<<7) // This bit masks, when set, the Parity bit: BT…
70850 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
70851 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
70852 …3].BB_BANK_BB_GEN_IF.i_bb_bank.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of ea…
70862 … (0x1<<3) // Enable ECC for memory ecc instance btb.BB_BANK_K…
70863 …TB_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_EN_SHIFT 3
70900 … (0x1<<22) // Enable ECC for memory ecc instance btb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i…
70902 … (0x1<<23) // Enable ECC for memory ecc instance btb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i…
70904 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
70914 … (0x1<<3) // Set parity only for memory ecc instance btb.BB_BANK…
70915 …TB_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_PRTY_SHIFT 3
70952 …(0x1<<22) // Set parity only for memory ecc instance btb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i…
70954 …(0x1<<23) // Set parity only for memory ecc instance btb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i…
70956 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
70966 … (0x1<<3) // Record if a correctable error occurred on memory ecc instance …
70967 …TB_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_CORRECT_SHIFT 3
71004 … a correctable error occurred on memory ecc instance btb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i…
71006 … a correctable error occurred on memory ecc instance btb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i…
71008 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71012 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71013 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71014 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71015 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71016 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71017 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71018 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71019 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71020 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
71021 … to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_…
71022 …04UL //Access:RW DataWidth:0xa // Number of valid bytes in header in 16-bytes resolution. Aft…
71030 … 0xdb0844UL //Access:RW DataWidth:0x8 // There is bit for each PACKET read client. When bit …
71031 …L_EN/d in Existance. Value for 40G mode (reset value, both BB and K2): 2880 - (34 + 2 + (9600+32)/…
71032 …bit for each PACKET read client. Bit 0 suits to client 0 and so on. If bit is set then packet will…
71034 …ty then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s…
71036 …ty then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s…
71038 …ty then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s…
71040 …ty then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s…
71042 …ty then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s…
71044 …ty then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s…
71046 …3 read client that is used in link list and big ram arbiters. If all read clients have identical …
71048 …3 read client that is used in link list and big ram arbiters. If all read clients have identical …
71050 …bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then packet wil…
71051 …bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then highest pr…
71052 …riority for SOP read client to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/…
71053 …quest of write client group to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/…
71054 …ple clients of identical priority is supported. Possible values are 1-3. Priority 3 is highest::s/…
71068 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
71069 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
71070 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
71071 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
71077 …bit per each read client interface: B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG …
71079 … (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate int…
71081 …bit per write client interface: B0 - NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - …
71084 …bit per each read client interface: B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG …
71086 … (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate int…
71088 … (0x1<<11) // There is bit for almost full interfaces. When bit is set then almost full inte…
71090 …bit for packet avalable interfaces. When bit is set then packet avalable interface is enabled. Whe…
71092 …s bit for release interfaces. When bit is set then release interface is enabled. When bit is reset…
71097 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
71101 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
71102 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
71103 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
71104 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
71105 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
71106 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
71107 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
71108 …us of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B3…
71109 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
71110 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
71111 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
71112 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
71113 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
71114 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
71115 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
71116 …us of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B3…
71117 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71118 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71119 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71120 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71121 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71122 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71123 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71124 …- read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 - - read client 3. 32 b…
71125 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
71126 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
71127 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
71136 …guration value will be 3, meaning after 1/(2power3) of the packet arrived it can be sent to the re…
71141 …ter for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - qu…
71144 … erad packet client interface: 0-NIG main port0; 1-NIG LB port0; 2-NIG main port1; 2-NIG LB port1.…
71148 … read packet client interface: 0-NIG main port0; 1-NIG LB port0; 2-NIG main port1; 2-NIG LB port1.…
71151 … strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}
71155 …Access:RW DataWidth:0xc // Link list dual port memory that contains per-block descriptor::s/B…
71156 …Access:RW DataWidth:0xd // Link list dual port memory that contains per-block descriptor::s/B…
71163 …1<<31) // This bit is set by the driver before it sets the MCP_RESET bit. When set this bit disabl…
71176 … (0x1<<30) // This bit is set when the watchdog timer expires. This bit reflects state of the …
71178 … (0x1<<31) // This bit is set any time an …
71183 …BLE (0x1<<31) // When this bit is set by the drive…
71190 … (0x1<<31) // When set this bit validates bits 10-0 of this r…
71195 … (0x1<<30) // When set this bit causes MCP heartbea…
71197 … (0x1<<31) // When set this bit resets the heartbea…
71202 … (0x1<<30) // When set this bit resets the watchdog…
71204 … (0x1<<31) // When set this bit resets the watchdog…
71209 … (0x1<<27) // When set this bit enables watchdog ti…
71211 …STALL_ENABLE (0x1<<28) // When this bit is set, expiration …
71213 … 0 and that it requires driver's attention. Low to high transition on this bit should generate MCP…
71215 … // When set this bit enables the watchdog timer to reset the MCP instead of halting it. The watch…
71217 … (0x1<<31) // When set this bit enables watchdog ti…
71224 …bit in order to obtain the lock over the shared resources within the chip. The actual "lock" is im…
71229 … (0x1<<31) // This bit tells driver the PC…
71232 … (0x3fff<<0) // Offset (in 32-bit words) of the mailb…
71236 … (0xfff<<20) // Mailbox size in 32-bit words. Default mail…
71239 … (0x3fff<<0) // Offset (in 32-bit words) of the mailb…
71243 … (0xfff<<20) // Mailbox size in 32-bit words. Default mail…
71248 …er to alert the MCP. Changing this register updates the corresponding per-PF bit in the MCP Doorbe…
71251 … (0xff<<0) // Register supports up to an 8 bit VFID. For smaller V…
71266 …taWidth:0x20 // Port mode for GRC Master transactions 0: 1-port mode, 1: 2-port mode, 2: 4-port …
71268 …W DataWidth:0x20 // EPIO mask for signal transitioning from high to low. 1 -> MASK the event
71269 …W DataWidth:0x20 // EPIO mask for signal transitioning from low to high. 1 -> MASK the event
71274 … (0x1<<0) // When this bit is written to a 1, the processor will reset as if …
71276 … (0x1<<1) // When this bit is set, the process…
71278 …bit enables the processor to halt and to latch the value of bit 3 of the state register when data …
71280 …3) // This bit enables the processor to halt and to latch the value of bit 4 of the state register…
71281 …CP_REG_CPU_MODE_PAGE_0_INST_ENA_SHIFT 3
71284 … (0x1<<6) // This is a simple RW bit.
71286 … (0x1<<7) // When this bit is set to 1, the interrupt is enabled. When this bit is zero, any inte…
71290 …bit is set, the CPU will halt. This bit is cleared by an exception or reset. If the processor does…
71292 …11) // When this bit is set, the CPU will halt when any condition that causes bit 5 in the CPU sta…
71294 …12) // When this bit is set, the CPU will halt when any condition that causes bit 6 in the CPU sta…
71296 … (0x1<<13) // When this bit is set, the CPU wil…
71300 … (0x1<<15) // When this bit is set, the CPU will halt when state bit…
71303 …bit is set while the processor is halted due reaching a hardware breakpoint as enabled in the mode…
71307 …1<<2) // This bit is set while the processor is halted due fetching an invalid instruction. This b…
71309 …3) // This bit is set while the processor is halted due to accessing data within page 0 (the first…
71310 …CP_REG_CPU_STATE_PAGE_0_DATA_HALTED_SHIFT 3
71311 …bit is set while the processor is halted due to executing an instruction within page 0 (the first …
71313 …x1<<5) // This bit is set while the processor is halted due to bad data reference address. This bi…
71315 …) // This bit is set while the processor is halted due to bad value in the Program Counter (PC). T…
71317 …bit is set while the processor is halted due to bad memory alignment problem on a load or store in…
71319 …bit is set while the processor is halted due to the generation of a abort condition by one, or mor…
71323 … (0x1<<10) // This bit is set while the processor is halted due to the set…
71325 … (0x1<<11) // This bit is each time an att…
71327 … (0x1<<12) // This bit is each time an interrupt input is asserted, regardless of the i…
71331 … (0x1<<14) // This bit is set while the pr…
71333 … (0x1<<15) // This bit is set while the pr…
71337 …bit indicates that a blocking data cache miss occurred, causing the CPU to stall while data is fet…
71339 …//Access:RW DataWidth:0x20 // This register provides one bit for each state register bit to en…
71340 … (0x1<<0) // This bit enables breakpoints…
71344 …SK (0x1<<2) // This bit enables invalid ins…
71346 …ALTED_MASK (0x1<<3) // This bit enables page 0…
71347 …CP_REG_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK_SHIFT 3
71348 …_MASK (0x1<<4) // This bit enables page 0 inst…
71350 …ED_MASK (0x1<<5) // This bit enables invalid dat…
71352 … (0x1<<6) // This bit enables invalid PC …
71354 … (0x1<<7) // This bit enables alignment e…
71356 … (0x1<<8) // This bit enables the attention output when bit …
71360 … (0x1<<10) // This bit enables soft halts …
71362 … (0x1<<11) // This bit attention when bit 11 of the …
71364 … (0x1<<12) // This bit attention when bit 12 of the …
71366 …nstruction in the decode stage of the pipeline. Bits 31-2 are implemented. '1's written to bits 1-…
71369 …bit 7 in mode register). This register is intended to allow a way to return from an interrupt serv…
71373 … (0x1<<0) // Reset: 1 When this bit is set, the hardwar…
71377 … (0x3fffffff<<2) // This field sets the 32-bit word on which the *…
71380 … (0x7ff<<0) // 11 bit set-1 debug visibility…
71382 … bit is '0', then the debug visiblity mux is controlled by the setting in the misc. block and is a…
71384 … (0xf<<12) // 4 bit select for the peek value of the set-1…
71386 … (0x7ff<<16) // 11 bit set-2 debug visibility…
71388 … bit is '0', then the debug visiblity mux is controlled by the setting in the misc. block and is a…
71390 … (0xf<<28) // 4 bit select for the peek value of the set-2…
71395 … (0x1<<1) // This bit indicates the type …
71399 …/ While the processor is halted, the general purpose processor registers (r0-r31) can be read and …
71402 …ff<<0) // This value is used to specify the bit at the auto-polled address that indicates "link up…
71404 …xffff<<16) // This value is used to define the register address in MDIO auto-poll transactions. Fo…
71407 …-B0, on the first read of this register when the START_BUSY bit returns to '0', this value, in the…
71413 … field controls the type of MDIO transaction that will be performed when the START_BUSY bit is set.
71415 …bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occ…
71417 …bit is self clearing. When written to a '1', the currently programmed MDIO transaction will activa…
71420 …/ This bit is updated by the MDIO interface if auto-polling is enabled. The value of this bit is r…
71422 … (0x1<<1) // This bit is manually control…
71427 … (0x1<<1) // If this bit is set, the 32-bit pre-amble will not be generated …
71431 …bit enables auto-polling. When auto-polling is on, the START_BUSY bit in the mdio_comm register mu…
71435 … (0x1<<8) // If this bit is '1', the MDIO interface is controlled by the MDIO, MDIO_OE, and MDC bi…
71437 …// The write value of this bit controls the drive state of the MDIO pin if the BIT_BANG bit is set…
71439 …/ Setting this bit to '1' will cause the MDIO pin to drive the value written to the MDIO bit if th…
71441 …s bit to '1' will cause the MDC pin to high if the BIT_BANG bit is set. . Setting this pin low wil…
71443 …is bit reflects the current state of the MDINT input pin from the Copper PHY. If the interrupt is …
71445 … of this bit reflects the current state of the External MDINT input pin. If the interrupt is asser…
71453 …bit indicates that the current MDIO transaction will be executed as a Clause 45 transaction. When …
71456 …(0x1<<0) // This bit is set each time an error is detected during a auto poll sequence. The bit is…
71458 …5900UL //Access:RW DataWidth:0x20 // This register controls accesses to 3 WarpCore SERDES micr…
71473 …ess:RW DataWidth:0x20 // This register controls the clock speed for the 3 WarpCore SERDES micr…
71476 …controls the address offset for the 3 WarpCore SERDES microcontroller program memory interfaces. T…
71479 …e0590cUL //Access:RW DataWidth:0x20 // Read/write data register for the 3 WarpCore SERDES micr…
71480 …:0x20 // This register controls the level of the uC_enable signal for the 3 WarpCore SERDES micr…
71481 … (0x1<<0) // Write this bit as a '1' to set ext…
71483 … (0x1<<1) // Write this bit as a '1' to set ext…
71485 … (0x1<<2) // Write this bit as a '1' to set ext…
71487 …_WARP_TARGET_ENABLE_UNUSED0 (0x1f<<3) //
71488 …CP_REG_UCINT_WARP_TARGET_ENABLE_UNUSED0_SHIFT 3
71489 … (0x1<<8) // Write this bit as a '1' to clear e…
71491 … (0x1<<9) // Write this bit as a '1' to clear e…
71493 … (0x1<<10) // Write this bit as a '1' to clear e…
71521 … 2 PCIE SERDES microcontroller program memory interfaces. This register auto-increments after each…
71526 … (0x1<<0) // Write this bit as a '1' to set ext…
71528 … (0x1<<1) // Write this bit as a '1' to set ext…
71532 … (0x1<<8) // Write this bit as a '1' to clear e…
71534 … (0x1<<9) // Write this bit as a '1' to clear e…
71542 …address offset for the AVS RBUS program memory interface. This register auto-increments after each…
71547 … (0x1f<<0) // Number of bytes to be transfered in Read or Write operation. Valid lengths are 0-16.
71561 … (0x1<<30) // Setting this bit will synchronously …
71563 … (0x1<<31) // Setting this bit enables the IMC Blo…
71570 …ice ID of the Slave Device. This is a 7-bit field as defined by the I2C spec, but can be written h…
71598 … (0x1<<0) // This bit indicates that M2P is currently sending a packet. …
71600 …0x1<<1) // This bit indicates that in In-Use Error has occured. This is generated if a new VDM tra…
71602 …RROR (0x1<<2) // This bit indicates that the …
71604 …FLOW_ERROR (0x1<<3) // This bit is set when th…
71605 …CP_REG_M2P_M2P_STATUS_M2P_PKT_UNDERFLOW_ERROR_SHIFT 3
71606 …ROR (0x1<<4) // This bit is set when a packe…
71617 … (0x1<<0) // Setting this bit will transmit the V…
71620 … (0x7f<<0) // This is the length of the VDM packet, in 32-bit DWords. 0x0 is an i…
71642 … (0x1<<0) // This bit selects whether the…
71654 … (0x1<<31) // This bit shows the current s…
71657 …0x1<<0) // Setting this bit will cause the P2M block to assert backpressure to the PXP when the pa…
71659 … (0x1<<1) // When set, this bit forces P2M to const…
71661 …<<2) // When set, this bit will cause any packet that doesn't match one of the two Vendor ID Filte…
71663 … (0x1fffffff<<3) // Reserved for fut…
71664 …CP_REG_P2M_P2M_CONFIG_RESERVED_SHIFT 3
71668 … (0x1<<16) // When set, this bit causes packets whic…
71675 … (0x1<<16) // When set, this bit causes packets whic…
71698 …/Access:R DataWidth:0x20 // Reading this register will give the next 32-bits of the current H…
71705 … (0x1fffffff<<3) // Reserved for fut…
71706 …CP_REG_P2M_P2M_HDR_FIFO_3_RESERVED_SHIFT 3
71707 … 0xe06240UL //Access:R DataWidth:0x20 // 32-bit Packet Data.
71709 … (0x7f<<0) // 7-bit Length from VDM Hea…
71712 … (0xffff<<0) // 16-bit PCI Requester ID fr…
71715 … (0xffff<<0) // 16-bit Vendor ID from VDM …
71718 … (0xffff<<0) // 16-bit FID from VDM Header.
71720 … 0xe06254UL //Access:R DataWidth:0x20 // 32-bit Vendor Defined DWor…
71726 … (0x7<<4) // This field is the 3 LSB's of the TLP Typ…
71730 … (0xff<<16) // This is the 8-bit Tag from VDM Header.
71734 …this bit is cleared then the look-up is bypassed and the scratchpad is always accessed with the ad…
71738 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71740 … (0x1<<1) // The data is in use. If the valid bit is clear this bit will be cl…
71744 …_0_NVRAM_PAGE_OFFSET (0x1ff<<3) // Offset in the PI…
71745 …CP_REG_CACHE_CACHE_CTRL_STATUS_0_NVRAM_PAGE_OFFSET_SHIFT 3
71747 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71749 … (0x1<<1) // The data is in use. If the valid bit is clear this bit will be cl…
71753 …_1_NVRAM_PAGE_OFFSET (0x1ff<<3) // Offset in the PI…
71754 …CP_REG_CACHE_CACHE_CTRL_STATUS_1_NVRAM_PAGE_OFFSET_SHIFT 3
71756 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71758 … (0x1<<1) // The data is in use. If the valid bit is clear this bit will be cl…
71762 …_2_NVRAM_PAGE_OFFSET (0x1ff<<3) // Offset in the PI…
71763 …CP_REG_CACHE_CACHE_CTRL_STATUS_2_NVRAM_PAGE_OFFSET_SHIFT 3
71764 … 0xe06318UL //Access:RW DataWidth:0x20 // Reflects the status of page 3.
71765 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71767 … (0x1<<1) // The data is in use. If the valid bit is clear this bit will be cl…
71771 …_3_NVRAM_PAGE_OFFSET (0x1ff<<3) // Offset in the PI…
71772 …CP_REG_CACHE_CACHE_CTRL_STATUS_3_NVRAM_PAGE_OFFSET_SHIFT 3
71774 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71776 … (0x1<<1) // The data is in use. If the valid bit is clear this bit will be cl…
71780 …_4_NVRAM_PAGE_OFFSET (0x1ff<<3) // Offset in the PI…
71781 …CP_REG_CACHE_CACHE_CTRL_STATUS_4_NVRAM_PAGE_OFFSET_SHIFT 3
71783 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71785 … (0x1<<1) // The data is in use. If the valid bit is clear this bit will be cl…
71789 …_5_NVRAM_PAGE_OFFSET (0x1ff<<3) // Offset in the PI…
71790 …CP_REG_CACHE_CACHE_CTRL_STATUS_5_NVRAM_PAGE_OFFSET_SHIFT 3
71792 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71794 … (0x1<<1) // The data is in use. If the valid bit is clear this bit will be cl…
71798 …_6_NVRAM_PAGE_OFFSET (0x1ff<<3) // Offset in the PI…
71799 …CP_REG_CACHE_CACHE_CTRL_STATUS_6_NVRAM_PAGE_OFFSET_SHIFT 3
71801 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71803 … (0x1<<1) // The data is in use. If the valid bit is clear this bit will be cl…
71807 …_7_NVRAM_PAGE_OFFSET (0x1ff<<3) // Offset in the PI…
71808 …CP_REG_CACHE_CACHE_CTRL_STATUS_7_NVRAM_PAGE_OFFSET_SHIFT 3
71810 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71812 … (0x1<<1) // The data is in use. If the valid bit is clear this bit will be cl…
71816 …_8_NVRAM_PAGE_OFFSET (0x1ff<<3) // Offset in the PI…
71817 …CP_REG_CACHE_CACHE_CTRL_STATUS_8_NVRAM_PAGE_OFFSET_SHIFT 3
71819 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71821 … (0x1<<1) // The data is in use. If the valid bit is clear this bit will be cl…
71825 …_9_NVRAM_PAGE_OFFSET (0x1ff<<3) // Offset in the PI…
71826 …CP_REG_CACHE_CACHE_CTRL_STATUS_9_NVRAM_PAGE_OFFSET_SHIFT 3
71828 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71830 … (0x1<<1) // The data is in use. If the valid bit is clear this bit will be cl…
71834 …_10_NVRAM_PAGE_OFFSET (0x1ff<<3) // Offset in the PI…
71835 …CP_REG_CACHE_CACHE_CTRL_STATUS_10_NVRAM_PAGE_OFFSET_SHIFT 3
71837 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71839 … (0x1<<1) // The data is in use. If the valid bit is clear this bit will be cl…
71843 …_11_NVRAM_PAGE_OFFSET (0x1ff<<3) // Offset in the PI…
71844 …CP_REG_CACHE_CACHE_CTRL_STATUS_11_NVRAM_PAGE_OFFSET_SHIFT 3
71846 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71848 … (0x1<<1) // The data is in use. If the valid bit is clear this bit will be cl…
71852 …_12_NVRAM_PAGE_OFFSET (0x1ff<<3) // Offset in the PI…
71853 …CP_REG_CACHE_CACHE_CTRL_STATUS_12_NVRAM_PAGE_OFFSET_SHIFT 3
71855 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71857 … (0x1<<1) // The data is in use. If the valid bit is clear this bit will be cl…
71861 …_13_NVRAM_PAGE_OFFSET (0x1ff<<3) // Offset in the PI…
71862 …CP_REG_CACHE_CACHE_CTRL_STATUS_13_NVRAM_PAGE_OFFSET_SHIFT 3
71864 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71866 … (0x1<<1) // The data is in use. If the valid bit is clear this bit will be cl…
71870 …_14_NVRAM_PAGE_OFFSET (0x1ff<<3) // Offset in the PI…
71871 …CP_REG_CACHE_CACHE_CTRL_STATUS_14_NVRAM_PAGE_OFFSET_SHIFT 3
71873 …0) // If set, this page is treated as part of the static memory. When this bit is set, the valid v…
71875 … (0x1<<1) // The data is in use. If the valid bit is clear this bit will be cl…
71879 …_15_NVRAM_PAGE_OFFSET (0x1ff<<3) // Offset in the PI…
71880 …CP_REG_CACHE_CACHE_CTRL_STATUS_15_NVRAM_PAGE_OFFSET_SHIFT 3
71906 …//Access:RW DataWidth:0x20 // Statistic: Incremented whenever a Pageable-memory instruction hi…
71907 …//Access:RW DataWidth:0x20 // Statistic: Incremented whenever a Pageable-memory instruction mi…
71933 … (0x1<<0) // When set, the entire NVM state machine is reset. This bit is self clearing.
71937 …3) // Sequence completion bit that is asserted when the command requested by assertion of the doit…
71938 …CP_REG_NVM_COMMAND_DONE_SHIFT 3
71939 …om software to start the defined command. The done bit must be clear before setting this bit. This…
71941 … (0x1<<5) // The Write/Not_Read command bit. Set high to execut…
71943 …) // The erase page/sector command bit. Set high to execute a page/sector erase_cmd. This bit is i…
71945 … (0x1<<7) // This bit is passed to the SEE_FSM or SPI_FSM if the pass_…
71947 … (0x1<<8) // When this bit is set, the next co…
71949 … (0x1<<9) // When this bit is set, the address…
71953 …mmand bit. Set '1' will make flash interface state machine Generate wren_cmd to flash device throu…
71955 …mmand bit. Set '1' will make flash interface state machine Generate wrdi_cmd to flash device throu…
71957 …18) // The erase all/chip command bit. Set high to execute an all/chip erase_all_cmd. This bit is …
71961 …nd bit. When set, the flash controller will read the ID register from the external flash device. T…
71963 … (0x1<<21) // The read status command bit. When set, the flas…
71965 …bit. A 256 byte page mode has been added to the block. This mode is normally on. The mode helps co…
71972 … (0xffffff<<0) // 24 bit address value used in read, write and erase operations…
71980 … (0x1<<2) // Enable pass-thru mode to the byte…
71982 … (0x1<<3) // Enable bit-bang mode to …
71983 …CP_REG_NVM_CFG1_BITBANG_MODE_SHIFT 3
71984 …Bit offset in status command response to interpret as the "ready" flag. For Atmel, this defaults t…
71992 … (0x1<<23) // Legacy strap_control[1] bit. Read only set to 1…
71996 … (0x1<<25) // Legacy strap_value[3]. Read only. Set bas…
72004 … (0x1<<29) // Legacy strap_value[3]. Read only. Set bas…
72006 … (0x1<<30) // Legacy strap_control[1] bit. Read only set to 1…
72008 … (0x1<<31) // Legacy bit. Acts as dummy R/W bit.
72022 …ete. For SEEPROM (flash_mode=0), this is SEEPROM write command. Bit[10:9] is address bit A1 and A0…
72026 …mory. For SEEPROM (flash_mode=0), this is SEEPROM read command. Bit[26:25] is address bit A1 and A…
72029 … (0x1<<0) // Set Software Arbitration request Bit 0. This bit is set by writing a '1' to this…
72031 … (0x1<<1) // Set Software Arbitration request Bit 1. This bit is set by writing a '1' to this…
72033 … (0x1<<2) // Set Software Arbitration request Bit 2. This bit is set by writing a '1' to this…
72035 … (0x1<<3) // Set Software Arbitration request Bit 3. This bit is set by wr…
72036 …CP_REG_NVM_SW_ARB_ARB_REQ_SET3_SHIFT 3
72037 … (0x1<<4) // Write this bit as a '1' to clear req0 bit.
72039 … (0x1<<5) // Write this bit as a '1' to clear req1 bit.
72041 … (0x1<<6) // Write this bit as a '1' to clear req2 bit.
72043 … (0x1<<7) // Write this bit as a '1' to clear req3 bit.
72045 …, this bit will be read as 1, when an operation is complete, then the CLR_ARB0 must be written to …
72047 …rbitration is won, this bit will be read as 1, when an operation is complete, then the CLR_ARB1 mu…
72049 …rbitration is won, this bit will be read as 1, when an operation is complete, then the CLR_ARB2 mu…
72051 …rbitration is won, this bit will be read as 1, when an operation is complete, then the CLR_ARB3 mu…
72053 … (0x1<<12) // This is the current status of requester 0. When this bit is one, it means th…
72055 … (0x1<<13) // This is the current status of requester 1. When this bit is one, it means th…
72057 … (0x1<<14) // This is the current status of requester 2. When this bit is one, it means th…
72059 … (0x1<<15) // This is the current status of requester 3. When this bit is one, it me…
72069 …rface state machine through SPI interface To flash device, and make the flash device write-enabled.
72071 …face state machine through SPI interface To flash device, and make the flash device write-disabled.
72082 …s not used by FLSH hardware. It is only used by software. This value is self-configured on reset b…
72084 … (0x1<<3) // This bit is self-configured…
72085 …CP_REG_NVM_CFG4_FLASH_VENDOR_SHIFT 3
72086 … (0x3<<4) // Bit location for hardware to insert an empty address bit when MODE_256 is not set …
72088 …bit determines how the status bit of the device status register is interpreted by hardware. If 0, …
72090 …bit is set in ST mode, fast read command is used. In Atmel mode, this bit should be set when using…
72092 … (0x1<<8) // When this bit is set, the SI input from the external flash device is latched one cyc…
72094 …bit is set, the pass mode data is captured one cycle later than normal. If using pass mode, this b…
72096 …bit is set, a turnaround cycle is inserted in between the address and data phases of a status read…
72102 …ng f(SCLK) = f(core_clk)/(2*(SPI_SLOW_CLK_DIV +1)). [Ex: SPI_SLOW_CLK_DIV=0 -> f(SCLK) = f(core…
72104 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72106 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72108 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72110 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72112 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72114 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72116 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72118 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72120 …e regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to opti…
72122 … 0xe06430UL //Access:RW DataWidth:0x20 // NVM re-configuration registe…
72123 … (0xf<<0) // Strap value from iologic pins. Only bit[0] is used. Bits[3:1] are for…
72129 …his bit is 0 on reset. After software finishes reconfiguring FLSH, they will set this bit to 1 to …
72132 …// Enable bit for the expansion ROM engine. When '1', the expansion ROM engine will automatically …
72134 … (0x1<<1) // When this bit is set to '1', the …
72146 … (0x1<<28) // This bit is set to '1' when …
72148 … (0x1<<29) // This bit is set to '1' when …
72150 … (0x1<<30) // This bit is set to '1' when …
72152 … (0x1<<31) // This bit is set to '1' when …
72167 …AR area, it will place the offset from the BAR value in this register and re-try the PCI bus to ma…
72169 … (0x3<<24) // The size of the PCI BAR rom read request. This value ranges from 1 to 3 dwords
72173 …0x1<<31) // This bit will be set if there is a pending request for action. This bit is equivalent …
72203 … (0x1<<24) // Setting this bit will cause the GRC …
72207 … (0x1<<28) // This bit indicates that ther…
72209 … (0x1<<29) // This bit indicates that ther…
72211 … (0x1<<30) // This bit indicates that this image loader engine is busy. Wh…
72213 … (0x1<<31) // This bit indicates that this…
72240 … (0x1<<24) // Setting this bit will cause the GRC …
72244 … (0x1<<28) // This bit indicates that ther…
72246 … (0x1<<29) // This bit indicates that ther…
72248 … (0x1<<30) // This bit indicates that this image loader engine is busy. Wh…
72250 … (0x1<<31) // This bit indicates that this…
72277 … (0x1<<24) // Setting this bit will cause the GRC …
72281 … (0x1<<28) // This bit indicates that ther…
72283 … (0x1<<29) // This bit indicates that ther…
72285 … (0x1<<30) // This bit indicates that this image loader engine is busy. Wh…
72287 … (0x1<<31) // This bit indicates that this…
72292 … (0x1<<7) // When this bit is set HW will serv…
72294 … (0x1<<8) // When this bit is set the SMBUS bl…
72296 … (0x1<<9) // When this bit is set the SMBUS bl…
72300 … (0xf<<16) // This bit indicates a number …
72304 … (0x1<<26) // When this bit is '1' the TIMESTAM…
72306 … (0x1<<27) // When this bit is '1' the SMBUS bl…
72308 … (0x1<<28) // When this bit is '1' the SMBUS bl…
72310 … (0x1<<29) // When this bit is '1', the SMBUS block is placed into bit-bang mode. SMBUS interface …
72312 … (0x1<<30) // When this bit is '1', the SMBUS b…
72314 … (0x1<<31) // When this bit is set it will rese…
72323 …me for which clock low time will be stretched after each byte (that is ACK bit) when the SMBUS blo…
72325 … (0x1<<31) // When this bit is set the SMBUS bl…
72328 …olved using ARP when the ARP function is enabled. When the PROMISCOUS_MODE bit is '1', this value …
72330 … (0x1<<7) // When this bit is '1' NIC_SMB_ADDR…
72332 …hich will be used to match for incoming messages. When the PROMISCOUS_MODE bit is '1', this value …
72334 … (0x1<<15) // When this bit is '1' NIC_SMB_ADDR…
72336 …COUS_MODE bit is '1', this value is ignored. 0x0 This address is also used for ARP. The address wi…
72338 … (0x1<<23) // When this bit is '1' NIC_SMB_ADDR…
72340 …hich will be used to match for incoming messages. When the PROMISCOUS_MODE bit is '1', this value …
72342 … (0x1<<31) // When this bit is '1' NIC_SMB_ADDR…
72355 …O_FLUSH (0x1<<30) // When this bit is set HW will flus…
72357 …O_FLUSH (0x1<<31) // When this bit is set HW will flus…
72370 …FLUSH (0x1<<30) // When this bit is set HW will flus…
72372 …FLUSH (0x1<<31) // When this bit is set HW will flus…
72377 …ed for bit-bang mode, this bit controlls the output enable for the SMBDAT pin. When this bit is '0…
72379 … (0x1<<29) // This bit reflects the current input value of the SMBDAT pin. When the SMB…
72381 …gured for bit-bang mode, this bit controlls the output enable for the CLK pin. When this bit is '0…
72383 … (0x1<<31) // This bit reflects the current input value of the SMBCLK pin. When the SMB…
72386 …<<0) // This value counts down to zero once each second and sets the WG_TO bit when it reaches zer…
72389 …<<0) // This value counts down to zero once each second and sets the HB_TO bit when it reaches zer…
72392 …<0) // This value counts down to zero once each 5 msec. and sets the PA_TO bit when it reaches zer…
72395 …) // This value counts down to zero once each 250 msec. and sets the PL_TO bit when it reaches zer…
72398 …<<0) // This value counts down to zero once each second and sets the RT_TO bit when it reaches zer…
72400 …zero each time it passes 0xffffffff. This counter only counts when the TIMESTAMP_CNT_EN bit is '1'.
72402 … number of bytes that SMBUS block should read from the slave in Block Write - Block Read Process C…
72414 …bit can be set at any time by the firmware or the driver in order to abort the transaction. The HW…
72416 …bit is self clearing. When written to a '1', the currently programmed SMBUS transaction will activ…
72429 …bit can be set at any time by the firmware or the driver in order to abort the transaction. The HW…
72431 …bit is self clearing. When written to a '1', the currently programmed SMBUS transaction will activ…
72440 …LL_LEGACY_TO_EN (0x1<<3) // When set enables…
72441 …CP_REG_SMBUS_EVENT_ENABLE_POLL_LEGACY_TO_EN_SHIFT 3
72446 …are to generate smbus event any time and ARP command is received and ARP_EN0 or ARP_EN1 bit is set.
72471 …bit changes to '1' each time the WATCHDOG timer reaches zero. Writing a '1' to this position will …
72473 …bit changes to '1' each time the HEARTBEAT timer reaches zero. Writing a '1' to this position will…
72475 …bit changes to '1' each time the POLL_ASF timer reaches zero. Writing a '1' to this position will …
72477 …3) // This bit changes to '1' each time the POLL_LEGACY timer reaches zero. Writing a '1' to this …
72478 …CP_REG_SMBUS_EVENT_STATUS_POLL_LEGACY_TO_SHIFT 3
72479 …bit changes to '1' each time the RETRANSMIT timer reaches zero. Writing a '1' to this position wil…
72483 … (0x1<<20) // This bit set when slave hardware received an ARP command and ARP_E…
72485 …bit is set when slave hardware detected read transaction directed toward the SMBUS block. Writing …
72487 …UN (0x1<<22) // This bit is set when Slave T…
72489 … bit is set when slave START_BUSY transitions from 1 to 0. Writing a '1' to this position will cle…
72491 …bit is set when the slave receive FIFO holds at least one valid transaction. Writing a '1' to this…
72493 …bit is set when the slave receive FIFO is equal to or larger than the Slave RX_FIFO_THRESHOLD. Wri…
72495 …his bit is set when the slave receive FIFO become full. Writing a '1' to this position will clear …
72497 …RUN (0x1<<27) // This bit is set when Master …
72499 … bit is set when master START_BUSY transitions from 1 to 0. Writing a '1' to this position will cl…
72501 …bit is set when the master receive FIFO holds at least one valid transaction. Writing a '1' to thi…
72503 …bit is set when the master receive FIFO is equal to or larger than the Master RX_FIFO_THRESHOLD. W…
72505 …his bit is set when the master receive FIFO become full. Writing a '1' to this position will clear…
72512 … (0x1<<31) // 0 - Byte other then last in an WMBUS transaction …
72519 … (0x1<<29) // PEC error. This bit indicates status of the PEC checking. HW will check the PEC onl…
72540 … (0x1<<0) // This bit should be set by firmware before ARP_EN0 bit is se…
72542 … (0x1<<1) // This bit should be set by firmware before ARP_EN0 bit is se…
72546 … (0x1<<4) // This bit should be set by firmware before ARP_EN1 bit is se…
72548 … (0x1<<5) // This bit should be set by firmware before ARP_EN1 bit is se…
72550 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN0 bit is set.
72559 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN0 bit is set.
72568 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN0 bit is set.
72577 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN0 bit is set.
72584 … (0xff<<24) // UDID_0 byte 3.
72586 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN1 bit is set.
72595 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN1 bit is set.
72604 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN1 bit is set.
72613 …/Access:RW DataWidth:0x20 // This register should be set by firmware before ARP_EN1 bit is set.
72620 … (0xff<<24) // UDID_1 byte 3.
72624 … (0x1<<0) // Setting this bit to '1' will flush t…
72626 … (0x1<<1) // Setting this bit to '1' will set the error bit for …
72637 … (0x1<<0) // This bit indicates that the …
72645 … (0x1<<0) // Setting this bit to '1' will indicat…
72649 … (0x1<<4) // Setting this bit to '1' will flush t…
72651 … (0x1<<5) // Setting this bit to '1' will clear a…
72654 … (0x1<<0) // This bit indicates that the …
72660 … (0x1<<4) // This bit indicates that the …
72662 … (0x1<<5) // This bit indicates that the …
72664 … (0x1<<6) // This bit indicates that the …
72666 … (0x1<<7) // This bit indicates that the …
72670 …ese bits indicate the incoming traffic class of the packet. These are bits [3:2] of the PKT_TC fro…
72672 …<<12) // These bits indicate the write client of the packet. These are bits[3:0] of PKT_PORT from …
72684 … processor. This can be modified at any time and may be used for processor-to-processor communicat…
72694 …ULL_IN_EN (0x1<<3) // Enable for input…
72695 …SDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN_SHIFT 3
72700 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
72702 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
72704 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
72706 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
72742 …D_OUT_EN (0x1<<3) // Enable for outpu…
72743 …SDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN_SHIFT 3
72750 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
72786 … (0x1<<0) // This bit should be set to di…
72788 … (0x1<<1) // This bit should be set to di…
72790 … (0x1<<2) // This bit should be set to di…
72792 …_LOAD (0x1<<3) // This bit should be set …
72793 …SDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD_SHIFT 3
72794 … (0x1<<4) // This bit should be set to di…
72796 … (0x1<<5) // This bit should be set to di…
72798 … (0x1<<6) // This bit should be set to di…
72800 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from …
72802 … (0x1<<8) // This bit should be set to di…
72804 … (0x1<<9) // This bit should be set to di…
72813 …RROR (0x1<<3) // PXP_HOST fifo in…
72814 …SDM_REG_INT_STS_ASYNC_HOST_ERROR_SHIFT 3
72815 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
72865 … (0x1<<29) // Last-cycle indication not …
72870 … (0x1<<0) // This bit masks, when set, the Interrupt bit: X…
72872 … (0x1<<1) // This bit masks, when set, the Interrupt bit: X…
72874 … (0x1<<2) // This bit masks, when set, the Interrupt bit: X…
72876 … (0x1<<3) // This bit masks, when set, the Interrupt …
72877 …SDM_REG_INT_MASK_ASYNC_HOST_ERROR_SHIFT 3
72878 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
72880 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
72882 … (0x1<<6) // This bit masks, when set, the Interrupt bit: X…
72884 … (0x1<<7) // This bit masks, when set, the Interrupt bit: X…
72886 … (0x1<<8) // This bit masks, when set, the Interrupt bit: X…
72888 … (0x1<<9) // This bit masks, when set, the Interrupt bit: X…
72890 … (0x1<<10) // This bit masks, when set, the Interrupt bit: X…
72892 … (0x1<<11) // This bit masks, when set, the Interrupt bit: X…
72894 … (0x1<<12) // This bit masks, when set, the Interrupt bit: X…
72896 … (0x1<<13) // This bit masks, when set, the Interrupt bit: X…
72898 … (0x1<<14) // This bit masks, when set, the Interrupt bit: X…
72900 … (0x1<<15) // This bit masks, when set, the Interrupt bit: X…
72902 … (0x1<<16) // This bit masks, when set, the Interrupt bit: X…
72904 … (0x1<<17) // This bit masks, when set, the Interrupt bit: X…
72906 … (0x1<<18) // This bit masks, when set, the Interrupt bit: X…
72908 … (0x1<<19) // This bit masks, when set, the Interrupt bit: X…
72910 … (0x1<<20) // This bit masks, when set, the Interrupt bit: X…
72912 … (0x1<<21) // This bit masks, when set, the Interrupt bit: X…
72914 … (0x1<<22) // This bit masks, when set, the Interrupt bit: X…
72916 … (0x1<<23) // This bit masks, when set, the Interrupt bit: X…
72918 … (0x1<<24) // This bit masks, when set, the Interrupt bit: X…
72920 … (0x1<<25) // This bit masks, when set, the Interrupt bit: X…
72922 … (0x1<<26) // This bit masks, when set, the Interrupt bit: X…
72924 … (0x1<<27) // This bit masks, when set, the Interrupt bit: X…
72926 … (0x1<<28) // This bit masks, when set, the Interrupt bit: X…
72928 … (0x1<<29) // This bit masks, when set, the Interrupt bit: X…
72930 … (0x1<<30) // This bit masks, when set, the Interrupt bit: X…
72939 …T_ERROR (0x1<<3) // PXP_HOST fifo in…
72940 …SDM_REG_INT_STS_WR_ASYNC_HOST_ERROR_SHIFT 3
72941 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
72991 …E5 (0x1<<29) // Last-cycle indication not …
73002 …ST_ERROR (0x1<<3) // PXP_HOST fifo in…
73003 …SDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR_SHIFT 3
73004 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73054 …_E5 (0x1<<29) // Last-cycle indication not …
73059 … (0x1<<5) // This bit masks, when set, the Parity bit: XS…
73061 … (0x1<<0) // This bit masks, when set, the Parity bit: XS…
73063 … (0x1<<0) // This bit masks, when set, the Parity bit: XS…
73065 … (0x1<<1) // This bit masks, when set, the Parity bit: XS…
73067 … (0x1<<1) // This bit masks, when set, the Parity bit: XS…
73069 … (0x1<<2) // This bit masks, when set, the Parity bit: XS…
73071 … (0x1<<2) // This bit masks, when set, the Parity bit: XS…
73073 … (0x1<<3) // This bit masks, when set, the Parity bi…
73074 …SDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5_SHIFT 3
73075 … (0x1<<4) // This bit masks, when set, the Parity bit: XS…
73077 … (0x1<<5) // This bit masks, when set, the Parity bit: XS…
73079 … (0x1<<6) // This bit masks, when set, the Parity bit: XS…
73081 … (0x1<<7) // This bit masks, when set, the Parity bit: XS…
73083 … (0x1<<8) // This bit masks, when set, the Parity bit: XS…
73085 … (0x1<<3) // This bit masks, when set, the Parity bi…
73086 …SDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT 3
73087 … (0x1<<9) // This bit masks, when set, the Parity bit: XS…
73089 … (0x1<<9) // This bit masks, when set, the Parity bit: XS…
73091 … (0x1<<10) // This bit masks, when set, the Parity bit: XS…
73096 …pes 3,5 or 8 are not supported by this interface as they require a completion message. If there is…
73100 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
73101 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
73102 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
73103 …in the event of an inp_queue_error interrupt. It contains a vector with a bit per input queue. Cl…
73104 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
73107 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
73127 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
73200 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
73201 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
73202 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
73203 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
73204 … 0xf82000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
73206 … 0xf82400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
73208 … 0xf82800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
73210 … 0xf82c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
73212 … 0xf83000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
73214 … 0xf83400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
73216 … 0xf83800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
73218 … 0xf83c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
73220 … 0xf84000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
73235 …ULL_IN_EN (0x1<<3) // Enable for input…
73236 …SDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN_SHIFT 3
73241 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
73243 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
73245 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
73247 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
73283 …D_OUT_EN (0x1<<3) // Enable for outpu…
73284 …SDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN_SHIFT 3
73291 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
73327 … (0x1<<0) // This bit should be set to di…
73329 … (0x1<<1) // This bit should be set to di…
73331 … (0x1<<2) // This bit should be set to di…
73333 …_LOAD (0x1<<3) // This bit should be set …
73334 …SDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD_SHIFT 3
73335 … (0x1<<4) // This bit should be set to di…
73337 … (0x1<<5) // This bit should be set to di…
73339 … (0x1<<6) // This bit should be set to di…
73341 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from …
73343 … (0x1<<8) // This bit should be set to di…
73345 … (0x1<<9) // This bit should be set to di…
73354 …RROR (0x1<<3) // PXP_HOST fifo in…
73355 …SDM_REG_INT_STS_ASYNC_HOST_ERROR_SHIFT 3
73356 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73406 … (0x1<<29) // Last-cycle indication not …
73411 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
73413 … (0x1<<1) // This bit masks, when set, the Interrupt bit: Y…
73415 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Y…
73417 … (0x1<<3) // This bit masks, when set, the Interrupt …
73418 …SDM_REG_INT_MASK_ASYNC_HOST_ERROR_SHIFT 3
73419 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
73421 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
73423 … (0x1<<6) // This bit masks, when set, the Interrupt bit: Y…
73425 … (0x1<<7) // This bit masks, when set, the Interrupt bit: Y…
73427 … (0x1<<8) // This bit masks, when set, the Interrupt bit: Y…
73429 … (0x1<<9) // This bit masks, when set, the Interrupt bit: Y…
73431 … (0x1<<10) // This bit masks, when set, the Interrupt bit: Y…
73433 … (0x1<<11) // This bit masks, when set, the Interrupt bit: Y…
73435 … (0x1<<12) // This bit masks, when set, the Interrupt bit: Y…
73437 … (0x1<<13) // This bit masks, when set, the Interrupt bit: Y…
73439 … (0x1<<14) // This bit masks, when set, the Interrupt bit: Y…
73441 … (0x1<<15) // This bit masks, when set, the Interrupt bit: Y…
73443 … (0x1<<16) // This bit masks, when set, the Interrupt bit: Y…
73445 … (0x1<<17) // This bit masks, when set, the Interrupt bit: Y…
73447 … (0x1<<18) // This bit masks, when set, the Interrupt bit: Y…
73449 … (0x1<<19) // This bit masks, when set, the Interrupt bit: Y…
73451 … (0x1<<20) // This bit masks, when set, the Interrupt bit: Y…
73453 … (0x1<<21) // This bit masks, when set, the Interrupt bit: Y…
73455 … (0x1<<22) // This bit masks, when set, the Interrupt bit: Y…
73457 … (0x1<<23) // This bit masks, when set, the Interrupt bit: Y…
73459 … (0x1<<24) // This bit masks, when set, the Interrupt bit: Y…
73461 … (0x1<<25) // This bit masks, when set, the Interrupt bit: Y…
73463 … (0x1<<26) // This bit masks, when set, the Interrupt bit: Y…
73465 … (0x1<<27) // This bit masks, when set, the Interrupt bit: Y…
73467 … (0x1<<28) // This bit masks, when set, the Interrupt bit: Y…
73469 … (0x1<<29) // This bit masks, when set, the Interrupt bit: Y…
73471 … (0x1<<30) // This bit masks, when set, the Interrupt bit: Y…
73480 …T_ERROR (0x1<<3) // PXP_HOST fifo in…
73481 …SDM_REG_INT_STS_WR_ASYNC_HOST_ERROR_SHIFT 3
73482 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73532 …E5 (0x1<<29) // Last-cycle indication not …
73543 …ST_ERROR (0x1<<3) // PXP_HOST fifo in…
73544 …SDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR_SHIFT 3
73545 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73595 …_E5 (0x1<<29) // Last-cycle indication not …
73600 … (0x1<<5) // This bit masks, when set, the Parity bit: YS…
73602 … (0x1<<0) // This bit masks, when set, the Parity bit: YS…
73604 … (0x1<<0) // This bit masks, when set, the Parity bit: YS…
73606 … (0x1<<1) // This bit masks, when set, the Parity bit: YS…
73608 … (0x1<<1) // This bit masks, when set, the Parity bit: YS…
73610 … (0x1<<2) // This bit masks, when set, the Parity bit: YS…
73612 … (0x1<<2) // This bit masks, when set, the Parity bit: YS…
73614 … (0x1<<3) // This bit masks, when set, the Parity bi…
73615 …SDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_E5_SHIFT 3
73616 … (0x1<<4) // This bit masks, when set, the Parity bit: YS…
73618 … (0x1<<5) // This bit masks, when set, the Parity bit: YS…
73620 … (0x1<<6) // This bit masks, when set, the Parity bit: YS…
73622 … (0x1<<7) // This bit masks, when set, the Parity bit: YS…
73624 … (0x1<<8) // This bit masks, when set, the Parity bit: YS…
73626 … (0x1<<3) // This bit masks, when set, the Parity bi…
73627 …SDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT 3
73628 … (0x1<<9) // This bit masks, when set, the Parity bit: YS…
73633 …pes 3,5 or 8 are not supported by this interface as they require a completion message. If there is…
73637 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
73638 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
73639 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
73640 …in the event of an inp_queue_error interrupt. It contains a vector with a bit per input queue. Cl…
73641 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
73644 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
73649 …M_REG_INIT_CREDIT_CM_RMT_SIZE 3
73665 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
73738 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
73739 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
73740 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
73741 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
73742 … 0xf92000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
73744 … 0xf92400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
73746 … 0xf92800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
73748 … 0xf92c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
73750 … 0xf93000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
73752 … 0xf93400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
73754 … 0xf93800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
73756 … 0xf93c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
73758 … 0xf94000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
73773 …ULL_IN_EN (0x1<<3) // Enable for input…
73774 …SDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN_SHIFT 3
73779 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
73781 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
73783 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
73785 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
73821 …D_OUT_EN (0x1<<3) // Enable for outpu…
73822 …SDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN_SHIFT 3
73829 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
73865 … (0x1<<0) // This bit should be set to di…
73867 … (0x1<<1) // This bit should be set to di…
73869 … (0x1<<2) // This bit should be set to di…
73871 …_LOAD (0x1<<3) // This bit should be set …
73872 …SDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD_SHIFT 3
73873 … (0x1<<4) // This bit should be set to di…
73875 … (0x1<<5) // This bit should be set to di…
73877 … (0x1<<6) // This bit should be set to di…
73879 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from …
73881 … (0x1<<8) // This bit should be set to di…
73883 … (0x1<<9) // This bit should be set to di…
73892 …RROR (0x1<<3) // PXP_HOST fifo in…
73893 …SDM_REG_INT_STS_ASYNC_HOST_ERROR_SHIFT 3
73894 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73944 … (0x1<<29) // Last-cycle indication not …
73949 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
73951 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
73953 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
73955 … (0x1<<3) // This bit masks, when set, the Interrupt …
73956 …SDM_REG_INT_MASK_ASYNC_HOST_ERROR_SHIFT 3
73957 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
73959 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
73961 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
73963 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
73965 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
73967 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
73969 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
73971 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
73973 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
73975 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
73977 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
73979 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
73981 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
73983 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
73985 … (0x1<<18) // This bit masks, when set, the Interrupt bit: P…
73987 … (0x1<<19) // This bit masks, when set, the Interrupt bit: P…
73989 … (0x1<<20) // This bit masks, when set, the Interrupt bit: P…
73991 … (0x1<<21) // This bit masks, when set, the Interrupt bit: P…
73993 … (0x1<<22) // This bit masks, when set, the Interrupt bit: P…
73995 … (0x1<<23) // This bit masks, when set, the Interrupt bit: P…
73997 … (0x1<<24) // This bit masks, when set, the Interrupt bit: P…
73999 … (0x1<<25) // This bit masks, when set, the Interrupt bit: P…
74001 … (0x1<<26) // This bit masks, when set, the Interrupt bit: P…
74003 … (0x1<<27) // This bit masks, when set, the Interrupt bit: P…
74005 … (0x1<<28) // This bit masks, when set, the Interrupt bit: P…
74007 … (0x1<<29) // This bit masks, when set, the Interrupt bit: P…
74009 … (0x1<<30) // This bit masks, when set, the Interrupt bit: P…
74018 …T_ERROR (0x1<<3) // PXP_HOST fifo in…
74019 …SDM_REG_INT_STS_WR_ASYNC_HOST_ERROR_SHIFT 3
74020 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74070 …E5 (0x1<<29) // Last-cycle indication not …
74081 …ST_ERROR (0x1<<3) // PXP_HOST fifo in…
74082 …SDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR_SHIFT 3
74083 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74133 …_E5 (0x1<<29) // Last-cycle indication not …
74138 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
74140 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
74142 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
74144 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
74146 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
74148 … (0x1<<3) // This bit masks, when set, the Parity bi…
74149 …SDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_E5_SHIFT 3
74150 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
74152 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
74154 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
74156 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
74158 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
74160 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
74162 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
74164 … (0x1<<6) // This bit masks, when set, the Parity bit: PS…
74166 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
74168 … (0x1<<3) // This bit masks, when set, the Parity bi…
74169 …SDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT 3
74170 … (0x1<<9) // This bit masks, when set, the Parity bit: PS…
74172 … (0x1<<7) // This bit masks, when set, the Parity bit: PS…
74174 … (0x1<<8) // This bit masks, when set, the Parity bit: PS…
74195 …pes 3,5 or 8 are not supported by this interface as they require a completion message. If there is…
74199 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
74200 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
74201 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
74202 …in the event of an inp_queue_error interrupt. It contains a vector with a bit per input queue. Cl…
74203 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
74206 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
74227 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
74300 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
74301 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
74302 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
74303 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
74304 … 0xfa2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
74306 … 0xfa2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
74308 … 0xfa2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
74310 … 0xfa2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
74312 … 0xfa3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
74314 … 0xfa3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
74316 … 0xfa3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
74318 … 0xfa3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
74320 … 0xfa4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
74335 …ULL_IN_EN (0x1<<3) // Enable for input…
74336 …SDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN_SHIFT 3
74341 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
74343 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
74345 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
74347 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
74383 …D_OUT_EN (0x1<<3) // Enable for outpu…
74384 …SDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN_SHIFT 3
74391 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
74427 … (0x1<<0) // This bit should be set to di…
74429 … (0x1<<1) // This bit should be set to di…
74431 … (0x1<<2) // This bit should be set to di…
74433 …_LOAD (0x1<<3) // This bit should be set …
74434 …SDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD_SHIFT 3
74435 … (0x1<<4) // This bit should be set to di…
74437 … (0x1<<5) // This bit should be set to di…
74439 … (0x1<<6) // This bit should be set to di…
74441 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from …
74443 … (0x1<<8) // This bit should be set to di…
74445 … (0x1<<9) // This bit should be set to di…
74454 …RROR (0x1<<3) // PXP_HOST fifo in…
74455 …SDM_REG_INT_STS_ASYNC_HOST_ERROR_SHIFT 3
74456 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74506 … (0x1<<29) // Last-cycle indication not …
74511 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
74513 … (0x1<<1) // This bit masks, when set, the Interrupt bit: T…
74515 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
74517 … (0x1<<3) // This bit masks, when set, the Interrupt …
74518 …SDM_REG_INT_MASK_ASYNC_HOST_ERROR_SHIFT 3
74519 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
74521 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
74523 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
74525 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
74527 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
74529 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
74531 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
74533 … (0x1<<11) // This bit masks, when set, the Interrupt bit: T…
74535 … (0x1<<12) // This bit masks, when set, the Interrupt bit: T…
74537 … (0x1<<13) // This bit masks, when set, the Interrupt bit: T…
74539 … (0x1<<14) // This bit masks, when set, the Interrupt bit: T…
74541 … (0x1<<15) // This bit masks, when set, the Interrupt bit: T…
74543 … (0x1<<16) // This bit masks, when set, the Interrupt bit: T…
74545 … (0x1<<17) // This bit masks, when set, the Interrupt bit: T…
74547 … (0x1<<18) // This bit masks, when set, the Interrupt bit: T…
74549 … (0x1<<19) // This bit masks, when set, the Interrupt bit: T…
74551 … (0x1<<20) // This bit masks, when set, the Interrupt bit: T…
74553 … (0x1<<21) // This bit masks, when set, the Interrupt bit: T…
74555 … (0x1<<22) // This bit masks, when set, the Interrupt bit: T…
74557 … (0x1<<23) // This bit masks, when set, the Interrupt bit: T…
74559 … (0x1<<24) // This bit masks, when set, the Interrupt bit: T…
74561 … (0x1<<25) // This bit masks, when set, the Interrupt bit: T…
74563 … (0x1<<26) // This bit masks, when set, the Interrupt bit: T…
74565 … (0x1<<27) // This bit masks, when set, the Interrupt bit: T…
74567 … (0x1<<28) // This bit masks, when set, the Interrupt bit: T…
74569 … (0x1<<29) // This bit masks, when set, the Interrupt bit: T…
74571 … (0x1<<30) // This bit masks, when set, the Interrupt bit: T…
74580 …T_ERROR (0x1<<3) // PXP_HOST fifo in…
74581 …SDM_REG_INT_STS_WR_ASYNC_HOST_ERROR_SHIFT 3
74582 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74632 …E5 (0x1<<29) // Last-cycle indication not …
74643 …ST_ERROR (0x1<<3) // PXP_HOST fifo in…
74644 …SDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR_SHIFT 3
74645 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74695 …_E5 (0x1<<29) // Last-cycle indication not …
74700 … (0x1<<6) // This bit masks, when set, the Parity bit: TS…
74702 … (0x1<<0) // This bit masks, when set, the Parity bit: TS…
74704 … (0x1<<0) // This bit masks, when set, the Parity bit: TS…
74706 … (0x1<<1) // This bit masks, when set, the Parity bit: TS…
74708 … (0x1<<1) // This bit masks, when set, the Parity bit: TS…
74710 … (0x1<<2) // This bit masks, when set, the Parity bit: TS…
74712 … (0x1<<2) // This bit masks, when set, the Parity bit: TS…
74714 … (0x1<<3) // This bit masks, when set, the Parity bi…
74715 …SDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5_SHIFT 3
74716 … (0x1<<3) // This bit masks, when set, the Parity bi…
74717 …SDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT 3
74718 … (0x1<<4) // This bit masks, when set, the Parity bit: TS…
74720 … (0x1<<5) // This bit masks, when set, the Parity bit: TS…
74722 … (0x1<<6) // This bit masks, when set, the Parity bit: TS…
74724 … (0x1<<7) // This bit masks, when set, the Parity bit: TS…
74726 … (0x1<<8) // This bit masks, when set, the Parity bit: TS…
74728 … (0x1<<9) // This bit masks, when set, the Parity bit: TS…
74730 … (0x1<<4) // This bit masks, when set, the Parity bit: TS…
74732 … (0x1<<10) // This bit masks, when set, the Parity bit: TS…
74737 …pes 3,5 or 8 are not supported by this interface as they require a completion message. If there is…
74741 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
74742 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
74743 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
74744 …in the event of an inp_queue_error interrupt. It contains a vector with a bit per input queue. Cl…
74745 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
74748 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
74768 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
74841 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
74842 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
74843 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
74844 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
74845 … 0xfb2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
74847 … 0xfb2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
74849 … 0xfb2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
74851 … 0xfb2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
74853 … 0xfb3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
74855 … 0xfb3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
74857 … 0xfb3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
74859 … 0xfb3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
74861 … 0xfb4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
74876 …ULL_IN_EN (0x1<<3) // Enable for input…
74877 …SDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN_SHIFT 3
74882 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
74884 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
74886 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
74888 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
74924 …D_OUT_EN (0x1<<3) // Enable for outpu…
74925 …SDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN_SHIFT 3
74932 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
74968 … (0x1<<0) // This bit should be set to di…
74970 … (0x1<<1) // This bit should be set to di…
74972 … (0x1<<2) // This bit should be set to di…
74974 …_LOAD (0x1<<3) // This bit should be set …
74975 …SDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD_SHIFT 3
74976 … (0x1<<4) // This bit should be set to di…
74978 … (0x1<<5) // This bit should be set to di…
74980 … (0x1<<6) // This bit should be set to di…
74982 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from …
74984 … (0x1<<8) // This bit should be set to di…
74986 … (0x1<<9) // This bit should be set to di…
74995 …RROR (0x1<<3) // PXP_HOST fifo in…
74996 …SDM_REG_INT_STS_ASYNC_HOST_ERROR_SHIFT 3
74997 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75047 … (0x1<<29) // Last-cycle indication not …
75052 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
75054 … (0x1<<1) // This bit masks, when set, the Interrupt bit: M…
75056 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
75058 … (0x1<<3) // This bit masks, when set, the Interrupt …
75059 …SDM_REG_INT_MASK_ASYNC_HOST_ERROR_SHIFT 3
75060 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
75062 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
75064 … (0x1<<6) // This bit masks, when set, the Interrupt bit: M…
75066 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
75068 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
75070 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
75072 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
75074 … (0x1<<11) // This bit masks, when set, the Interrupt bit: M…
75076 … (0x1<<12) // This bit masks, when set, the Interrupt bit: M…
75078 … (0x1<<13) // This bit masks, when set, the Interrupt bit: M…
75080 … (0x1<<14) // This bit masks, when set, the Interrupt bit: M…
75082 … (0x1<<15) // This bit masks, when set, the Interrupt bit: M…
75084 … (0x1<<16) // This bit masks, when set, the Interrupt bit: M…
75086 … (0x1<<17) // This bit masks, when set, the Interrupt bit: M…
75088 … (0x1<<18) // This bit masks, when set, the Interrupt bit: M…
75090 … (0x1<<19) // This bit masks, when set, the Interrupt bit: M…
75092 … (0x1<<20) // This bit masks, when set, the Interrupt bit: M…
75094 … (0x1<<21) // This bit masks, when set, the Interrupt bit: M…
75096 … (0x1<<22) // This bit masks, when set, the Interrupt bit: M…
75098 … (0x1<<23) // This bit masks, when set, the Interrupt bit: M…
75100 … (0x1<<24) // This bit masks, when set, the Interrupt bit: M…
75102 … (0x1<<25) // This bit masks, when set, the Interrupt bit: M…
75104 … (0x1<<26) // This bit masks, when set, the Interrupt bit: M…
75106 … (0x1<<27) // This bit masks, when set, the Interrupt bit: M…
75108 … (0x1<<28) // This bit masks, when set, the Interrupt bit: M…
75110 … (0x1<<29) // This bit masks, when set, the Interrupt bit: M…
75112 … (0x1<<30) // This bit masks, when set, the Interrupt bit: M…
75121 …T_ERROR (0x1<<3) // PXP_HOST fifo in…
75122 …SDM_REG_INT_STS_WR_ASYNC_HOST_ERROR_SHIFT 3
75123 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75173 …E5 (0x1<<29) // Last-cycle indication not …
75184 …ST_ERROR (0x1<<3) // PXP_HOST fifo in…
75185 …SDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR_SHIFT 3
75186 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75236 …_E5 (0x1<<29) // Last-cycle indication not …
75241 … (0x1<<0) // This bit masks, when set, the Parity bit: MS…
75243 … (0x1<<1) // This bit masks, when set, the Parity bit: MS…
75245 … (0x1<<10) // This bit masks, when set, the Parity bit: MS…
75247 … (0x1<<2) // This bit masks, when set, the Parity bit: MS…
75249 … (0x1<<0) // This bit masks, when set, the Parity bit: MS…
75251 … (0x1<<3) // This bit masks, when set, the Parity bi…
75252 …SDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_E5_SHIFT 3
75253 … (0x1<<1) // This bit masks, when set, the Parity bit: MS…
75255 … (0x1<<4) // This bit masks, when set, the Parity bit: MS…
75257 … (0x1<<2) // This bit masks, when set, the Parity bit: MS…
75259 … (0x1<<5) // This bit masks, when set, the Parity bit: MS…
75261 … (0x1<<3) // This bit masks, when set, the Parity bi…
75262 …SDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT 3
75263 … (0x1<<6) // This bit masks, when set, the Parity bit: MS…
75265 … (0x1<<5) // This bit masks, when set, the Parity bit: MS…
75267 … (0x1<<7) // This bit masks, when set, the Parity bit: MS…
75269 … (0x1<<8) // This bit masks, when set, the Parity bit: MS…
75271 … (0x1<<7) // This bit masks, when set, the Parity bit: MS…
75273 … (0x1<<9) // This bit masks, when set, the Parity bit: MS…
75275 … (0x1<<4) // This bit masks, when set, the Parity bit: MS…
75277 … (0x1<<10) // This bit masks, when set, the Parity bit: MS…
75279 … (0x1<<6) // This bit masks, when set, the Parity bit: MS…
75281 … (0x1<<11) // This bit masks, when set, the Parity bit: MS…
75283 … (0x1<<8) // This bit masks, when set, the Parity bit: MS…
75285 … (0x1<<9) // This bit masks, when set, the Parity bit: MS…
75306 …pes 3,5 or 8 are not supported by this interface as they require a completion message. If there is…
75310 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
75311 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
75312 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
75313 …in the event of an inp_queue_error interrupt. It contains a vector with a bit per input queue. Cl…
75314 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
75317 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
75323 …M_REG_INIT_CREDIT_CM_RMT_SIZE_E5 3
75339 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
75412 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
75413 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
75414 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
75415 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
75416 … 0xfc2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
75418 … 0xfc2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
75420 … 0xfc2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
75422 … 0xfc2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
75424 … 0xfc3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
75426 … 0xfc3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
75428 … 0xfc3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
75430 … 0xfc3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
75432 … 0xfc4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
75447 …ULL_IN_EN (0x1<<3) // Enable for input…
75448 …SDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN_SHIFT 3
75453 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
75455 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
75457 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
75459 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
75495 …D_OUT_EN (0x1<<3) // Enable for outpu…
75496 …SDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN_SHIFT 3
75503 … (0x1<<7) // Enable for output data to pxp-HW interface in DMA_R…
75539 … (0x1<<0) // This bit should be set to di…
75541 … (0x1<<1) // This bit should be set to di…
75543 … (0x1<<2) // This bit should be set to di…
75545 …_LOAD (0x1<<3) // This bit should be set …
75546 …SDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD_SHIFT 3
75547 … (0x1<<4) // This bit should be set to di…
75549 … (0x1<<5) // This bit should be set to di…
75551 … (0x1<<6) // This bit should be set to di…
75553 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from …
75555 … (0x1<<8) // This bit should be set to di…
75557 … (0x1<<9) // This bit should be set to di…
75566 …RROR (0x1<<3) // PXP_HOST fifo in…
75567 …SDM_REG_INT_STS_ASYNC_HOST_ERROR_SHIFT 3
75568 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75618 … (0x1<<29) // Last-cycle indication not …
75623 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
75625 … (0x1<<1) // This bit masks, when set, the Interrupt bit: U…
75627 … (0x1<<2) // This bit masks, when set, the Interrupt bit: U…
75629 … (0x1<<3) // This bit masks, when set, the Interrupt …
75630 …SDM_REG_INT_MASK_ASYNC_HOST_ERROR_SHIFT 3
75631 … (0x1<<4) // This bit masks, when set, the Interrupt bit: U…
75633 … (0x1<<5) // This bit masks, when set, the Interrupt bit: U…
75635 … (0x1<<6) // This bit masks, when set, the Interrupt bit: U…
75637 … (0x1<<7) // This bit masks, when set, the Interrupt bit: U…
75639 … (0x1<<8) // This bit masks, when set, the Interrupt bit: U…
75641 … (0x1<<9) // This bit masks, when set, the Interrupt bit: U…
75643 … (0x1<<10) // This bit masks, when set, the Interrupt bit: U…
75645 … (0x1<<11) // This bit masks, when set, the Interrupt bit: U…
75647 … (0x1<<12) // This bit masks, when set, the Interrupt bit: U…
75649 … (0x1<<13) // This bit masks, when set, the Interrupt bit: U…
75651 … (0x1<<14) // This bit masks, when set, the Interrupt bit: U…
75653 … (0x1<<15) // This bit masks, when set, the Interrupt bit: U…
75655 … (0x1<<16) // This bit masks, when set, the Interrupt bit: U…
75657 … (0x1<<17) // This bit masks, when set, the Interrupt bit: U…
75659 … (0x1<<18) // This bit masks, when set, the Interrupt bit: U…
75661 … (0x1<<19) // This bit masks, when set, the Interrupt bit: U…
75663 … (0x1<<20) // This bit masks, when set, the Interrupt bit: U…
75665 … (0x1<<21) // This bit masks, when set, the Interrupt bit: U…
75667 … (0x1<<22) // This bit masks, when set, the Interrupt bit: U…
75669 … (0x1<<23) // This bit masks, when set, the Interrupt bit: U…
75671 … (0x1<<24) // This bit masks, when set, the Interrupt bit: U…
75673 … (0x1<<25) // This bit masks, when set, the Interrupt bit: U…
75675 … (0x1<<26) // This bit masks, when set, the Interrupt bit: U…
75677 … (0x1<<27) // This bit masks, when set, the Interrupt bit: U…
75679 … (0x1<<28) // This bit masks, when set, the Interrupt bit: U…
75681 … (0x1<<29) // This bit masks, when set, the Interrupt bit: U…
75683 … (0x1<<30) // This bit masks, when set, the Interrupt bit: U…
75692 …T_ERROR (0x1<<3) // PXP_HOST fifo in…
75693 …SDM_REG_INT_STS_WR_ASYNC_HOST_ERROR_SHIFT 3
75694 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75744 …E5 (0x1<<29) // Last-cycle indication not …
75755 …ST_ERROR (0x1<<3) // PXP_HOST fifo in…
75756 …SDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR_SHIFT 3
75757 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75807 …_E5 (0x1<<29) // Last-cycle indication not …
75812 … (0x1<<9) // This bit masks, when set, the Parity bit: US…
75814 … (0x1<<0) // This bit masks, when set, the Parity bit: US…
75816 … (0x1<<0) // This bit masks, when set, the Parity bit: US…
75818 … (0x1<<1) // This bit masks, when set, the Parity bit: US…
75820 … (0x1<<1) // This bit masks, when set, the Parity bit: US…
75822 … (0x1<<2) // This bit masks, when set, the Parity bit: US…
75824 … (0x1<<2) // This bit masks, when set, the Parity bit: US…
75826 … (0x1<<3) // This bit masks, when set, the Parity bi…
75827 …SDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_E5_SHIFT 3
75828 … (0x1<<4) // This bit masks, when set, the Parity bit: US…
75830 … (0x1<<5) // This bit masks, when set, the Parity bit: US…
75832 … (0x1<<6) // This bit masks, when set, the Parity bit: US…
75834 … (0x1<<7) // This bit masks, when set, the Parity bit: US…
75836 … (0x1<<8) // This bit masks, when set, the Parity bit: US…
75838 … (0x1<<3) // This bit masks, when set, the Parity bi…
75839 …SDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT 3
75840 … (0x1<<9) // This bit masks, when set, the Parity bit: US…
75842 … (0x1<<5) // This bit masks, when set, the Parity bit: US…
75844 … (0x1<<10) // This bit masks, when set, the Parity bit: US…
75849 …pes 3,5 or 8 are not supported by this interface as they require a completion message. If there is…
75853 …ompletion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b…
75854 …for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-in…
75855 …ss to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination…
75856 …in the event of an inp_queue_error interrupt. It contains a vector with a bit per input queue. Cl…
75857 …of completion messages that can be allocated to PXP-Async transactions at any given time. If the P…
75860 …taWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the interna…
75881 …ve: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode…
75954 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
75955 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
75956 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
75957 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
75958 … 0xfd2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
75960 … 0xfd2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
75962 … 0xfd2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
75964 … 0xfd2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
75966 … 0xfd3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
75968 … 0xfd3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
75970 … 0xfd3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
75972 … 0xfd3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
75974 … 0xfd4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write acc…
75982 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
75986 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
75987 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
75988 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
75989 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
76026 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76027 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76028 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76029 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76030 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76031 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76032 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76033 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76034 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76035 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76036 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76037 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76038 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76039 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76040 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76041 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76042 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76043 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76044 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76045 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76046 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76047 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76048 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76049 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76050 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76051 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76052 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76053 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76054 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76055 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76056 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76057 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76058 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76059 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76060 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76061 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76062 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76063 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76064 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76065 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76066 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76067 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76068 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76069 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76070 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76071 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76072 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76073 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76074 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76082 …L_ERR (0x1<<3) // Write to full MS…
76083 …CM_REG_INT_STS_0_IS_MSDM_OVFL_ERR_SHIFT 3
76113 … (0x1<<0) // This bit masks, when set, the Interrupt bit: X…
76115 … (0x1<<1) // This bit masks, when set, the Interrupt bit: X…
76117 … (0x1<<2) // This bit masks, when set, the Interrupt bit: X…
76119 … (0x1<<3) // This bit masks, when set, the Interrupt …
76120 …CM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR_SHIFT 3
76121 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
76123 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
76125 … (0x1<<6) // This bit masks, when set, the Interrupt bit: X…
76127 … (0x1<<7) // This bit masks, when set, the Interrupt bit: X…
76129 … (0x1<<8) // This bit masks, when set, the Interrupt bit: X…
76131 … (0x1<<9) // This bit masks, when set, the Interrupt bit: X…
76133 … (0x1<<10) // This bit masks, when set, the Interrupt bit: X…
76135 … (0x1<<11) // This bit masks, when set, the Interrupt bit: X…
76137 … (0x1<<12) // This bit masks, when set, the Interrupt bit: X…
76139 … (0x1<<13) // This bit masks, when set, the Interrupt bit: X…
76141 … (0x1<<14) // This bit masks, when set, the Interrupt bit: X…
76143 … (0x1<<15) // This bit masks, when set, the Interrupt bit: X…
76145 … (0x1<<16) // This bit masks, when set, the Interrupt bit: X…
76147 … (0x1<<17) // This bit masks, when set, the Interrupt bit: X…
76156 …OVFL_ERR (0x1<<3) // Write to full MS…
76157 …CM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR_SHIFT 3
76193 …_OVFL_ERR (0x1<<3) // Write to full MS…
76194 …CM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR_SHIFT 3
76230 …_ERR (0x1<<3) // Write to full Pb…
76231 …CM_REG_INT_STS_1_IS_PBF_OVFL_ERR_SHIFT 3
76262 … (0x1<<19) // In-process Table overflo…
76275 … (0x1<<0) // This bit masks, when set, the Interrupt bit: X…
76277 … (0x1<<1) // This bit masks, when set, the Interrupt bit: X…
76279 … (0x1<<2) // This bit masks, when set, the Interrupt bit: X…
76281 … (0x1<<3) // This bit masks, when set, the Interrupt …
76282 …CM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_SHIFT 3
76283 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
76285 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
76287 … (0x1<<6) // This bit masks, when set, the Interrupt bit: X…
76289 … (0x1<<7) // This bit masks, when set, the Interrupt bit: X…
76291 … (0x1<<8) // This bit masks, when set, the Interrupt bit: X…
76293 … (0x1<<9) // This bit masks, when set, the Interrupt bit: X…
76295 … (0x1<<10) // This bit masks, when set, the Interrupt bit: X…
76297 … (0x1<<11) // This bit masks, when set, the Interrupt bit: X…
76299 … (0x1<<12) // This bit masks, when set, the Interrupt bit: X…
76301 … (0x1<<13) // This bit masks, when set, the Interrupt bit: X…
76303 … (0x1<<14) // This bit masks, when set, the Interrupt bit: X…
76305 … (0x1<<15) // This bit masks, when set, the Interrupt bit: X…
76307 … (0x1<<16) // This bit masks, when set, the Interrupt bit: X…
76309 … (0x1<<17) // This bit masks, when set, the Interrupt bit: X…
76311 … (0x1<<18) // This bit masks, when set, the Interrupt bit: X…
76313 … (0x1<<19) // This bit masks, when set, the Interrupt bit: X…
76315 … (0x1<<20) // This bit masks, when set, the Interrupt bit: X…
76317 … (0x1<<21) // This bit masks, when set, the Interrupt bit: X…
76319 … (0x1<<22) // This bit masks, when set, the Interrupt bit: X…
76321 … (0x1<<23) // This bit masks, when set, the Interrupt bit: X…
76323 … (0x1<<24) // This bit masks, when set, the Interrupt bit: X…
76332 …VFL_ERR (0x1<<3) // Write to full Pb…
76333 …CM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_SHIFT 3
76364 … (0x1<<19) // In-process Table overflo…
76383 …OVFL_ERR (0x1<<3) // Write to full Pb…
76384 …CM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_SHIFT 3
76415 … (0x1<<19) // In-process Table overflo…
76434 …NT_EXT_LD_OVFL (0x1<<3) // QM Active State …
76435 …CM_REG_INT_STS_2_QM_ACT_ST_CNT_EXT_LD_OVFL_SHIFT 3
76445 … (0x1<<0) // This bit masks, when set, the Interrupt bit: X…
76447 … (0x1<<1) // This bit masks, when set, the Interrupt bit: X…
76449 … (0x1<<2) // This bit masks, when set, the Interrupt bit: X…
76451 … (0x1<<3) // This bit masks, when set, the Interrupt …
76452 …CM_REG_INT_MASK_2_QM_ACT_ST_CNT_EXT_LD_OVFL_SHIFT 3
76453 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
76455 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
76457 … (0x1<<6) // This bit masks, when set, the Interrupt bit: X…
76459 … (0x1<<7) // This bit masks, when set, the Interrupt bit: X…
76468 …T_CNT_EXT_LD_OVFL (0x1<<3) // QM Active State …
76469 …CM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_EXT_LD_OVFL_SHIFT 3
76485 …ST_CNT_EXT_LD_OVFL (0x1<<3) // QM Active State …
76486 …CM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_EXT_LD_OVFL_SHIFT 3
76496 … (0x1<<0) // This bit masks, when set, the Parity bit: XC…
76498 … (0x1<<0) // This bit masks, when set, the Parity bit: XC…
76500 … (0x1<<1) // This bit masks, when set, the Parity bit: XC…
76502 … (0x1<<2) // This bit masks, when set, the Parity bit: XC…
76504 … (0x1<<3) // This bit masks, when set, the Parity bi…
76505 …CM_REG_PRTY_MASK_H_0_MEM003_I_ECC_2_RF_INT_SHIFT 3
76506 … (0x1<<4) // This bit masks, when set, the Parity bit: XC…
76508 … (0x1<<5) // This bit masks, when set, the Parity bit: XC…
76510 … (0x1<<6) // This bit masks, when set, the Parity bit: XC…
76512 … (0x1<<6) // This bit masks, when set, the Parity bit: XC…
76514 … (0x1<<7) // This bit masks, when set, the Parity bit: XC…
76516 … (0x1<<7) // This bit masks, when set, the Parity bit: XC…
76518 … (0x1<<8) // This bit masks, when set, the Parity bit: XC…
76520 … (0x1<<9) // This bit masks, when set, the Parity bit: XC…
76522 … (0x1<<10) // This bit masks, when set, the Parity bit: XC…
76524 … (0x1<<11) // This bit masks, when set, the Parity bit: XC…
76526 … (0x1<<14) // This bit masks, when set, the Parity bit: XC…
76528 … (0x1<<12) // This bit masks, when set, the Parity bit: XC…
76530 … (0x1<<12) // This bit masks, when set, the Parity bit: XC…
76532 … (0x1<<13) // This bit masks, when set, the Parity bit: XC…
76534 … (0x1<<13) // This bit masks, when set, the Parity bit: XC…
76536 … (0x1<<14) // This bit masks, when set, the Parity bit: XC…
76538 … (0x1<<27) // This bit masks, when set, the Parity bit: XC…
76540 … (0x1<<15) // This bit masks, when set, the Parity bit: XC…
76542 … (0x1<<15) // This bit masks, when set, the Parity bit: XC…
76544 … (0x1<<16) // This bit masks, when set, the Parity bit: XC…
76546 … (0x1<<16) // This bit masks, when set, the Parity bit: XC…
76548 … (0x1<<17) // This bit masks, when set, the Parity bit: XC…
76550 … (0x1<<17) // This bit masks, when set, the Parity bit: XC…
76552 … (0x1<<18) // This bit masks, when set, the Parity bit: XC…
76554 … (0x1<<18) // This bit masks, when set, the Parity bit: XC…
76556 … (0x1<<19) // This bit masks, when set, the Parity bit: XC…
76558 … (0x1<<19) // This bit masks, when set, the Parity bit: XC…
76560 … (0x1<<20) // This bit masks, when set, the Parity bit: XC…
76562 … (0x1<<20) // This bit masks, when set, the Parity bit: XC…
76564 … (0x1<<21) // This bit masks, when set, the Parity bit: XC…
76566 … (0x1<<21) // This bit masks, when set, the Parity bit: XC…
76568 … (0x1<<22) // This bit masks, when set, the Parity bit: XC…
76570 … (0x1<<22) // This bit masks, when set, the Parity bit: XC…
76572 … (0x1<<24) // This bit masks, when set, the Parity bit: XC…
76574 … (0x1<<23) // This bit masks, when set, the Parity bit: XC…
76576 … (0x1<<23) // This bit masks, when set, the Parity bit: XC…
76578 … (0x1<<25) // This bit masks, when set, the Parity bit: XC…
76580 … (0x1<<24) // This bit masks, when set, the Parity bit: XC…
76582 … (0x1<<24) // This bit masks, when set, the Parity bit: XC…
76584 … (0x1<<25) // This bit masks, when set, the Parity bit: XC…
76586 … (0x1<<25) // This bit masks, when set, the Parity bit: XC…
76588 … (0x1<<26) // This bit masks, when set, the Parity bit: XC…
76590 … (0x1<<26) // This bit masks, when set, the Parity bit: XC…
76592 … (0x1<<27) // This bit masks, when set, the Parity bit: XC…
76594 … (0x1<<28) // This bit masks, when set, the Parity bit: XC…
76596 … (0x1<<28) // This bit masks, when set, the Parity bit: XC…
76598 … (0x1<<29) // This bit masks, when set, the Parity bit: XC…
76600 … (0x1<<29) // This bit masks, when set, the Parity bit: XC…
76602 … (0x1<<30) // This bit masks, when set, the Parity bit: XC…
76604 … (0x1<<0) // This bit masks, when set, the Parity bit: XC…
76606 … (0x1<<5) // This bit masks, when set, the Parity bit: XC…
76608 … (0x1<<8) // This bit masks, when set, the Parity bit: XC…
76610 … (0x1<<23) // This bit masks, when set, the Parity bit: XC…
76612 … (0x1<<27) // This bit masks, when set, the Parity bit: XC…
76614 … (0x1<<6) // This bit masks, when set, the Parity bit: XC…
76616 … (0x1<<7) // This bit masks, when set, the Parity bit: XC…
76618 … (0x1<<8) // This bit masks, when set, the Parity bit: XC…
76620 … (0x1<<30) // This bit masks, when set, the Parity bit: XC…
76623 … (0x1<<0) // This bit masks, when set, the Parity bit: XC…
76625 … (0x1<<1) // This bit masks, when set, the Parity bit: XC…
76627 … (0x1<<1) // This bit masks, when set, the Parity bit: XC…
76629 … (0x1<<2) // This bit masks, when set, the Parity bit: XC…
76631 … (0x1<<2) // This bit masks, when set, the Parity bit: XC…
76633 … (0x1<<3) // This bit masks, when set, the Parity bi…
76634 …CM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_K2_E5_SHIFT 3
76635 … (0x1<<3) // This bit masks, when set, the Parity bi…
76636 …CM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_BB_SHIFT 3
76637 … (0x1<<4) // This bit masks, when set, the Parity bit: XC…
76639 … (0x1<<4) // This bit masks, when set, the Parity bit: XC…
76641 … (0x1<<5) // This bit masks, when set, the Parity bit: XC…
76643 … (0x1<<5) // This bit masks, when set, the Parity bit: XC…
76645 … (0x1<<6) // This bit masks, when set, the Parity bit: XC…
76647 … (0x1<<6) // This bit masks, when set, the Parity bit: XC…
76649 … (0x1<<7) // This bit masks, when set, the Parity bit: XC…
76651 … (0x1<<7) // This bit masks, when set, the Parity bit: XC…
76653 … (0x1<<8) // This bit masks, when set, the Parity bit: XC…
76655 … (0x1<<8) // This bit masks, when set, the Parity bit: XC…
76657 … (0x1<<9) // This bit masks, when set, the Parity bit: XC…
76659 … (0x1<<9) // This bit masks, when set, the Parity bit: XC…
76661 … (0x1<<10) // This bit masks, when set, the Parity bit: XC…
76663 … (0x1<<10) // This bit masks, when set, the Parity bit: XC…
76665 … (0x1<<11) // This bit masks, when set, the Parity bit: XC…
76667 … (0x1<<0) // This bit masks, when set, the Parity bit: XC…
76678 …03_I_ECC_2_EN (0x1<<3) // Enable ECC for m…
76679 …CM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_2_EN_SHIFT 3
76715 …_MEM003_I_ECC_2_PRTY (0x1<<3) // Set parity only …
76716 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_2_PRTY_SHIFT 3
76752 …ED_0_MEM003_I_ECC_2_CORRECT (0x1<<3) // Record if a corr…
76753 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_2_CORRECT_SHIFT 3
76781 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
76783 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76784 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76785 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76786 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76787 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76788 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76789 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76790 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76791 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76792 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76793 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76794 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76795 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76796 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76797 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76798 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76799 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76800 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76801 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76802 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76803 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76804 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76805 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76806 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76807 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76808 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76809 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76810 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76811 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76812 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76813 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76814 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76815 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76816 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76817 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76818 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76819 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76820 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76821 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76822 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76823 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76824 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76825 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76826 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76827 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76828 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76829 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76830 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76831 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76832 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76833 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76834 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76835 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76836 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76849 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76850 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76851 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76852 …esponding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir gr…
76853 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76854 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
76855 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
76856 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76857 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76858 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76859 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76860 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76861 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76862 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76863 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76864 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76865 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76866 … 0x1000680UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
76868 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
76879 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
76880 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
76881 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
76883 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
76888 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
76889 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
76890 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
76891 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
76905 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76906 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76907 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76908 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76909 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76910 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76911 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76912 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76913 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76914 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76915 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76916 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76917 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76918 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76919 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76920 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76921 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76922 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76923 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76924 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76925 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76926 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76927 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76928 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
76937 …CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.
76939 …CON_BUF_CRD_AGGST.SM_CON_BUF_CRD_AGGST need be no more than Storm Connection command buffer size=3.
76942 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
76943 …-Other PQ; 1-TX PQ); if bit[9]=0; then [8:6] reserved; [5:0] Physical queue connection number (que…
76944 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
76945 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
76946 … 0x1000a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
76947 … 0x1000a10UL //Access:R DataWidth:0x1 // In-process Table almost …
76953 … 0x1000a28UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76954 … 0x1000a2cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76955 … 0x1000a30UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76956 … 0x1000a34UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76957 … 0x1000a38UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76958 … 0x1000a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76959 … 0x1000a40UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76960 … 0x1000a44UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76961 … 0x1000a48UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76962 … 0x1000a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76963 … 0x1000a50UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76964 … 0x1000a54UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76965 … 0x1000a58UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76966 … 0x1000a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76967 … 0x1000a60UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76968 … 0x1000a64UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
76969 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
76970 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
76971 …th:0x5 // QM output initial credit (XCM TX queues). Max credit available - 16.Write writes the …
76972 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
77008 …tive counter overflow/uder-run. Is reset on read. [0] - If set, there was under-run; [1] - If set,…
77025 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
77028 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
77030 …ess:R DataWidth:0x20 // Debug read from XSEM Input stage buffer with 32-bits granularity. Rea…
77032 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
77034 …ess:R DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Rea…
77036 …ess:R DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Rea…
77038 …ess:R DataWidth:0x20 // Debug read from XSDM Input stage buffer with 32-bits granularity. Rea…
77040 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
77042 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
77043 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
77044 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
77050 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
77053 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
77247 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77248 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77249 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77250 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77251 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77252 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77253 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77254 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77255 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77256 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77257 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77258 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77259 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77260 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77261 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77262 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77273 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
77283 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
77284 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
77286 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
77288 …alue. [28:20] PQ number. [29:29] Reserved. [31:30] Command type: 0 - SET; 1 - DEC; 2 - INC; The ad…
77291 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
77293 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
77294 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
77295 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
77296 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
77333 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77334 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77335 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77336 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77337 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77338 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77346 …L_ERR (0x1<<3) // Write to full MS…
77347 …CM_REG_INT_STS_0_IS_MSDM_OVFL_ERR_SHIFT 3
77371 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
77373 … (0x1<<1) // This bit masks, when set, the Interrupt bit: Y…
77375 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Y…
77377 … (0x1<<3) // This bit masks, when set, the Interrupt …
77378 …CM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR_SHIFT 3
77379 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
77381 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
77383 … (0x1<<6) // This bit masks, when set, the Interrupt bit: Y…
77385 … (0x1<<7) // This bit masks, when set, the Interrupt bit: Y…
77387 … (0x1<<8) // This bit masks, when set, the Interrupt bit: Y…
77389 … (0x1<<9) // This bit masks, when set, the Interrupt bit: Y…
77391 … (0x1<<10) // This bit masks, when set, the Interrupt bit: Y…
77393 … (0x1<<11) // This bit masks, when set, the Interrupt bit: Y…
77395 … (0x1<<12) // This bit masks, when set, the Interrupt bit: Y…
77397 … (0x1<<13) // This bit masks, when set, the Interrupt bit: Y…
77399 … (0x1<<14) // This bit masks, when set, the Interrupt bit: Y…
77408 …OVFL_ERR (0x1<<3) // Write to full MS…
77409 …CM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR_SHIFT 3
77439 …_OVFL_ERR (0x1<<3) // Write to full MS…
77440 …CM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR_SHIFT 3
77470 …ER_ERR (0x1<<3) // Read from empty …
77471 …CM_REG_INT_STS_1_IS_QM_P_UNDER_ERR_SHIFT 3
77492 … (0x1<<14) // In-process Table overflo…
77511 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
77513 … (0x1<<1) // This bit masks, when set, the Interrupt bit: Y…
77515 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Y…
77517 … (0x1<<3) // This bit masks, when set, the Interrupt …
77518 …CM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR_SHIFT 3
77519 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
77521 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
77523 … (0x1<<6) // This bit masks, when set, the Interrupt bit: Y…
77525 … (0x1<<7) // This bit masks, when set, the Interrupt bit: Y…
77527 … (0x1<<8) // This bit masks, when set, the Interrupt bit: Y…
77529 … (0x1<<9) // This bit masks, when set, the Interrupt bit: Y…
77531 … (0x1<<10) // This bit masks, when set, the Interrupt bit: Y…
77533 … (0x1<<11) // This bit masks, when set, the Interrupt bit: Y…
77535 … (0x1<<12) // This bit masks, when set, the Interrupt bit: Y…
77537 … (0x1<<13) // This bit masks, when set, the Interrupt bit: Y…
77539 … (0x1<<14) // This bit masks, when set, the Interrupt bit: Y…
77541 … (0x1<<15) // This bit masks, when set, the Interrupt bit: Y…
77543 … (0x1<<16) // This bit masks, when set, the Interrupt bit: Y…
77545 … (0x1<<17) // This bit masks, when set, the Interrupt bit: Y…
77547 … (0x1<<18) // This bit masks, when set, the Interrupt bit: Y…
77549 … (0x1<<19) // This bit masks, when set, the Interrupt bit: Y…
77551 … (0x1<<20) // This bit masks, when set, the Interrupt bit: Y…
77553 … (0x1<<21) // This bit masks, when set, the Interrupt bit: Y…
77555 … (0x1<<22) // This bit masks, when set, the Interrupt bit: Y…
77564 …UNDER_ERR (0x1<<3) // Read from empty …
77565 …CM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR_SHIFT 3
77586 … (0x1<<14) // In-process Table overflo…
77611 …_UNDER_ERR (0x1<<3) // Read from empty …
77612 …CM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR_SHIFT 3
77633 … (0x1<<14) // In-process Table overflo…
77655 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
77664 … (0x1<<0) // This bit masks, when set, the Parity bit: YC…
77666 … (0x1<<1) // This bit masks, when set, the Parity bit: YC…
77668 … (0x1<<2) // This bit masks, when set, the Parity bit: YC…
77670 … (0x1<<3) // This bit masks, when set, the Parity bi…
77671 …CM_REG_PRTY_MASK_H_0_MEM027_I_ECC_0_RF_INT_E5_SHIFT 3
77672 … (0x1<<4) // This bit masks, when set, the Parity bit: YC…
77674 … (0x1<<6) // This bit masks, when set, the Parity bit: YC…
77676 … (0x1<<5) // This bit masks, when set, the Parity bit: YC…
77678 … (0x1<<7) // This bit masks, when set, the Parity bit: YC…
77680 … (0x1<<6) // This bit masks, when set, the Parity bit: YC…
77682 … (0x1<<7) // This bit masks, when set, the Parity bit: YC…
77684 … (0x1<<8) // This bit masks, when set, the Parity bit: YC…
77686 … (0x1<<9) // This bit masks, when set, the Parity bit: YC…
77688 … (0x1<<27) // This bit masks, when set, the Parity bit: YC…
77690 … (0x1<<10) // This bit masks, when set, the Parity bit: YC…
77692 … (0x1<<13) // This bit masks, when set, the Parity bit: YC…
77694 … (0x1<<14) // This bit masks, when set, the Parity bit: YC…
77696 … (0x1<<11) // This bit masks, when set, the Parity bit: YC…
77698 … (0x1<<26) // This bit masks, when set, the Parity bit: YC…
77700 … (0x1<<11) // This bit masks, when set, the Parity bit: YC…
77702 … (0x1<<12) // This bit masks, when set, the Parity bit: YC…
77704 … (0x1<<25) // This bit masks, when set, the Parity bit: YC…
77706 … (0x1<<13) // This bit masks, when set, the Parity bit: YC…
77708 … (0x1<<10) // This bit masks, when set, the Parity bit: YC…
77710 … (0x1<<14) // This bit masks, when set, the Parity bit: YC…
77712 … (0x1<<11) // This bit masks, when set, the Parity bit: YC…
77714 … (0x1<<12) // This bit masks, when set, the Parity bit: YC…
77716 … (0x1<<15) // This bit masks, when set, the Parity bit: YC…
77718 … (0x1<<16) // This bit masks, when set, the Parity bit: YC…
77720 … (0x1<<23) // This bit masks, when set, the Parity bit: YC…
77722 … (0x1<<17) // This bit masks, when set, the Parity bit: YC…
77724 … (0x1<<24) // This bit masks, when set, the Parity bit: YC…
77726 … (0x1<<18) // This bit masks, when set, the Parity bit: YC…
77728 … (0x1<<12) // This bit masks, when set, the Parity bit: YC…
77730 … (0x1<<13) // This bit masks, when set, the Parity bit: YC…
77732 … (0x1<<19) // This bit masks, when set, the Parity bit: YC…
77734 … (0x1<<16) // This bit masks, when set, the Parity bit: YC…
77736 … (0x1<<17) // This bit masks, when set, the Parity bit: YC…
77738 … (0x1<<20) // This bit masks, when set, the Parity bit: YC…
77740 … (0x1<<17) // This bit masks, when set, the Parity bit: YC…
77742 … (0x1<<18) // This bit masks, when set, the Parity bit: YC…
77744 … (0x1<<21) // This bit masks, when set, the Parity bit: YC…
77746 … (0x1<<18) // This bit masks, when set, the Parity bit: YC…
77748 … (0x1<<19) // This bit masks, when set, the Parity bit: YC…
77750 … (0x1<<22) // This bit masks, when set, the Parity bit: YC…
77752 … (0x1<<14) // This bit masks, when set, the Parity bit: YC…
77754 … (0x1<<15) // This bit masks, when set, the Parity bit: YC…
77756 … (0x1<<23) // This bit masks, when set, the Parity bit: YC…
77758 … (0x1<<24) // This bit masks, when set, the Parity bit: YC…
77760 … (0x1<<25) // This bit masks, when set, the Parity bit: YC…
77762 … (0x1<<26) // This bit masks, when set, the Parity bit: YC…
77764 … (0x1<<22) // This bit masks, when set, the Parity bit: YC…
77766 … (0x1<<23) // This bit masks, when set, the Parity bit: YC…
77768 … (0x1<<27) // This bit masks, when set, the Parity bit: YC…
77770 … (0x1<<20) // This bit masks, when set, the Parity bit: YC…
77772 … (0x1<<22) // This bit masks, when set, the Parity bit: YC…
77774 … (0x1<<28) // This bit masks, when set, the Parity bit: YC…
77776 … (0x1<<29) // This bit masks, when set, the Parity bit: YC…
77778 … (0x1<<20) // This bit masks, when set, the Parity bit: YC…
77780 … (0x1<<30) // This bit masks, when set, the Parity bit: YC…
77782 … (0x1<<0) // This bit masks, when set, the Parity bit: YC…
77784 … (0x1<<3) // This bit masks, when set, the Parity bi…
77785 …CM_REG_PRTY_MASK_H_0_MEM022_I_ECC_0_RF_INT_K2_SHIFT 3
77786 … (0x1<<4) // This bit masks, when set, the Parity bit: YC…
77788 … (0x1<<5) // This bit masks, when set, the Parity bit: YC…
77790 … (0x1<<8) // This bit masks, when set, the Parity bit: YC…
77792 … (0x1<<9) // This bit masks, when set, the Parity bit: YC…
77794 … (0x1<<15) // This bit masks, when set, the Parity bit: YC…
77796 … (0x1<<16) // This bit masks, when set, the Parity bit: YC…
77798 … (0x1<<19) // This bit masks, when set, the Parity bit: YC…
77800 … (0x1<<21) // This bit masks, when set, the Parity bit: YC…
77802 … (0x1<<24) // This bit masks, when set, the Parity bit: YC…
77804 … (0x1<<25) // This bit masks, when set, the Parity bit: YC…
77806 … (0x1<<26) // This bit masks, when set, the Parity bit: YC…
77808 … (0x1<<27) // This bit masks, when set, the Parity bit: YC…
77810 … (0x1<<28) // This bit masks, when set, the Parity bit: YC…
77812 … (0x1<<28) // This bit masks, when set, the Parity bit: YC…
77814 … (0x1<<29) // This bit masks, when set, the Parity bit: YC…
77816 … (0x1<<29) // This bit masks, when set, the Parity bit: YC…
77818 … (0x1<<30) // This bit masks, when set, the Parity bit: YC…
77820 … (0x1<<0) // This bit masks, when set, the Parity bit: YC…
77822 … (0x1<<3) // This bit masks, when set, the Parity bi…
77823 …CM_REG_PRTY_MASK_H_0_MEM021_I_ECC_0_RF_INT_BB_SHIFT 3
77824 … (0x1<<4) // This bit masks, when set, the Parity bit: YC…
77826 … (0x1<<5) // This bit masks, when set, the Parity bit: YC…
77828 … (0x1<<8) // This bit masks, when set, the Parity bit: YC…
77830 … (0x1<<9) // This bit masks, when set, the Parity bit: YC…
77832 … (0x1<<21) // This bit masks, when set, the Parity bit: YC…
77834 … (0x1<<30) // This bit masks, when set, the Parity bit: YC…
77837 … (0x1<<0) // This bit masks, when set, the Parity bit: YC…
77839 … (0x1<<1) // This bit masks, when set, the Parity bit: YC…
77841 … (0x1<<2) // This bit masks, when set, the Parity bit: YC…
77843 … (0x1<<0) // This bit masks, when set, the Parity bit: YC…
77845 … (0x1<<3) // This bit masks, when set, the Parity bi…
77846 …CM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5_SHIFT 3
77847 … (0x1<<0) // This bit masks, when set, the Parity bit: YC…
77849 … (0x1<<1) // This bit masks, when set, the Parity bit: YC…
77851 … (0x1<<4) // This bit masks, when set, the Parity bit: YC…
77853 … (0x1<<5) // This bit masks, when set, the Parity bit: YC…
77855 … (0x1<<1) // This bit masks, when set, the Parity bit: YC…
77857 … (0x1<<2) // This bit masks, when set, the Parity bit: YC…
77859 … (0x1<<6) // This bit masks, when set, the Parity bit: YC…
77861 … (0x1<<2) // This bit masks, when set, the Parity bit: YC…
77863 … (0x1<<3) // This bit masks, when set, the Parity bi…
77864 …CM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2_SHIFT 3
77865 … (0x1<<7) // This bit masks, when set, the Parity bit: YC…
77867 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
77868 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
77869 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
77878 …27_I_ECC_0_EN_E5 (0x1<<3) // Enable ECC for m…
77879 …CM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_0_EN_E5_SHIFT 3
77898 …22_I_ECC_0_EN_K2 (0x1<<3) // Enable ECC for m…
77899 …CM_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_0_EN_K2_SHIFT 3
77910 …21_I_ECC_0_EN_BB (0x1<<3) // Enable ECC for m…
77911 …CM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_0_EN_BB_SHIFT 3
77928 …_MEM027_I_ECC_0_PRTY_E5 (0x1<<3) // Set parity only …
77929 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_0_PRTY_E5_SHIFT 3
77948 …_MEM022_I_ECC_0_PRTY_K2 (0x1<<3) // Set parity only …
77949 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_0_PRTY_K2_SHIFT 3
77960 …_MEM021_I_ECC_0_PRTY_BB (0x1<<3) // Set parity only …
77961 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_0_PRTY_BB_SHIFT 3
77978 …ED_0_MEM027_I_ECC_0_CORRECT_E5 (0x1<<3) // Record if a corr…
77979 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_0_CORRECT_E5_SHIFT 3
77998 …ED_0_MEM022_I_ECC_0_CORRECT_K2 (0x1<<3) // Record if a corr…
77999 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_0_CORRECT_K2_SHIFT 3
78010 …ED_0_MEM021_I_ECC_0_CORRECT_BB (0x1<<3) // Record if a corr…
78011 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_0_CORRECT_BB_SHIFT 3
78022 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
78072 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78073 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78074 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78075 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78076 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78077 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78078 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78079 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78080 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78081 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78091 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78092 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78093 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78094 …esponding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir gr…
78095 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78096 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
78097 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
78098 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78099 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78100 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78101 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78102 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78103 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78104 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78105 … 0x1080664UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
78107 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
78108 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
78121 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
78122 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
78123 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
78125 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
78130 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
78131 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
78132 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
78133 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
78150 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78151 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78152 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78153 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78154 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78155 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78156 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78157 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78158 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78159 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78160 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78161 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78162 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78163 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78164 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78165 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78166 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78167 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78168 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78169 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78170 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78171 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78172 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78173 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
78192 …CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.
78194 …CON_BUF_CRD_AGGST.SM_CON_BUF_CRD_AGGST need be no more than Storm Connection command buffer size=3.
78201 …TASK_CMD_BUF_CRD_DIR.SM_TASK_CMD_BUF_CRD_DIR need be no more than Storm Task command buffer size=3.
78203 …_SM_TASK_BUF_CRD_AGGST.SM_TASK_BUF_CRD_AGGST need be no more than Storm Task command buffer size=3.
78213 …3 (REGQ) complies to 320 LCIDs. Maximum context size per LCID is 12. Maximum number of LCIDs allow…
78214 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
78219 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78220 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78221 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78222 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78223 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78224 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78225 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78226 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78227 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78228 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78229 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78230 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78231 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78232 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78233 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78234 … 0x1080964UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
78235 … 0x1080968UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
78236 … 0x108096cUL //Access:RW DataWidth:0x3 // EventID bit width per task type…
78237 … 0x1080970UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
78238 … 0x1080974UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
78239 … 0x1080978UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
78240 … 0x108097cUL //Access:RW DataWidth:0x3 // EventID bit width per task type…
78241 … 0x1080980UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
78242 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
78243 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
78244 … 0x1080a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
78245 … 0x1080a10UL //Access:R DataWidth:0x1 // In-process Table almost …
78253 … 0x1080a30UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78254 … 0x1080a34UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78255 … 0x1080a38UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78256 … 0x1080a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78257 … 0x1080a40UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78258 … 0x1080a44UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78259 … 0x1080a48UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78260 … 0x1080a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78261 … 0x1080a50UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78262 … 0x1080a54UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78263 … 0x1080a58UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78264 … 0x1080a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78265 … 0x1080a60UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78266 … 0x1080a64UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78267 … 0x1080a68UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78268 … 0x1080a6cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
78269 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
78270 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
78271 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
78272 …1 // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the i…
78273 …th:0x3 // TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the i…
78312 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
78314 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
78316 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
78318 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
78320 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
78321 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
78322 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
78323 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
78324 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
78333 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
78336 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
78516 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
78517 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
78519 …ess:R DataWidth:0x20 // Debug read from XYLD Input stage buffer with 32-bits granularity. Rea…
78520 …ess:R DataWidth:0x20 // Debug read from XYLD Input stage buffer with 32-bits granularity. Rea…
78525 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
78526 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
78529 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78530 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78531 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78532 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78533 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78534 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78535 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
78536 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
78539 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
78541 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
78542 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
78543 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
78544 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
78556 …L_ERR (0x1<<3) // Write to full PS…
78557 …CM_REG_INT_STS_0_IS_PSDM_OVFL_ERR_SHIFT 3
78569 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
78571 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
78573 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
78575 … (0x1<<3) // This bit masks, when set, the Interrupt …
78576 …CM_REG_INT_MASK_0_IS_PSDM_OVFL_ERR_SHIFT 3
78577 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
78579 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
78581 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
78583 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
78585 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
78594 …OVFL_ERR (0x1<<3) // Write to full PS…
78595 …CM_REG_INT_STS_WR_0_IS_PSDM_OVFL_ERR_SHIFT 3
78613 …_OVFL_ERR (0x1<<3) // Write to full PS…
78614 …CM_REG_INT_STS_CLR_0_IS_PSDM_OVFL_ERR_SHIFT 3
78630 …R_ERR0_BB_K2 (0x1<<3) // Read from empty …
78631 …CM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_BB_K2_SHIFT 3
78640 …R_ERR1_E5 (0x1<<3) // Read from empty …
78641 …CM_REG_INT_STS_1_IS_GRC_UNDER_ERR1_E5_SHIFT 3
78658 …K2 (0x1<<10) // In-process Table overflo…
78660 … (0x1<<8) // In-process Table overflo…
78679 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
78681 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
78683 … (0x1<<3) // This bit masks, when set, the Interrupt …
78684 …CM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_BB_K2_SHIFT 3
78685 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
78687 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
78689 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
78691 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
78693 … (0x1<<3) // This bit masks, when set, the Interrupt …
78694 …CM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1_E5_SHIFT 3
78695 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
78697 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
78699 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
78701 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
78703 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
78705 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
78707 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
78709 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
78711 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
78713 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
78715 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
78717 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
78719 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
78721 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
78723 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
78725 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
78727 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
78729 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
78736 …NDER_ERR0_BB_K2 (0x1<<3) // Read from empty …
78737 …CM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_BB_K2_SHIFT 3
78746 …NDER_ERR1_E5 (0x1<<3) // Read from empty …
78747 …CM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1_E5_SHIFT 3
78764 …BB_K2 (0x1<<10) // In-process Table overflo…
78766 …_E5 (0x1<<8) // In-process Table overflo…
78789 …UNDER_ERR0_BB_K2 (0x1<<3) // Read from empty …
78790 …CM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_BB_K2_SHIFT 3
78799 …UNDER_ERR1_E5 (0x1<<3) // Read from empty …
78800 …CM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1_E5_SHIFT 3
78817 …_BB_K2 (0x1<<10) // In-process Table overflo…
78819 …L_E5 (0x1<<8) // In-process Table overflo…
78841 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
78850 … (0x1<<0) // This bit masks, when set, the Parity bit: PC…
78852 … (0x1<<1) // This bit masks, when set, the Parity bit: PC…
78854 … (0x1<<2) // This bit masks, when set, the Parity bit: PC…
78856 … (0x1<<3) // This bit masks, when set, the Parity bi…
78857 …CM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_SHIFT 3
78858 … (0x1<<4) // This bit masks, when set, the Parity bit: PC…
78860 … (0x1<<3) // This bit masks, when set, the Parity bi…
78861 …CM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5_SHIFT 3
78862 … (0x1<<4) // This bit masks, when set, the Parity bit: PC…
78864 … (0x1<<5) // This bit masks, when set, the Parity bit: PC…
78866 … (0x1<<4) // This bit masks, when set, the Parity bit: PC…
78868 … (0x1<<3) // This bit masks, when set, the Parity bi…
78869 …CM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT 3
78870 … (0x1<<5) // This bit masks, when set, the Parity bit: PC…
78872 … (0x1<<13) // This bit masks, when set, the Parity bit: PC…
78874 … (0x1<<6) // This bit masks, when set, the Parity bit: PC…
78876 … (0x1<<5) // This bit masks, when set, the Parity bit: PC…
78878 … (0x1<<6) // This bit masks, when set, the Parity bit: PC…
78880 … (0x1<<7) // This bit masks, when set, the Parity bit: PC…
78882 … (0x1<<6) // This bit masks, when set, the Parity bit: PC…
78884 … (0x1<<7) // This bit masks, when set, the Parity bit: PC…
78886 … (0x1<<8) // This bit masks, when set, the Parity bit: PC…
78888 … (0x1<<7) // This bit masks, when set, the Parity bit: PC…
78890 … (0x1<<8) // This bit masks, when set, the Parity bit: PC…
78892 … (0x1<<9) // This bit masks, when set, the Parity bit: PC…
78894 … (0x1<<8) // This bit masks, when set, the Parity bit: PC…
78896 … (0x1<<9) // This bit masks, when set, the Parity bit: PC…
78898 … (0x1<<10) // This bit masks, when set, the Parity bit: PC…
78900 … (0x1<<11) // This bit masks, when set, the Parity bit: PC…
78902 … (0x1<<10) // This bit masks, when set, the Parity bit: PC…
78904 … (0x1<<12) // This bit masks, when set, the Parity bit: PC…
78906 … (0x1<<13) // This bit masks, when set, the Parity bit: PC…
78908 … (0x1<<9) // This bit masks, when set, the Parity bit: PC…
78910 … (0x1<<14) // This bit masks, when set, the Parity bit: PC…
78912 … (0x1<<10) // This bit masks, when set, the Parity bit: PC…
78914 … (0x1<<14) // This bit masks, when set, the Parity bit: PC…
78916 … (0x1<<15) // This bit masks, when set, the Parity bit: PC…
78918 … (0x1<<0) // This bit masks, when set, the Parity bit: PC…
78920 … (0x1<<1) // This bit masks, when set, the Parity bit: PC…
78922 … (0x1<<2) // This bit masks, when set, the Parity bit: PC…
78924 … (0x1<<11) // This bit masks, when set, the Parity bit: PC…
78926 … (0x1<<12) // This bit masks, when set, the Parity bit: PC…
78928 … (0x1<<0) // This bit masks, when set, the Parity bit: PC…
78930 … (0x1<<1) // This bit masks, when set, the Parity bit: PC…
78932 … (0x1<<2) // This bit masks, when set, the Parity bit: PC…
78934 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
78935 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
78936 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
78937 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
78938 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
78939 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
78998 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
79003 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79004 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79005 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79006 …esponding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir gr…
79007 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79008 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
79009 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
79010 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79011 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79012 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79013 … 0x110063cUL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
79015 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
79025 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
79026 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
79027 … DataWidth:0x2 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
79029 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
79034 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
79035 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
79036 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
79037 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
79049 …CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.
79050 …CON_BUF_CRD_AGGST.SM_CON_BUF_CRD_AGGST need be no more than Storm Connection command buffer size=3.
79052 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
79053 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
79054 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
79055 … 0x1100a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
79056 … 0x1100a10UL //Access:R DataWidth:0x1 // In-process Table almost …
79060 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
79076 …ess:R DataWidth:0x20 // Debug read from PSEM Input stage buffer with 32-bits granularity. Rea…
79079 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
79081 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
79082 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
79085 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
79087 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
79123 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
79124 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
79131 …ess:R DataWidth:0x20 // Debug read from YPLD Input stage buffer with 32-bits granularity. Rea…
79133 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
79135 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
79137 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
79138 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
79139 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
79140 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
79177 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79178 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79179 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79180 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79181 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79182 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79183 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79184 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79185 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79186 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79187 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79188 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79189 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79190 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79191 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79192 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79193 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79194 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79195 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79196 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79197 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79198 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79199 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79207 …L_ERR_E5 (0x1<<3) // Write to full MS…
79208 …CM_REG_INT_STS_0_IS_MSDM_OVFL_ERR_E5_SHIFT 3
79211 …L_ERR_BB_K2 (0x1<<3) // Write to full TS…
79212 …CM_REG_INT_STS_0_IS_TSDM_OVFL_ERR_BB_K2_SHIFT 3
79240 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
79242 … (0x1<<1) // This bit masks, when set, the Interrupt bit: T…
79244 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
79246 … (0x1<<3) // This bit masks, when set, the Interrupt …
79247 …CM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR_E5_SHIFT 3
79248 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
79250 … (0x1<<3) // This bit masks, when set, the Interrupt …
79251 …CM_REG_INT_MASK_0_IS_TSDM_OVFL_ERR_BB_K2_SHIFT 3
79252 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
79254 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
79256 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
79258 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
79260 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
79262 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
79264 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
79266 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
79268 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
79270 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
79272 … (0x1<<11) // This bit masks, when set, the Interrupt bit: T…
79274 … (0x1<<12) // This bit masks, when set, the Interrupt bit: T…
79276 … (0x1<<13) // This bit masks, when set, the Interrupt bit: T…
79285 …OVFL_ERR_E5 (0x1<<3) // Write to full MS…
79286 …CM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR_E5_SHIFT 3
79289 …OVFL_ERR_BB_K2 (0x1<<3) // Write to full TS…
79290 …CM_REG_INT_STS_WR_0_IS_TSDM_OVFL_ERR_BB_K2_SHIFT 3
79324 …_OVFL_ERR_E5 (0x1<<3) // Write to full MS…
79325 …CM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR_E5_SHIFT 3
79328 …_OVFL_ERR_BB_K2 (0x1<<3) // Write to full TS…
79329 …CM_REG_INT_STS_CLR_0_IS_TSDM_OVFL_ERR_BB_K2_SHIFT 3
79363 …_ERR (0x1<<3) // Write to full Pb…
79364 …CM_REG_INT_STS_1_IS_PBF_OVFL_ERR_SHIFT 3
79399 … (0x1<<21) // In-process Table overflo…
79426 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
79428 … (0x1<<1) // This bit masks, when set, the Interrupt bit: T…
79430 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
79432 … (0x1<<3) // This bit masks, when set, the Interrupt …
79433 …CM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_SHIFT 3
79434 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
79436 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
79438 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
79440 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
79442 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
79444 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
79446 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
79448 … (0x1<<11) // This bit masks, when set, the Interrupt bit: T…
79450 … (0x1<<12) // This bit masks, when set, the Interrupt bit: T…
79452 … (0x1<<13) // This bit masks, when set, the Interrupt bit: T…
79454 … (0x1<<14) // This bit masks, when set, the Interrupt bit: T…
79456 … (0x1<<15) // This bit masks, when set, the Interrupt bit: T…
79458 … (0x1<<16) // This bit masks, when set, the Interrupt bit: T…
79460 … (0x1<<17) // This bit masks, when set, the Interrupt bit: T…
79462 … (0x1<<18) // This bit masks, when set, the Interrupt bit: T…
79464 … (0x1<<19) // This bit masks, when set, the Interrupt bit: T…
79466 … (0x1<<20) // This bit masks, when set, the Interrupt bit: T…
79468 … (0x1<<21) // This bit masks, when set, the Interrupt bit: T…
79470 … (0x1<<22) // This bit masks, when set, the Interrupt bit: T…
79472 … (0x1<<23) // This bit masks, when set, the Interrupt bit: T…
79474 … (0x1<<24) // This bit masks, when set, the Interrupt bit: T…
79476 … (0x1<<25) // This bit masks, when set, the Interrupt bit: T…
79478 … (0x1<<26) // This bit masks, when set, the Interrupt bit: T…
79480 … (0x1<<27) // This bit masks, when set, the Interrupt bit: T…
79482 … (0x1<<28) // This bit masks, when set, the Interrupt bit: T…
79484 … (0x1<<29) // This bit masks, when set, the Interrupt bit: T…
79486 … (0x1<<30) // This bit masks, when set, the Interrupt bit: T…
79488 … (0x1<<31) // This bit masks, when set, the Interrupt bit: T…
79490 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
79492 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
79501 …VFL_ERR (0x1<<3) // Write to full Pb…
79502 …CM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_SHIFT 3
79537 … (0x1<<21) // In-process Table overflo…
79570 …OVFL_ERR (0x1<<3) // Write to full Pb…
79571 …CM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_SHIFT 3
79606 … (0x1<<21) // In-process Table overflo…
79636 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
79645 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
79647 … (0x1<<1) // This bit masks, when set, the Parity bit: TC…
79649 … (0x1<<2) // This bit masks, when set, the Parity bit: TC…
79651 … (0x1<<3) // This bit masks, when set, the Parity bi…
79652 …CM_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_E5_SHIFT 3
79653 … (0x1<<4) // This bit masks, when set, the Parity bit: TC…
79655 … (0x1<<5) // This bit masks, when set, the Parity bit: TC…
79657 … (0x1<<6) // This bit masks, when set, the Parity bit: TC…
79659 … (0x1<<7) // This bit masks, when set, the Parity bit: TC…
79661 … (0x1<<8) // This bit masks, when set, the Parity bit: TC…
79663 … (0x1<<9) // This bit masks, when set, the Parity bit: TC…
79665 … (0x1<<25) // This bit masks, when set, the Parity bit: TC…
79667 … (0x1<<10) // This bit masks, when set, the Parity bit: TC…
79669 … (0x1<<23) // This bit masks, when set, the Parity bit: TC…
79671 … (0x1<<11) // This bit masks, when set, the Parity bit: TC…
79673 … (0x1<<24) // This bit masks, when set, the Parity bit: TC…
79675 … (0x1<<12) // This bit masks, when set, the Parity bit: TC…
79677 … (0x1<<26) // This bit masks, when set, the Parity bit: TC…
79679 … (0x1<<13) // This bit masks, when set, the Parity bit: TC…
79681 … (0x1<<12) // This bit masks, when set, the Parity bit: TC…
79683 … (0x1<<13) // This bit masks, when set, the Parity bit: TC…
79685 … (0x1<<14) // This bit masks, when set, the Parity bit: TC…
79687 … (0x1<<9) // This bit masks, when set, the Parity bit: TC…
79689 … (0x1<<15) // This bit masks, when set, the Parity bit: TC…
79691 … (0x1<<26) // This bit masks, when set, the Parity bit: TC…
79693 … (0x1<<15) // This bit masks, when set, the Parity bit: TC…
79695 … (0x1<<16) // This bit masks, when set, the Parity bit: TC…
79697 … (0x1<<27) // This bit masks, when set, the Parity bit: TC…
79699 … (0x1<<17) // This bit masks, when set, the Parity bit: TC…
79701 … (0x1<<15) // This bit masks, when set, the Parity bit: TC…
79703 … (0x1<<16) // This bit masks, when set, the Parity bit: TC…
79705 … (0x1<<18) // This bit masks, when set, the Parity bit: TC…
79707 … (0x1<<21) // This bit masks, when set, the Parity bit: TC…
79709 … (0x1<<19) // This bit masks, when set, the Parity bit: TC…
79711 … (0x1<<11) // This bit masks, when set, the Parity bit: TC…
79713 … (0x1<<12) // This bit masks, when set, the Parity bit: TC…
79715 … (0x1<<20) // This bit masks, when set, the Parity bit: TC…
79717 … (0x1<<14) // This bit masks, when set, the Parity bit: TC…
79719 … (0x1<<10) // This bit masks, when set, the Parity bit: TC…
79721 … (0x1<<21) // This bit masks, when set, the Parity bit: TC…
79723 … (0x1<<16) // This bit masks, when set, the Parity bit: TC…
79725 … (0x1<<17) // This bit masks, when set, the Parity bit: TC…
79727 … (0x1<<22) // This bit masks, when set, the Parity bit: TC…
79729 … (0x1<<17) // This bit masks, when set, the Parity bit: TC…
79731 … (0x1<<18) // This bit masks, when set, the Parity bit: TC…
79733 … (0x1<<23) // This bit masks, when set, the Parity bit: TC…
79735 … (0x1<<18) // This bit masks, when set, the Parity bit: TC…
79737 … (0x1<<19) // This bit masks, when set, the Parity bit: TC…
79739 … (0x1<<24) // This bit masks, when set, the Parity bit: TC…
79741 … (0x1<<10) // This bit masks, when set, the Parity bit: TC…
79743 … (0x1<<11) // This bit masks, when set, the Parity bit: TC…
79745 … (0x1<<25) // This bit masks, when set, the Parity bit: TC…
79747 … (0x1<<26) // This bit masks, when set, the Parity bit: TC…
79749 … (0x1<<27) // This bit masks, when set, the Parity bit: TC…
79751 … (0x1<<28) // This bit masks, when set, the Parity bit: TC…
79753 … (0x1<<29) // This bit masks, when set, the Parity bit: TC…
79755 … (0x1<<20) // This bit masks, when set, the Parity bit: TC…
79757 … (0x1<<30) // This bit masks, when set, the Parity bit: TC…
79759 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
79761 … (0x1<<3) // This bit masks, when set, the Parity bi…
79762 …CM_REG_PRTY_MASK_H_0_MEM022_I_ECC_0_RF_INT_K2_SHIFT 3
79763 … (0x1<<4) // This bit masks, when set, the Parity bit: TC…
79765 … (0x1<<5) // This bit masks, when set, the Parity bit: TC…
79767 … (0x1<<6) // This bit masks, when set, the Parity bit: TC…
79769 … (0x1<<7) // This bit masks, when set, the Parity bit: TC…
79771 … (0x1<<8) // This bit masks, when set, the Parity bit: TC…
79773 … (0x1<<13) // This bit masks, when set, the Parity bit: TC…
79775 … (0x1<<14) // This bit masks, when set, the Parity bit: TC…
79777 … (0x1<<19) // This bit masks, when set, the Parity bit: TC…
79779 … (0x1<<21) // This bit masks, when set, the Parity bit: TC…
79781 … (0x1<<20) // This bit masks, when set, the Parity bit: TC…
79783 … (0x1<<22) // This bit masks, when set, the Parity bit: TC…
79785 … (0x1<<22) // This bit masks, when set, the Parity bit: TC…
79787 … (0x1<<23) // This bit masks, when set, the Parity bit: TC…
79789 … (0x1<<24) // This bit masks, when set, the Parity bit: TC…
79791 … (0x1<<25) // This bit masks, when set, the Parity bit: TC…
79793 … (0x1<<27) // This bit masks, when set, the Parity bit: TC…
79795 … (0x1<<28) // This bit masks, when set, the Parity bit: TC…
79797 … (0x1<<28) // This bit masks, when set, the Parity bit: TC…
79799 … (0x1<<29) // This bit masks, when set, the Parity bit: TC…
79801 … (0x1<<29) // This bit masks, when set, the Parity bit: TC…
79803 … (0x1<<30) // This bit masks, when set, the Parity bit: TC…
79805 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
79807 … (0x1<<3) // This bit masks, when set, the Parity bi…
79808 …CM_REG_PRTY_MASK_H_0_MEM021_I_ECC_0_RF_INT_BB_SHIFT 3
79809 … (0x1<<4) // This bit masks, when set, the Parity bit: TC…
79811 … (0x1<<7) // This bit masks, when set, the Parity bit: TC…
79813 … (0x1<<8) // This bit masks, when set, the Parity bit: TC…
79815 … (0x1<<30) // This bit masks, when set, the Parity bit: TC…
79818 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
79820 … (0x1<<1) // This bit masks, when set, the Parity bit: TC…
79822 … (0x1<<2) // This bit masks, when set, the Parity bit: TC…
79824 … (0x1<<3) // This bit masks, when set, the Parity bi…
79825 …CM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_0_E5_SHIFT 3
79826 … (0x1<<4) // This bit masks, when set, the Parity bit: TC…
79828 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
79830 … (0x1<<5) // This bit masks, when set, the Parity bit: TC…
79832 … (0x1<<6) // This bit masks, when set, the Parity bit: TC…
79834 … (0x1<<0) // This bit masks, when set, the Parity bit: TC…
79836 … (0x1<<1) // This bit masks, when set, the Parity bit: TC…
79838 … (0x1<<7) // This bit masks, when set, the Parity bit: TC…
79840 … (0x1<<1) // This bit masks, when set, the Parity bit: TC…
79842 … (0x1<<2) // This bit masks, when set, the Parity bit: TC…
79844 … (0x1<<8) // This bit masks, when set, the Parity bit: TC…
79853 …04_I_ECC_EN_E5 (0x1<<3) // Enable ECC for m…
79854 …CM_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_E5_SHIFT 3
79869 …22_I_ECC_0_EN_K2 (0x1<<3) // Enable ECC for m…
79870 …CM_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_0_EN_K2_SHIFT 3
79883 …21_I_ECC_0_EN_BB (0x1<<3) // Enable ECC for m…
79884 …CM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_0_EN_BB_SHIFT 3
79898 …_MEM004_I_ECC_PRTY_E5 (0x1<<3) // Set parity only …
79899 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_E5_SHIFT 3
79914 …_MEM022_I_ECC_0_PRTY_K2 (0x1<<3) // Set parity only …
79915 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_0_PRTY_K2_SHIFT 3
79928 …_MEM021_I_ECC_0_PRTY_BB (0x1<<3) // Set parity only …
79929 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_0_PRTY_BB_SHIFT 3
79943 …ED_0_MEM004_I_ECC_CORRECT_E5 (0x1<<3) // Record if a corr…
79944 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_E5_SHIFT 3
79959 …ED_0_MEM022_I_ECC_0_CORRECT_K2 (0x1<<3) // Record if a corr…
79960 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_0_CORRECT_K2_SHIFT 3
79973 …ED_0_MEM021_I_ECC_0_CORRECT_BB (0x1<<3) // Record if a corr…
79974 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_0_CORRECT_BB_SHIFT 3
79982 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
80024 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80025 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80026 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80027 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80028 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80029 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80030 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80031 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80032 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80033 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80034 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80035 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80036 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80037 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80038 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80039 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80040 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80041 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80042 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80043 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80053 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80054 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80055 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80056 …esponding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir gr…
80057 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80058 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
80059 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
80060 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80061 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80062 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80063 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80064 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80065 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80066 … 0x1180664UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
80068 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
80069 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
80082 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
80083 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
80084 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
80086 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
80091 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
80092 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
80093 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
80094 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
80111 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80112 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80113 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80114 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80115 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80116 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80117 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80118 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80119 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80120 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80121 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80122 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80123 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80124 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80125 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80126 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80127 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80128 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80129 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80130 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80131 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80132 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80133 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80134 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
80153 …CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.
80155 …CON_BUF_CRD_AGGST.SM_CON_BUF_CRD_AGGST need be no more than Storm Connection command buffer size=3.
80162 …TASK_CMD_BUF_CRD_DIR.SM_TASK_CMD_BUF_CRD_DIR need be no more than Storm Task command buffer size=3.
80164 …_SM_TASK_BUF_CRD_AGGST.SM_TASK_BUF_CRD_AGGST need be no more than Storm Task command buffer size=3.
80174 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
80175 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
80180 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80181 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80182 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80183 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80184 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80185 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80186 … 0x118099cUL //Access:RW DataWidth:0x3 // EventID bit width per task type…
80187 … 0x11809a0UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
80188 … 0x11809a4UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
80189 … 0x11809a8UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
80190 … 0x11809acUL //Access:RW DataWidth:0x3 // EventID bit width per task type…
80191 … 0x11809b0UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
80192 … 0x11809b4UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
80193 … 0x11809b8UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
80194 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
80195 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
80196 … 0x1180a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
80197 … 0x1180a10UL //Access:R DataWidth:0x1 // In-process Table almost …
80207 … 0x1180a38UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80208 … 0x1180a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80209 … 0x1180a40UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80210 … 0x1180a44UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80211 … 0x1180a48UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80212 … 0x1180a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80213 … 0x1180a50UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80214 … 0x1180a54UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80215 … 0x1180a58UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80216 … 0x1180a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80217 … 0x1180a60UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80218 … 0x1180a64UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80219 … 0x1180a68UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80220 … 0x1180a6cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80221 … 0x1180a70UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80222 … 0x1180a74UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
80223 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
80224 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
80225 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
80226 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
80264 …ess:R DataWidth:0x20 // Debug read from TSEM Input stage buffer with 32-bits granularity. Rea…
80267 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
80269 …cess:R DataWidth:0x20 // Debug read from PRS Input stage buffer with 32-bits granularity. Rea…
80271 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
80273 …ess:R DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Rea…
80275 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
80276 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
80277 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
80278 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
80279 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
80288 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
80291 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
80341 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80342 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80343 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80344 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80345 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80346 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80347 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80348 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80349 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80350 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80351 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80352 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80353 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80354 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80355 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80356 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80357 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80358 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80359 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80360 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80361 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80362 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80363 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80364 …size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligne…
80495 …ess:R DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Rea…
80496 …ess:R DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Rea…
80503 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
80510 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
80520 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
80521 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
80528 …ess:R DataWidth:0x20 // Debug read from PTLD Input stage buffer with 32-bits granularity. Rea…
80530 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80531 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80532 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80533 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80534 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80535 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80536 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80537 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80538 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80539 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80540 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80541 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80542 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80543 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80544 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80545 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80546 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
80549 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
80551 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
80552 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
80553 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
80554 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
80591 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80592 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80593 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80594 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80595 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80596 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80604 …L_ERR (0x1<<3) // Write to full MS…
80605 …CM_REG_INT_STS_0_IS_MSDM_OVFL_ERR_SHIFT 3
80653 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
80655 … (0x1<<1) // This bit masks, when set, the Interrupt bit: M…
80657 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
80659 … (0x1<<3) // This bit masks, when set, the Interrupt …
80660 …CM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR_SHIFT 3
80661 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
80663 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
80665 … (0x1<<6) // This bit masks, when set, the Interrupt bit: M…
80667 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
80669 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
80671 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
80673 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
80675 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
80677 … (0x1<<11) // This bit masks, when set, the Interrupt bit: M…
80679 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
80681 … (0x1<<12) // This bit masks, when set, the Interrupt bit: M…
80683 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
80685 … (0x1<<13) // This bit masks, when set, the Interrupt bit: M…
80687 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
80689 … (0x1<<14) // This bit masks, when set, the Interrupt bit: M…
80691 … (0x1<<11) // This bit masks, when set, the Interrupt bit: M…
80693 … (0x1<<15) // This bit masks, when set, the Interrupt bit: M…
80695 … (0x1<<12) // This bit masks, when set, the Interrupt bit: M…
80697 … (0x1<<16) // This bit masks, when set, the Interrupt bit: M…
80699 … (0x1<<13) // This bit masks, when set, the Interrupt bit: M…
80701 … (0x1<<17) // This bit masks, when set, the Interrupt bit: M…
80703 … (0x1<<18) // This bit masks, when set, the Interrupt bit: M…
80705 … (0x1<<19) // This bit masks, when set, the Interrupt bit: M…
80714 …OVFL_ERR (0x1<<3) // Write to full MS…
80715 …CM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR_SHIFT 3
80769 …_OVFL_ERR (0x1<<3) // Write to full MS…
80770 …CM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR_SHIFT 3
80824 …L_ERR (0x1<<3) // Write to full QM…
80825 …CM_REG_INT_STS_1_IS_QM_P_OVFL_ERR_SHIFT 3
80848 … (0x1<<15) // In-process Table overflo…
80871 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
80873 … (0x1<<1) // This bit masks, when set, the Interrupt bit: M…
80875 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
80877 … (0x1<<3) // This bit masks, when set, the Interrupt …
80878 …CM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR_SHIFT 3
80879 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
80881 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
80883 … (0x1<<6) // This bit masks, when set, the Interrupt bit: M…
80885 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
80887 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
80889 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
80891 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
80893 … (0x1<<11) // This bit masks, when set, the Interrupt bit: M…
80895 … (0x1<<12) // This bit masks, when set, the Interrupt bit: M…
80897 … (0x1<<13) // This bit masks, when set, the Interrupt bit: M…
80899 … (0x1<<14) // This bit masks, when set, the Interrupt bit: M…
80901 … (0x1<<15) // This bit masks, when set, the Interrupt bit: M…
80903 … (0x1<<16) // This bit masks, when set, the Interrupt bit: M…
80905 … (0x1<<17) // This bit masks, when set, the Interrupt bit: M…
80907 … (0x1<<18) // This bit masks, when set, the Interrupt bit: M…
80909 … (0x1<<19) // This bit masks, when set, the Interrupt bit: M…
80911 … (0x1<<20) // This bit masks, when set, the Interrupt bit: M…
80913 … (0x1<<21) // This bit masks, when set, the Interrupt bit: M…
80915 … (0x1<<22) // This bit masks, when set, the Interrupt bit: M…
80917 … (0x1<<23) // This bit masks, when set, the Interrupt bit: M…
80919 … (0x1<<24) // This bit masks, when set, the Interrupt bit: M…
80921 … (0x1<<25) // This bit masks, when set, the Interrupt bit: M…
80930 …OVFL_ERR (0x1<<3) // Write to full QM…
80931 …CM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR_SHIFT 3
80954 … (0x1<<15) // In-process Table overflo…
80983 …_OVFL_ERR (0x1<<3) // Write to full QM…
80984 …CM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR_SHIFT 3
81007 … (0x1<<15) // In-process Table overflo…
81033 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
81042 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
81044 … (0x1<<1) // This bit masks, when set, the Parity bit: MC…
81046 … (0x1<<2) // This bit masks, when set, the Parity bit: MC…
81048 … (0x1<<3) // This bit masks, when set, the Parity bi…
81049 …CM_REG_PRTY_MASK_H_0_MEM029_I_ECC_1_RF_INT_E5_SHIFT 3
81050 … (0x1<<4) // This bit masks, when set, the Parity bit: MC…
81052 … (0x1<<5) // This bit masks, when set, the Parity bit: MC…
81054 … (0x1<<6) // This bit masks, when set, the Parity bit: MC…
81056 … (0x1<<7) // This bit masks, when set, the Parity bit: MC…
81058 … (0x1<<8) // This bit masks, when set, the Parity bit: MC…
81060 … (0x1<<14) // This bit masks, when set, the Parity bit: MC…
81062 … (0x1<<9) // This bit masks, when set, the Parity bit: MC…
81064 … (0x1<<10) // This bit masks, when set, the Parity bit: MC…
81066 … (0x1<<13) // This bit masks, when set, the Parity bit: MC…
81068 … (0x1<<11) // This bit masks, when set, the Parity bit: MC…
81070 … (0x1<<12) // This bit masks, when set, the Parity bit: MC…
81072 … (0x1<<9) // This bit masks, when set, the Parity bit: MC…
81074 … (0x1<<13) // This bit masks, when set, the Parity bit: MC…
81076 … (0x1<<11) // This bit masks, when set, the Parity bit: MC…
81078 … (0x1<<14) // This bit masks, when set, the Parity bit: MC…
81080 … (0x1<<15) // This bit masks, when set, the Parity bit: MC…
81082 … (0x1<<26) // This bit masks, when set, the Parity bit: MC…
81084 … (0x1<<16) // This bit masks, when set, the Parity bit: MC…
81086 … (0x1<<27) // This bit masks, when set, the Parity bit: MC…
81088 … (0x1<<17) // This bit masks, when set, the Parity bit: MC…
81090 … (0x1<<18) // This bit masks, when set, the Parity bit: MC…
81092 … (0x1<<24) // This bit masks, when set, the Parity bit: MC…
81094 … (0x1<<19) // This bit masks, when set, the Parity bit: MC…
81096 … (0x1<<15) // This bit masks, when set, the Parity bit: MC…
81098 … (0x1<<20) // This bit masks, when set, the Parity bit: MC…
81100 … (0x1<<17) // This bit masks, when set, the Parity bit: MC…
81102 … (0x1<<21) // This bit masks, when set, the Parity bit: MC…
81104 … (0x1<<18) // This bit masks, when set, the Parity bit: MC…
81106 … (0x1<<22) // This bit masks, when set, the Parity bit: MC…
81108 … (0x1<<19) // This bit masks, when set, the Parity bit: MC…
81110 … (0x1<<23) // This bit masks, when set, the Parity bit: MC…
81112 … (0x1<<12) // This bit masks, when set, the Parity bit: MC…
81114 … (0x1<<24) // This bit masks, when set, the Parity bit: MC…
81116 … (0x1<<25) // This bit masks, when set, the Parity bit: MC…
81118 … (0x1<<26) // This bit masks, when set, the Parity bit: MC…
81120 … (0x1<<27) // This bit masks, when set, the Parity bit: MC…
81122 … (0x1<<23) // This bit masks, when set, the Parity bit: MC…
81124 … (0x1<<28) // This bit masks, when set, the Parity bit: MC…
81126 … (0x1<<21) // This bit masks, when set, the Parity bit: MC…
81128 … (0x1<<29) // This bit masks, when set, the Parity bit: MC…
81130 … (0x1<<30) // This bit masks, when set, the Parity bit: MC…
81132 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
81134 … (0x1<<2) // This bit masks, when set, the Parity bit: MC…
81136 … (0x1<<3) // This bit masks, when set, the Parity bi…
81137 …CM_REG_PRTY_MASK_H_0_MEM023_I_ECC_1_RF_INT_BB_K2_SHIFT 3
81138 … (0x1<<6) // This bit masks, when set, the Parity bit: MC…
81140 … (0x1<<7) // This bit masks, when set, the Parity bit: MC…
81142 … (0x1<<8) // This bit masks, when set, the Parity bit: MC…
81144 … (0x1<<16) // This bit masks, when set, the Parity bit: MC…
81146 … (0x1<<20) // This bit masks, when set, the Parity bit: MC…
81148 … (0x1<<22) // This bit masks, when set, the Parity bit: MC…
81150 … (0x1<<25) // This bit masks, when set, the Parity bit: MC…
81152 … (0x1<<28) // This bit masks, when set, the Parity bit: MC…
81154 … (0x1<<29) // This bit masks, when set, the Parity bit: MC…
81156 … (0x1<<30) // This bit masks, when set, the Parity bit: MC…
81159 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
81161 … (0x1<<1) // This bit masks, when set, the Parity bit: MC…
81163 … (0x1<<2) // This bit masks, when set, the Parity bit: MC…
81165 … (0x1<<3) // This bit masks, when set, the Parity bi…
81166 …CM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_1_E5_SHIFT 3
81167 … (0x1<<0) // This bit masks, when set, the Parity bit: MC…
81169 … (0x1<<4) // This bit masks, when set, the Parity bit: MC…
81171 … (0x1<<1) // This bit masks, when set, the Parity bit: MC…
81173 … (0x1<<5) // This bit masks, when set, the Parity bit: MC…
81175 … (0x1<<6) // This bit masks, when set, the Parity bit: MC…
81177 … (0x1<<2) // This bit masks, when set, the Parity bit: MC…
81179 … (0x1<<7) // This bit masks, when set, the Parity bit: MC…
81181 … (0x1<<3) // This bit masks, when set, the Parity bi…
81182 …CM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_K2_SHIFT 3
81183 … (0x1<<8) // This bit masks, when set, the Parity bit: MC…
81185 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
81186 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
81187 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
81188 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
81196 …29_I_ECC_1_EN_E5 (0x1<<3) // Enable ECC for m…
81197 …CM_REG_MEM_ECC_ENABLE_0_MEM029_I_ECC_1_EN_E5_SHIFT 3
81212 …23_I_ECC_1_EN_BB_K2 (0x1<<3) // Enable ECC for m…
81213 …CM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_1_EN_BB_K2_SHIFT 3
81227 …_MEM029_I_ECC_1_PRTY_E5 (0x1<<3) // Set parity only …
81228 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM029_I_ECC_1_PRTY_E5_SHIFT 3
81243 …_MEM023_I_ECC_1_PRTY_BB_K2 (0x1<<3) // Set parity only …
81244 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_1_PRTY_BB_K2_SHIFT 3
81258 …ED_0_MEM029_I_ECC_1_CORRECT_E5 (0x1<<3) // Record if a corr…
81259 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM029_I_ECC_1_CORRECT_E5_SHIFT 3
81274 …ED_0_MEM023_I_ECC_1_CORRECT_BB_K2 (0x1<<3) // Record if a corr…
81275 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_1_CORRECT_BB_K2_SHIFT 3
81283 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
81333 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81334 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81335 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81336 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81337 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81338 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81339 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81340 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81341 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81342 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81352 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81353 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81354 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81355 …esponding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir gr…
81356 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81357 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
81358 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
81359 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81360 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81361 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81362 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81363 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81364 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81365 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81366 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81367 … 0x120066cUL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
81369 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
81370 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
81383 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
81384 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
81385 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
81387 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
81392 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
81393 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
81394 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
81395 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
81412 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81413 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81414 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81415 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81416 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81417 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81418 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81419 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81420 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81421 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81422 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81423 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81424 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81425 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81426 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81427 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81428 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81429 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81430 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81431 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81432 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81433 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81434 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81435 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
81454 …CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.
81456 …CON_BUF_CRD_AGGST.SM_CON_BUF_CRD_AGGST need be no more than Storm Connection command buffer size=3.
81463 …TASK_CMD_BUF_CRD_DIR.SM_TASK_CMD_BUF_CRD_DIR need be no more than Storm Task command buffer size=3.
81465 …_SM_TASK_BUF_CRD_AGGST.SM_TASK_BUF_CRD_AGGST need be no more than Storm Task command buffer size=3.
81475 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
81476 …e 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER…
81481 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81482 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81483 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81484 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81485 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81486 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81487 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81488 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81489 … 0x1200960UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
81490 … 0x1200964UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
81491 … 0x1200968UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
81492 … 0x120096cUL //Access:RW DataWidth:0x3 // EventID bit width per task type…
81493 … 0x1200970UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
81494 … 0x1200974UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
81495 … 0x1200978UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
81496 … 0x120097cUL //Access:RW DataWidth:0x3 // EventID bit width per task type…
81497 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
81498 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
81499 … 0x1200a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
81500 … 0x1200a10UL //Access:R DataWidth:0x1 // In-process Table almost …
81508 … 0x1200a30UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81509 … 0x1200a34UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81510 … 0x1200a38UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81511 … 0x1200a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81512 … 0x1200a40UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81513 … 0x1200a44UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81514 … 0x1200a48UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81515 … 0x1200a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81516 … 0x1200a50UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81517 … 0x1200a54UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81518 … 0x1200a58UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81519 … 0x1200a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81520 … 0x1200a60UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81521 … 0x1200a64UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81522 … 0x1200a68UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81523 … 0x1200a6cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
81524 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
81525 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
81526 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
81527 …1 // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the i…
81528 …th:0x3 // TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the i…
81568 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
81571 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
81573 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
81575 …ess:R DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Rea…
81577 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
81579 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
81580 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
81581 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
81582 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
81583 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
81592 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
81595 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
81765 …ess:R DataWidth:0x20 // Debug read from TMLD Input stage buffer with 32-bits granularity. Rea…
81766 …ess:R DataWidth:0x20 // Debug read from TMLD Input stage buffer with 32-bits granularity. Rea…
81774 …ess:R DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Rea…
81781 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
81793 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
81794 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
81804 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
81805 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
81808 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81809 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81810 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81811 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81812 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81813 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81814 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81815 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81816 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
81817 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
81820 …fic states and statuses. To initialise the state - write 1 into register; to enable working after …
81826 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
81827 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
81828 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
81829 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
81866 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81867 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81868 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81869 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81870 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81871 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81872 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81873 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81874 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81875 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81876 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81877 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81878 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81879 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81880 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81881 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81889 …L_ERR (0x1<<3) // Write to full XS…
81890 …CM_REG_INT_STS_0_IS_XSDM_OVFL_ERR_SHIFT 3
81924 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
81926 … (0x1<<1) // This bit masks, when set, the Interrupt bit: U…
81928 … (0x1<<2) // This bit masks, when set, the Interrupt bit: U…
81930 … (0x1<<3) // This bit masks, when set, the Interrupt …
81931 …CM_REG_INT_MASK_0_IS_XSDM_OVFL_ERR_SHIFT 3
81932 … (0x1<<4) // This bit masks, when set, the Interrupt bit: U…
81934 … (0x1<<5) // This bit masks, when set, the Interrupt bit: U…
81936 … (0x1<<6) // This bit masks, when set, the Interrupt bit: U…
81938 … (0x1<<7) // This bit masks, when set, the Interrupt bit: U…
81940 … (0x1<<8) // This bit masks, when set, the Interrupt bit: U…
81942 … (0x1<<9) // This bit masks, when set, the Interrupt bit: U…
81944 … (0x1<<10) // This bit masks, when set, the Interrupt bit: U…
81946 … (0x1<<11) // This bit masks, when set, the Interrupt bit: U…
81948 … (0x1<<12) // This bit masks, when set, the Interrupt bit: U…
81950 … (0x1<<13) // This bit masks, when set, the Interrupt bit: U…
81952 … (0x1<<14) // This bit masks, when set, the Interrupt bit: U…
81954 … (0x1<<15) // This bit masks, when set, the Interrupt bit: U…
81956 … (0x1<<16) // This bit masks, when set, the Interrupt bit: U…
81958 … (0x1<<17) // This bit masks, when set, the Interrupt bit: U…
81960 … (0x1<<15) // This bit masks, when set, the Interrupt bit: U…
81962 … (0x1<<16) // This bit masks, when set, the Interrupt bit: U…
81971 …OVFL_ERR (0x1<<3) // Write to full XS…
81972 …CM_REG_INT_STS_WR_0_IS_XSDM_OVFL_ERR_SHIFT 3
82012 …_OVFL_ERR (0x1<<3) // Write to full XS…
82013 …CM_REG_INT_STS_CLR_0_IS_XSDM_OVFL_ERR_SHIFT 3
82059 …_ERR_E5 (0x1<<3) // Write to full Pb…
82060 …CM_REG_INT_STS_1_IS_PBF_OVFL_ERR_E5_SHIFT 3
82061 …R_ERR_BB_K2 (0x1<<3) // Read from empty …
82062 …CM_REG_INT_STS_1_IS_PBF_UNDER_ERR_BB_K2_SHIFT 3
82121 …K2 (0x1<<18) // In-process Table overflo…
82123 … (0x1<<19) // In-process Table overflo…
82166 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
82168 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
82170 … (0x1<<1) // This bit masks, when set, the Interrupt bit: U…
82172 … (0x1<<1) // This bit masks, when set, the Interrupt bit: U…
82174 … (0x1<<2) // This bit masks, when set, the Interrupt bit: U…
82176 … (0x1<<2) // This bit masks, when set, the Interrupt bit: U…
82178 … (0x1<<3) // This bit masks, when set, the Interrupt …
82179 …CM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_E5_SHIFT 3
82180 … (0x1<<3) // This bit masks, when set, the Interrupt …
82181 …CM_REG_INT_MASK_1_IS_PBF_UNDER_ERR_BB_K2_SHIFT 3
82182 … (0x1<<4) // This bit masks, when set, the Interrupt bit: U…
82184 … (0x1<<4) // This bit masks, when set, the Interrupt bit: U…
82186 … (0x1<<5) // This bit masks, when set, the Interrupt bit: U…
82188 … (0x1<<5) // This bit masks, when set, the Interrupt bit: U…
82190 … (0x1<<6) // This bit masks, when set, the Interrupt bit: U…
82192 … (0x1<<6) // This bit masks, when set, the Interrupt bit: U…
82194 … (0x1<<7) // This bit masks, when set, the Interrupt bit: U…
82196 … (0x1<<7) // This bit masks, when set, the Interrupt bit: U…
82198 … (0x1<<8) // This bit masks, when set, the Interrupt bit: U…
82200 … (0x1<<8) // This bit masks, when set, the Interrupt bit: U…
82202 … (0x1<<9) // This bit masks, when set, the Interrupt bit: U…
82204 … (0x1<<9) // This bit masks, when set, the Interrupt bit: U…
82206 … (0x1<<10) // This bit masks, when set, the Interrupt bit: U…
82208 … (0x1<<10) // This bit masks, when set, the Interrupt bit: U…
82210 … (0x1<<11) // This bit masks, when set, the Interrupt bit: U…
82212 … (0x1<<11) // This bit masks, when set, the Interrupt bit: U…
82214 … (0x1<<12) // This bit masks, when set, the Interrupt bit: U…
82216 … (0x1<<12) // This bit masks, when set, the Interrupt bit: U…
82218 … (0x1<<13) // This bit masks, when set, the Interrupt bit: U…
82220 … (0x1<<13) // This bit masks, when set, the Interrupt bit: U…
82222 … (0x1<<14) // This bit masks, when set, the Interrupt bit: U…
82224 … (0x1<<14) // This bit masks, when set, the Interrupt bit: U…
82226 … (0x1<<15) // This bit masks, when set, the Interrupt bit: U…
82228 … (0x1<<15) // This bit masks, when set, the Interrupt bit: U…
82230 … (0x1<<16) // This bit masks, when set, the Interrupt bit: U…
82232 … (0x1<<16) // This bit masks, when set, the Interrupt bit: U…
82234 … (0x1<<17) // This bit masks, when set, the Interrupt bit: U…
82236 … (0x1<<17) // This bit masks, when set, the Interrupt bit: U…
82238 … (0x1<<18) // This bit masks, when set, the Interrupt bit: U…
82240 … (0x1<<18) // This bit masks, when set, the Interrupt bit: U…
82242 … (0x1<<19) // This bit masks, when set, the Interrupt bit: U…
82244 … (0x1<<19) // This bit masks, when set, the Interrupt bit: U…
82246 … (0x1<<20) // This bit masks, when set, the Interrupt bit: U…
82248 … (0x1<<20) // This bit masks, when set, the Interrupt bit: U…
82250 … (0x1<<21) // This bit masks, when set, the Interrupt bit: U…
82252 … (0x1<<21) // This bit masks, when set, the Interrupt bit: U…
82254 … (0x1<<22) // This bit masks, when set, the Interrupt bit: U…
82256 … (0x1<<22) // This bit masks, when set, the Interrupt bit: U…
82258 … (0x1<<23) // This bit masks, when set, the Interrupt bit: U…
82260 … (0x1<<23) // This bit masks, when set, the Interrupt bit: U…
82262 … (0x1<<24) // This bit masks, when set, the Interrupt bit: U…
82264 … (0x1<<24) // This bit masks, when set, the Interrupt bit: U…
82266 … (0x1<<25) // This bit masks, when set, the Interrupt bit: U…
82268 … (0x1<<25) // This bit masks, when set, the Interrupt bit: U…
82270 … (0x1<<26) // This bit masks, when set, the Interrupt bit: U…
82272 … (0x1<<26) // This bit masks, when set, the Interrupt bit: U…
82274 … (0x1<<27) // This bit masks, when set, the Interrupt bit: U…
82276 … (0x1<<27) // This bit masks, when set, the Interrupt bit: U…
82278 … (0x1<<28) // This bit masks, when set, the Interrupt bit: U…
82280 … (0x1<<28) // This bit masks, when set, the Interrupt bit: U…
82282 … (0x1<<29) // This bit masks, when set, the Interrupt bit: U…
82297 …VFL_ERR_E5 (0x1<<3) // Write to full Pb…
82298 …CM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_E5_SHIFT 3
82299 …NDER_ERR_BB_K2 (0x1<<3) // Read from empty …
82300 …CM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR_BB_K2_SHIFT 3
82359 …BB_K2 (0x1<<18) // In-process Table overflo…
82361 …E5 (0x1<<19) // In-process Table overflo…
82416 …OVFL_ERR_E5 (0x1<<3) // Write to full Pb…
82417 …CM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_E5_SHIFT 3
82418 …UNDER_ERR_BB_K2 (0x1<<3) // Read from empty …
82419 …CM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR_BB_K2_SHIFT 3
82478 …_BB_K2 (0x1<<18) // In-process Table overflo…
82480 …_E5 (0x1<<19) // In-process Table overflo…
82526 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
82535 … (0x1<<0) // This bit masks, when set, the Parity bit: UC…
82537 … (0x1<<1) // This bit masks, when set, the Parity bit: UC…
82539 … (0x1<<2) // This bit masks, when set, the Parity bit: UC…
82541 … (0x1<<3) // This bit masks, when set, the Parity bi…
82542 …CM_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_E5_SHIFT 3
82543 … (0x1<<4) // This bit masks, when set, the Parity bit: UC…
82545 … (0x1<<5) // This bit masks, when set, the Parity bit: UC…
82547 … (0x1<<6) // This bit masks, when set, the Parity bit: UC…
82549 … (0x1<<7) // This bit masks, when set, the Parity bit: UC…
82551 … (0x1<<9) // This bit masks, when set, the Parity bit: UC…
82553 … (0x1<<8) // This bit masks, when set, the Parity bit: UC…
82555 … (0x1<<10) // This bit masks, when set, the Parity bit: UC…
82557 … (0x1<<9) // This bit masks, when set, the Parity bit: UC…
82559 … (0x1<<13) // This bit masks, when set, the Parity bit: UC…
82561 … (0x1<<10) // This bit masks, when set, the Parity bit: UC…
82563 … (0x1<<17) // This bit masks, when set, the Parity bit: UC…
82565 … (0x1<<11) // This bit masks, when set, the Parity bit: UC…
82567 … (0x1<<12) // This bit masks, when set, the Parity bit: UC…
82569 … (0x1<<15) // This bit masks, when set, the Parity bit: UC…
82571 … (0x1<<13) // This bit masks, when set, the Parity bit: UC…
82573 … (0x1<<16) // This bit masks, when set, the Parity bit: UC…
82575 … (0x1<<14) // This bit masks, when set, the Parity bit: UC…
82577 … (0x1<<14) // This bit masks, when set, the Parity bit: UC…
82579 … (0x1<<15) // This bit masks, when set, the Parity bit: UC…
82581 … (0x1<<29) // This bit masks, when set, the Parity bit: UC…
82583 … (0x1<<16) // This bit masks, when set, the Parity bit: UC…
82585 … (0x1<<18) // This bit masks, when set, the Parity bit: UC…
82587 … (0x1<<17) // This bit masks, when set, the Parity bit: UC…
82589 … (0x1<<19) // This bit masks, when set, the Parity bit: UC…
82591 … (0x1<<18) // This bit masks, when set, the Parity bit: UC…
82593 … (0x1<<20) // This bit masks, when set, the Parity bit: UC…
82595 … (0x1<<19) // This bit masks, when set, the Parity bit: UC…
82597 … (0x1<<21) // This bit masks, when set, the Parity bit: UC…
82599 … (0x1<<20) // This bit masks, when set, the Parity bit: UC…
82601 … (0x1<<23) // This bit masks, when set, the Parity bit: UC…
82603 … (0x1<<21) // This bit masks, when set, the Parity bit: UC…
82605 … (0x1<<24) // This bit masks, when set, the Parity bit: UC…
82607 … (0x1<<22) // This bit masks, when set, the Parity bit: UC…
82609 … (0x1<<23) // This bit masks, when set, the Parity bit: UC…
82611 … (0x1<<24) // This bit masks, when set, the Parity bit: UC…
82613 … (0x1<<26) // This bit masks, when set, the Parity bit: UC…
82615 … (0x1<<25) // This bit masks, when set, the Parity bit: UC…
82617 … (0x1<<27) // This bit masks, when set, the Parity bit: UC…
82619 … (0x1<<26) // This bit masks, when set, the Parity bit: UC…
82621 … (0x1<<27) // This bit masks, when set, the Parity bit: UC…
82623 … (0x1<<28) // This bit masks, when set, the Parity bit: UC…
82625 … (0x1<<30) // This bit masks, when set, the Parity bit: UC…
82627 … (0x1<<29) // This bit masks, when set, the Parity bit: UC…
82629 … (0x1<<30) // This bit masks, when set, the Parity bit: UC…
82631 … (0x1<<0) // This bit masks, when set, the Parity bit: UC…
82633 … (0x1<<3) // This bit masks, when set, the Parity bi…
82634 …CM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT_BB_K2_SHIFT 3
82635 … (0x1<<4) // This bit masks, when set, the Parity bit: UC…
82637 … (0x1<<5) // This bit masks, when set, the Parity bit: UC…
82639 … (0x1<<6) // This bit masks, when set, the Parity bit: UC…
82641 … (0x1<<7) // This bit masks, when set, the Parity bit: UC…
82643 … (0x1<<8) // This bit masks, when set, the Parity bit: UC…
82645 … (0x1<<11) // This bit masks, when set, the Parity bit: UC…
82647 … (0x1<<22) // This bit masks, when set, the Parity bit: UC…
82649 … (0x1<<25) // This bit masks, when set, the Parity bit: UC…
82651 … (0x1<<28) // This bit masks, when set, the Parity bit: UC…
82654 … (0x1<<1) // This bit masks, when set, the Parity bit: UC…
82656 … (0x1<<0) // This bit masks, when set, the Parity bit: UC…
82658 … (0x1<<2) // This bit masks, when set, the Parity bit: UC…
82660 … (0x1<<1) // This bit masks, when set, the Parity bit: UC…
82662 … (0x1<<3) // This bit masks, when set, the Parity bi…
82663 …CM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY_BB_K2_SHIFT 3
82664 … (0x1<<2) // This bit masks, when set, the Parity bit: UC…
82666 … (0x1<<4) // This bit masks, when set, the Parity bit: UC…
82668 … (0x1<<3) // This bit masks, when set, the Parity bi…
82669 …CM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_E5_SHIFT 3
82670 … (0x1<<5) // This bit masks, when set, the Parity bit: UC…
82672 … (0x1<<4) // This bit masks, when set, the Parity bit: UC…
82674 … (0x1<<6) // This bit masks, when set, the Parity bit: UC…
82676 … (0x1<<5) // This bit masks, when set, the Parity bit: UC…
82678 … (0x1<<0) // This bit masks, when set, the Parity bit: UC…
82680 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
82681 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
82682 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
82683 …e msb of each word is an error enable and the other bits decode which data bit should have an erro…
82691 …06_I_ECC_EN_E5 (0x1<<3) // Enable ECC for m…
82692 …CM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_E5_SHIFT 3
82711 …24_I_ECC_0_EN_BB_K2 (0x1<<3) // Enable ECC for m…
82712 …CM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_0_EN_BB_K2_SHIFT 3
82732 …_MEM006_I_ECC_PRTY_E5 (0x1<<3) // Set parity only …
82733 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_E5_SHIFT 3
82752 …_MEM024_I_ECC_0_PRTY_BB_K2 (0x1<<3) // Set parity only …
82753 …CM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_0_PRTY_BB_K2_SHIFT 3
82773 …ED_0_MEM006_I_ECC_CORRECT_E5 (0x1<<3) // Record if a corr…
82774 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_E5_SHIFT 3
82793 …ED_0_MEM024_I_ECC_0_CORRECT_BB_K2 (0x1<<3) // Record if a corr…
82794 …CM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_0_CORRECT_BB_K2_SHIFT 3
82808 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
82850 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82851 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82852 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82853 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82854 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82855 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82856 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82857 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82858 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82859 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82860 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82861 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82862 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82863 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82864 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82865 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82866 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82867 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82882 …onding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82883 …onding to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82884 …onding to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82885 …esponding to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir gr…
82886 …onding to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82887 …onding to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group…
82888 …-usual arbitration operation relative to usual once in a while. Two values have special meaning: 8…
82889 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82890 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82891 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82892 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82893 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82894 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82895 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82896 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82897 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82898 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82899 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82900 … 0x1280684UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
82902 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
82903 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
82916 …Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.
82917 …Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.
82918 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
82920 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
82925 …Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
82926 …Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
82927 …Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx…
82928 …-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is…
82945 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82946 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82947 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82948 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82949 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82950 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82951 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82952 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82953 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82954 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82955 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82956 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82957 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82958 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82959 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82960 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82961 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82962 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82963 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82964 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82965 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82966 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82967 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82968 …ss:RW DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict num…
82987 …CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.
82989 …CON_BUF_CRD_AGGST.SM_CON_BUF_CRD_AGGST need be no more than Storm Connection command buffer size=3.
82996 …TASK_CMD_BUF_CRD_DIR.SM_TASK_CMD_BUF_CRD_DIR need be no more than Storm Task command buffer size=3.
82998 …_SM_TASK_BUF_CRD_AGGST.SM_TASK_BUF_CRD_AGGST need be no more than Storm Task command buffer size=3.
83000 …. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whi…
83001 …. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whi…
83002 …. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whi…
83003 …. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whi…
83004 …. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whi…
83005 …. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whi…
83006 …. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whi…
83007 …. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whi…
83008 …e 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER…
83009 …3 (REGQ) complies to 320 LTIDs. Maximum context size per LTID is 12. Maximum number of LTIDs allow…
83014 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83015 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83016 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83017 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83018 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83019 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83020 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83021 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83022 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83023 … 0x128098cUL //Access:RW DataWidth:0x3 // EventID bit width per task type…
83024 … 0x1280990UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
83025 … 0x1280994UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
83026 … 0x1280998UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
83027 … 0x128099cUL //Access:RW DataWidth:0x3 // EventID bit width per task type…
83028 … 0x12809a0UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
83029 … 0x12809a4UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
83030 … 0x12809a8UL //Access:RW DataWidth:0x3 // EventID bit width per task type…
83031 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
83032 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
83033 … 0x1280a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
83034 … 0x1280a10UL //Access:R DataWidth:0x1 // In-process Table almost …
83044 … 0x1280a38UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83045 … 0x1280a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83046 … 0x1280a40UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83047 … 0x1280a44UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83048 … 0x1280a48UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83049 … 0x1280a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83050 … 0x1280a50UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83051 … 0x1280a54UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83052 … 0x1280a58UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83053 … 0x1280a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83054 … 0x1280a60UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83055 … 0x1280a64UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83056 … 0x1280a68UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83057 … 0x1280a6cUL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83058 … 0x1280a70UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83059 … 0x1280a74UL //Access:RW DataWidth:0x3 // EventID bit width per connectio…
83060 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
83061 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
83062 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
83063 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
83124 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
83127 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
83129 …ess:R DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Rea…
83131 …ess:R DataWidth:0x20 // Debug read from RDIF Input stage buffer with 32-bits granularity. Rea…
83133 …ess:R DataWidth:0x20 // Debug read from TDIF Input stage buffer with 32-bits granularity. Rea…
83135 …ess:R DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Rea…
83137 …ess:R DataWidth:0x20 // Debug read from XSDM Input stage buffer with 32-bits granularity. Rea…
83139 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
83141 …ess:R DataWidth:0x20 // Debug read from YULD Input stage buffer with 32-bits granularity. Rea…
83143 …/Access:RW DataWidth:0x10 // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - off…
83144 …n idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The…
83145 …only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The…
83146 …only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The…
83147 …lowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The…
83156 …- Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: …
83159 …- Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9…
83353 …ess:R DataWidth:0x20 // Debug read from MULD Input stage buffer with 32-bits granularity. Rea…
83354 …ess:R DataWidth:0x20 // Debug read from MULD Input stage buffer with 32-bits granularity. Rea…
83363 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
83365 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83366 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83367 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83368 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83369 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83370 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83371 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83372 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83373 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83374 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83375 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83376 …taWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.
83384 … (0x1<<2) // FIC input enable bit used to enable/disa…
83386 … (0x1<<3) // FOC acknowledge input enable bit us…
83387 …SEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_BB_K2_SHIFT 3
83405 … (0x1<<2) // FOC output otuput enable bit used to enable/disa…
83407 …NABLE_OUT_BB_K2 (0x1<<3) // Passive full out…
83408 …SEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_BB_K2_SHIFT 3
83411 … (0x1<<5) // Stall output enable bit used to enable/disa…
83424 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
83435 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
83438 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
83440 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
83442 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
83444 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
83446 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
83449 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
83451 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
83453 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
83455 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
83458 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
83460 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
83462 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
83464 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
83487 …R_PB_AFFINITY_CORE_A_ONLY_E5 (0x1<<3) // When set, the Af…
83488 …SEM_REG_PASSIVE_BUFFER_DRA_WR_PB_AFFINITY_CORE_A_ONLY_E5_SHIFT 3
83494 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83496 …RROR (0x1<<3) // Error in any one…
83497 …SEM_REG_INT_STS_0_FIC_FIFO_ERROR_SHIFT 3
83522 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83570 … (0x1<<11) // Signals an unknown address in the fast-memory window.
83609 … (0x1<<0) // This bit masks, when set, the Interrupt bit: X…
83611 … (0x1<<1) // This bit masks, when set, the Interrupt bit: X…
83613 … (0x1<<2) // This bit masks, when set, the Interrupt bit: X…
83615 … (0x1<<3) // This bit masks, when set, the Interrupt …
83616 …SEM_REG_INT_MASK_0_FIC_FIFO_ERROR_SHIFT 3
83617 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
83619 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
83621 … (0x1<<6) // This bit masks, when set, the Interrupt bit: X…
83623 … (0x1<<7) // This bit masks, when set, the Interrupt bit: X…
83625 … (0x1<<8) // This bit masks, when set, the Interrupt bit: X…
83627 … (0x1<<9) // This bit masks, when set, the Interrupt bit: X…
83629 … (0x1<<23) // This bit masks, when set, the Interrupt bit: X…
83631 … (0x1<<10) // This bit masks, when set, the Interrupt bit: X…
83633 … (0x1<<25) // This bit masks, when set, the Interrupt bit: X…
83635 … (0x1<<11) // This bit masks, when set, the Interrupt bit: X…
83637 … (0x1<<12) // This bit masks, when set, the Interrupt bit: X…
83639 … (0x1<<13) // This bit masks, when set, the Interrupt bit: X…
83641 … (0x1<<14) // This bit masks, when set, the Interrupt bit: X…
83643 … (0x1<<15) // This bit masks, when set, the Interrupt bit: X…
83645 … (0x1<<16) // This bit masks, when set, the Interrupt bit: X…
83647 … (0x1<<17) // This bit masks, when set, the Interrupt bit: X…
83649 … (0x1<<18) // This bit masks, when set, the Interrupt bit: X…
83651 … (0x1<<19) // This bit masks, when set, the Interrupt bit: X…
83653 … (0x1<<20) // This bit masks, when set, the Interrupt bit: X…
83655 … (0x1<<21) // This bit masks, when set, the Interrupt bit: X…
83657 … (0x1<<22) // This bit masks, when set, the Interrupt bit: X…
83659 … (0x1<<23) // This bit masks, when set, the Interrupt bit: X…
83661 … (0x1<<24) // This bit masks, when set, the Interrupt bit: X…
83663 … (0x1<<25) // This bit masks, when set, the Interrupt bit: X…
83665 … (0x1<<26) // This bit masks, when set, the Interrupt bit: X…
83667 … (0x1<<27) // This bit masks, when set, the Interrupt bit: X…
83669 … (0x1<<28) // This bit masks, when set, the Interrupt bit: X…
83671 … (0x1<<29) // This bit masks, when set, the Interrupt bit: X…
83673 … (0x1<<30) // This bit masks, when set, the Interrupt bit: X…
83675 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
83677 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
83679 … (0x1<<6) // This bit masks, when set, the Interrupt bit: X…
83681 … (0x1<<7) // This bit masks, when set, the Interrupt bit: X…
83683 … (0x1<<8) // This bit masks, when set, the Interrupt bit: X…
83685 … (0x1<<9) // This bit masks, when set, the Interrupt bit: X…
83687 … (0x1<<10) // This bit masks, when set, the Interrupt bit: X…
83689 … (0x1<<11) // This bit masks, when set, the Interrupt bit: X…
83691 … (0x1<<12) // This bit masks, when set, the Interrupt bit: X…
83693 … (0x1<<13) // This bit masks, when set, the Interrupt bit: X…
83695 … (0x1<<14) // This bit masks, when set, the Interrupt bit: X…
83697 … (0x1<<15) // This bit masks, when set, the Interrupt bit: X…
83699 … (0x1<<16) // This bit masks, when set, the Interrupt bit: X…
83701 … (0x1<<17) // This bit masks, when set, the Interrupt bit: X…
83703 … (0x1<<18) // This bit masks, when set, the Interrupt bit: X…
83705 … (0x1<<19) // This bit masks, when set, the Interrupt bit: X…
83707 … (0x1<<20) // This bit masks, when set, the Interrupt bit: X…
83709 … (0x1<<21) // This bit masks, when set, the Interrupt bit: X…
83711 … (0x1<<22) // This bit masks, when set, the Interrupt bit: X…
83713 … (0x1<<24) // This bit masks, when set, the Interrupt bit: X…
83715 … (0x1<<26) // This bit masks, when set, the Interrupt bit: X…
83717 … (0x1<<27) // This bit masks, when set, the Interrupt bit: X…
83719 … (0x1<<28) // This bit masks, when set, the Interrupt bit: X…
83721 … (0x1<<29) // This bit masks, when set, the Interrupt bit: X…
83723 … (0x1<<30) // This bit masks, when set, the Interrupt bit: X…
83725 … (0x1<<31) // This bit masks, when set, the Interrupt bit: X…
83732 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83734 …O_ERROR (0x1<<3) // Error in any one…
83735 …SEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR_SHIFT 3
83760 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83808 … (0x1<<11) // Signals an unknown address in the fast-memory window.
83851 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83853 …FO_ERROR (0x1<<3) // Error in any one…
83854 …SEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR_SHIFT 3
83879 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83927 … (0x1<<11) // Signals an unknown address in the fast-memory window.
83972 …OAD_POP_ERROR_A_E5 (0x1<<3) // fast external lo…
83973 …SEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
84036 …END_WR_ERROR_BB_K2 (0x1<<3) // There was an att…
84037 …SEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
84038 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
84040 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
84042 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
84044 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84054 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
84057 … (0x1<<0) // This bit masks, when set, the Interrupt bit: X…
84059 … (0x1<<1) // This bit masks, when set, the Interrupt bit: X…
84061 … (0x1<<2) // This bit masks, when set, the Interrupt bit: X…
84063 … (0x1<<3) // This bit masks, when set, the Interrupt …
84064 …SEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
84065 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
84067 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
84069 … (0x1<<6) // This bit masks, when set, the Interrupt bit: X…
84071 … (0x1<<7) // This bit masks, when set, the Interrupt bit: X…
84073 … (0x1<<8) // This bit masks, when set, the Interrupt bit: X…
84075 … (0x1<<9) // This bit masks, when set, the Interrupt bit: X…
84077 … (0x1<<10) // This bit masks, when set, the Interrupt bit: X…
84079 … (0x1<<11) // This bit masks, when set, the Interrupt bit: X…
84081 … (0x1<<12) // This bit masks, when set, the Interrupt bit: X…
84083 … (0x1<<13) // This bit masks, when set, the Interrupt bit: X…
84085 … (0x1<<14) // This bit masks, when set, the Interrupt bit: X…
84087 … (0x1<<15) // This bit masks, when set, the Interrupt bit: X…
84089 … (0x1<<16) // This bit masks, when set, the Interrupt bit: X…
84091 … (0x1<<17) // This bit masks, when set, the Interrupt bit: X…
84093 … (0x1<<18) // This bit masks, when set, the Interrupt bit: X…
84095 … (0x1<<19) // This bit masks, when set, the Interrupt bit: X…
84097 … (0x1<<20) // This bit masks, when set, the Interrupt bit: X…
84099 … (0x1<<21) // This bit masks, when set, the Interrupt bit: X…
84101 … (0x1<<22) // This bit masks, when set, the Interrupt bit: X…
84103 … (0x1<<23) // This bit masks, when set, the Interrupt bit: X…
84105 … (0x1<<24) // This bit masks, when set, the Interrupt bit: X…
84107 … (0x1<<25) // This bit masks, when set, the Interrupt bit: X…
84109 … (0x1<<26) // This bit masks, when set, the Interrupt bit: X…
84111 … (0x1<<27) // This bit masks, when set, the Interrupt bit: X…
84113 … (0x1<<28) // This bit masks, when set, the Interrupt bit: X…
84115 … (0x1<<29) // This bit masks, when set, the Interrupt bit: X…
84117 … (0x1<<30) // This bit masks, when set, the Interrupt bit: X…
84119 … (0x1<<31) // This bit masks, when set, the Interrupt bit: X…
84121 … (0x1<<0) // This bit masks, when set, the Interrupt bit: X…
84123 … (0x1<<1) // This bit masks, when set, the Interrupt bit: X…
84125 … (0x1<<2) // This bit masks, when set, the Interrupt bit: X…
84127 … (0x1<<3) // This bit masks, when set, the Interrupt …
84128 …SEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
84129 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
84131 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
84133 … (0x1<<6) // This bit masks, when set, the Interrupt bit: X…
84135 … (0x1<<7) // This bit masks, when set, the Interrupt bit: X…
84137 … (0x1<<8) // This bit masks, when set, the Interrupt bit: X…
84139 … (0x1<<9) // This bit masks, when set, the Interrupt bit: X…
84141 … (0x1<<10) // This bit masks, when set, the Interrupt bit: X…
84143 … (0x1<<11) // This bit masks, when set, the Interrupt bit: X…
84145 … (0x1<<12) // This bit masks, when set, the Interrupt bit: X…
84154 …T_LOAD_POP_ERROR_A_E5 (0x1<<3) // fast external lo…
84155 …SEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
84218 …D_PEND_WR_ERROR_BB_K2 (0x1<<3) // There was an att…
84219 …SEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
84220 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
84222 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
84224 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
84226 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84236 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
84245 …XT_LOAD_POP_ERROR_A_E5 (0x1<<3) // fast external lo…
84246 …SEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
84309 …AD_PEND_WR_ERROR_BB_K2 (0x1<<3) // There was an att…
84310 …SEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
84311 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
84313 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
84315 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
84317 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84327 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
84336 …AST_DBG_PUSH_ERROR_B_E5 (0x1<<3) // Fast Debug FIFO …
84337 …SEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
84356 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84358 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84393 … (0x1<<0) // This bit masks, when set, the Interrupt bit: X…
84395 … (0x1<<1) // This bit masks, when set, the Interrupt bit: X…
84397 … (0x1<<2) // This bit masks, when set, the Interrupt bit: X…
84399 … (0x1<<3) // This bit masks, when set, the Interrupt …
84400 …SEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
84401 … (0x1<<4) // This bit masks, when set, the Interrupt bit: X…
84403 … (0x1<<5) // This bit masks, when set, the Interrupt bit: X…
84405 … (0x1<<6) // This bit masks, when set, the Interrupt bit: X…
84407 … (0x1<<7) // This bit masks, when set, the Interrupt bit: X…
84409 … (0x1<<8) // This bit masks, when set, the Interrupt bit: X…
84411 … (0x1<<9) // This bit masks, when set, the Interrupt bit: X…
84413 … (0x1<<10) // This bit masks, when set, the Interrupt bit: X…
84415 … (0x1<<11) // This bit masks, when set, the Interrupt bit: X…
84417 … (0x1<<12) // This bit masks, when set, the Interrupt bit: X…
84419 … (0x1<<13) // This bit masks, when set, the Interrupt bit: X…
84421 … (0x1<<14) // This bit masks, when set, the Interrupt bit: X…
84423 … (0x1<<15) // This bit masks, when set, the Interrupt bit: X…
84425 … (0x1<<16) // This bit masks, when set, the Interrupt bit: X…
84427 … (0x1<<17) // This bit masks, when set, the Interrupt bit: X…
84429 … (0x1<<18) // This bit masks, when set, the Interrupt bit: X…
84431 … (0x1<<19) // This bit masks, when set, the Interrupt bit: X…
84433 … (0x1<<20) // This bit masks, when set, the Interrupt bit: X…
84435 … (0x1<<21) // This bit masks, when set, the Interrupt bit: X…
84437 … (0x1<<22) // This bit masks, when set, the Interrupt bit: X…
84439 … (0x1<<23) // This bit masks, when set, the Interrupt bit: X…
84441 … (0x1<<24) // This bit masks, when set, the Interrupt bit: X…
84443 … (0x1<<25) // This bit masks, when set, the Interrupt bit: X…
84445 …E5 (0x1<<26) // This bit masks, when set, the Interrupt bit: X…
84447 …E5 (0x1<<27) // This bit masks, when set, the Interrupt bit: X…
84449 … (0x1<<28) // This bit masks, when set, the Interrupt bit: X…
84451 … (0x1<<29) // This bit masks, when set, the Interrupt bit: X…
84453 … (0x1<<30) // This bit masks, when set, the Interrupt bit: X…
84462 …C_FAST_DBG_PUSH_ERROR_B_E5 (0x1<<3) // Fast Debug FIFO …
84463 …SEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
84482 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84484 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84525 …BC_FAST_DBG_PUSH_ERROR_B_E5 (0x1<<3) // Fast Debug FIFO …
84526 …SEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
84545 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84547 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84582 … (0x1<<0) // This bit masks, when set, the Parity bit: XS…
84584 … (0x1<<1) // This bit masks, when set, the Parity bit: XS…
84586 … (0x1<<2) // This bit masks, when set, the Parity bit: XS…
84588 … (0x1<<2) // This bit masks, when set, the Parity bit: XS…
84590 … (0x1<<3) // This bit masks, when set, the Parity bi…
84591 …SEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR_E5_SHIFT 3
84592 … (0x1<<4) // This bit masks, when set, the Parity bit: XS…
84594 … (0x1<<1) // This bit masks, when set, the Parity bit: XS…
84597 … (0x1<<0) // This bit masks, when set, the Parity bit: XS…
84599 … (0x1<<1) // This bit masks, when set, the Parity bit: XS…
84601 … (0x1<<2) // This bit masks, when set, the Parity bit: XS…
84603 … (0x1<<3) // This bit masks, when set, the Parity bi…
84604 …SEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT 3
84605 … (0x1<<4) // This bit masks, when set, the Parity bit: XS…
84607 … (0x1<<5) // This bit masks, when set, the Parity bit: XS…
84609 … (0x1<<6) // This bit masks, when set, the Parity bit: XS…
84628 … 0x1400408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
84629 … 0x140040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
84630 …_R DataWidth:0xf0 // This read-only register provides a vector of bits having an error indicatio…
84633 … DataWidth:0x10 // This read-only register provides a vector of bits having an error indicatio…
84640 … 0x1400458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mod…
84641 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
84642 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
84643 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
84647 … 0x1400600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
84649 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
84650 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
84653 … 0x14006c0UL //Access:RW DataWidth:0x1 // When set, this bit allows the DRA read…
84656 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
84658 …abled even if the partition being written is owned by a thread whose valid bit is not set. Otherwi…
84659 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
84660 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
84662 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
84664 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
84667 …0x1400b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
84674 …1400b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
84675 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
84677 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
84681 …UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assign…
84683 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
84685 …L //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enable vector.
84686 … //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enable vector.
84696 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
84701 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
84711 … DataWidth:0x2 // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit 0 FIFO of Core A, bit 1 FIFO o…
84714 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
84717 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
84720 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
84721 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
84733 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
84734 … DataWidth:0x2 // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit 0 for Core A and bit 1 for Cor…
84738 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
84749 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
84751 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
84756 …ckets. Setting a bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0…
84772 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
84778 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
84779 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
84780 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
84781 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
84782 … 0x1408000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the ex…
84788 …3 - state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. …
84793 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
84794 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
84807 … (0x1<<2) // FIC input enable bit used to enable/disa…
84809 … (0x1<<3) // FOC acknowledge input enable bit us…
84810 …SEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_BB_K2_SHIFT 3
84828 … (0x1<<2) // FOC output otuput enable bit used to enable/disa…
84830 …NABLE_OUT_BB_K2 (0x1<<3) // Passive full out…
84831 …SEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_BB_K2_SHIFT 3
84834 … (0x1<<5) // Stall output enable bit used to enable/disa…
84847 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
84858 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
84861 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
84863 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
84865 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
84867 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
84869 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
84872 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
84874 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
84876 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
84878 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
84881 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
84883 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
84885 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
84887 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
84910 …R_PB_AFFINITY_CORE_A_ONLY_E5 (0x1<<3) // When set, the Af…
84911 …SEM_REG_PASSIVE_BUFFER_DRA_WR_PB_AFFINITY_CORE_A_ONLY_E5_SHIFT 3
84917 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
84919 …RROR (0x1<<3) // Error in any one…
84920 …SEM_REG_INT_STS_0_FIC_FIFO_ERROR_SHIFT 3
84945 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84993 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85032 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
85034 … (0x1<<1) // This bit masks, when set, the Interrupt bit: Y…
85036 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Y…
85038 … (0x1<<3) // This bit masks, when set, the Interrupt …
85039 …SEM_REG_INT_MASK_0_FIC_FIFO_ERROR_SHIFT 3
85040 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
85042 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
85044 … (0x1<<6) // This bit masks, when set, the Interrupt bit: Y…
85046 … (0x1<<7) // This bit masks, when set, the Interrupt bit: Y…
85048 … (0x1<<8) // This bit masks, when set, the Interrupt bit: Y…
85050 … (0x1<<9) // This bit masks, when set, the Interrupt bit: Y…
85052 … (0x1<<23) // This bit masks, when set, the Interrupt bit: Y…
85054 … (0x1<<10) // This bit masks, when set, the Interrupt bit: Y…
85056 … (0x1<<25) // This bit masks, when set, the Interrupt bit: Y…
85058 … (0x1<<11) // This bit masks, when set, the Interrupt bit: Y…
85060 … (0x1<<12) // This bit masks, when set, the Interrupt bit: Y…
85062 … (0x1<<13) // This bit masks, when set, the Interrupt bit: Y…
85064 … (0x1<<14) // This bit masks, when set, the Interrupt bit: Y…
85066 … (0x1<<15) // This bit masks, when set, the Interrupt bit: Y…
85068 … (0x1<<16) // This bit masks, when set, the Interrupt bit: Y…
85070 … (0x1<<17) // This bit masks, when set, the Interrupt bit: Y…
85072 … (0x1<<18) // This bit masks, when set, the Interrupt bit: Y…
85074 … (0x1<<19) // This bit masks, when set, the Interrupt bit: Y…
85076 … (0x1<<20) // This bit masks, when set, the Interrupt bit: Y…
85078 … (0x1<<21) // This bit masks, when set, the Interrupt bit: Y…
85080 … (0x1<<22) // This bit masks, when set, the Interrupt bit: Y…
85082 … (0x1<<23) // This bit masks, when set, the Interrupt bit: Y…
85084 … (0x1<<24) // This bit masks, when set, the Interrupt bit: Y…
85086 … (0x1<<25) // This bit masks, when set, the Interrupt bit: Y…
85088 … (0x1<<26) // This bit masks, when set, the Interrupt bit: Y…
85090 … (0x1<<27) // This bit masks, when set, the Interrupt bit: Y…
85092 … (0x1<<28) // This bit masks, when set, the Interrupt bit: Y…
85094 … (0x1<<29) // This bit masks, when set, the Interrupt bit: Y…
85096 … (0x1<<30) // This bit masks, when set, the Interrupt bit: Y…
85098 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
85100 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
85102 … (0x1<<6) // This bit masks, when set, the Interrupt bit: Y…
85104 … (0x1<<7) // This bit masks, when set, the Interrupt bit: Y…
85106 … (0x1<<8) // This bit masks, when set, the Interrupt bit: Y…
85108 … (0x1<<9) // This bit masks, when set, the Interrupt bit: Y…
85110 … (0x1<<10) // This bit masks, when set, the Interrupt bit: Y…
85112 … (0x1<<11) // This bit masks, when set, the Interrupt bit: Y…
85114 … (0x1<<12) // This bit masks, when set, the Interrupt bit: Y…
85116 … (0x1<<13) // This bit masks, when set, the Interrupt bit: Y…
85118 … (0x1<<14) // This bit masks, when set, the Interrupt bit: Y…
85120 … (0x1<<15) // This bit masks, when set, the Interrupt bit: Y…
85122 … (0x1<<16) // This bit masks, when set, the Interrupt bit: Y…
85124 … (0x1<<17) // This bit masks, when set, the Interrupt bit: Y…
85126 … (0x1<<18) // This bit masks, when set, the Interrupt bit: Y…
85128 … (0x1<<19) // This bit masks, when set, the Interrupt bit: Y…
85130 … (0x1<<20) // This bit masks, when set, the Interrupt bit: Y…
85132 … (0x1<<21) // This bit masks, when set, the Interrupt bit: Y…
85134 … (0x1<<22) // This bit masks, when set, the Interrupt bit: Y…
85136 … (0x1<<24) // This bit masks, when set, the Interrupt bit: Y…
85138 … (0x1<<26) // This bit masks, when set, the Interrupt bit: Y…
85140 … (0x1<<27) // This bit masks, when set, the Interrupt bit: Y…
85142 … (0x1<<28) // This bit masks, when set, the Interrupt bit: Y…
85144 … (0x1<<29) // This bit masks, when set, the Interrupt bit: Y…
85146 … (0x1<<30) // This bit masks, when set, the Interrupt bit: Y…
85148 … (0x1<<31) // This bit masks, when set, the Interrupt bit: Y…
85155 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
85157 …O_ERROR (0x1<<3) // Error in any one…
85158 …SEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR_SHIFT 3
85183 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85231 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85274 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
85276 …FO_ERROR (0x1<<3) // Error in any one…
85277 …SEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR_SHIFT 3
85302 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85350 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85395 …OAD_POP_ERROR_A_E5 (0x1<<3) // fast external lo…
85396 …SEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
85459 …END_WR_ERROR_BB_K2 (0x1<<3) // There was an att…
85460 …SEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
85461 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
85463 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
85465 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
85467 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85477 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
85480 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
85482 … (0x1<<1) // This bit masks, when set, the Interrupt bit: Y…
85484 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Y…
85486 … (0x1<<3) // This bit masks, when set, the Interrupt …
85487 …SEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
85488 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
85490 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
85492 … (0x1<<6) // This bit masks, when set, the Interrupt bit: Y…
85494 … (0x1<<7) // This bit masks, when set, the Interrupt bit: Y…
85496 … (0x1<<8) // This bit masks, when set, the Interrupt bit: Y…
85498 … (0x1<<9) // This bit masks, when set, the Interrupt bit: Y…
85500 … (0x1<<10) // This bit masks, when set, the Interrupt bit: Y…
85502 … (0x1<<11) // This bit masks, when set, the Interrupt bit: Y…
85504 … (0x1<<12) // This bit masks, when set, the Interrupt bit: Y…
85506 … (0x1<<13) // This bit masks, when set, the Interrupt bit: Y…
85508 … (0x1<<14) // This bit masks, when set, the Interrupt bit: Y…
85510 … (0x1<<15) // This bit masks, when set, the Interrupt bit: Y…
85512 … (0x1<<16) // This bit masks, when set, the Interrupt bit: Y…
85514 … (0x1<<17) // This bit masks, when set, the Interrupt bit: Y…
85516 … (0x1<<18) // This bit masks, when set, the Interrupt bit: Y…
85518 … (0x1<<19) // This bit masks, when set, the Interrupt bit: Y…
85520 … (0x1<<20) // This bit masks, when set, the Interrupt bit: Y…
85522 … (0x1<<21) // This bit masks, when set, the Interrupt bit: Y…
85524 … (0x1<<22) // This bit masks, when set, the Interrupt bit: Y…
85526 … (0x1<<23) // This bit masks, when set, the Interrupt bit: Y…
85528 … (0x1<<24) // This bit masks, when set, the Interrupt bit: Y…
85530 … (0x1<<25) // This bit masks, when set, the Interrupt bit: Y…
85532 … (0x1<<26) // This bit masks, when set, the Interrupt bit: Y…
85534 … (0x1<<27) // This bit masks, when set, the Interrupt bit: Y…
85536 … (0x1<<28) // This bit masks, when set, the Interrupt bit: Y…
85538 … (0x1<<29) // This bit masks, when set, the Interrupt bit: Y…
85540 … (0x1<<30) // This bit masks, when set, the Interrupt bit: Y…
85542 … (0x1<<31) // This bit masks, when set, the Interrupt bit: Y…
85544 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
85546 … (0x1<<1) // This bit masks, when set, the Interrupt bit: Y…
85548 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Y…
85550 … (0x1<<3) // This bit masks, when set, the Interrupt …
85551 …SEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
85552 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
85554 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
85556 … (0x1<<6) // This bit masks, when set, the Interrupt bit: Y…
85558 … (0x1<<7) // This bit masks, when set, the Interrupt bit: Y…
85560 … (0x1<<8) // This bit masks, when set, the Interrupt bit: Y…
85562 … (0x1<<9) // This bit masks, when set, the Interrupt bit: Y…
85564 … (0x1<<10) // This bit masks, when set, the Interrupt bit: Y…
85566 … (0x1<<11) // This bit masks, when set, the Interrupt bit: Y…
85568 … (0x1<<12) // This bit masks, when set, the Interrupt bit: Y…
85577 …T_LOAD_POP_ERROR_A_E5 (0x1<<3) // fast external lo…
85578 …SEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
85641 …D_PEND_WR_ERROR_BB_K2 (0x1<<3) // There was an att…
85642 …SEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
85643 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
85645 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
85647 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
85649 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85659 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
85668 …XT_LOAD_POP_ERROR_A_E5 (0x1<<3) // fast external lo…
85669 …SEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
85732 …AD_PEND_WR_ERROR_BB_K2 (0x1<<3) // There was an att…
85733 …SEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
85734 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
85736 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
85738 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
85740 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85750 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
85759 …AST_DBG_PUSH_ERROR_B_E5 (0x1<<3) // Fast Debug FIFO …
85760 …SEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
85779 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85781 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
85816 … (0x1<<0) // This bit masks, when set, the Interrupt bit: Y…
85818 … (0x1<<1) // This bit masks, when set, the Interrupt bit: Y…
85820 … (0x1<<2) // This bit masks, when set, the Interrupt bit: Y…
85822 … (0x1<<3) // This bit masks, when set, the Interrupt …
85823 …SEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
85824 … (0x1<<4) // This bit masks, when set, the Interrupt bit: Y…
85826 … (0x1<<5) // This bit masks, when set, the Interrupt bit: Y…
85828 … (0x1<<6) // This bit masks, when set, the Interrupt bit: Y…
85830 … (0x1<<7) // This bit masks, when set, the Interrupt bit: Y…
85832 … (0x1<<8) // This bit masks, when set, the Interrupt bit: Y…
85834 … (0x1<<9) // This bit masks, when set, the Interrupt bit: Y…
85836 … (0x1<<10) // This bit masks, when set, the Interrupt bit: Y…
85838 … (0x1<<11) // This bit masks, when set, the Interrupt bit: Y…
85840 … (0x1<<12) // This bit masks, when set, the Interrupt bit: Y…
85842 … (0x1<<13) // This bit masks, when set, the Interrupt bit: Y…
85844 … (0x1<<14) // This bit masks, when set, the Interrupt bit: Y…
85846 … (0x1<<15) // This bit masks, when set, the Interrupt bit: Y…
85848 … (0x1<<16) // This bit masks, when set, the Interrupt bit: Y…
85850 … (0x1<<17) // This bit masks, when set, the Interrupt bit: Y…
85852 … (0x1<<18) // This bit masks, when set, the Interrupt bit: Y…
85854 … (0x1<<19) // This bit masks, when set, the Interrupt bit: Y…
85856 … (0x1<<20) // This bit masks, when set, the Interrupt bit: Y…
85858 … (0x1<<21) // This bit masks, when set, the Interrupt bit: Y…
85860 … (0x1<<22) // This bit masks, when set, the Interrupt bit: Y…
85862 … (0x1<<23) // This bit masks, when set, the Interrupt bit: Y…
85864 … (0x1<<24) // This bit masks, when set, the Interrupt bit: Y…
85866 … (0x1<<25) // This bit masks, when set, the Interrupt bit: Y…
85868 …E5 (0x1<<26) // This bit masks, when set, the Interrupt bit: Y…
85870 …E5 (0x1<<27) // This bit masks, when set, the Interrupt bit: Y…
85872 … (0x1<<28) // This bit masks, when set, the Interrupt bit: Y…
85874 … (0x1<<29) // This bit masks, when set, the Interrupt bit: Y…
85876 … (0x1<<30) // This bit masks, when set, the Interrupt bit: Y…
85885 …C_FAST_DBG_PUSH_ERROR_B_E5 (0x1<<3) // Fast Debug FIFO …
85886 …SEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
85905 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85907 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
85948 …BC_FAST_DBG_PUSH_ERROR_B_E5 (0x1<<3) // Fast Debug FIFO …
85949 …SEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
85968 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85970 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
86005 … (0x1<<0) // This bit masks, when set, the Parity bit: YS…
86007 … (0x1<<1) // This bit masks, when set, the Parity bit: YS…
86009 … (0x1<<2) // This bit masks, when set, the Parity bit: YS…
86011 … (0x1<<2) // This bit masks, when set, the Parity bit: YS…
86013 … (0x1<<3) // This bit masks, when set, the Parity bi…
86014 …SEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR_E5_SHIFT 3
86015 … (0x1<<4) // This bit masks, when set, the Parity bit: YS…
86017 … (0x1<<1) // This bit masks, when set, the Parity bit: YS…
86020 … (0x1<<0) // This bit masks, when set, the Parity bit: YS…
86022 … (0x1<<1) // This bit masks, when set, the Parity bit: YS…
86024 … (0x1<<2) // This bit masks, when set, the Parity bit: YS…
86026 … (0x1<<3) // This bit masks, when set, the Parity bi…
86027 …SEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT 3
86028 … (0x1<<4) // This bit masks, when set, the Parity bit: YS…
86030 … (0x1<<5) // This bit masks, when set, the Parity bit: YS…
86032 … (0x1<<6) // This bit masks, when set, the Parity bit: YS…
86051 … 0x1500408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
86052 … 0x150040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
86053 …_R DataWidth:0xf0 // This read-only register provides a vector of bits having an error indicatio…
86056 … DataWidth:0x10 // This read-only register provides a vector of bits having an error indicatio…
86063 … 0x1500458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mod…
86064 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
86065 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
86066 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
86070 … 0x1500600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
86072 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
86073 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
86076 … 0x15006c0UL //Access:RW DataWidth:0x1 // When set, this bit allows the DRA read…
86079 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
86081 …abled even if the partition being written is owned by a thread whose valid bit is not set. Otherwi…
86082 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
86083 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
86085 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
86087 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
86090 …0x1500b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
86097 …1500b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
86098 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
86100 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
86104 …UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assign…
86106 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
86108 …L //Access:RW DataWidth:0xe // Provides access to the thread ordering queue pop-enable vector.
86109 … //Access:RW DataWidth:0xe // Provides access to the thread ordering queue wake-enable vector.
86119 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
86124 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
86134 … DataWidth:0x2 // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit 0 FIFO of Core A, bit 1 FIFO o…
86137 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
86140 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
86143 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
86144 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
86156 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
86157 … DataWidth:0x2 // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit 0 for Core A and bit 1 for Cor…
86161 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
86172 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
86174 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
86179 …ckets. Setting a bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0…
86195 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
86201 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
86202 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
86203 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
86204 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
86205 … 0x1508000UL //Access:WB_R DataWidth:0x4c // Provides read-only access of the ex…
86211 …3 - state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. …
86216 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
86217 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
86231 … (0x1<<2) // FIC input enable bit used to enable/disa…
86233 … (0x1<<3) // FOC acknowledge input enable bit us…
86234 …SEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_BB_K2_SHIFT 3
86252 … (0x1<<2) // FOC output otuput enable bit used to enable/disa…
86254 …NABLE_OUT_BB_K2 (0x1<<3) // Passive full out…
86255 …SEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_BB_K2_SHIFT 3
86258 … (0x1<<5) // Stall output enable bit used to enable/disa…
86271 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
86282 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
86285 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
86287 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
86289 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
86291 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
86293 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
86296 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
86298 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
86300 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
86302 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
86305 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
86307 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
86309 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
86311 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
86334 …R_PB_AFFINITY_CORE_A_ONLY_E5 (0x1<<3) // When set, the Af…
86335 …SEM_REG_PASSIVE_BUFFER_DRA_WR_PB_AFFINITY_CORE_A_ONLY_E5_SHIFT 3
86341 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86343 …RROR (0x1<<3) // Error in any one…
86344 …SEM_REG_INT_STS_0_FIC_FIFO_ERROR_SHIFT 3
86369 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86417 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86456 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
86458 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
86460 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
86462 … (0x1<<3) // This bit masks, when set, the Interrupt …
86463 …SEM_REG_INT_MASK_0_FIC_FIFO_ERROR_SHIFT 3
86464 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
86466 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
86468 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
86470 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
86472 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
86474 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
86476 … (0x1<<23) // This bit masks, when set, the Interrupt bit: P…
86478 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
86480 … (0x1<<25) // This bit masks, when set, the Interrupt bit: P…
86482 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
86484 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
86486 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
86488 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
86490 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
86492 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
86494 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
86496 … (0x1<<18) // This bit masks, when set, the Interrupt bit: P…
86498 … (0x1<<19) // This bit masks, when set, the Interrupt bit: P…
86500 … (0x1<<20) // This bit masks, when set, the Interrupt bit: P…
86502 … (0x1<<21) // This bit masks, when set, the Interrupt bit: P…
86504 … (0x1<<22) // This bit masks, when set, the Interrupt bit: P…
86506 … (0x1<<23) // This bit masks, when set, the Interrupt bit: P…
86508 … (0x1<<24) // This bit masks, when set, the Interrupt bit: P…
86510 … (0x1<<25) // This bit masks, when set, the Interrupt bit: P…
86512 … (0x1<<26) // This bit masks, when set, the Interrupt bit: P…
86514 … (0x1<<27) // This bit masks, when set, the Interrupt bit: P…
86516 … (0x1<<28) // This bit masks, when set, the Interrupt bit: P…
86518 … (0x1<<29) // This bit masks, when set, the Interrupt bit: P…
86520 … (0x1<<30) // This bit masks, when set, the Interrupt bit: P…
86522 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
86524 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
86526 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
86528 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
86530 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
86532 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
86534 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
86536 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
86538 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
86540 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
86542 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
86544 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
86546 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
86548 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
86550 … (0x1<<18) // This bit masks, when set, the Interrupt bit: P…
86552 … (0x1<<19) // This bit masks, when set, the Interrupt bit: P…
86554 … (0x1<<20) // This bit masks, when set, the Interrupt bit: P…
86556 … (0x1<<21) // This bit masks, when set, the Interrupt bit: P…
86558 … (0x1<<22) // This bit masks, when set, the Interrupt bit: P…
86560 … (0x1<<24) // This bit masks, when set, the Interrupt bit: P…
86562 … (0x1<<26) // This bit masks, when set, the Interrupt bit: P…
86564 … (0x1<<27) // This bit masks, when set, the Interrupt bit: P…
86566 … (0x1<<28) // This bit masks, when set, the Interrupt bit: P…
86568 … (0x1<<29) // This bit masks, when set, the Interrupt bit: P…
86570 … (0x1<<30) // This bit masks, when set, the Interrupt bit: P…
86572 … (0x1<<31) // This bit masks, when set, the Interrupt bit: P…
86579 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86581 …O_ERROR (0x1<<3) // Error in any one…
86582 …SEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR_SHIFT 3
86607 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86655 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86698 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86700 …FO_ERROR (0x1<<3) // Error in any one…
86701 …SEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR_SHIFT 3
86726 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86774 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86819 …OAD_POP_ERROR_A_E5 (0x1<<3) // fast external lo…
86820 …SEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
86883 …END_WR_ERROR_BB_K2 (0x1<<3) // There was an att…
86884 …SEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
86885 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
86887 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
86889 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
86891 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86901 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
86904 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
86906 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
86908 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
86910 … (0x1<<3) // This bit masks, when set, the Interrupt …
86911 …SEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
86912 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
86914 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
86916 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
86918 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
86920 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
86922 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
86924 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
86926 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
86928 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
86930 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
86932 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
86934 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
86936 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
86938 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
86940 … (0x1<<18) // This bit masks, when set, the Interrupt bit: P…
86942 … (0x1<<19) // This bit masks, when set, the Interrupt bit: P…
86944 … (0x1<<20) // This bit masks, when set, the Interrupt bit: P…
86946 … (0x1<<21) // This bit masks, when set, the Interrupt bit: P…
86948 … (0x1<<22) // This bit masks, when set, the Interrupt bit: P…
86950 … (0x1<<23) // This bit masks, when set, the Interrupt bit: P…
86952 … (0x1<<24) // This bit masks, when set, the Interrupt bit: P…
86954 … (0x1<<25) // This bit masks, when set, the Interrupt bit: P…
86956 … (0x1<<26) // This bit masks, when set, the Interrupt bit: P…
86958 … (0x1<<27) // This bit masks, when set, the Interrupt bit: P…
86960 … (0x1<<28) // This bit masks, when set, the Interrupt bit: P…
86962 … (0x1<<29) // This bit masks, when set, the Interrupt bit: P…
86964 … (0x1<<30) // This bit masks, when set, the Interrupt bit: P…
86966 … (0x1<<31) // This bit masks, when set, the Interrupt bit: P…
86968 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
86970 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
86972 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
86974 … (0x1<<3) // This bit masks, when set, the Interrupt …
86975 …SEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
86976 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
86978 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
86980 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
86982 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
86984 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
86986 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
86988 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
86990 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
86992 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
87001 …T_LOAD_POP_ERROR_A_E5 (0x1<<3) // fast external lo…
87002 …SEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
87065 …D_PEND_WR_ERROR_BB_K2 (0x1<<3) // There was an att…
87066 …SEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
87067 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
87069 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
87071 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
87073 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
87083 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
87092 …XT_LOAD_POP_ERROR_A_E5 (0x1<<3) // fast external lo…
87093 …SEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
87156 …AD_PEND_WR_ERROR_BB_K2 (0x1<<3) // There was an att…
87157 …SEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
87158 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
87160 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
87162 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
87164 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
87174 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
87183 …AST_DBG_PUSH_ERROR_B_E5 (0x1<<3) // Fast Debug FIFO …
87184 …SEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
87203 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87205 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87240 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
87242 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
87244 … (0x1<<2) // This bit masks, when set, the Interrupt bit: P…
87246 … (0x1<<3) // This bit masks, when set, the Interrupt …
87247 …SEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
87248 … (0x1<<4) // This bit masks, when set, the Interrupt bit: P…
87250 … (0x1<<5) // This bit masks, when set, the Interrupt bit: P…
87252 … (0x1<<6) // This bit masks, when set, the Interrupt bit: P…
87254 … (0x1<<7) // This bit masks, when set, the Interrupt bit: P…
87256 … (0x1<<8) // This bit masks, when set, the Interrupt bit: P…
87258 … (0x1<<9) // This bit masks, when set, the Interrupt bit: P…
87260 … (0x1<<10) // This bit masks, when set, the Interrupt bit: P…
87262 … (0x1<<11) // This bit masks, when set, the Interrupt bit: P…
87264 … (0x1<<12) // This bit masks, when set, the Interrupt bit: P…
87266 … (0x1<<13) // This bit masks, when set, the Interrupt bit: P…
87268 … (0x1<<14) // This bit masks, when set, the Interrupt bit: P…
87270 … (0x1<<15) // This bit masks, when set, the Interrupt bit: P…
87272 … (0x1<<16) // This bit masks, when set, the Interrupt bit: P…
87274 … (0x1<<17) // This bit masks, when set, the Interrupt bit: P…
87276 … (0x1<<18) // This bit masks, when set, the Interrupt bit: P…
87278 … (0x1<<19) // This bit masks, when set, the Interrupt bit: P…
87280 … (0x1<<20) // This bit masks, when set, the Interrupt bit: P…
87282 … (0x1<<21) // This bit masks, when set, the Interrupt bit: P…
87284 … (0x1<<22) // This bit masks, when set, the Interrupt bit: P…
87286 … (0x1<<23) // This bit masks, when set, the Interrupt bit: P…
87288 … (0x1<<24) // This bit masks, when set, the Interrupt bit: P…
87290 … (0x1<<25) // This bit masks, when set, the Interrupt bit: P…
87292 …E5 (0x1<<26) // This bit masks, when set, the Interrupt bit: P…
87294 …E5 (0x1<<27) // This bit masks, when set, the Interrupt bit: P…
87296 … (0x1<<28) // This bit masks, when set, the Interrupt bit: P…
87298 … (0x1<<29) // This bit masks, when set, the Interrupt bit: P…
87300 … (0x1<<30) // This bit masks, when set, the Interrupt bit: P…
87309 …C_FAST_DBG_PUSH_ERROR_B_E5 (0x1<<3) // Fast Debug FIFO …
87310 …SEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
87329 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87331 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87372 …BC_FAST_DBG_PUSH_ERROR_B_E5 (0x1<<3) // Fast Debug FIFO …
87373 …SEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
87392 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87394 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87429 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
87431 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
87433 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
87435 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
87437 … (0x1<<3) // This bit masks, when set, the Parity bi…
87438 …SEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR_E5_SHIFT 3
87439 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
87441 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
87444 … (0x1<<0) // This bit masks, when set, the Parity bit: PS…
87446 … (0x1<<1) // This bit masks, when set, the Parity bit: PS…
87448 … (0x1<<2) // This bit masks, when set, the Parity bit: PS…
87450 … (0x1<<3) // This bit masks, when set, the Parity bi…
87451 …SEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT 3
87452 … (0x1<<4) // This bit masks, when set, the Parity bit: PS…
87454 … (0x1<<5) // This bit masks, when set, the Parity bit: PS…
87473 … 0x1600408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
87474 … 0x160040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
87475 …_R DataWidth:0xf0 // This read-only register provides a vector of bits having an error indicatio…
87478 … DataWidth:0x10 // This read-only register provides a vector of bits having an error indicatio…
87485 … 0x1600458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mod…
87486 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
87487 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
87488 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
87492 … 0x1600600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
87493 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
87494 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
87497 … 0x16006c0UL //Access:RW DataWidth:0x1 // When set, this bit allows the DRA read…
87500 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
87502 …abled even if the partition being written is owned by a thread whose valid bit is not set. Otherwi…
87503 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
87504 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
87506 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
87508 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
87511 …0x1600b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
87518 …1600b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
87519 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
87521 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
87525 …UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assign…
87527 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
87529 …L //Access:RW DataWidth:0x4 // Provides access to the thread ordering queue pop-enable vector.
87530 … //Access:RW DataWidth:0x4 // Provides access to the thread ordering queue wake-enable vector.
87540 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
87545 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
87554 … DataWidth:0x2 // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit 0 FIFO of Core A, bit 1 FIFO o…
87557 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
87560 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
87563 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
87564 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
87575 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
87576 … DataWidth:0x2 // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit 0 for Core A and bit 1 for Cor…
87580 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
87591 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
87593 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
87598 …ckets. Setting a bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0…
87614 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
87620 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
87621 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
87622 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
87623 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
87624 … 0x1608000UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the ex…
87630 …3 - state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. …
87635 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
87636 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
87650 … (0x1<<2) // FIC input enable bit used to enable/disa…
87652 … (0x1<<3) // FOC acknowledge input enable bit us…
87653 …SEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_BB_K2_SHIFT 3
87671 … (0x1<<2) // FOC output otuput enable bit used to enable/disa…
87673 …NABLE_OUT_BB_K2 (0x1<<3) // Passive full out…
87674 …SEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_BB_K2_SHIFT 3
87677 … (0x1<<5) // Stall output enable bit used to enable/disa…
87690 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
87701 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
87704 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
87706 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
87708 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
87710 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
87712 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
87715 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
87717 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
87719 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
87721 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
87724 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
87726 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
87728 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
87730 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
87753 …R_PB_AFFINITY_CORE_A_ONLY_E5 (0x1<<3) // When set, the Af…
87754 …SEM_REG_PASSIVE_BUFFER_DRA_WR_PB_AFFINITY_CORE_A_ONLY_E5_SHIFT 3
87760 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
87762 …RROR (0x1<<3) // Error in any one…
87763 …SEM_REG_INT_STS_0_FIC_FIFO_ERROR_SHIFT 3
87788 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
87836 … (0x1<<11) // Signals an unknown address in the fast-memory window.
87875 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
87877 … (0x1<<1) // This bit masks, when set, the Interrupt bit: T…
87879 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
87881 … (0x1<<3) // This bit masks, when set, the Interrupt …
87882 …SEM_REG_INT_MASK_0_FIC_FIFO_ERROR_SHIFT 3
87883 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
87885 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
87887 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
87889 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
87891 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
87893 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
87895 … (0x1<<23) // This bit masks, when set, the Interrupt bit: T…
87897 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
87899 … (0x1<<25) // This bit masks, when set, the Interrupt bit: T…
87901 … (0x1<<11) // This bit masks, when set, the Interrupt bit: T…
87903 … (0x1<<12) // This bit masks, when set, the Interrupt bit: T…
87905 … (0x1<<13) // This bit masks, when set, the Interrupt bit: T…
87907 … (0x1<<14) // This bit masks, when set, the Interrupt bit: T…
87909 … (0x1<<15) // This bit masks, when set, the Interrupt bit: T…
87911 … (0x1<<16) // This bit masks, when set, the Interrupt bit: T…
87913 … (0x1<<17) // This bit masks, when set, the Interrupt bit: T…
87915 … (0x1<<18) // This bit masks, when set, the Interrupt bit: T…
87917 … (0x1<<19) // This bit masks, when set, the Interrupt bit: T…
87919 … (0x1<<20) // This bit masks, when set, the Interrupt bit: T…
87921 … (0x1<<21) // This bit masks, when set, the Interrupt bit: T…
87923 … (0x1<<22) // This bit masks, when set, the Interrupt bit: T…
87925 … (0x1<<23) // This bit masks, when set, the Interrupt bit: T…
87927 … (0x1<<24) // This bit masks, when set, the Interrupt bit: T…
87929 … (0x1<<25) // This bit masks, when set, the Interrupt bit: T…
87931 … (0x1<<26) // This bit masks, when set, the Interrupt bit: T…
87933 … (0x1<<27) // This bit masks, when set, the Interrupt bit: T…
87935 … (0x1<<28) // This bit masks, when set, the Interrupt bit: T…
87937 … (0x1<<29) // This bit masks, when set, the Interrupt bit: T…
87939 … (0x1<<30) // This bit masks, when set, the Interrupt bit: T…
87941 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
87943 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
87945 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
87947 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
87949 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
87951 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
87953 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
87955 … (0x1<<11) // This bit masks, when set, the Interrupt bit: T…
87957 … (0x1<<12) // This bit masks, when set, the Interrupt bit: T…
87959 … (0x1<<13) // This bit masks, when set, the Interrupt bit: T…
87961 … (0x1<<14) // This bit masks, when set, the Interrupt bit: T…
87963 … (0x1<<15) // This bit masks, when set, the Interrupt bit: T…
87965 … (0x1<<16) // This bit masks, when set, the Interrupt bit: T…
87967 … (0x1<<17) // This bit masks, when set, the Interrupt bit: T…
87969 … (0x1<<18) // This bit masks, when set, the Interrupt bit: T…
87971 … (0x1<<19) // This bit masks, when set, the Interrupt bit: T…
87973 … (0x1<<20) // This bit masks, when set, the Interrupt bit: T…
87975 … (0x1<<21) // This bit masks, when set, the Interrupt bit: T…
87977 … (0x1<<22) // This bit masks, when set, the Interrupt bit: T…
87979 … (0x1<<24) // This bit masks, when set, the Interrupt bit: T…
87981 … (0x1<<26) // This bit masks, when set, the Interrupt bit: T…
87983 … (0x1<<27) // This bit masks, when set, the Interrupt bit: T…
87985 … (0x1<<28) // This bit masks, when set, the Interrupt bit: T…
87987 … (0x1<<29) // This bit masks, when set, the Interrupt bit: T…
87989 … (0x1<<30) // This bit masks, when set, the Interrupt bit: T…
87991 … (0x1<<31) // This bit masks, when set, the Interrupt bit: T…
87998 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
88000 …O_ERROR (0x1<<3) // Error in any one…
88001 …SEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR_SHIFT 3
88026 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88074 … (0x1<<11) // Signals an unknown address in the fast-memory window.
88117 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
88119 …FO_ERROR (0x1<<3) // Error in any one…
88120 …SEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR_SHIFT 3
88145 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88193 … (0x1<<11) // Signals an unknown address in the fast-memory window.
88238 …OAD_POP_ERROR_A_E5 (0x1<<3) // fast external lo…
88239 …SEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
88302 …END_WR_ERROR_BB_K2 (0x1<<3) // There was an att…
88303 …SEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
88304 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
88306 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
88308 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
88310 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88320 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
88323 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
88325 … (0x1<<1) // This bit masks, when set, the Interrupt bit: T…
88327 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
88329 … (0x1<<3) // This bit masks, when set, the Interrupt …
88330 …SEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
88331 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
88333 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
88335 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
88337 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
88339 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
88341 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
88343 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
88345 … (0x1<<11) // This bit masks, when set, the Interrupt bit: T…
88347 … (0x1<<12) // This bit masks, when set, the Interrupt bit: T…
88349 … (0x1<<13) // This bit masks, when set, the Interrupt bit: T…
88351 … (0x1<<14) // This bit masks, when set, the Interrupt bit: T…
88353 … (0x1<<15) // This bit masks, when set, the Interrupt bit: T…
88355 … (0x1<<16) // This bit masks, when set, the Interrupt bit: T…
88357 … (0x1<<17) // This bit masks, when set, the Interrupt bit: T…
88359 … (0x1<<18) // This bit masks, when set, the Interrupt bit: T…
88361 … (0x1<<19) // This bit masks, when set, the Interrupt bit: T…
88363 … (0x1<<20) // This bit masks, when set, the Interrupt bit: T…
88365 … (0x1<<21) // This bit masks, when set, the Interrupt bit: T…
88367 … (0x1<<22) // This bit masks, when set, the Interrupt bit: T…
88369 … (0x1<<23) // This bit masks, when set, the Interrupt bit: T…
88371 … (0x1<<24) // This bit masks, when set, the Interrupt bit: T…
88373 … (0x1<<25) // This bit masks, when set, the Interrupt bit: T…
88375 … (0x1<<26) // This bit masks, when set, the Interrupt bit: T…
88377 … (0x1<<27) // This bit masks, when set, the Interrupt bit: T…
88379 … (0x1<<28) // This bit masks, when set, the Interrupt bit: T…
88381 … (0x1<<29) // This bit masks, when set, the Interrupt bit: T…
88383 … (0x1<<30) // This bit masks, when set, the Interrupt bit: T…
88385 … (0x1<<31) // This bit masks, when set, the Interrupt bit: T…
88387 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
88389 … (0x1<<1) // This bit masks, when set, the Interrupt bit: T…
88391 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
88393 … (0x1<<3) // This bit masks, when set, the Interrupt …
88394 …SEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
88395 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
88397 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
88399 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
88401 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
88403 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
88405 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
88407 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
88409 … (0x1<<11) // This bit masks, when set, the Interrupt bit: T…
88411 … (0x1<<12) // This bit masks, when set, the Interrupt bit: T…
88420 …T_LOAD_POP_ERROR_A_E5 (0x1<<3) // fast external lo…
88421 …SEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
88484 …D_PEND_WR_ERROR_BB_K2 (0x1<<3) // There was an att…
88485 …SEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
88486 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
88488 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
88490 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
88492 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88502 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
88511 …XT_LOAD_POP_ERROR_A_E5 (0x1<<3) // fast external lo…
88512 …SEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
88575 …AD_PEND_WR_ERROR_BB_K2 (0x1<<3) // There was an att…
88576 …SEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
88577 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
88579 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
88581 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
88583 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88593 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
88602 …AST_DBG_PUSH_ERROR_B_E5 (0x1<<3) // Fast Debug FIFO …
88603 …SEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
88622 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88624 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88659 … (0x1<<0) // This bit masks, when set, the Interrupt bit: T…
88661 … (0x1<<1) // This bit masks, when set, the Interrupt bit: T…
88663 … (0x1<<2) // This bit masks, when set, the Interrupt bit: T…
88665 … (0x1<<3) // This bit masks, when set, the Interrupt …
88666 …SEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
88667 … (0x1<<4) // This bit masks, when set, the Interrupt bit: T…
88669 … (0x1<<5) // This bit masks, when set, the Interrupt bit: T…
88671 … (0x1<<6) // This bit masks, when set, the Interrupt bit: T…
88673 … (0x1<<7) // This bit masks, when set, the Interrupt bit: T…
88675 … (0x1<<8) // This bit masks, when set, the Interrupt bit: T…
88677 … (0x1<<9) // This bit masks, when set, the Interrupt bit: T…
88679 … (0x1<<10) // This bit masks, when set, the Interrupt bit: T…
88681 … (0x1<<11) // This bit masks, when set, the Interrupt bit: T…
88683 … (0x1<<12) // This bit masks, when set, the Interrupt bit: T…
88685 … (0x1<<13) // This bit masks, when set, the Interrupt bit: T…
88687 … (0x1<<14) // This bit masks, when set, the Interrupt bit: T…
88689 … (0x1<<15) // This bit masks, when set, the Interrupt bit: T…
88691 … (0x1<<16) // This bit masks, when set, the Interrupt bit: T…
88693 … (0x1<<17) // This bit masks, when set, the Interrupt bit: T…
88695 … (0x1<<18) // This bit masks, when set, the Interrupt bit: T…
88697 … (0x1<<19) // This bit masks, when set, the Interrupt bit: T…
88699 … (0x1<<20) // This bit masks, when set, the Interrupt bit: T…
88701 … (0x1<<21) // This bit masks, when set, the Interrupt bit: T…
88703 … (0x1<<22) // This bit masks, when set, the Interrupt bit: T…
88705 … (0x1<<23) // This bit masks, when set, the Interrupt bit: T…
88707 … (0x1<<24) // This bit masks, when set, the Interrupt bit: T…
88709 … (0x1<<25) // This bit masks, when set, the Interrupt bit: T…
88711 …E5 (0x1<<26) // This bit masks, when set, the Interrupt bit: T…
88713 …E5 (0x1<<27) // This bit masks, when set, the Interrupt bit: T…
88715 … (0x1<<28) // This bit masks, when set, the Interrupt bit: T…
88717 … (0x1<<29) // This bit masks, when set, the Interrupt bit: T…
88719 … (0x1<<30) // This bit masks, when set, the Interrupt bit: T…
88728 …C_FAST_DBG_PUSH_ERROR_B_E5 (0x1<<3) // Fast Debug FIFO …
88729 …SEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
88748 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88750 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88791 …BC_FAST_DBG_PUSH_ERROR_B_E5 (0x1<<3) // Fast Debug FIFO …
88792 …SEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
88811 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88813 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88848 … (0x1<<0) // This bit masks, when set, the Parity bit: TS…
88850 … (0x1<<1) // This bit masks, when set, the Parity bit: TS…
88852 … (0x1<<2) // This bit masks, when set, the Parity bit: TS…
88854 … (0x1<<2) // This bit masks, when set, the Parity bit: TS…
88856 … (0x1<<3) // This bit masks, when set, the Parity bi…
88857 …SEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR_E5_SHIFT 3
88858 … (0x1<<4) // This bit masks, when set, the Parity bit: TS…
88860 … (0x1<<1) // This bit masks, when set, the Parity bit: TS…
88863 … (0x1<<0) // This bit masks, when set, the Parity bit: TS…
88865 … (0x1<<1) // This bit masks, when set, the Parity bit: TS…
88867 … (0x1<<2) // This bit masks, when set, the Parity bit: TS…
88869 … (0x1<<3) // This bit masks, when set, the Parity bi…
88870 …SEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT 3
88871 … (0x1<<4) // This bit masks, when set, the Parity bit: TS…
88873 … (0x1<<5) // This bit masks, when set, the Parity bit: TS…
88892 … 0x1700408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
88893 … 0x170040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
88894 …_R DataWidth:0xf0 // This read-only register provides a vector of bits having an error indicatio…
88897 … DataWidth:0x10 // This read-only register provides a vector of bits having an error indicatio…
88904 … 0x1700458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mod…
88905 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
88906 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
88907 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
88911 … 0x1700600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
88912 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
88913 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
88916 … 0x17006c0UL //Access:RW DataWidth:0x1 // When set, this bit allows the DRA read…
88919 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
88921 …abled even if the partition being written is owned by a thread whose valid bit is not set. Otherwi…
88922 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
88923 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
88925 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
88927 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
88930 …0x1700b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
88937 …1700b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
88938 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
88940 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
88944 …UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assign…
88946 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
88948 …L //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enable vector.
88949 … //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enable vector.
88959 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
88964 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
88973 … DataWidth:0x2 // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit 0 FIFO of Core A, bit 1 FIFO o…
88976 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
88979 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
88982 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
88983 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
88994 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
88995 … DataWidth:0x2 // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit 0 for Core A and bit 1 for Cor…
88999 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
89010 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
89012 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
89017 …ckets. Setting a bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0…
89033 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
89039 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
89040 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
89041 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
89042 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
89043 … 0x1708000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the ex…
89049 …3 - state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. …
89054 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
89055 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
89068 … (0x1<<2) // FIC input enable bit used to enable/disa…
89070 … (0x1<<3) // FOC acknowledge input enable bit us…
89071 …SEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_BB_K2_SHIFT 3
89089 … (0x1<<2) // FOC output otuput enable bit used to enable/disa…
89091 …NABLE_OUT_BB_K2 (0x1<<3) // Passive full out…
89092 …SEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_BB_K2_SHIFT 3
89095 … (0x1<<5) // Stall output enable bit used to enable/disa…
89108 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
89119 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
89122 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
89124 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
89126 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
89128 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
89130 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
89133 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
89135 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
89137 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
89139 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
89142 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
89144 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
89146 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
89148 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
89171 …R_PB_AFFINITY_CORE_A_ONLY_E5 (0x1<<3) // When set, the Af…
89172 …SEM_REG_PASSIVE_BUFFER_DRA_WR_PB_AFFINITY_CORE_A_ONLY_E5_SHIFT 3
89178 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89180 …RROR (0x1<<3) // Error in any one…
89181 …SEM_REG_INT_STS_0_FIC_FIFO_ERROR_SHIFT 3
89206 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89254 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89293 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
89295 … (0x1<<1) // This bit masks, when set, the Interrupt bit: M…
89297 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
89299 … (0x1<<3) // This bit masks, when set, the Interrupt …
89300 …SEM_REG_INT_MASK_0_FIC_FIFO_ERROR_SHIFT 3
89301 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
89303 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
89305 … (0x1<<6) // This bit masks, when set, the Interrupt bit: M…
89307 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
89309 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
89311 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
89313 … (0x1<<23) // This bit masks, when set, the Interrupt bit: M…
89315 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
89317 … (0x1<<25) // This bit masks, when set, the Interrupt bit: M…
89319 … (0x1<<11) // This bit masks, when set, the Interrupt bit: M…
89321 … (0x1<<12) // This bit masks, when set, the Interrupt bit: M…
89323 … (0x1<<13) // This bit masks, when set, the Interrupt bit: M…
89325 … (0x1<<14) // This bit masks, when set, the Interrupt bit: M…
89327 … (0x1<<15) // This bit masks, when set, the Interrupt bit: M…
89329 … (0x1<<16) // This bit masks, when set, the Interrupt bit: M…
89331 … (0x1<<17) // This bit masks, when set, the Interrupt bit: M…
89333 … (0x1<<18) // This bit masks, when set, the Interrupt bit: M…
89335 … (0x1<<19) // This bit masks, when set, the Interrupt bit: M…
89337 … (0x1<<20) // This bit masks, when set, the Interrupt bit: M…
89339 … (0x1<<21) // This bit masks, when set, the Interrupt bit: M…
89341 … (0x1<<22) // This bit masks, when set, the Interrupt bit: M…
89343 … (0x1<<23) // This bit masks, when set, the Interrupt bit: M…
89345 … (0x1<<24) // This bit masks, when set, the Interrupt bit: M…
89347 … (0x1<<25) // This bit masks, when set, the Interrupt bit: M…
89349 … (0x1<<26) // This bit masks, when set, the Interrupt bit: M…
89351 … (0x1<<27) // This bit masks, when set, the Interrupt bit: M…
89353 … (0x1<<28) // This bit masks, when set, the Interrupt bit: M…
89355 … (0x1<<29) // This bit masks, when set, the Interrupt bit: M…
89357 … (0x1<<30) // This bit masks, when set, the Interrupt bit: M…
89359 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
89361 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
89363 … (0x1<<6) // This bit masks, when set, the Interrupt bit: M…
89365 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
89367 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
89369 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
89371 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
89373 … (0x1<<11) // This bit masks, when set, the Interrupt bit: M…
89375 … (0x1<<12) // This bit masks, when set, the Interrupt bit: M…
89377 … (0x1<<13) // This bit masks, when set, the Interrupt bit: M…
89379 … (0x1<<14) // This bit masks, when set, the Interrupt bit: M…
89381 … (0x1<<15) // This bit masks, when set, the Interrupt bit: M…
89383 … (0x1<<16) // This bit masks, when set, the Interrupt bit: M…
89385 … (0x1<<17) // This bit masks, when set, the Interrupt bit: M…
89387 … (0x1<<18) // This bit masks, when set, the Interrupt bit: M…
89389 … (0x1<<19) // This bit masks, when set, the Interrupt bit: M…
89391 … (0x1<<20) // This bit masks, when set, the Interrupt bit: M…
89393 … (0x1<<21) // This bit masks, when set, the Interrupt bit: M…
89395 … (0x1<<22) // This bit masks, when set, the Interrupt bit: M…
89397 … (0x1<<24) // This bit masks, when set, the Interrupt bit: M…
89399 … (0x1<<26) // This bit masks, when set, the Interrupt bit: M…
89401 … (0x1<<27) // This bit masks, when set, the Interrupt bit: M…
89403 … (0x1<<28) // This bit masks, when set, the Interrupt bit: M…
89405 … (0x1<<29) // This bit masks, when set, the Interrupt bit: M…
89407 … (0x1<<30) // This bit masks, when set, the Interrupt bit: M…
89409 … (0x1<<31) // This bit masks, when set, the Interrupt bit: M…
89416 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89418 …O_ERROR (0x1<<3) // Error in any one…
89419 …SEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR_SHIFT 3
89444 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89492 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89535 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89537 …FO_ERROR (0x1<<3) // Error in any one…
89538 …SEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR_SHIFT 3
89563 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89611 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89656 …OAD_POP_ERROR_A_E5 (0x1<<3) // fast external lo…
89657 …SEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
89720 …END_WR_ERROR_BB_K2 (0x1<<3) // There was an att…
89721 …SEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
89722 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
89724 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
89726 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
89728 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89738 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
89741 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
89743 … (0x1<<1) // This bit masks, when set, the Interrupt bit: M…
89745 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
89747 … (0x1<<3) // This bit masks, when set, the Interrupt …
89748 …SEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
89749 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
89751 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
89753 … (0x1<<6) // This bit masks, when set, the Interrupt bit: M…
89755 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
89757 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
89759 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
89761 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
89763 … (0x1<<11) // This bit masks, when set, the Interrupt bit: M…
89765 … (0x1<<12) // This bit masks, when set, the Interrupt bit: M…
89767 … (0x1<<13) // This bit masks, when set, the Interrupt bit: M…
89769 … (0x1<<14) // This bit masks, when set, the Interrupt bit: M…
89771 … (0x1<<15) // This bit masks, when set, the Interrupt bit: M…
89773 … (0x1<<16) // This bit masks, when set, the Interrupt bit: M…
89775 … (0x1<<17) // This bit masks, when set, the Interrupt bit: M…
89777 … (0x1<<18) // This bit masks, when set, the Interrupt bit: M…
89779 … (0x1<<19) // This bit masks, when set, the Interrupt bit: M…
89781 … (0x1<<20) // This bit masks, when set, the Interrupt bit: M…
89783 … (0x1<<21) // This bit masks, when set, the Interrupt bit: M…
89785 … (0x1<<22) // This bit masks, when set, the Interrupt bit: M…
89787 … (0x1<<23) // This bit masks, when set, the Interrupt bit: M…
89789 … (0x1<<24) // This bit masks, when set, the Interrupt bit: M…
89791 … (0x1<<25) // This bit masks, when set, the Interrupt bit: M…
89793 … (0x1<<26) // This bit masks, when set, the Interrupt bit: M…
89795 … (0x1<<27) // This bit masks, when set, the Interrupt bit: M…
89797 … (0x1<<28) // This bit masks, when set, the Interrupt bit: M…
89799 … (0x1<<29) // This bit masks, when set, the Interrupt bit: M…
89801 … (0x1<<30) // This bit masks, when set, the Interrupt bit: M…
89803 … (0x1<<31) // This bit masks, when set, the Interrupt bit: M…
89805 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
89807 … (0x1<<1) // This bit masks, when set, the Interrupt bit: M…
89809 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
89811 … (0x1<<3) // This bit masks, when set, the Interrupt …
89812 …SEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
89813 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
89815 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
89817 … (0x1<<6) // This bit masks, when set, the Interrupt bit: M…
89819 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
89821 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
89823 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
89825 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
89827 … (0x1<<11) // This bit masks, when set, the Interrupt bit: M…
89829 … (0x1<<12) // This bit masks, when set, the Interrupt bit: M…
89838 …T_LOAD_POP_ERROR_A_E5 (0x1<<3) // fast external lo…
89839 …SEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
89902 …D_PEND_WR_ERROR_BB_K2 (0x1<<3) // There was an att…
89903 …SEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
89904 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
89906 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
89908 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
89910 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89920 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
89929 …XT_LOAD_POP_ERROR_A_E5 (0x1<<3) // fast external lo…
89930 …SEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
89993 …AD_PEND_WR_ERROR_BB_K2 (0x1<<3) // There was an att…
89994 …SEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
89995 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
89997 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
89999 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
90001 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90011 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
90020 …AST_DBG_PUSH_ERROR_B_E5 (0x1<<3) // Fast Debug FIFO …
90021 …SEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
90040 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90042 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90077 … (0x1<<0) // This bit masks, when set, the Interrupt bit: M…
90079 … (0x1<<1) // This bit masks, when set, the Interrupt bit: M…
90081 … (0x1<<2) // This bit masks, when set, the Interrupt bit: M…
90083 … (0x1<<3) // This bit masks, when set, the Interrupt …
90084 …SEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
90085 … (0x1<<4) // This bit masks, when set, the Interrupt bit: M…
90087 … (0x1<<5) // This bit masks, when set, the Interrupt bit: M…
90089 … (0x1<<6) // This bit masks, when set, the Interrupt bit: M…
90091 … (0x1<<7) // This bit masks, when set, the Interrupt bit: M…
90093 … (0x1<<8) // This bit masks, when set, the Interrupt bit: M…
90095 … (0x1<<9) // This bit masks, when set, the Interrupt bit: M…
90097 … (0x1<<10) // This bit masks, when set, the Interrupt bit: M…
90099 … (0x1<<11) // This bit masks, when set, the Interrupt bit: M…
90101 … (0x1<<12) // This bit masks, when set, the Interrupt bit: M…
90103 … (0x1<<13) // This bit masks, when set, the Interrupt bit: M…
90105 … (0x1<<14) // This bit masks, when set, the Interrupt bit: M…
90107 … (0x1<<15) // This bit masks, when set, the Interrupt bit: M…
90109 … (0x1<<16) // This bit masks, when set, the Interrupt bit: M…
90111 … (0x1<<17) // This bit masks, when set, the Interrupt bit: M…
90113 … (0x1<<18) // This bit masks, when set, the Interrupt bit: M…
90115 … (0x1<<19) // This bit masks, when set, the Interrupt bit: M…
90117 … (0x1<<20) // This bit masks, when set, the Interrupt bit: M…
90119 … (0x1<<21) // This bit masks, when set, the Interrupt bit: M…
90121 … (0x1<<22) // This bit masks, when set, the Interrupt bit: M…
90123 … (0x1<<23) // This bit masks, when set, the Interrupt bit: M…
90125 … (0x1<<24) // This bit masks, when set, the Interrupt bit: M…
90127 … (0x1<<25) // This bit masks, when set, the Interrupt bit: M…
90129 …E5 (0x1<<26) // This bit masks, when set, the Interrupt bit: M…
90131 …E5 (0x1<<27) // This bit masks, when set, the Interrupt bit: M…
90133 … (0x1<<28) // This bit masks, when set, the Interrupt bit: M…
90135 … (0x1<<29) // This bit masks, when set, the Interrupt bit: M…
90137 … (0x1<<30) // This bit masks, when set, the Interrupt bit: M…
90146 …C_FAST_DBG_PUSH_ERROR_B_E5 (0x1<<3) // Fast Debug FIFO …
90147 …SEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
90166 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90168 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90209 …BC_FAST_DBG_PUSH_ERROR_B_E5 (0x1<<3) // Fast Debug FIFO …
90210 …SEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
90229 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90231 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90266 … (0x1<<0) // This bit masks, when set, the Parity bit: MS…
90268 … (0x1<<1) // This bit masks, when set, the Parity bit: MS…
90270 … (0x1<<2) // This bit masks, when set, the Parity bit: MS…
90272 … (0x1<<2) // This bit masks, when set, the Parity bit: MS…
90274 … (0x1<<3) // This bit masks, when set, the Parity bi…
90275 …SEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR_E5_SHIFT 3
90276 … (0x1<<4) // This bit masks, when set, the Parity bit: MS…
90278 … (0x1<<1) // This bit masks, when set, the Parity bit: MS…
90281 … (0x1<<0) // This bit masks, when set, the Parity bit: MS…
90283 … (0x1<<1) // This bit masks, when set, the Parity bit: MS…
90285 … (0x1<<2) // This bit masks, when set, the Parity bit: MS…
90287 … (0x1<<3) // This bit masks, when set, the Parity bi…
90288 …SEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_3_RF_INT_E5_SHIFT 3
90289 … (0x1<<4) // This bit masks, when set, the Parity bit: MS…
90291 … (0x1<<5) // This bit masks, when set, the Parity bit: MS…
90293 … (0x1<<6) // This bit masks, when set, the Parity bit: MS…
90295 … (0x1<<7) // This bit masks, when set, the Parity bit: MS…
90297 … (0x1<<5) // This bit masks, when set, the Parity bit: MS…
90299 … (0x1<<8) // This bit masks, when set, the Parity bit: MS…
90301 … (0x1<<2) // This bit masks, when set, the Parity bit: MS…
90303 … (0x1<<9) // This bit masks, when set, the Parity bit: MS…
90305 … (0x1<<10) // This bit masks, when set, the Parity bit: MS…
90307 … (0x1<<4) // This bit masks, when set, the Parity bit: MS…
90309 … (0x1<<11) // This bit masks, when set, the Parity bit: MS…
90311 … (0x1<<12) // This bit masks, when set, the Parity bit: MS…
90313 … (0x1<<3) // This bit masks, when set, the Parity bi…
90314 …SEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT 3
90315 … (0x1<<13) // This bit masks, when set, the Parity bit: MS…
90317 … (0x1<<14) // This bit masks, when set, the Parity bit: MS…
90319 … (0x1<<15) // This bit masks, when set, the Parity bit: MS…
90328 …005_I_ECC_3_EN_E5 (0x1<<3) // Enable ECC for m…
90329 …SEM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_3_EN_E5_SHIFT 3
90345 …0_MEM005_I_ECC_3_PRTY_E5 (0x1<<3) // Set parity only …
90346 …SEM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_3_PRTY_E5_SHIFT 3
90362 …TED_0_MEM005_I_ECC_3_CORRECT_E5 (0x1<<3) // Record if a corr…
90363 …SEM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_3_CORRECT_E5_SHIFT 3
90374 … 0x1800408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
90375 … 0x180040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
90376 …_R DataWidth:0xf0 // This read-only register provides a vector of bits having an error indicatio…
90379 … DataWidth:0x10 // This read-only register provides a vector of bits having an error indicatio…
90386 … 0x1800458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mod…
90387 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
90388 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
90389 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
90393 … 0x1800600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
90394 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
90395 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
90398 … 0x18006c0UL //Access:RW DataWidth:0x1 // When set, this bit allows the DRA read…
90401 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
90403 …abled even if the partition being written is owned by a thread whose valid bit is not set. Otherwi…
90404 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
90405 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
90407 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
90409 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
90412 …0x1800b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
90419 …1800b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
90420 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
90422 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
90426 …UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assign…
90428 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
90430 …L //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enable vector.
90431 … //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enable vector.
90441 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
90446 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
90455 … DataWidth:0x2 // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit 0 FIFO of Core A, bit 1 FIFO o…
90458 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
90461 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
90464 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
90465 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
90476 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
90477 … DataWidth:0x2 // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit 0 for Core A and bit 1 for Cor…
90481 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
90492 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
90494 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
90499 …ckets. Setting a bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0…
90515 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
90521 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
90522 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
90523 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
90524 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
90525 … 0x1808000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the ex…
90531 …3 - state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. …
90536 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
90537 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
90551 … (0x1<<2) // FIC input enable bit used to enable/disa…
90553 … (0x1<<3) // FOC acknowledge input enable bit us…
90554 …SEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_BB_K2_SHIFT 3
90572 … (0x1<<2) // FOC output otuput enable bit used to enable/disa…
90574 …NABLE_OUT_BB_K2 (0x1<<3) // Passive full out…
90575 …SEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_BB_K2_SHIFT 3
90578 … (0x1<<5) // Stall output enable bit used to enable/disa…
90591 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
90602 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
90605 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
90607 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
90609 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
90611 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
90613 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
90616 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
90618 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
90620 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
90622 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
90625 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
90627 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
90629 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
90631 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
90654 …R_PB_AFFINITY_CORE_A_ONLY_E5 (0x1<<3) // When set, the Af…
90655 …SEM_REG_PASSIVE_BUFFER_DRA_WR_PB_AFFINITY_CORE_A_ONLY_E5_SHIFT 3
90661 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
90663 …RROR (0x1<<3) // Error in any one…
90664 …SEM_REG_INT_STS_0_FIC_FIFO_ERROR_SHIFT 3
90689 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90737 … (0x1<<11) // Signals an unknown address in the fast-memory window.
90776 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
90778 … (0x1<<1) // This bit masks, when set, the Interrupt bit: U…
90780 … (0x1<<2) // This bit masks, when set, the Interrupt bit: U…
90782 … (0x1<<3) // This bit masks, when set, the Interrupt …
90783 …SEM_REG_INT_MASK_0_FIC_FIFO_ERROR_SHIFT 3
90784 … (0x1<<4) // This bit masks, when set, the Interrupt bit: U…
90786 … (0x1<<5) // This bit masks, when set, the Interrupt bit: U…
90788 … (0x1<<6) // This bit masks, when set, the Interrupt bit: U…
90790 … (0x1<<7) // This bit masks, when set, the Interrupt bit: U…
90792 … (0x1<<8) // This bit masks, when set, the Interrupt bit: U…
90794 … (0x1<<9) // This bit masks, when set, the Interrupt bit: U…
90796 … (0x1<<23) // This bit masks, when set, the Interrupt bit: U…
90798 … (0x1<<10) // This bit masks, when set, the Interrupt bit: U…
90800 … (0x1<<25) // This bit masks, when set, the Interrupt bit: U…
90802 … (0x1<<11) // This bit masks, when set, the Interrupt bit: U…
90804 … (0x1<<12) // This bit masks, when set, the Interrupt bit: U…
90806 … (0x1<<13) // This bit masks, when set, the Interrupt bit: U…
90808 … (0x1<<14) // This bit masks, when set, the Interrupt bit: U…
90810 … (0x1<<15) // This bit masks, when set, the Interrupt bit: U…
90812 … (0x1<<16) // This bit masks, when set, the Interrupt bit: U…
90814 … (0x1<<17) // This bit masks, when set, the Interrupt bit: U…
90816 … (0x1<<18) // This bit masks, when set, the Interrupt bit: U…
90818 … (0x1<<19) // This bit masks, when set, the Interrupt bit: U…
90820 … (0x1<<20) // This bit masks, when set, the Interrupt bit: U…
90822 … (0x1<<21) // This bit masks, when set, the Interrupt bit: U…
90824 … (0x1<<22) // This bit masks, when set, the Interrupt bit: U…
90826 … (0x1<<23) // This bit masks, when set, the Interrupt bit: U…
90828 … (0x1<<24) // This bit masks, when set, the Interrupt bit: U…
90830 … (0x1<<25) // This bit masks, when set, the Interrupt bit: U…
90832 … (0x1<<26) // This bit masks, when set, the Interrupt bit: U…
90834 … (0x1<<27) // This bit masks, when set, the Interrupt bit: U…
90836 … (0x1<<28) // This bit masks, when set, the Interrupt bit: U…
90838 … (0x1<<29) // This bit masks, when set, the Interrupt bit: U…
90840 … (0x1<<30) // This bit masks, when set, the Interrupt bit: U…
90842 … (0x1<<4) // This bit masks, when set, the Interrupt bit: U…
90844 … (0x1<<5) // This bit masks, when set, the Interrupt bit: U…
90846 … (0x1<<6) // This bit masks, when set, the Interrupt bit: U…
90848 … (0x1<<7) // This bit masks, when set, the Interrupt bit: U…
90850 … (0x1<<8) // This bit masks, when set, the Interrupt bit: U…
90852 … (0x1<<9) // This bit masks, when set, the Interrupt bit: U…
90854 … (0x1<<10) // This bit masks, when set, the Interrupt bit: U…
90856 … (0x1<<11) // This bit masks, when set, the Interrupt bit: U…
90858 … (0x1<<12) // This bit masks, when set, the Interrupt bit: U…
90860 … (0x1<<13) // This bit masks, when set, the Interrupt bit: U…
90862 … (0x1<<14) // This bit masks, when set, the Interrupt bit: U…
90864 … (0x1<<15) // This bit masks, when set, the Interrupt bit: U…
90866 … (0x1<<16) // This bit masks, when set, the Interrupt bit: U…
90868 … (0x1<<17) // This bit masks, when set, the Interrupt bit: U…
90870 … (0x1<<18) // This bit masks, when set, the Interrupt bit: U…
90872 … (0x1<<19) // This bit masks, when set, the Interrupt bit: U…
90874 … (0x1<<20) // This bit masks, when set, the Interrupt bit: U…
90876 … (0x1<<21) // This bit masks, when set, the Interrupt bit: U…
90878 … (0x1<<22) // This bit masks, when set, the Interrupt bit: U…
90880 … (0x1<<24) // This bit masks, when set, the Interrupt bit: U…
90882 … (0x1<<26) // This bit masks, when set, the Interrupt bit: U…
90884 … (0x1<<27) // This bit masks, when set, the Interrupt bit: U…
90886 … (0x1<<28) // This bit masks, when set, the Interrupt bit: U…
90888 … (0x1<<29) // This bit masks, when set, the Interrupt bit: U…
90890 … (0x1<<30) // This bit masks, when set, the Interrupt bit: U…
90892 … (0x1<<31) // This bit masks, when set, the Interrupt bit: U…
90899 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
90901 …O_ERROR (0x1<<3) // Error in any one…
90902 …SEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR_SHIFT 3
90927 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90975 … (0x1<<11) // Signals an unknown address in the fast-memory window.
91018 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
91020 …FO_ERROR (0x1<<3) // Error in any one…
91021 …SEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR_SHIFT 3
91046 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91094 … (0x1<<11) // Signals an unknown address in the fast-memory window.
91139 …OAD_POP_ERROR_A_E5 (0x1<<3) // fast external lo…
91140 …SEM_REG_INT_STS_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
91203 …END_WR_ERROR_BB_K2 (0x1<<3) // There was an att…
91204 …SEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
91205 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
91207 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
91209 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
91211 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91221 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
91224 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
91226 … (0x1<<1) // This bit masks, when set, the Interrupt bit: U…
91228 … (0x1<<2) // This bit masks, when set, the Interrupt bit: U…
91230 … (0x1<<3) // This bit masks, when set, the Interrupt …
91231 …SEM_REG_INT_MASK_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
91232 … (0x1<<4) // This bit masks, when set, the Interrupt bit: U…
91234 … (0x1<<5) // This bit masks, when set, the Interrupt bit: U…
91236 … (0x1<<6) // This bit masks, when set, the Interrupt bit: U…
91238 … (0x1<<7) // This bit masks, when set, the Interrupt bit: U…
91240 … (0x1<<8) // This bit masks, when set, the Interrupt bit: U…
91242 … (0x1<<9) // This bit masks, when set, the Interrupt bit: U…
91244 … (0x1<<10) // This bit masks, when set, the Interrupt bit: U…
91246 … (0x1<<11) // This bit masks, when set, the Interrupt bit: U…
91248 … (0x1<<12) // This bit masks, when set, the Interrupt bit: U…
91250 … (0x1<<13) // This bit masks, when set, the Interrupt bit: U…
91252 … (0x1<<14) // This bit masks, when set, the Interrupt bit: U…
91254 … (0x1<<15) // This bit masks, when set, the Interrupt bit: U…
91256 … (0x1<<16) // This bit masks, when set, the Interrupt bit: U…
91258 … (0x1<<17) // This bit masks, when set, the Interrupt bit: U…
91260 … (0x1<<18) // This bit masks, when set, the Interrupt bit: U…
91262 … (0x1<<19) // This bit masks, when set, the Interrupt bit: U…
91264 … (0x1<<20) // This bit masks, when set, the Interrupt bit: U…
91266 … (0x1<<21) // This bit masks, when set, the Interrupt bit: U…
91268 … (0x1<<22) // This bit masks, when set, the Interrupt bit: U…
91270 … (0x1<<23) // This bit masks, when set, the Interrupt bit: U…
91272 … (0x1<<24) // This bit masks, when set, the Interrupt bit: U…
91274 … (0x1<<25) // This bit masks, when set, the Interrupt bit: U…
91276 … (0x1<<26) // This bit masks, when set, the Interrupt bit: U…
91278 … (0x1<<27) // This bit masks, when set, the Interrupt bit: U…
91280 … (0x1<<28) // This bit masks, when set, the Interrupt bit: U…
91282 … (0x1<<29) // This bit masks, when set, the Interrupt bit: U…
91284 … (0x1<<30) // This bit masks, when set, the Interrupt bit: U…
91286 … (0x1<<31) // This bit masks, when set, the Interrupt bit: U…
91288 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
91290 … (0x1<<1) // This bit masks, when set, the Interrupt bit: U…
91292 … (0x1<<2) // This bit masks, when set, the Interrupt bit: U…
91294 … (0x1<<3) // This bit masks, when set, the Interrupt …
91295 …SEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
91296 … (0x1<<4) // This bit masks, when set, the Interrupt bit: U…
91298 … (0x1<<5) // This bit masks, when set, the Interrupt bit: U…
91300 … (0x1<<6) // This bit masks, when set, the Interrupt bit: U…
91302 … (0x1<<7) // This bit masks, when set, the Interrupt bit: U…
91304 … (0x1<<8) // This bit masks, when set, the Interrupt bit: U…
91306 … (0x1<<9) // This bit masks, when set, the Interrupt bit: U…
91308 … (0x1<<10) // This bit masks, when set, the Interrupt bit: U…
91310 … (0x1<<11) // This bit masks, when set, the Interrupt bit: U…
91312 … (0x1<<12) // This bit masks, when set, the Interrupt bit: U…
91321 …T_LOAD_POP_ERROR_A_E5 (0x1<<3) // fast external lo…
91322 …SEM_REG_INT_STS_WR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
91385 …D_PEND_WR_ERROR_BB_K2 (0x1<<3) // There was an att…
91386 …SEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
91387 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
91389 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
91391 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
91393 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91403 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
91412 …XT_LOAD_POP_ERROR_A_E5 (0x1<<3) // fast external lo…
91413 …SEM_REG_INT_STS_CLR_1_FAST_EXT_LOAD_POP_ERROR_A_E5_SHIFT 3
91476 …AD_PEND_WR_ERROR_BB_K2 (0x1<<3) // There was an att…
91477 …SEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_BB_K2_SHIFT 3
91478 …as a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to rel…
91480 … (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
91482 …(0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
91484 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91494 …-running thread onto a thread- order queue when it was not at the head of the queue or firmware at…
91503 …AST_DBG_PUSH_ERROR_B_E5 (0x1<<3) // Fast Debug FIFO …
91504 …SEM_REG_INT_STS_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
91523 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91525 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91560 … (0x1<<0) // This bit masks, when set, the Interrupt bit: U…
91562 … (0x1<<1) // This bit masks, when set, the Interrupt bit: U…
91564 … (0x1<<2) // This bit masks, when set, the Interrupt bit: U…
91566 … (0x1<<3) // This bit masks, when set, the Interrupt …
91567 …SEM_REG_INT_MASK_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
91568 … (0x1<<4) // This bit masks, when set, the Interrupt bit: U…
91570 … (0x1<<5) // This bit masks, when set, the Interrupt bit: U…
91572 … (0x1<<6) // This bit masks, when set, the Interrupt bit: U…
91574 … (0x1<<7) // This bit masks, when set, the Interrupt bit: U…
91576 … (0x1<<8) // This bit masks, when set, the Interrupt bit: U…
91578 … (0x1<<9) // This bit masks, when set, the Interrupt bit: U…
91580 … (0x1<<10) // This bit masks, when set, the Interrupt bit: U…
91582 … (0x1<<11) // This bit masks, when set, the Interrupt bit: U…
91584 … (0x1<<12) // This bit masks, when set, the Interrupt bit: U…
91586 … (0x1<<13) // This bit masks, when set, the Interrupt bit: U…
91588 … (0x1<<14) // This bit masks, when set, the Interrupt bit: U…
91590 … (0x1<<15) // This bit masks, when set, the Interrupt bit: U…
91592 … (0x1<<16) // This bit masks, when set, the Interrupt bit: U…
91594 … (0x1<<17) // This bit masks, when set, the Interrupt bit: U…
91596 … (0x1<<18) // This bit masks, when set, the Interrupt bit: U…
91598 … (0x1<<19) // This bit masks, when set, the Interrupt bit: U…
91600 … (0x1<<20) // This bit masks, when set, the Interrupt bit: U…
91602 … (0x1<<21) // This bit masks, when set, the Interrupt bit: U…
91604 … (0x1<<22) // This bit masks, when set, the Interrupt bit: U…
91606 … (0x1<<23) // This bit masks, when set, the Interrupt bit: U…
91608 … (0x1<<24) // This bit masks, when set, the Interrupt bit: U…
91610 … (0x1<<25) // This bit masks, when set, the Interrupt bit: U…
91612 …E5 (0x1<<26) // This bit masks, when set, the Interrupt bit: U…
91614 …E5 (0x1<<27) // This bit masks, when set, the Interrupt bit: U…
91616 … (0x1<<28) // This bit masks, when set, the Interrupt bit: U…
91618 … (0x1<<29) // This bit masks, when set, the Interrupt bit: U…
91620 … (0x1<<30) // This bit masks, when set, the Interrupt bit: U…
91629 …C_FAST_DBG_PUSH_ERROR_B_E5 (0x1<<3) // Fast Debug FIFO …
91630 …SEM_REG_INT_STS_WR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
91649 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91651 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91692 …BC_FAST_DBG_PUSH_ERROR_B_E5 (0x1<<3) // Fast Debug FIFO …
91693 …SEM_REG_INT_STS_CLR_2_SYNC_RBC_FAST_DBG_PUSH_ERROR_B_E5_SHIFT 3
91712 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91714 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91749 … (0x1<<0) // This bit masks, when set, the Parity bit: US…
91751 … (0x1<<1) // This bit masks, when set, the Parity bit: US…
91753 … (0x1<<2) // This bit masks, when set, the Parity bit: US…
91755 … (0x1<<2) // This bit masks, when set, the Parity bit: US…
91757 … (0x1<<3) // This bit masks, when set, the Parity bi…
91758 …SEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR_E5_SHIFT 3
91759 … (0x1<<4) // This bit masks, when set, the Parity bit: US…
91761 … (0x1<<1) // This bit masks, when set, the Parity bit: US…
91764 … (0x1<<0) // This bit masks, when set, the Parity bit: US…
91766 … (0x1<<1) // This bit masks, when set, the Parity bit: US…
91768 … (0x1<<2) // This bit masks, when set, the Parity bit: US…
91770 … (0x1<<3) // This bit masks, when set, the Parity bi…
91771 …SEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT 3
91772 … (0x1<<4) // This bit masks, when set, the Parity bit: US…
91774 … (0x1<<5) // This bit masks, when set, the Parity bit: US…
91793 … 0x1900408UL //Access:WR DataWidth:0x1 // This VF-split register provid…
91794 … 0x190040cUL //Access:WR DataWidth:0x1 // This PF-split register provid…
91795 …_R DataWidth:0xf0 // This read-only register provides a vector of bits having an error indicatio…
91798 … DataWidth:0x10 // This read-only register provides a vector of bits having an error indicatio…
91805 … 0x1900458UL //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mod…
91806 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
91807 … write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode. 10 - Use r…
91808 …sly with read (as long that no coherency violations occur). 0- cut through mode disabled. 1- cut t…
91812 … 0x1900600UL //Access:RW DataWidth:0x6 // Per-FIC interface registe…
91813 …e "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require…
91814 … FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.
91817 … 0x19006c0UL //Access:RW DataWidth:0x1 // When set, this bit allows the DRA read…
91820 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
91822 …abled even if the partition being written is owned by a thread whose valid bit is not set. Otherwi…
91823 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
91824 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
91826 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
91828 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
91831 …0x1900b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
91838 …1900b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
91839 …r to start. The values define in this register represents the number of Quad-IOR that the maximum …
91841 …ers provides read/write access to the head pointers assigned to each of the thread-ordering queues.
91845 …UL //Access:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assign…
91847 …-list array of the thread-ordering queue. Because the actual depth is based on the number of threa…
91849 …L //Access:RW DataWidth:0x10 // Provides access to the thread ordering queue pop-enable vector.
91850 … //Access:RW DataWidth:0x10 // Provides access to the thread ordering queue wake-enable vector.
91860 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
91865 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
91874 … DataWidth:0x2 // EXT_LOAD FIFO is empty in sem_slow_ls_ext, bit 0 FIFO of Core A, bit 1 FIFO o…
91877 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
91880 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
91883 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
91884 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
91895 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
91896 … DataWidth:0x2 // EXT_LOAD FIFO is full in sem_slow_ls_ext, bit 0 for Core A and bit 1 for Cor…
91900 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
91911 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
91913 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
91918 …ckets. Setting a bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0…
91934 …) of threads that are waiting for ready indication to be run on Storm. Note -this statistic does n…
91940 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
91941 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
91942 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
91943 … DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line…
91944 … 0x1908000UL //Access:WB_R DataWidth:0x4c // Provides read-only access of the ex…
91950 …3 - state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. …
91955 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
91956 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…