Lines Matching +full:3 +full:- +full:bit

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
12 #define DATA_RATE_NOT_HT_IDX_MASK	GENMASK(3, 0)
18 #define DATA_RATE_VHT_HE_IDX_MASK	GENMASK(3, 0)
27 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
40 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
48 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
56 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
65 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
66 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
67 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
70 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7)
71 #define RTW89_TXWD_BODY0_HW_AMSDU BIT(5)
72 #define RTW89_TXWD_BODY0_HW_SSN_SEL GENMASK(3, 2)
79 #define RTW89_TXWD_BODY1_SEC_TYPE GENMASK(3, 0)
83 #define RTW89_TXWD_BODY2_TID_INDICATE BIT(23)
87 /* TX WD BODY DWORD 3 */
88 #define RTW89_TXWD_BODY3_BK BIT(13)
89 #define RTW89_TXWD_BODY3_AGG_EN BIT(12)
105 #define RTW89_TXWD_BODY7_USE_RATE_V1 BIT(31)
111 #define RTW89_TXWD_INFO0_USE_RATE BIT(30)
115 #define RTW89_TXWD_INFO0_DATA_ER BIT(15)
116 #define RTW89_TXWD_INFO0_DATA_STBC BIT(12)
117 #define RTW89_TXWD_INFO0_DATA_LDPC BIT(11)
118 #define RTW89_TXWD_INFO0_DISDATAFB BIT(10)
119 #define RTW89_TXWD_INFO0_DATA_BW_ER BIT(8)
124 #define RTW89_TXWD_INFO1_A_CTRL_BSR BIT(14)
130 #define RTW89_TXWD_INFO2_SEC_HW_ENC BIT(8)
131 #define RTW89_TXWD_INFO2_FORCE_KEY_EN BIT(8)
134 /* TX WD INFO DWORD 3 */
137 #define RTW89_TXWD_INFO4_RTS_EN BIT(27)
138 #define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31)
145 #define BE_TXD_BODY0_HWAMSDU BIT(5)
146 #define BE_TXD_BODY0_HW_SEC_IV BIT(6)
147 #define BE_TXD_BODY0_WD_PAGE BIT(7)
148 #define BE_TXD_BODY0_CHK_EN BIT(8)
149 #define BE_TXD_BODY0_WP_INT BIT(9)
150 #define BE_TXD_BODY0_STF_MODE BIT(10)
153 #define BE_TXD_BODY0_SMH_EN BIT(20)
154 #define BE_TXD_BODY0_PKT_OFFSET BIT(21)
155 #define BE_TXD_BODY0_WDINFO_EN BIT(22)
156 #define BE_TXD_BODY0_MOREDATA BIT(23)
158 #define BE_TXD_BODY0_AZ_FTM_SEC_V1 BIT(28)
160 #define BE_TXD_BODY0_HCI_SEQNUM_MODE BIT(31)
167 #define BE_TXD_BODY1_SW_SEC_IV BIT(18)
174 #define BE_TXD_BODY2_AGG_EN BIT(14)
175 #define BE_TXD_BODY2_BK BIT(15)
176 #define BE_TXD_BODY2_MACID_EXTEND BIT(16)
178 #define BE_TXD_BODY2_TID_IND BIT(23)
181 /* TX WD BODY DWORD 3 */
183 #define BE_TXD_BODY3_MLO_FLAG BIT(12)
184 #define BE_TXD_BODY3_IS_MLD_SW_EN BIT(13)
185 #define BE_TXD_BODY3_TRY_RATE BIT(14)
186 #define BE_TXD_BODY3_RELINK_FLAG_V1 BIT(15)
189 #define BE_TXD_BODY3_RU_RTY BIT(28)
190 #define BE_TXD_BODY3_MU_PRI_RTY BIT(29)
191 #define BE_TXD_BODY3_MU_2ND_RTY BIT(30)
192 #define BE_TXD_BODY3_BAND1_SU_RTY_V1 BIT(31)
208 #define BE_TXD_BODY6_PS160 BIT(10)
209 #define BE_TXD_BODY6_BMC BIT(11)
210 #define BE_TXD_BODY6_NO_ACK BIT(12)
211 #define BE_TXD_BODY6_UPD_WLAN_HDR BIT(13)
212 #define BE_TXD_BODY6_A4_HDR BIT(14)
213 #define BE_TXD_BODY6_EOSP_BIT BIT(15)
220 #define BE_TXD_BODY7_DATA_ER BIT(10)
221 #define BE_TXD_BODY7_DATA_BW_ER BIT(11)
222 #define BE_TXD_BODY7_DATA_DCM BIT(12)
226 #define BE_TXD_BODY7_USERATE_SEL BIT(31)
229 #define BE_TXD_INFO0_MBSSID GENMASK(3, 0)
231 #define BE_TXD_INFO0_DISRTSFB BIT(9)
232 #define BE_TXD_INFO0_DISDATAFB BIT(10)
233 #define BE_TXD_INFO0_DATA_LDPC BIT(11)
234 #define BE_TXD_INFO0_DATA_STBC BIT(12)
236 #define BE_TXD_INFO0_DATA_TXCNT_LMT_SEL BIT(22)
237 #define BE_TXD_INFO0_RESP_PHYSTS_CSI_EN_V1 BIT(23)
238 #define BE_TXD_INFO0_RLS_TO_CPUIO BIT(30)
239 #define BE_TXD_INFO0_ACK_CH_INFO BIT(31)
244 #define BE_TXD_INFO1_NAVUSEHDR BIT(10)
245 #define BE_TXD_INFO1_A_CTRL_BQR BIT(12)
246 #define BE_TXD_INFO1_A_CTRL_BSR BIT(14)
247 #define BE_TXD_INFO1_A_CTRL_CAS BIT(15)
253 #define BE_TXD_INFO2_FORCE_KEY_EN BIT(8)
255 #define BE_TXD_INFO2_FORCE_TXOP BIT(17)
257 #define BE_TXD_INFO2_LSIG_TXOP_EN BIT(21)
259 #define BE_TXD_INFO2_SPE_RPT_V1 BIT(30)
260 #define BE_TXD_INFO2_SIFS_TX_V1 BIT(31)
262 /* TX WD INFO DWORD 3 */
263 #define BE_TXD_INFO3_SPE_PKT GENMASK(3, 0)
265 #define BE_TXD_INFO3_CQI_SND BIT(8)
266 #define BE_TXD_INFO3_RTT_EN BIT(9)
267 #define BE_TXD_INFO3_HT_DATA_SND_V1 BIT(10)
268 #define BE_TXD_INFO3_BT_NULL BIT(11)
269 #define BE_TXD_INFO3_TRI_FRAME BIT(12)
270 #define BE_TXD_INFO3_NULL_0 BIT(13)
271 #define BE_TXD_INFO3_NULL_1 BIT(14)
272 #define BE_TXD_INFO3_RAW BIT(15)
274 #define BE_TXD_INFO3_SIGNALING_TA_PKT_EN BIT(25)
275 #define BE_TXD_INFO3_BCNPKT_TSF_CTRL BIT(26)
277 #define BE_TXD_INFO3_FORCE_BSS_CLR BIT(31)
282 #define BE_TXD_INFO4_SW_TX_OK_0 BIT(18)
283 #define BE_TXD_INFO4_SW_TX_OK_1 BIT(19)
285 #define BE_TXD_INFO4_RTS_EN BIT(27)
286 #define BE_TXD_INFO4_CTS2SELF BIT(28)
288 #define BE_TXD_INFO4_HW_RTS_EN BIT(31)
292 #define BE_TXD_INFO5_SR_EN_V1 BIT(5)
298 #define BE_TXD_INFO6_UL_DOPPLER BIT(15)
299 #define BE_TXD_INFO6_UL_STBC BIT(16)
304 #define BE_TXD_INFO7_UL_FIXED_GAIN_EN BIT(0)
306 #define BE_TXD_INFO7_ELNA_IDX BIT(8)
310 #define BE_TXD_INFO7_UL_EHT_USR_PRES BIT(16)
321 #define AX_RXD_BB_SEL BIT(22)
322 #define AX_RXD_MAC_INFO_VLD BIT(23)
325 #define AX_RXD_LONG_RXD BIT(31)
328 #define AX_RXD_PPDU_TYPE_MASK GENMASK(3, 0)
330 #define AX_RXD_SR_EN BIT(7)
335 #define AX_RXD_NON_SRG_PPDU BIT(28)
336 #define AX_RXD_INTER_PPDU BIT(29)
337 #define AX_RXD_NON_SRG_PPDU_v1 BIT(14)
338 #define AX_RXD_INTER_PPDU_v1 BIT(15)
346 #define AX_RXD_A1_MATCH BIT(0)
347 #define AX_RXD_SW_DEC BIT(1)
348 #define AX_RXD_HW_DEC BIT(2)
349 #define AX_RXD_AMPDU BIT(3)
350 #define AX_RXD_AMPDU_END_PKT BIT(4)
351 #define AX_RXD_AMSDU BIT(5)
352 #define AX_RXD_AMSDU_CUT BIT(6)
353 #define AX_RXD_LAST_MSDU BIT(7)
354 #define AX_RXD_BYPASS BIT(8)
355 #define AX_RXD_CRC32_ERR BIT(9)
356 #define AX_RXD_ICV_ERR BIT(10)
357 #define AX_RXD_MAGIC_WAKE BIT(11)
358 #define AX_RXD_UNICAST_WAKE BIT(12)
359 #define AX_RXD_PATTERN_WAKE BIT(13)
363 #define AX_RXD_CHKSUM_OFFLOAD_EN BIT(24)
364 #define AX_RXD_WITH_LLC BIT(25)
365 #define AX_RXD_RX_STATISTICS BIT(26)
369 #define AX_RXD_MC BIT(2)
370 #define AX_RXD_BC BIT(3)
371 #define AX_RXD_MD BIT(4)
372 #define AX_RXD_MF BIT(5)
373 #define AX_RXD_PWR BIT(6)
374 #define AX_RXD_QOS BIT(7)
376 #define AX_RXD_EOSP BIT(12)
377 #define AX_RXD_HTC BIT(13)
378 #define AX_RXD_QNULL BIT(14)
387 #define AX_RXD_ADDR_CAM_VLD BIT(28)
388 #define AX_RXD_ADDR_FWD_EN BIT(29)
389 #define AX_RXD_RX_PL_MATCH BIT(30)
396 #define AX_RXD_SMART_ANT BIT(16)
398 #define AX_RXD_HDR_CNV BIT(21)
400 #define AX_RXD_BIP_KEYID BIT(27)
401 #define AX_RXD_BIP_ENC BIT(28)
407 #define RTW89_RXINFO_USER_MAC_ID_VALID BIT(0)
408 #define RTW89_RXINFO_USER_DATA BIT(1)
409 #define RTW89_RXINFO_USER_CTRL BIT(2)
410 #define RTW89_RXINFO_USER_MGMT BIT(3)
411 #define RTW89_RXINFO_USER_BCM BIT(4)
420 #define RTW89_RXINFO_W0_USR_NUM GENMASK(3, 0)
425 #define RTW89_RXINFO_W0_INVALID_V1 BIT(27)
426 #define RTW89_RXINFO_W0_IS_TO_SELF BIT(28)
427 #define RTW89_RXINFO_W0_RX_CNT_VLD BIT(29)
438 #define RTW89_PHY_STS_HDR_W0_VALID BIT(7)
460 #define BE_RXD_BB_SEL BIT(30)
461 #define BE_RXD_LONG_RXD BIT(31)
467 #define BE_RXD_FW_RLS BIT(26)
472 #define BE_RXD_LAST_MSDU BIT(12)
473 #define BE_RXD_AMSDU_CUT BIT(13)
474 #define BE_RXD_ADDR_CAM_VLD BIT(14)
475 #define BE_RXD_REORDER BIT(15)
480 #define BE_RXD_SEC_TYPE_MASK GENMASK(3, 0)
481 #define BE_RXD_BIP_KEYID BIT(4)
482 #define BE_RXD_BIP_ENC BIT(5)
483 #define BE_RXD_CRC32_ERR BIT(6)
484 #define BE_RXD_ICV_ERR BIT(7)
485 #define BE_RXD_HW_DEC BIT(8)
486 #define BE_RXD_SW_DEC BIT(9)
487 #define BE_RXD_A1_MATCH BIT(10)
488 #define BE_RXD_AMPDU BIT(11)
489 #define BE_RXD_AMPDU_EOF BIT(12)
490 #define BE_RXD_AMSDU BIT(13)
491 #define BE_RXD_MC BIT(14)
492 #define BE_RXD_BC BIT(15)
493 #define BE_RXD_MD BIT(16)
494 #define BE_RXD_MF BIT(17)
495 #define BE_RXD_PWR BIT(18)
496 #define BE_RXD_QOS BIT(19)
497 #define BE_RXD_EOSP BIT(20)
498 #define BE_RXD_HTC BIT(21)
499 #define BE_RXD_QNULL BIT(22)
500 #define BE_RXD_A4_FRAME BIT(23)
509 #define BE_RXD_RX_REORDER_FIELD_EN BIT(19)
517 #define BE_RXD_SR_EN BIT(13)
518 #define BE_RXD_NON_SRG_PPDU BIT(14)
519 #define BE_RXD_INTER_PPDU BIT(15)
521 #define BE_RXD_RX_STATISTICS BIT(22)
522 #define BE_RXD_SMART_ANT BIT(23)
527 #define BE_RXD_MAGIC_WAKE BIT(5)
528 #define BE_RXD_UNICAST_WAKE BIT(6)
529 #define BE_RXD_PATTERN_WAKE BIT(7)
530 #define BE_RXD_RX_PL_MATCH BIT(8)
532 #define BE_RXD_HDR_CNV BIT(16)
533 #define BE_RXD_NAT25_HIT BIT(17)
534 #define BE_RXD_IS_DA BIT(18)
535 #define BE_RXD_CHKSUM_OFFLOAD_EN BIT(19)
537 #define BE_RXD_RXSC_HIT BIT(23)
538 #define BE_RXD_WITH_LLC BIT(24)
539 #define BE_RXD_RX_AGG_FIELD_EN BIT(25)
561 #define RTW89_PHY_STS_IE01_W2_LDPC BIT(28)
562 #define RTW89_PHY_STS_IE01_W2_STBC BIT(30)
568 	RTW89_TXCH_ACH3	= 3,
581 	RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1
590 	RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1
635 	case 3:
677 	case 3: