Lines Matching +full:3 +full:- +full:bit
1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
81 #define DP_LINK_DESC_SHIFT 3
188 #define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; })
235 /* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */
238 /* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */
255 #define DP_INVALID_BANK_ID -1
332 * - reo_cmd_list
333 * - reo_cmd_cache_flush_list
334 * - reo_cmd_cache_flush_count
361 #define HTT_TCL_META_DATA_TYPE BIT(0)
362 #define HTT_TCL_META_DATA_VALID_HTT BIT(1)
367 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12)
376 #define HTT_TX_WBM_COMP_INFO1_REINJECT_REASON GENMASK(3, 0)
377 #define HTT_TX_WBM_COMP_INFO1_EXCEPTION_FRAME BIT(4)
427 /* host -> target HTT_SRING_SETUP message
438 * |--------------- +-----------------+----------------+------------------|
440 * |----------------------------------------------------------------------|
442 * |----------------------------------------------------------------------|
444 * |----------------------------------------------------------------------|
446 * |----------------------------------------------------------------------|
448 * |----------------------------------------------------------------------|
450 * |----------------------------------------------------------------------|
452 * |----------------------------------------------------------------------|
454 * |----------------------------------------------------------------------|
456 * |----------------------------------------------------------------------|
458 * |----------------------------------------------------------------------|
460 * |----------------------------------------------------------------------|
462 * |----------------------------------------------------------------------|
464 * |----------------------------------------------------------------------|
471 * dword0 - b'0:7 - msg_type: This will be set to
473 * b'8:15 - pdev_id:
475 * 1/2/3 mac id (for rings at LMAC level)
476 * b'16:23 - ring_id: identify which ring is to setup,
478 * b'24:31 - ring_type: identify type of host rings,
480 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address
481 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address
482 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words
483 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units
484 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and
487 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo:
489 * storing the 4-byte word offset that identifies the head
493 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi:
495 * storing the 4-byte word offset that identifies the head
499 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo:
501 * storing the 4-byte word offset that identifies the tail
505 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi:
507 * storing the 4-byte word offset that identifies the tail
511 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address
513 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address
515 * dword10 - b'0:31 - ring_msi_data: MSI data
518 * dword11 - b'0:14 - intr_batch_counter_th:
519 * batch counter threshold is in units of 4-byte words.
524 * b'15 - sw_intr_mode:
529 * b'16:31 - intr_timer_th:
533 * dword12 - b'0:15 - intr_low_threshold:
538 * b'16:18 - prefetch_timer_cfg:
543 * 3'b000: (Prefetch feature disabled; used only for debug)
544 * 3'b001: 1 usec
545 * 3'b010: 4 usec
546 * 3'b011: 8 usec (default)
547 * 3'b100: 16 usec
549 * b'19 - response_required:
551 * b'20:31 - reserved: reserved for future use
561 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25)
562 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27)
563 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28)
564 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29)
567 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15)
572 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19)
590 /* host -> target FW PPDU_STATS config message
599 * |-----------------------------------------------------------|
600 * | REQ bit mask | pdev_mask | msg type |
601 * |-----------------------------------------------------------|
603 * - MSG_TYPE
607 * - PDEV_MASK
612 * Bit 8 : Reserved for SOC stats
613 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC
615 * - REQ_TLV_BIT_MASK
617 * Purpose: each set bit indicates the corresponding PPDU stats TLV type
651 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \
652 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \
653 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \
654 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \
655 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \
656 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \
657 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \
658 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY))
660 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \
661 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \
662 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \
663 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \
664 BIT(HTT_PPDU_STATS_TAG_INFO) | \
665 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \
686 * |-----------------+----------------+----------------+---------------|
688 * |-------------------------------------------------------------------|
690 * |-------------------------------------------------------------------|
692 * |-------------------------------------------------------------------|
694 * |-------------------------------------------------------------------|
696 * |-------------------------------------------------------------------|
698 * |-------------------------------------------------------------------|
700 * |-------------------------------------------------------------------|
705 * dword0 - b'0:7 - msg_type: This will be set to
707 * b'8:15 - pdev_id:
709 * 1/2/3 mac id (for rings at LMAC level)
710 * b'16:23 - ring_id : Identify the ring to configure.
712 * b'24 - status_swap: 1 is to swap status TLV
713 * b'25 - pkt_swap: 1 is to swap packet TLV
714 * b'26:31 - rsvd1: reserved for future use
715 * dword1 - b'0:16 - ring_buffer_size: size of bufferes referenced by rx ring,
718 * - b'16:31 - rsvd2: Reserved for future use
719 * dword2 - b'0:31 - packet_type_enable_flags_0:
721 * bits from low to high: FP, MD, MO - 3 bits
725 * 10 mgmt subtypes * 3 bits -> 30 bits
727 * dword3 - b'0:31 - packet_type_enable_flags_1:
729 * bits from low to high: FP, MD, MO - 3 bits
731 * dword4 - b'0:31 - packet_type_enable_flags_2:
733 * bits from low to high: FP, MD, MO - 3 bits
735 * dword5 - b'0:31 - packet_type_enable_flags_3:
738 * bits from low to high: FP, MD, MO - 3 bits
740 * dword6 - b'0:31 - tlv_filter_in_flags:
748 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24)
749 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25)
751 #define HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID BIT(26)
762 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0),
763 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1),
764 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2),
765 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3),
766 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4),
767 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5),
768 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6),
769 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7),
770 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8),
771 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9),
772 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10),
773 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11),
774 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12),
778 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0),
779 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1),
780 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2),
781 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3),
782 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4),
783 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5),
784 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6),
785 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7),
786 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8),
787 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9),
788 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10),
789 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11),
790 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12),
791 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13),
792 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14),
793 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15),
794 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16),
795 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17),
796 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18),
797 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19),
798 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20),
799 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21),
800 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22),
801 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23),
802 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24),
803 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25),
804 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26),
805 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27),
806 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28),
807 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29),
811 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0),
812 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1),
813 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2),
814 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3),
815 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4),
816 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5),
817 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6),
818 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7),
819 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8),
820 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9),
821 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10),
822 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11),
823 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12),
824 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13),
825 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14),
826 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15),
827 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16),
828 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17),
832 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0),
833 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1),
834 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2),
835 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3),
836 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4),
837 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5),
838 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6),
839 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7),
840 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8),
841 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9),
842 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10),
843 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11),
844 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12),
845 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13),
846 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14),
847 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15),
848 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16),
849 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17),
850 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18),
851 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19),
852 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20),
853 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21),
854 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22),
855 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23),
856 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24),
857 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25),
858 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26),
859 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27),
860 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28),
861 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29),
865 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0),
866 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1),
867 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2),
868 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3),
869 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4),
870 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5),
871 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6),
872 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7),
873 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8),
874 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9),
875 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10),
876 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11),
877 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12),
878 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13),
879 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14),
880 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15),
881 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16),
882 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17),
886 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18),
887 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19),
888 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20),
889 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21),
890 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22),
891 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23),
892 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24),
893 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25),
894 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26),
1110 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24)
1111 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25)
1129 __le32 reserved[3];
1132 #define HTT_TX_RING_TLV_FILTER_MGMT_DMA_LEN GENMASK(3, 0)
1163 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS = BIT(1),
1164 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS = BIT(2),
1165 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START = BIT(3),
1166 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END = BIT(4),
1167 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU = BIT(5),
1168 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU = BIT(6),
1169 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA = BIT(7),
1170 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA = BIT(8),
1171 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT = BIT(9),
1172 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT = BIT(10),
1173 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE = BIT(11),
1174 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_BITMAP_ACK = BIT(12),
1175 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_1K_BITMAP_ACK = BIT(13),
1176 HTT_TX_FILTER_TLV_FLAGS0_COEX_TX_STATUS = BIT(14),
1177 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO = BIT(15),
1178 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2 = BIT(16),
1181 #define HTT_TX_FILTER_TLV_FLAGS2_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 BIT(11)
1183 /* HTT message target->host */
1202 #define HTT_TARGET_VERSION_MAJOR 3
1217 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16)
1294 * |----------------------------------------------------------------------|
1296 * |----------------------------------------------------------------------|
1298 * |----------------------------------------------------------------------|
1300 * |----------------------------------------------------------------------|
1302 * |----------------------------------------------------------------------|
1303 * | type-specific stats info |
1305 * |----------------------------------------------------------------------|
1307 * - MSG_TYPE
1312 * - mac_id
1315 * Value: 0-3
1316 * - pdev_id
1319 * Value: 0-3
1321 * 1/2/3 PDEV -> 0/1/2
1322 * - payload_size
1355 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3,
1363 /* bw - HTT_PPDU_STATS_BW */
1377 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted
1378 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted
1391 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0)
1407 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0)
1411 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2)
1412 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3)
1419 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28)
1420 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29)
1436 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2)
1437 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3)
1444 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28)
1445 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29)
1463 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8)
1466 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14)
1498 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0)
1500 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8)
1566 /* @brief target -> host MLO offset indiciation message
1574 * |---------------------------------------------------------------------|
1576 * |---------------------------------------------------------------------|
1578 * |---------------------------------------------------------------------|
1580 * |---------------------------------------------------------------------|
1582 * |---------------------------------------------------------------------|
1584 * |---------------------------------------------------------------------|
1586 * |---------------------------------------------------------------------|
1588 * |---------------------------------------------------------------------|
1590 * |---------------------------------------------------------------------|
1592 * - MSG_TYPE
1595 * - PDEV_ID
1598 * - CHIP_ID
1601 * - MAC_FREQ
1603 * - SYNC_TIMESTAMP_LO_US
1608 * - SYNC_TIMESTAMP_HI_US
1612 * - MLO_OFFSET_LO
1615 * - MLO_OFFSET_HI
1618 * - MLO_COMP_US
1621 * - MLO_COMP_CLCKS
1624 * - MLO_COMP_TIMER
1643 /* @brief host -> target FW extended statistics retrieve
1651 * |-----------------------------------------------------------|
1653 * |-----------------------------------------------------------|
1655 * |-----------------------------------------------------------|
1657 * |-----------------------------------------------------------|
1659 * |-----------------------------------------------------------|
1660 * | config param [3] |
1661 * |-----------------------------------------------------------|
1663 * |-----------------------------------------------------------|
1665 * |-----------------------------------------------------------|
1667 * |-----------------------------------------------------------|
1669 * - MSG_TYPE
1673 * - PDEV_MASK
1678 * Bit 8 : Reserved for SOC stats
1679 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC
1681 * - STATS_TYPE
1685 * - Reserved
1687 * - CONFIG_PARAM [0]
1690 * Value: stats-type specific configuration value
1692 * - CONFIG_PARAM [1]
1695 * Value: stats-type specific configuration value
1697 * - CONFIG_PARAM [2]
1700 * Value: stats-type specific configuration value
1702 * - CONFIG_PARAM [3]
1705 * Value: stats-type specific configuration value
1707 * - Reserved [31:0] for future use.
1708 * - COOKIE_LSBS
1710 * Purpose: Provide a mechanism to match a target->host stats confirmation
1711 * message with its preceding host->target stats request message.
1712 * Value: LSBs of the opaque cookie specified by the host-side requestor
1713 * - COOKIE_MSBS
1715 * Purpose: Provide a mechanism to match a target->host stats confirmation
1716 * message with its preceding host->target stats request message.
1717 * Value: MSBs of the opaque cookie specified by the host-side requestor
1751 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request
1752 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t
1756 * 0 bit htt_peer_stats_cmn_tlv
1757 * 1 bit htt_peer_details_tlv
1758 * 2 bit htt_tx_peer_rate_stats_tlv
1759 * 3 bit htt_rx_peer_rate_stats_tlv
1760 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv
1761 * 5 bit htt_rx_tid_stats_tlv
1762 * 6 bit htt_msdu_flow_stats_tlv
1767 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0)
1781 ATH12K_STATS_TIMER_DUR_2SEC = 3,
1787 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4); in ath12k_dp_get_mac_addr()