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/linux/arch/powerpc/crypto/
H A Dcurve25519-ppc64le_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 # [1] https://github.com/dot-asm/cryptogams/
11 # Copyright (c) 2006-2017, CRYPTOGAMS by <appro@openssl.org>
58 # - Added x25519_fe51_sqr_times, x25519_fe51_frombytes, x25519_fe51_tobytes
61 # Copyright 2024- IBM Corp.
63 # X25519 lower-level primitives for PPC64.
73 stdu 1,-144(1)
77 std 24,80(1)
89 ld 9,16(4)
90 ld 10,24(4)
[all …]
H A Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
43 #include <asm/asm-offsets.h>
44 #include <asm/asm-compat.h>
81 stdu 1,-752(1)
93 SAVE_GPR 24, 192, 1
102 addi 9, 1, 256
103 SAVE_VRS 20, 0, 9
104 SAVE_VRS 21, 16, 9
105 SAVE_VRS 22, 32, 9
[all …]
H A Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
26 # to 9 vectors for multiplications.
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt8195-apmixedsys.c1 // SPDX-License-Identifier: GPL-2.0-only
4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
6 #include "clk-fhctl.h"
7 #include "clk-gate.h"
8 #include "clk-mtk.h"
9 #include "clk-pll.h"
10 #include "clk-pllfh.h"
12 #include <dt-bindings/clock/mt8195-clk.h>
63 0, 0, 22, 0x0398, 24, 0, 0, 0, 0x0398, 0, 0x0398, 0, 9),
65 0, 0, 22, 0x0198, 24, 0, 0, 0, 0x0198, 0, 0x0198, 0, 9),
[all …]
H A Dclk-mt8188-apmixedsys.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
11 #include "clk-gate.h"
12 #include "clk-mtk.h"
13 #include "clk-pll.h"
62 0, 0, 22, 0x0450, 24, 0, 0, 0, 0x0450, 0, 0, 0, 9),
64 0, 0, 22, 0x0518, 24, 0, 0, 0, 0x0518, 0, 0, 0, 9),
66 0, 0, 22, 0x0528, 24, 0, 0, 0, 0x0528, 0, 0, 0, 9),
68 0, 0, 22, 0x0538, 24, 0, 0, 0, 0x0538, 0, 0, 0, 9),
70 HAVE_RST_BAR, BIT(23), 22, 0x0548, 24, 0, 0, 0, 0x0548, 0, 0, 0, 9),
[all …]
/linux/include/dt-bindings/memory/
H A Dmt8195-memory-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <dt-bindings/memory/mtk-memory-port.h>
20 * modules dma-address-region larbs-ports
22 * vcodec 4G ~ 8G larb19/20/21/22/23/24
29 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
30 * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
100 #define M4U_PORT_L9_IMG_IMGI_T1_A MTK_M4U_ID(9, 0)
101 #define M4U_PORT_L9_IMG_IMGBI_T1_A MTK_M4U_ID(9, 1)
102 #define M4U_PORT_L9_IMG_IMGCI_T1_A MTK_M4U_ID(9, 2)
103 #define M4U_PORT_L9_IMG_SMTI_T1_A MTK_M4U_ID(9, 3)
[all …]
/linux/arch/alpha/kernel/
H A Dentry.S1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Kernel entry-points.
8 #include <asm/asm-offsets.h>
32 .cfi_rel_offset $16, 24
39 .size \func, . - \func
43 * This defines the normal kernel pt-regs layout.
45 * regs 9-15 preserved by C code
46 * regs 16-18 saved by PAL-code
47 * regs 29-30 saved and set up by PAL-code
48 * JRP - Save regs 16-18 in a special area of the stack, so that
[all …]
/linux/arch/arm/mach-omap1/
H A Dmux.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/arch/arm/mach-omap1/mux.c
7 * Copyright (C) 2003 - 2008 Nokia Corporation
15 #include <linux/soc/ti/omap1-io.h>
30 MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
31 MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
37 MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
42 MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)
44 MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)
53 MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1)
[all …]
/linux/Documentation/translations/zh_CN/core-api/
H A Dpacking.rst1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
77 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
89 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
[all …]
/linux/drivers/gpu/drm/display/
H A Ddrm_dsc_helper.c1 // SPDX-License-Identifier: MIT
35 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
49 pps_header->HB1 = DP_SDP_PPS; in drm_dsc_dp_pps_header_init()
50 pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; in drm_dsc_dp_pps_header_init()
55 * drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes
57 * @rc_buffer_size: number of blocks - 1, according to DPCD offset 63h
82 * drm_dsc_pps_payload_pack() - Populates the DSC PPS
110 pps_payload->dsc_version = in drm_dsc_pps_payload_pack()
111 dsc_cfg->dsc_version_minor | in drm_dsc_pps_payload_pack()
112 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; in drm_dsc_pps_payload_pack()
[all …]
/linux/drivers/ras/amd/atl/
H A Dreg_fields.h1 /* SPDX-License-Identifier: GPL-2.0 */
51 * DF3 ComponentIdMask [9:0]
60 #define DF3_COMPONENT_ID_MASK GENMASK(9, 0)
73 * DF3 DstFabricID [9:0]
83 #define DF3_DST_FABRIC_ID GENMASK(9, 0)
122 * DF2 DieIdShift [27:24]
129 #define DF2_DIE_ID_SHIFT GENMASK(27, 24)
183 * DF2 DramHoleBase [31:24]
184 * DF3 DramHoleBase [31:24]
185 * DF3p5 DramHoleBase [31:24]
[all …]
/linux/arch/arm/probes/kprobes/
H A Dtest-arm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/kernel/kprobes-test-arm.c
14 #include "test-core.h"
55 TEST_GROUP("Data-processing (register), (register-shifted register), (immediate)") in kprobe_arm_test_cases()
69 TEST_RRR( op s "hi r8, r",9, VAL1,", r",14,val, ", lsl r",0, 3,"")\ in kprobe_arm_test_cases()
70 TEST_RRR( op s "ls r9, r",9, VAL1,", r",14,val, ", lsr r",7, 4,"")\ in kprobe_arm_test_cases()
96 TEST_RRR( op "ls r",9, VAL1,", r",14,val, ", lsl r",0, 3,"") \ in kprobe_arm_test_cases()
97 TEST_RRR( op "hi r",9, VAL1,", r",14,val, ", lsr r",7, 4,"") \ in kprobe_arm_test_cases()
117 TEST_RR( op s "hi r9, r",9, val, ", lsr r",7, 4,"") \ in kprobe_arm_test_cases()
118 TEST_RR( op s "ls r10, r",9, val, ", asr r",7, 5,"") \ in kprobe_arm_test_cases()
[all …]
H A Dtest-thumb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/probes/kprobes/test-thumb.c
13 #include "test-core.h"
89 TEST_GROUP("16-bit Thumb data-processing instructions") in kprobe_thumb16_test_cases()
118 TEST_R( "add sp" ", r",8,-8, "") in kprobe_thumb16_test_cases()
120 TEST_BF_R("add pc" ", r",0,2f-1f-8,"") in kprobe_thumb16_test_cases()
125 TEST_R( "cmp sp" ", r",8,-8, "") in kprobe_thumb16_test_cases()
130 TEST_P( "mov sp, r",8,-8, "") in kprobe_thumb16_test_cases()
164 TEST_GROUP("16-bit Thumb Load/store instructions") in kprobe_thumb16_test_cases()
166 TEST_RPR("str r",0, VAL1,", [r",1, 24,", r",2, 48,"]") in kprobe_thumb16_test_cases()
[all …]
/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-reg.h1 /* SPDX-License-Identifier: GPL-2.0
3 * mt8186-reg.h -- Mediatek 8186 audio driver reg definition
39 #define PDN_ADC_SFT 24
40 #define PDN_ADC_MASK_SFT BIT(24)
53 #define PDN_24M_SFT 9
54 #define PDN_24M_MASK_SFT BIT(9)
141 #define DL6_ON_SFT 9
142 #define DL6_ON_MASK_SFT BIT(9)
215 #define I2S3_UPDATE_WORD_SFT 24
216 #define I2S3_UPDATE_WORD_MASK_SFT GENMASK(28, 24)
[all …]
/linux/arch/arm/mach-davinci/
H A Dda830.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
14 #include <linux/irqchip/irq-davinci-cp-intc.h>
16 #include <clocksource/timer-davinci.h>
55 MUX_CFG(DA830, NEMB_RAS, 0, 24, 0xf, 1, false)
63 MUX_CFG(DA830, EMB_A_4, 1, 24, 0xf, 1, false)
71 MUX_CFG(DA830, GPIO7_6, 1, 24, 0xf, 8, false)
79 MUX_CFG(DA830, EMB_A_12, 2, 24, 0xf, 1, false)
87 MUX_CFG(DA830, GPIO3_13, 2, 24, 0xf, 8, false)
94 MUX_CFG(DA830, EMB_D_24, 3, 24, 0xf, 1, false)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
40 #define MT_TX_FREE_MSDU_CNT GENMASK(9, 0)
51 #define MT_TXD0_PKT_FMT GENMASK(24, 23)
57 #define MT_TXD1_OWN_MAC GENMASK(29, 24)
65 #define MT_TXD1_WLAN_IDX GENMASK(9, 0)
69 #define MT_TXD2_POWER_OFFSET GENMASK(29, 24)
76 #define MT_TXD2_RTS BIT(9)
103 #define MT_TXD5_TX_STATUS_MCU BIT(9)
128 #define MT_TXD7_TX_TIME GENMASK(9, 0)
135 #define MT_TX_RATE_MODE GENMASK(9, 6)
[all …]
H A Dmt76_connac3_mac.h1 /* SPDX-License-Identifier: ISC */
45 #define MT_RXD1_NORMAL_CLM BIT(24)
62 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
80 #define MT_RXD3_NORMAL_FCS_ERR BIT(24)
91 #define MT_RXV_HDR_BAND_IDX BIT(24)
101 /* P-RXV */
109 #define MT_PRXV_RCPI3 GENMASK(31, 24)
114 #define MT_PRXV_HT_STBC GENMASK(10, 9)
119 /* C-RXV */
137 #define MT_CRXV_HE_SR3_MASK GENMASK(24, 21)
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
33 #define B_AX_APFM_OFFMAC BIT(9)
56 #define B_AX_EF_VDDQST_MASK GENMASK(26, 24)
60 #define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8)
78 #define B_AX_WDT_WAKE_USB_EN BIT(9)
90 #define B_AX_PO_BT_PTA_PINS BIT(9)
111 #define B_AX_GPIO_MOD_15_TO_8_MASK GENMASK(31, 24)
150 #define B_AX_LPSOP_DSWRM BIT(9)
156 #define B_MAC_AX_SB_FW_MASK GENMASK(30, 24)
[all …]
H A Dtxrx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
28 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_rate_mode()
41 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_ht_mcs()
49 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_mcs()
62 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_nss()
69 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24)
70 #define RTW89_TXWD_BODY0_WP_OFFSET_V1 GENMASK(28, 24)
88 #define RTW89_TXWD_BODY2_MACID GENMASK(30, 24)
99 #define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24)
103 #define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24)
[all …]
/linux/arch/arm/mach-omap2/
H A Dcm-regbits-54xx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
9 * Benoit Cousson (b-cousson@ti.com)
13 * with the public linux-omap@vger.kernel.org mailing list and the
15 * up-to-date with the file contents.
23 #define OMAP54XX_CLKSEL_SHIFT 24
27 #define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24
31 #define OMAP54XX_CLKSEL_FCLK_SHIFT 24
33 #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24
41 #define OMAP54XX_CLKSEL_SOURCE_SHIFT 24
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8365.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/pinctrl/mt65xx.h>
14 #include "pinctrl-mtk-common.h"
15 #include "pinctrl-mtk-mt8365.h"
37 MTK_PIN_DRV_GRP(9, 0x710, 8, 2),
48 MTK_PIN_DRV_GRP(20, 0x710, 24, 2),
49 MTK_PIN_DRV_GRP(21, 0x710, 24, 2),
52 MTK_PIN_DRV_GRP(24, 0x720, 0, 2),
77 MTK_PIN_DRV_GRP(49, 0x720, 24, 2),
78 MTK_PIN_DRV_GRP(50, 0x720, 24, 2),
[all …]
/linux/Documentation/devicetree/bindings/eeprom/
H A Dat24.yaml1 # SPDX-License-Identifier: GPL-2.0-only
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
14 - $ref: /schemas/nvmem/nvmem.yaml
15 - $ref: /schemas/nvmem/nvmem-deprecated-cells.yaml
22 - pattern: "^atmel,(24(c|cs|mac)[0-9]+|spd)$"
23 - enum: ["microchip,24aa025e48", "microchip,24aa025e64"]
25 - compatible
29 pattern: "^eeprom@[0-9a-f]{1,2}$"
[all …]
/linux/drivers/staging/media/rkvdec/
H A Drkvdec-h264.c1 // SPDX-License-Identifier: GPL-2.0
9 * Jeffy Chen <jeffy.chen@rock-chips.com>
12 #include <media/v4l2-h264.h>
13 #include <media/v4l2-mem2mem.h>
16 #include "rkvdec-regs.h"
55 #define PIC_WIDTH_IN_MBS PS_FIELD(38, 9)
56 #define PIC_HEIGHT_IN_MBS PS_FIELD(47, 9)
133 /* Table 9-12 – Values of variables m and n for ctxIdx from 0 to 10 */
134 CABAC_ENTRY(0, 20, -15, 20, -15, 20, -15, 20, -15),
137 CABAC_ENTRY(3, 20, -15, 20, -15, 20, -15, 20, -15),
[all …]
/linux/drivers/clk/ti/
H A Dclk-44xx.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Tero Kristo (t-kristo@ti.com)
15 #include <dt-bindings/clock/omap4.h>
54 { 24, TI_CLK_DIVIDER, omap4_aess_fclk_parents, &omap4_aess_fclk_data },
59 "abe-clkctrl:0018:26",
73 { 24, TI_CLK_MUX, omap4_func_dmic_abe_gfclk_parents, NULL },
79 "abe-clkctrl:0020:26",
86 { 24, TI_CLK_MUX, omap4_func_mcasp_abe_gfclk_parents, NULL },
92 "abe-clkctrl:0028:26",
99 { 24, TI_CLK_MUX, omap4_func_mcbsp1_gfclk_parents, NULL },
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
23 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
48 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
68 #define MT_RXD3_NORMAL_PATTERN_DROP BIT(9)
81 #define MT_RXV1_VHTA2_B8_B3 GENMASK(29, 24)
91 #define MT_RXV1_HT_AD_CODE BIT(9)
101 #define MT_RXV3_WB_RSSI GENMASK(31, 24)
104 #define MT_RXV4_RCPI3 GENMASK(31, 24)
111 #define MT_RXV6_NF3 GENMASK(31, 24)
[all …]

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