Lines Matching +full:24 +full:- +full:9

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
33 #define B_AX_APFM_OFFMAC BIT(9)
56 #define B_AX_EF_VDDQST_MASK GENMASK(26, 24)
60 #define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8)
78 #define B_AX_WDT_WAKE_USB_EN BIT(9)
90 #define B_AX_PO_BT_PTA_PINS BIT(9)
111 #define B_AX_GPIO_MOD_15_TO_8_MASK GENMASK(31, 24)
150 #define B_AX_LPSOP_DSWRM BIT(9)
156 #define B_MAC_AX_SB_FW_MASK GENMASK(30, 24)
199 #define B_AX_IDMEM_SHARE_MODE_RECORD_MASK GENMASK(27, 24)
215 #define PS_CPWM_RSP_SEQ_NUM GENMASK(9, 8)
257 #define B_AX_WL_XTAL_SI_MODE_MASK GENMASK(25, 24)
274 #define B_AX_XTAL_SC_INIT_A_BLOCK_MASK GENMASK(30, 24)
292 #define B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK GENMASK(27, 24)
307 #define B_AX_WLRF1_CTRL_1 BIT(9)
313 #define B_AX_WLMAC_PWR_STE_MASK GENMASK(9, 8)
324 #define B_AX_S1_LDO_VSEL_F_MASK GENMASK(25, 24)
338 #define B_AX_WD_ITVL_ACT_V1_MASK GENMASK(27, 24)
348 #define B_AX_HAXI_MAX_RXDMA_MASK GENMASK(9, 8)
365 #define B_AX_STOP_ACH1 BIT(9)
380 #define B_AX_ACH1_BUSY BIT(9)
408 #define B_AX_LTR_CURR_IDX_HW_MASK GENMASK(9, 8)
515 #define B_AX_STA_SCH_EN BIT(24)
532 #define B_AX_STA_SCH_CLK_EN BIT(24)
539 #define B_AX_AXIDMA_CLK_EN BIT(9)
585 #define B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU BIT(24)
595 #define B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX BIT(9)
619 #define B_AX_APB_BRIDGE_ERR_INT_EN BIT(9)
638 #define B_AX_APB_BRIDGE_ERR_FLAG BIT(9)
650 #define B_AX_PL_PAGE_128B_SEL BIT(9)
666 #define B_AX_HDT_RXAGG_CFG_ERR_INT_EN BIT(24)
679 #define B_AX_HDT_WD_CHK_ERR_INT_EN BIT(9)
739 #define B_AX_HR_AGG_CFG_ERR_INT_EN BIT(24)
752 #define B_AX_HT_WD_CHKSUM_ERR_INT_EN BIT(9)
806 #define B_AX_CPU_RXAGG_CFG_ERR_INT_EN BIT(24)
818 #define B_AX_CPU_CHANNEL_DMA_ERR_INT_EN BIT(9)
866 #define B_AX_CR_SHIFT_EN_ERR_INT_EN BIT(24)
879 #define B_AX_CT_CHANNEL_DMA_ERR_INT_EN BIT(9)
929 #define B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN BIT(24)
935 #define B_AX_PLE_NULL_PKT_ERR_INT_EN BIT(9)
968 #define B_AX_STF_CMD_OVERFLOW_ERR_INT_EN BIT(24)
1033 #define B_AX_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8)
1041 #define B_AX_PREC_PAGE_CH12_MASK GENMASK(24, 16)
1095 #define B_AX_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16)
1114 #define B_AX_WDE_ERR_FLAG_NUM1_MSTIDX_MASK GENMASK(27, 24)
1125 #define B_AX_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24)
1231 #define B_AX_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24)
1238 #define B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9)
1300 #define B_AX_WDE_DATCHN_ARBT_ERR BIT(24)
1371 #define B_AX_PLE_ERR_FLAG_NUM1_MSTIDX_MASK GENMASK(27, 24)
1381 #define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9)
1392 #define B_AX_PLE_BUFMGN_FRZTO_ERR_V1 BIT(9)
1406 #define B_AX_PLE_DATCHN_ARBT_ERR_INT_EN BIT(24)
1463 #define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9)
1557 #define B_AX_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24)
1569 #define B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN BIT(9)
1699 #define B_AX_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24)
1705 #define B_AX_CPUQ_OP_SRC_PID_MASK GENMASK(24, 22)
1748 #define B_AX_TX_KSRCH_ERR_EN BIT(9)
1799 #define B_AX_CLK_EN_WAPI BIT(9)
1849 #define B_AX_SS_REL_QUEUE_MASK GENMASK(29, 24)
1883 #define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR BIT(24)
1888 #define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9)
1914 #define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9)
1946 #define B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE BIT(9)
1985 #define B_AX_B0_ISR_ERR_CMDPSR_CMDTYPE BIT(9)
2014 #define B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE BIT(9)
2054 #define B_AX_B1_ISR_ERR_CMDPSR_CMDTYPE BIT(9)
2177 #define B_AX_SYNC_PORT_SRC GENMASK(26, 24)
2208 #define B_AX_SIFS_TIMEOUT_TB_AGGR_MASK GENMASK(30, 24)
2217 #define B_AX_BTCCA_BRK_TXOP_EN BIT(9)
2233 #define B_AX_CTN_TXEN_MGQ1 BIT(9)
2273 #define B_AX_TB_CHK_CCA_P20 BIT(24)
2328 #define B_AX_BCN_FORCETX_EN BIT(9)
2398 #define B_AX_BCN_ERR_CNT_SUM_MASK GENMASK(31, 24)
2472 #define B_AX_P0MB9_EN BIT(9)
2500 #define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
2518 #define B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24)
2537 #define B_AX_S_TXCNT_LMT_MASK GENMASK(29, 24)
2543 #define B_AX_RATE_SEL_MASK GENMASK(29, 24)
2550 #define B_AX_F2PCMD_FWWD_RLS_MODE BIT(9)
2562 #define B_AX_BT_PLT_RST BIT(9)
2575 #define B_AX_BSS_COLOB_AX_PORT_3_MASK GENMASK(29, 24)
2593 #define B_AX_TX_SPF_U3_PKTID_ERR_INT_EN BIT(24)
2600 #define B_AX_TXPRT_FULL_DROP_ERR_INT_EN BIT(9)
2657 #define AX_PTCL_DBG_BCNQ_NUM1 9
2680 #define B_AX_RX_RU5_FSM_HANG_ERR BIT(24)
2695 #define B_AX_RX_RXSTS_ZERO_LEN_ERR BIT(9)
2715 #define B_AX_RXDMA_DIS_CSI_RELEASE BIT(9)
2733 #define B_AX_RXDMA_DEFAULT_PAGE_V1_MASK GENMASK(28, 24)
2749 #define B_AX_RXDMA_F2PCMD_QUEUE_ID_SW_EN BIT(24)
2754 #define B_AX_RXDMA_F2PCMD_QUEUE_ID_TGT_SW_1_MASK GENMASK(9, 4)
2765 #define B_AX_RX_DBG_SEL_MASK GENMASK(24, 19)
2767 #define B_AX_RXSTS_CS_MASK GENMASK(13, 9)
2783 #define B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK BIT(24)
2798 #define B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK BIT(9)
2868 #define B_AX_TX_RU7_FSM_HANG_ERR_MSK BIT(24)
2902 #define B_AX_TCR_ZLD_NUM_MASK GENMASK(31, 24)
2907 #define B_AX_TCR_VHTSIGA1_TXPS BIT(9)
2943 #define B_AX_NON_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(28, 24)
2954 #define B_AX_MACTX_MPDU_CNT GENMASK(31, 24)
2958 #define B_AX_LENGTH_ERR_FLAG_U1 BIT(9)
2996 #define B_AX_RSP_CHK_EDCCA BIT(24)
3013 #define B_AX_FTM_RRSR_RATE_EN_MASK GENMASK(27, 24)
3020 #define B_AX_WMAC_RESP_REF_RATE_SEL BIT(9)
3040 #define B_AX_RXTRIG_MACID_MASK GENMASK(31, 24)
3113 #define B_AX_TMAC_RESP_INT_EN BIT(9)
3160 #define B_AXC_PHY_TXON_TIMEOUT BIT(24)
3182 #define B_AX_BFMER_HE_CSI_OFFSET_MASK GENMASK(31, 24)
3190 #define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK GENMASK(31, 24)
3208 #define B_AX_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24)
3221 #define B_AX_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8)
3265 #define B_AX_UID_FILTER_MASK GENMASK(31, 24)
3275 #define B_AX_A_BCN_CHK_RULE_MASK GENMASK(9, 8)
3340 #define B_AX_CSIPRT_VHTSU_AID_EN BIT(24)
3384 #define B_AX_RX_ERR_TRIG_ACT_TO_MSK BIT(9)
3428 #define B_AX_FORCE_PWR_BY_RATE_EN BIT(9)
3448 #define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_MASK GENMASK(28, 24)
3460 #define B_AX_FORCE_TXSC_VALUE_MASK GENMASK(12, 9)
3471 #define B_AX_PWR_UL_TB_1T_NORM_BW160 GENMASK(31, 24)
3475 #define B_AX_PWR_UL_TB_2T_NORM_BW160 GENMASK(31, 24)
3555 #define B_AX_BTC_MODE_MASK GENMASK(25, 24)
3569 #define B_AX_BT_BLE_EN_V1 BIT(24)
3574 #define B_AX_BT_H_TX_ULTRA_MASK GENMASK(9, 8)
3653 #define B_AX_GNT_BT_RFC_S1_VAL BIT(9)
3714 #define B_AX_GNT_WL_BB_S1_SW_CTRL BIT(24)
3725 #define B_AX_GNT_WL_BB_S0_SW_VAL BIT(9)
3752 #define B_BE_ISO_RFDIO BIT(9)
3770 #define B_BE_SOP_EXTL BIT(24)
3784 #define B_BE_APFM_OFFMAC BIT(9)
3813 #define B_BE_CPHY_POWER_READY_CHK BIT(24)
3827 #define B_BE_DIS_CLK_REG9_GATE BIT(9)
3850 #define B_BE_R_SYM_DIS_PCIE_FLR BIT(9)
3867 #define B_BE_R_SYM_WLPOFF_PC_EN BIT(24)
3878 #define B_BE_R_SYM_WLBBOFF1_P4_PC_EN BIT(9)
3894 #define B_BE_R_SYM_WLCMAC0_PC_EN BIT(24)
3909 #define B_BE_IMEM1_PC_EN BIT(9)
3932 #define B_BE_GPIO_MOD_15_TO_8_MASK GENMASK(31, 24)
3955 #define B_BE_BT_AFE_PLL_EN BIT(9)
3967 #define B_BE_PCIE_SEC_LOAD_CLR BIT(24)
3978 #define B_BE_PCIE_WAIT_TIME BIT(9)
3994 #define B_BE_HAXIDMA_IO_EN BIT(24)
4009 #define B_BE_USB_LPM_NY BIT(9)
4024 #define B_BE_R_SYM_ISO_DMEM12PP BIT(24)
4035 #define B_BE_R_SYM_LDOBTSDIO_EN BIT(9)
4046 #define B_BE_R_SYM_ISO_CMAC02PP BIT(24)
4056 #define B_BE_FEN_BB1_IP_RSTN BIT(9)
4067 #define B_BE_WCPU_WARM_EN BIT(9)
4091 #define B_BE_LPSOP_DSWRM BIT(9)
4107 #define B_BE_LPSROP_IMEM4_RSU_EN BIT(24)
4117 #define B_BE_LPSROP_HIOE BIT(9)
4127 #define B_BE_R_SYM_AUTOLOAD_WITH_PMC_SEL BIT(24)
4139 #define B_BE_EFUSE_BURN_GNT_MASK GENMASK(31, 24)
4141 #define B_BE_STOP_WL_PMC BIT(9)
4159 #define B_BE_IMEM4_WLMCU_DS BIT(24)
4167 #define B_BE_MEM_SDIO_LS BIT(9)
4176 #define B_BE_AON_MIO_EPHY_1K_SEL_MASK GENMASK(29, 24)
4204 #define B_BE_WDT_WAKE_USB_EN BIT(9)
4212 #define B_BE_FS_RPWM_INT_EN_V1 BIT(24)
4222 #define B_BE_FS_GPIO25_INT_EN BIT(9)
4235 #define B_BE_HALT_D2H_INT_EN BIT(24)
4249 #define B_BE_GPIO9_INT_EN BIT(9)
4262 #define B_BE_HALT_D2H_INT BIT(24)
4276 #define B_BE_GPIO9_INT BIT(9)
4296 #define B_BE_WLANCPU_FWDL_EN BIT(9)
4312 #define B_BE_UDM0_TX_RPT_CNT_MASK GENMASK(27, 24)
4334 #define B_BE_REG_LPF_R2_MASK GENMASK(28, 24)
4340 #define B_BE_REG_CP_ICP_SEL_MASK GENMASK(9, 6)
4352 #define B_BE_REG_SDM_EDGE_SEL BIT(24)
4367 #define B_BE_LDO_VSEL_D2S_0_MASK GENMASK(25, 24)
4376 #define B_BE_REG_CK1920M_EN BIT(9)
4391 #define B_BE_WL_XTAL_SI_MODE_MASK GENMASK(25, 24)
4399 #define B_BE_WLMAC_PWR_STE_MASK GENMASK(9, 8)
4411 #define B_BE_DCPU_WARM_EN BIT(9)
4528 #define B_BE_LAT_LTR_IDX_DRV_VLD_V1 BIT(24)
4536 #define B_BE_LTR_IDX_DISABLE_V1_MASK GENMASK(9, 8)
4578 #define B_BE_STA_SCH_EN BIT(24)
4591 #define B_BE_P_AXIDMA_EN BIT(9)
4602 #define B_BE_STA_SCH_CLK_EN BIT(24)
4614 #define B_BE_P_AXIDMA_CKEN BIT(9)
4647 #define B_BE_SER_L1_COUNTER_MASK GENMASK(27, 24)
4661 #define B_BE_DMAC_BB_CTRL_32 BIT(24)
4676 #define B_BE_DMAC_BB_CTRL_17 BIT(9)
4691 #define B_BE_PLE_EMPTY_QTA_DMAC_WLAN_CPU BIT(24)
4706 #define B_BE_PLE_EMPTY_QUE_DMAC_SEC_TX BIT(9)
4732 #define B_BE_SER_L1_WDRLS_CNT_MASK GENMASK(31, 24)
4738 #define B_BE_SER_L1_WDE_CNT_MASK GENMASK(31, 24)
4744 #define B_BE_SER_L1_DISP_CNT_MASK GENMASK(31, 24)
4750 #define B_BE_SER_L1_HCI_BUF_CNT_MASK GENMASK(31, 24)
4756 #define B_BE_SER_L1_PLDRLS_ERR_CNT_MASK GENMASK(31, 24)
4780 #define B_BE_APB_BRIDGE_ERR_INT_EN BIT(9)
4801 #define B_BE_APB_BRIDGE_ERR_FLAG BIT(9)
4820 #define B_BE_STF_CMD_OVERFLOW_ERR BIT(24)
4834 #define B_BE_PLE_NULL_PKT_ERR BIT(9)
4852 #define B_BE_HR_AGG_CFG_ERR BIT(24)
4864 #define B_BE_HT_WD_CHKSUM_ERR BIT(9)
4881 #define B_BE_CR_SHIFT_EN_ERR BIT(24)
4894 #define B_BE_CT_CHANNEL_DMA_ERR BIT(9)
4912 #define B_BE_STF_CMD_OVERFLOW_ERR_INT_EN BIT(24)
4926 #define B_BE_PLE_NULL_PKT_ERR_INT_EN BIT(9)
4980 #define B_BE_HR_AGG_CFG_ERR_INT_EN BIT(24)
4992 #define B_BE_HT_WD_CHKSUM_ERR_INT_EN BIT(9)
5056 #define B_BE_CR_SHIFT_EN_ERR_INT_EN BIT(24)
5069 #define B_BE_CT_CHANNEL_DMA_ERR_INT_EN BIT(9)
5133 #define B_BE_FWD_WLAN_CPU_TYPE_10_MASK GENMASK(25, 24)
5141 #define B_BE_FWD_WLAN_CPU_TYPE_2_MASK GENMASK(9, 8)
5154 #define B_BE_WDE_AVAL_UPD_QTAID_MASK GENMASK(27, 24)
5163 #define B_BE_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24)
5176 #define B_BE_WDE_BUFMGN_FRZTO_ERR_INT_EN BIT(9)
5275 #define B_BE_PLE_AVAL_UPD_QTAID_MASK GENMASK(27, 24)
5284 #define B_BE_PLE_DATCHN_ARBT_ERR_INT_EN BIT(24)
5297 #define B_BE_PLE_BUFMGN_FRZTO_ERR_INT_EN BIT(9)
5419 #define B_BE_PLE_SRCHPG_FRZTO_IMR BIT(24)
5448 #define B_BE_WDRLS_RPT0_FRZTO_ERR_INT_EN BIT(9)
5474 #define B_BE_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24)
5515 #define B_BE_CHIF_HDR_SEGLEN_ISR_EN BIT(9)
5543 #define B_BE_WD_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24)
5548 #define B_BE_WD_CPUQ_OP_SRC_QID_MASK GENMASK(9, 4)
5553 #define B_BE_WD_CPUQ_OP_DST_QID_MASK GENMASK(9, 4)
5576 #define B_BE_PL_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24)
5581 #define B_BE_PL_CPUQ_OP_SRC_QID_MASK GENMASK(9, 4)
5586 #define B_BE_PL_CPUQ_OP_DST_QID_MASK GENMASK(9, 4)
5636 #define B_BE_WPKT_FW_RLS BIT(24)
5663 #define B_BE_MPDU_CUT_CTRL_EN BIT(24)
5695 #define B_BE_WAPI_SPEC BIT(24)
5704 #define B_BE_CLK_EN_WAPI BIT(9)
5780 #define B_BE_B0_IMR_DBG_USRCTL_RDNRLSCMD BIT(24)
5785 #define B_BE_B0_IMR_ERR_CMDPSR_CMDTYPE BIT(9)
5820 #define B_BE_B1_IMR_DBG_USRCTL_RDNRLSCMD BIT(24)
5825 #define B_BE_B1_IMR_ERR_CMDPSR_CMDTYPE BIT(9)
5889 #define B_BE_DLYTX_SEL_MASK GENMASK(25, 24)
5897 #define B_BE_BAND1_TRIG_EN BIT(9)
5925 #define B_BE_CFG_WD_PERIOD_ACTIVE_MASK GENMASK(27, 24)
5952 #define B_BE_STOP_CH9 BIT(9)
6005 #define B_BE_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8)
6044 #define B_BE_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16)
6059 #define B_BE_FORCE_BTCOEX_REG_GCKEN BIT(24)
6067 #define B_BE_ACQCHK_ERR_FLAG_MASK GENMASK(31, 24)
6077 #define B_BE_WL_ACT2_SWCTRL BIT(24)
6092 #define B_BE_GNT_BT_BB1_VAL BIT(9)
6189 #define B_BE_RRSR_HE_MASK GENMASK(31, 24)
6204 #define B_BE_PTCL_TX_IDLETO_IDCT_EN BIT(9)
6218 #define B_BE_PTCL_TX_IDLETO_IDCT BIT(9)
6231 #define B_BE_SER_L0_PHYINTF_CNT_MASK GENMASK(31, 24)
6254 #define B_BE_SER_L0_SUBMODULE_BIT24_CNT BIT(24)
6269 #define B_BE_SER_L0_SUBMODULE_BIT9_CNT BIT(9)
6285 #define B_BE_P0_SYNC_PORT_SRC_SEL_MASK GENMASK(26, 24)
6290 #define B_BE_BCNQ_CW_MASK GENMASK(31, 24)
6298 #define B_BE_100NS_TIME_MASK GENMASK(28, 24)
6305 #define B_BE_SIFS_TIMEOUT_TB_AGGR_MASK GENMASK(31, 24)
6312 #define B_BE_R_SIFS_AGGR_TIME_V1_MASK GENMASK(31, 24)
6323 #define B_BE_NO_GNT_WL_BRK_TXOP_EN BIT(9)
6336 #define B_BE_OTHER_LINK_BKF_BLK_TX_THD_MASK GENMASK(30, 24)
6351 #define B_BE_SIFS_TIMEOUT_TB_T2_MASK GENMASK(30, 24)
6369 #define B_BE_CTN_TXEN_MGQ1 BIT(9)
6389 #define B_BE_TB_CHK_EDCCA_S40 BIT(9)
6408 #define B_BE_HE_SIFS_CHK_EDCCA_S40 BIT(9)
6427 #define B_BE_HE_CTN_CHK_EDCCA_S40 BIT(9)
6459 #define B_BE_BCN_FORCETX_EN_P0 BIT(9)
6504 #define B_BE_BCN_ERR_CNT_SUM_P0_MASK GENMASK(31, 24)
6550 #define B_BE_P0MB9_EN BIT(9)
6590 #define B_BE_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
6604 #define B_BE_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24)
6612 #define B_BE_LATENCY_PADDING_PKT_TH_MASK GENMASK(31, 24)
6624 #define B_BE_RATE_SEL_MASK GENMASK(29, 24)
6631 #define B_BE_BT_PLT_RST BIT(9)
6644 #define B_BE_BSS_COLOB_BE_PORT_3_MASK GENMASK(29, 24)
6686 #define B_BE_TX_SPF_U2_PKTID_IMR BIT(24)
6694 #define B_BE_TXPRT_FULL_DROP_IMR BIT(9)
6722 #define B_BE_TX_SPF_U2_PKTID_ERR BIT(24)
6730 #define B_BE_TXPRT_FULL_DROP_ERR BIT(9)
6736 #define B_BE_PTCL_FSM2_TO_THR_MASK GENMASK(29, 24)
6764 #define B_BE_RX_RU5_FSM_HANG_ERROR BIT(24)
6779 #define B_BE_RX_RXSTS_ZERO_LENGTH_ERROR BIT(9)
6799 #define B_BE_RX_RU5_FSM_HANG_ERROR_IMR BIT(24)
6814 #define B_BE_RX_RXSTS_ZERO_LENGTH_ERROR_IMR BIT(9)
6887 #define B_BE_TX_RU7_FSM_HANG_ERROR BIT(24)
6908 #define B_BE_TX_RU7_FSM_HANG_ERROR_IMR BIT(24)
6963 #define B_BE_RX_RU13_FSM_HANG_ERROR BIT(24)
6982 #define B_BE_RX_RU13_FSM_HANG_ERROR_IMR BIT(24)
7040 #define B_BE_EHT_HE_PPDU_4XLTF_ZLD_USTIMER_MASK GENMASK(28, 24)
7050 #define B_BE_RESP_TX_ABORT_TEST_EN BIT(24)
7064 #define B_BE_RESP_TB_CHK_TXTIME BIT(24)
7080 #define B_BE_FTM_RRSR_RATE_EN_MASK GENMASK(28, 24)
7110 #define B_BE_RXTRIG_MACID_MASK GENMASK(31, 24)
7120 #define B_BE_WMAC_FTM_TIMEOUT_THR_MASK GENMASK(29, 24)
7123 #define B_BE_RMAC_BFMER BIT(9)
7156 #define B_BE_BFMER_ERR_FLAG BIT(9)
7178 #define B_BE_PHYINTF_MIMO_EN_PHASE_MASK GENMASK(25, 24)
7223 #define B_BE_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24)
7236 #define B_BE_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8)
7243 #define B_BE_BFMEE_BE_CSI_RRSC_BITMAP_MASK GENMASK(31, 24)
7252 #define B_BE_BFMEE_EHT_CSI_RATE_MASK GENMASK(31, 24)
7267 #define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_EDCCA40 BIT(9)
7287 #define B_BE_ACK_BA_RESP_HE_CHK_SEC_EDCCA40 BIT(9)
7307 #define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_EDCCA40 BIT(9)
7326 #define B_BE_DRV_INFO_SZ_MASK GENMASK(9, 8)
7357 #define B_BE_UID_FILTER_MASK GENMASK(31, 24)
7364 #define B_BE_A_BCN_CHK_RULE_MASK GENMASK(9, 8)
7394 #define B_BE_DIS_ADDR_CLK_GATED BIT(9)
7402 #define B_BE_BACAM_SKIP_ALL_QOSNULL BIT(24)
7448 #define B_BE_CSIPRT_VHTSU_AID_EN BIT(24)
7452 #define B_BE_RX_ERR_TRIG_ACT_TO BIT(9)
7465 #define B_BE_RX_ERR_TRIG_ACT_TO_MSK BIT(9)
7497 #define B_BE_PLCP_STBC_SRC BIT(9)
7522 #define B_BE_RESP_RXDMA_REQ_INVLD_ERR_ISR_EN BIT(9)
7563 #define B_BE_PWR_REF_CTRL_OFDM GENMASK(9, 1)
7585 #define B_BE_PWR_OFST_RULMT_DB GENMASK(17, 9)
7589 #define B_BE_PWR_FORCE_MACID_ON BIT(9)
7602 #define B_BE_PWR_OFST_SW_DB GENMASK(27, 24)
7636 #define RR_MOD_RXB GENMASK(9, 5)
7648 #define RR_MOD_M_RXBB GENMASK(9, 5)
7663 #define RR_LOKVB_COQ GENMASK(9, 4)
7670 #define RR_CHTR_TXRX GENMASK(9, 0)
7681 #define RR_CFGCH_BAND0 GENMASK(9, 8)
7706 #define RR_RCKO_OFF GENMASK(13, 9)
7712 #define RR_RSV4_PLLCH GENMASK(9, 0)
7718 #define RR_LUTWA_MASK GENMASK(9, 0)
7745 #define RR_GAINTX_PAD GENMASK(9, 5)
7750 #define RR_TXMO_FII GENMASK(9, 6)
7789 #define RR_RXBB_C1G GENMASK(9, 8)
7800 #define RR_RXA_DPK GENMASK(9, 8)
7804 #define RR_RAA2_SWATT GENMASK(15, 9)
7806 #define RR_RXA2_C2 GENMASK(9, 3)
7818 #define RR_RXBB2_IDAC GENMASK(11, 9)
7821 #define RR_XALNA2_SW2 GENMASK(9, 8)
7825 #define RR_DCK_TIA GENMASK(15, 9)
7831 #define RR_DCK1_TIA GENMASK(15, 9)
7859 #define RR_VCO_SEL GENMASK(9, 8)
7880 #define RR_IQKPLL_MOD GENMASK(9, 8)
7923 #define B_ANAPAR_PW15 GENMASK(31, 24)
7924 #define B_ANAPAR_PW15_H GENMASK(27, 24)
7954 #define B_HTMCS_LMT GENMASK(9, 8)
7958 #define B_RXEHT_N_USER_MAX GENMASK(31, 24)
7972 #define B_UPD_CLK_ADC_ON BIT(24)
7975 #define B_RSTB_ASYNC_BW80 GENMASK(9, 8)
8063 #define B_PD_HIT_DIS BIT(9)
8074 #define B_TXRX_FORCE_VAL GENMASK(9, 0)
8091 #define B_RXHT_MCS_LIMIT GENMASK(9, 8)
8112 #define B_CLK_GCK GENMASK(24, 0)
8115 #define B_ADC_FIFO_EN_V1 GENMASK(31, 24)
8140 #define B_S0_RXDC2_SEL GENMASK(9, 8)
8157 #define B_SWSI_W_BUSY_V1 BIT(24)
8175 #define B_IFS_T4_HIS_MSK GENMASK(31, 24)
8202 #define B_TSSI_THER GENMASK(29, 24)
8207 #define B_TXAGC_BTP GENMASK(31, 24)
8210 #define B_TXAGC_BB GENMASK(31, 24)
8215 #define B_S0_ADDCK_I GENMASK(9, 0)
8218 #define B_TXCKEN_FORCE_ALL GENMASK(24, 0)
8222 #define B_ADC_FIFO_RST GENMASK(31, 24)
8225 #define B_ADC_FIFO_A2 BIT(24)
8311 #define B_S1_RXDC2_SEL GENMASK(9, 8)
8315 #define B_TXAGC_BB_S1 GENMASK(31, 24)
8319 #define B_S1_ADDCK_I GENMASK(9, 0)
8322 #define B_OP1DB_A GENMASK(31, 24)
8331 #define B_BACKOFF_LNA_A GENMASK(29, 24)
8370 #define B_ASSIGN_SBD_OPT_EN BIT(24)
8375 #define B_DCFO_WEIGHT_MSK GENMASK(27, 24)
8378 #define B_TXSHAPE_TRIANGULAR_CFG GENMASK(25, 24)
8385 #define B_LNA6 GENMASK(31, 24)
8394 #define B_BACKOFF_LNA_B GENMASK(29, 24)
8431 #define B_PATH0_LNA_ERR_G1_A_MSK GENMASK(29, 24)
8439 #define B_PATH0_LNA_ERR_G4_G_MSK GENMASK(29, 24)
8444 #define B_PATH0_LNA_ERR_G6_A_MSK GENMASK(29, 24)
8459 #define B_PATH0_RXB_INIT_IDX_MSK GENMASK(9, 5)
8462 #define B_PATH0_LNA_INIT_IDX_MSK GENMASK(26, 24)
8480 #define B_PATH0_G_LNA6_OP1DB_V1 GENMASK(31, 24)
8507 #define B_PATH1_LNA_INIT_IDX_MSK GENMASK(26, 24)
8509 #define B_PATH0_TIA_INIT_IDX_MSK_V1 BIT(9)
8515 #define B_PATH1_RXB_INIT_IDX_MSK GENMASK(9, 5)
8517 #define B_PATH1_G_LNA6_OP1DB_V1 GENMASK(31, 24)
8549 #define B_EDCCA_LVL_MSK3 GENMASK(31, 24)
8581 #define B_P0_RPL1_41_MASK GENMASK(31, 24)
8588 #define B_P0_RTL2_8A_MASK GENMASK(31, 24)
8593 #define B_P0_RTL3_89_MASK GENMASK(31, 24)
8613 #define B_PATH1_TIA_INIT_IDX_MSK_V1 BIT(9)
8628 #define B_PATH0_TX_CFR_LGC0 GENMASK(9, 0)
8685 #define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24)
8695 #define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24)
8703 #define B_P0_TSSI_ALIM13 GENMASK(9, 0)
8705 #define B_P0_TSSI_ALIM31 GENMASK(9, 0)
8725 #define B_DPD_PWR_CW GENMASK(17, 9)
8736 #define B_P0_TMETER_TRK BIT(24)
8738 #define B_P0_ADCFF_EN BIT(24)
8798 #define B_TXGAIN_SCALE_OFT GENMASK(31, 24)
8881 #define B_MGA_AEND GENMASK(31, 24)
8883 #define B_BY_SLOPE GENMASK(31, 24)
8910 #define B_P1_TSSI_ALIM13 GENMASK(9, 0)
8912 #define B_P1_TSSI_ALIM31 GENMASK(9, 0)
8926 #define B_P1_TMETER_TRK BIT(24)
8944 #define B_P1_ADCFF_EN BIT(24)
9011 #define B_DPK_IDL_SEL GENMASK(10, 9)
9039 #define B_DPK_MPA_T1 BIT(9)
9062 #define B_COEF_SEL_MDPD_V1 GENMASK(9, 8)
9095 #define B_DPK_GN_AG GENMASK(9, 0)
9100 #define B_DPD_BND_1 GENMASK(24, 16)
9104 #define B_DPD_ORDER GENMASK(26, 24)
9152 #define B_IQKINF_VER GENMASK(31, 24)
9186 #define B_DACK_S0M0 GENMASK(31, 24)
9189 #define B_DACK_DADCK00 GENMASK(31, 24)
9195 #define B_DACK_S0M1 GENMASK(31, 24)
9198 #define B_DACK_DADCK01 GENMASK(31, 24)
9200 #define B_DRCK_LAT BIT(9)
9203 #define B_DRCK_IDLE BIT(9)
9210 #define B_DRCK_V1_SEL BIT(9)
9239 #define B_ADDCK0 GENMASK(9, 8)
9251 #define B_ADDCKR0_A1 GENMASK(9, 0)
9270 #define B_DACK10S GENMASK(31, 24)
9274 #define B_DACK_DADCK10 GENMASK(31, 24)
9280 #define B_DACK11S GENMASK(31, 24)
9284 #define B_DACK_DADCK11 GENMASK(31, 24)
9297 #define B_ADDCK1 GENMASK(9, 8)
9307 #define B_ADDCKR1_A1 GENMASK(9, 0)
9335 #define B_TSSI_MAP_OFST_OFDM GENMASK(17, 9)
9340 #define B_TXAGC_REF0_CCK_DBM GENMASK(17, 9)