Lines Matching +full:24 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0-only
7 * Tero Kristo (t-kristo@ti.com)
15 #include <dt-bindings/clock/omap4.h>
54 { 24, TI_CLK_DIVIDER, omap4_aess_fclk_parents, &omap4_aess_fclk_data },
59 "abe-clkctrl:0018:26",
73 { 24, TI_CLK_MUX, omap4_func_dmic_abe_gfclk_parents, NULL },
79 "abe-clkctrl:0020:26",
86 { 24, TI_CLK_MUX, omap4_func_mcasp_abe_gfclk_parents, NULL },
92 "abe-clkctrl:0028:26",
99 { 24, TI_CLK_MUX, omap4_func_mcbsp1_gfclk_parents, NULL },
105 "abe-clkctrl:0030:26",
112 { 24, TI_CLK_MUX, omap4_func_mcbsp2_gfclk_parents, NULL },
118 "abe-clkctrl:0038:26",
125 { 24, TI_CLK_MUX, omap4_func_mcbsp3_gfclk_parents, NULL },
152 { 9, TI_CLK_GATE, omap4_slimbus1_fclk_1_parents, NULL },
165 { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
170 { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
175 { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
180 { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
186 { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
188 { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
189 { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe-clkctrl:0020:24" },
190 { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
191 { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
192 { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
193 { OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0040:8" },
194 { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
195 { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
196 { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
197 { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
284 { 24, TI_CLK_DIVIDER, omap4_fdif_fck_parents, &omap4_fdif_fck_data },
290 { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss-clkctrl:0008:24" },
316 { 9, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
323 { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3-dss-clkctrl:0000:8" },
334 { 24, TI_CLK_MUX, omap4_sgx_clk_mux_parents, NULL },
339 { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3-gfx-clkctrl:0000:24" },
350 { 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
355 { 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
370 { 24, TI_CLK_DIVIDER, omap4_hsi_fck_parents, &omap4_hsi_fck_data },
375 "l3-init-clkctrl:0038:24",
380 "l3-init-clkctrl:0038:25",
408 { 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p2_clk_parents, NULL },
415 { 24, TI_CLK_MUX, omap4_utmi_p1_gfclk_parents, NULL },
421 "l3-init-clkctrl:0040:24",
433 { 24, TI_CLK_MUX, omap4_otg_60m_gfclk_parents, NULL },
439 { 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
455 { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0008:24" },
456 { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0010:24" },
457 { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:0018:24" },
462 …{ OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:00c…
473 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
478 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
483 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
488 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
493 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
498 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
533 "l4-per-clkctrl:00c0:26",
545 { 24, TI_CLK_MUX, omap4_per_mcbsp4_gfclk_parents, NULL },
567 { 9, TI_CLK_GATE, omap4_slimbus2_fclk_1_parents, NULL },
573 { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0008:24" },
574 { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0010:24" },
575 { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0018:24" },
576 { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0020:24" },
577 { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0028:24" },
578 { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0030:24" },
591 { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:00c0:24" },
598 { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0118:8" },
625 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
633 { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4-wkup-clkctrl:0020:24" },
647 "emu-sys-clkctrl:0000:22",
657 -1,
665 "emu-sys-clkctrl:0000:20",
677 { 24, TI_CLK_DIVIDER, omap4_trace_clk_div_div_ck_parents, &omap4_trace_clk_div_div_ck_data },
719 DT_CLK(NULL, "aess_fclk", "abe-clkctrl:0008:24"),
720 DT_CLK(NULL, "cm2_dm10_mux", "l4-per-clkctrl:0008:24"),
721 DT_CLK(NULL, "cm2_dm11_mux", "l4-per-clkctrl:0010:24"),
722 DT_CLK(NULL, "cm2_dm2_mux", "l4-per-clkctrl:0018:24"),
723 DT_CLK(NULL, "cm2_dm3_mux", "l4-per-clkctrl:0020:24"),
724 DT_CLK(NULL, "cm2_dm4_mux", "l4-per-clkctrl:0028:24"),
725 DT_CLK(NULL, "cm2_dm9_mux", "l4-per-clkctrl:0030:24"),
726 DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
727 DT_CLK(NULL, "dmt1_clk_mux", "l4-wkup-clkctrl:0020:24"),
728 DT_CLK(NULL, "dss_48mhz_clk", "l3-dss-clkctrl:0000:9"),
729 DT_CLK(NULL, "dss_dss_clk", "l3-dss-clkctrl:0000:8"),
730 DT_CLK(NULL, "dss_sys_clk", "l3-dss-clkctrl:0000:10"),
731 DT_CLK(NULL, "dss_tv_clk", "l3-dss-clkctrl:0000:11"),
732 DT_CLK(NULL, "fdif_fck", "iss-clkctrl:0008:24"),
733 DT_CLK(NULL, "func_dmic_abe_gfclk", "abe-clkctrl:0018:24"),
734 DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe-clkctrl:0020:24"),
735 DT_CLK(NULL, "func_mcbsp1_gfclk", "abe-clkctrl:0028:24"),
736 DT_CLK(NULL, "func_mcbsp2_gfclk", "abe-clkctrl:0030:24"),
737 DT_CLK(NULL, "func_mcbsp3_gfclk", "abe-clkctrl:0038:24"),
738 DT_CLK(NULL, "gpio1_dbclk", "l4-wkup-clkctrl:0018:8"),
739 DT_CLK(NULL, "gpio2_dbclk", "l4-per-clkctrl:0040:8"),
740 DT_CLK(NULL, "gpio3_dbclk", "l4-per-clkctrl:0048:8"),
741 DT_CLK(NULL, "gpio4_dbclk", "l4-per-clkctrl:0050:8"),
742 DT_CLK(NULL, "gpio5_dbclk", "l4-per-clkctrl:0058:8"),
743 DT_CLK(NULL, "gpio6_dbclk", "l4-per-clkctrl:0060:8"),
744 DT_CLK(NULL, "hsi_fck", "l3-init-clkctrl:0018:24"),
745 DT_CLK(NULL, "hsmmc1_fclk", "l3-init-clkctrl:0008:24"),
746 DT_CLK(NULL, "hsmmc2_fclk", "l3-init-clkctrl:0010:24"),
747 DT_CLK(NULL, "iss_ctrlclk", "iss-clkctrl:0000:8"),
748 DT_CLK(NULL, "mcasp_sync_mux_ck", "abe-clkctrl:0020:26"),
749 DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
750 DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
751 DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
752 DT_CLK("40122000.mcbsp", "prcm_fck", "abe-clkctrl:0028:26"),
753 DT_CLK("40124000.mcbsp", "prcm_fck", "abe-clkctrl:0030:26"),
754 DT_CLK("40126000.mcbsp", "prcm_fck", "abe-clkctrl:0038:26"),
755 DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4-per-clkctrl:00c0:26"),
756 DT_CLK("48096000.mcbsp", "prcm_fck", "l4-per-clkctrl:00c0:26"),
757 DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3-init-clkctrl:00c0:8"),
758 DT_CLK(NULL, "otg_60m_gfclk", "l3-init-clkctrl:0040:24"),
760 DT_CLK(NULL, "per_mcbsp4_gfclk", "l4-per-clkctrl:00c0:24"),
761 DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu-sys-clkctrl:0000:20"),
762 DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu-sys-clkctrl:0000:22"),
763 DT_CLK(NULL, "sgx_clk_mux", "l3-gfx-clkctrl:0000:24"),
764 DT_CLK(NULL, "slimbus1_fclk_0", "abe-clkctrl:0040:8"),
765 DT_CLK(NULL, "slimbus1_fclk_1", "abe-clkctrl:0040:9"),
766 DT_CLK(NULL, "slimbus1_fclk_2", "abe-clkctrl:0040:10"),
767 DT_CLK(NULL, "slimbus1_slimbus_clk", "abe-clkctrl:0040:11"),
768 DT_CLK(NULL, "slimbus2_fclk_0", "l4-per-clkctrl:0118:8"),
769 DT_CLK(NULL, "slimbus2_fclk_1", "l4-per-clkctrl:0118:9"),
770 DT_CLK(NULL, "slimbus2_slimbus_clk", "l4-per-clkctrl:0118:10"),
771 DT_CLK(NULL, "stm_clk_div_ck", "emu-sys-clkctrl:0000:27"),
772 DT_CLK(NULL, "timer5_sync_mux", "abe-clkctrl:0048:24"),
773 DT_CLK(NULL, "timer6_sync_mux", "abe-clkctrl:0050:24"),
774 DT_CLK(NULL, "timer7_sync_mux", "abe-clkctrl:0058:24"),
775 DT_CLK(NULL, "timer8_sync_mux", "abe-clkctrl:0060:24"),
776 DT_CLK(NULL, "trace_clk_div_div_ck", "emu-sys-clkctrl:0000:24"),
777 DT_CLK(NULL, "usb_host_hs_func48mclk", "l3-init-clkctrl:0038:15"),
778 DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3-init-clkctrl:0038:13"),
779 DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3-init-clkctrl:0038:14"),
780 DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3-init-clkctrl:0038:11"),
781 DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3-init-clkctrl:0038:12"),
782 DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3-init-clkctrl:0038:8"),
783 DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3-init-clkctrl:0038:9"),
784 DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init-clkctrl:0038:10"),
785 DT_CLK(NULL, "usb_otg_hs_xclk", "l3-init-clkctrl:0040:8"),
786 DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3-init-clkctrl:0048:8"),
787 DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3-init-clkctrl:0048:9"),
788 DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3-init-clkctrl:0048:10"),
789 DT_CLK(NULL, "utmi_p1_gfclk", "l3-init-clkctrl:0038:24"),
790 DT_CLK(NULL, "utmi_p2_gfclk", "l3-init-clkctrl:0038:25"),
815 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power in omap4xxx_dt_clk_init()