Lines Matching +full:24 +full:- +full:9
1 /* SPDX-License-Identifier: ISC */
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
23 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
48 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
68 #define MT_RXD3_NORMAL_PATTERN_DROP BIT(9)
81 #define MT_RXV1_VHTA2_B8_B3 GENMASK(29, 24)
91 #define MT_RXV1_HT_AD_CODE BIT(9)
101 #define MT_RXV3_WB_RSSI GENMASK(31, 24)
104 #define MT_RXV4_RCPI3 GENMASK(31, 24)
111 #define MT_RXV6_NF3 GENMASK(31, 24)
158 #define MT_TXD0_UDP_TCP_SUM BIT(24)
164 #define MT_TXD1_PKT_FMT GENMASK(25, 24)
178 #define MT_TXD2_POWER_OFFSET GENMASK(28, 24)
185 #define MT_TXD2_RTS BIT(9)
206 #define MT_TXD5_TX_STATUS_MCU BIT(9)
220 /* MT7663 DW7 HW-AMSDU */
231 #define MT_TX_RATE_NSS GENMASK(10, 9)
237 #define MT_TXS0_PID GENMASK(31, 24)
259 #define MT_TXS1_TID GENMASK(11, 9)
264 #define MT_TXS2_WCID GENMASK(31, 24)
269 #define MT_TXS3_TX_COUNT GENMASK(28, 24)
278 #define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0)
283 #define MT_TXS6_F1_RCPI_3 GENMASK(31, 24)