Lines Matching +full:24 +full:- +full:9
1 /* SPDX-License-Identifier: GPL-2.0 */
51 * DF3 ComponentIdMask [9:0]
60 #define DF3_COMPONENT_ID_MASK GENMASK(9, 0)
73 * DF3 DstFabricID [9:0]
83 #define DF3_DST_FABRIC_ID GENMASK(9, 0)
122 * DF2 DieIdShift [27:24]
129 #define DF2_DIE_ID_SHIFT GENMASK(27, 24)
183 * DF2 DramHoleBase [31:24]
184 * DF3 DramHoleBase [31:24]
185 * DF3p5 DramHoleBase [31:24]
188 * DF4 DramHoleBase [31:24]
189 * DF4p5 DramHoleBase [31:24]
191 #define DF_DRAM_HOLE_BASE_MASK GENMASK(31, 24)
236 * HashIntlvCtl2M [9]
242 * HashIntlvCtl2M [9]
250 #define DF4_HASH_CTL_2M BIT(9)
269 * DF4 HiAddrOffset [24:1]
270 * DF4p5 HiAddrOffset [24:1]
308 * DF3 IntLvAddrSel [11:9]
309 * DF3p5 IntLvAddrSel [11:9]
318 #define DF3_INTLV_ADDR_SEL GENMASK(11, 9)
338 * DF4p5 IntLvNumChan [9:4]
344 #define DF4p5_INTLV_NUM_CHAN GENMASK(9, 4)
427 * D18F2x90 [Non-power-of-2 channel Configuration Register for COH_ST DRAM Address Maps]
449 * DF4 MajorRevision [27:24]
450 * DF4p5 MajorRevision [27:24]
452 #define DF_MAJOR_REVISION GENMASK(27, 24)
570 * DF3 SocketIdMask [26:24]
580 #define DF3_SOCKET_ID_MASK GENMASK(26, 24)
595 * DF3 SocketIdShift [9:8]
605 #define DF3_SOCKET_ID_SHIFT GENMASK(9, 8)