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/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmedia5200.dts28 PowerPC,5200@0 {
35 memory@0 {
36 reg = <0x00000000 0x08000000>; // 128MB RAM
72 phy0: ethernet-phy@0 {
73 reg = <0>;
78 reg = <0x1000 0x100>;
83 interrupt-map-mask = <0xf800 0 0 7>;
84 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
85 0xc000 0 0 2 &media5200_fpga 0 3
86 0xc000 0 0 3 &media5200_fpga 0 4
[all …]
/freebsd/sys/contrib/device-tree/Bindings/watchdog/
H A Darmada-37xx-wdt.txt15 reg = <0xd000 0x1000>;
20 reg = <0x8300 0x40>;
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dqcom,sm8250-camss.yaml113 port@0:
308 reg = <0 0xac6a000 0 0x2000>,
309 <0 0xac6c000 0 0x2000>,
310 <0 0xac6e000 0 0x1000>,
311 <0 0xac70000 0 0x1000>,
312 <0 0xac72000 0 0x1000>,
313 <0 0xac74000 0 0x1000>,
314 <0 0xacb4000 0 0xd000>,
315 <0 0xacc3000 0 0xd000>,
316 <0 0xacd9000 0 0x2200>,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,postmask.yaml77 reg = <0 0x1400d000 0 0x1000>;
78 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
81 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dsyna.txt57 reg = <0xf7dd0000 0x10000>;
91 reg = <0xea0000 0x400>;
98 reg = <0xd000 0x100>;
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dinterlaken-lac-portals.dtsi34 #address-cells = <0x1>;
35 #size-cells = <0x1>;
38 lportal0: lac-portal@0 {
39 compatible = "fsl,interlaken-lac-portal-v1.0";
40 reg = <0x0 0x1000>;
44 compatible = "fsl,interlaken-lac-portal-v1.0";
45 reg = <0x1000 0x1000>;
49 compatible = "fsl,interlaken-lac-portal-v1.0";
50 reg = <0x2000 0x1000>;
54 compatible = "fsl,interlaken-lac-portal-v1.0";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm53573.dtsi26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x0>;
37 ranges = <0x00000000 0x18310000 0x00008000>;
44 #address-cells = <0>;
46 reg = <0x1000 0x1000>,
47 <0x200
[all...]
/freebsd/sys/dts/arm/
H A Dzynq-7000.dtsi36 memreserve = <0x00000000 0x00080000>;
45 ranges = <0x0 0xf8000000 0xf10000>;
50 reg = <0x0 0x1000>;
57 #address-cells = <0>;
59 reg = <0xf01000 0x1000>, // distributer registers
60 <0xf00100 0x0100>; // CPU if registers
66 reg = <0xf02000 0x1000>;
67 interrupts = <0 2 4>;
74 reg = <0x7000 0x1000>;
75 interrupts = <0 8 4>;
[all …]
/freebsd/sys/dev/ice/
H A Dice_protocol_type.h41 * e.g. recipes 0, 1, 2, and 3 can provide intermediate results to recipe 4.
58 ICE_MAC_OFOS = 0,
83 ICE_NON_TUN = 0,
107 ICE_PROT_ID_INVAL = 0,
181 #define ICE_TUN_FLAG_MASK 0xFF
182 #define ICE_FROM_NETWORK_FLAG_MASK 0x8
183 #define ICE_DIR_FLAG_MASK 0x10
184 #define ICE_TUN_FLAG_IN_VLAN_MASK 0x80 /* VLAN inside tunneled header */
185 #define ICE_TUN_FLAG_VLAN_MASK 0x01
190 #define ICE_PKT_FLAGS_0_TO_15_VLAN_FLAGS_MASK 0xD00
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/synaptics/
H A Dberlin4ct.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0x0>;
41 reg = <0x1>;
50 reg = <0x2>;
59 reg = <0x3>;
73 CPU_SLEEP_0: cpu-sleep-0 {
76 arm,psci-suspend-param = <0x0010000>;
86 #clock-cells = <0>;
114 ranges = <0 0 0xf7000000 0x1000000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dinterlaken-lac.txt31 There is a full register set at 0x0000-0x0FFF (also known as the "hypervisor"
32 version), and a subset at 0x1000-0x1FFF. The former is a superset of the
45 IP Block Revision Register (IPBRR0) at offset 0x0BF8.
51 0x02000100 T4240
78 reg = <0x229000 0x1000>;
84 reg = <0x228000 0x1000>;
136 Register (IPBRR0), at offset 0x0BF8, and Y is the Minor version
161 #address-cells = <0x1>;
162 #size-cells = <0x1>;
164 ranges = <0x0 0xf 0xf4400000 0x20000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/bcm4908/
H A Dbcm4908.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
31 reg = <0x0>;
33 cpu-release-addr = <0x0 0xfff8>;
40 reg = <0x1>;
42 cpu-release-addr = <0x0 0xfff8>;
49 reg = <0x2>;
51 cpu-release-addr = <0x0 0xfff8>;
58 reg = <0x3>;
60 cpu-release-addr = <0x0 0xfff8>;
[all …]
/freebsd/sys/dev/usb/net/
H A Dif_urereg.h30 #define URE_CONFIG_IDX 0 /* config number 1 */
31 #define URE_IFACE_IDX 0
33 #define URE_CTL_READ 0x01
34 #define URE_CTL_WRITE 0x02
39 #define URE_BYTE_EN_DWORD 0xff
40 #define URE_BYTE_EN_WORD 0x33
41 #define URE_BYTE_EN_BYTE 0x11
42 #define URE_BYTE_EN_SIX_BYTES 0x3f
49 #define URE_PLA_IDR 0xc000
50 #define URE_PLA_RCR 0xc010
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-37xx.dtsi35 reg = <0 0x4000000 0 0x200000>;
40 reg = <0 0x4400000 0 0x1000000>;
47 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0>;
85 /* 32M internal register @ 0xd000_0000 */
86 ranges = <0x0 0x0 0xd0000000 0x2000000>;
90 reg = <0x8300 0x40>;
98 reg = <0xd000 0x1000>;
104 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/bcmbca/
H A Dbcm4908.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
31 reg = <0x0>;
33 cpu-release-addr = <0x0 0xfff8>;
40 reg = <0x1>;
42 cpu-release-addr = <0x0 0xfff8>;
49 reg = <0x2>;
51 cpu-release-addr = <0x
[all...]
/freebsd/sys/contrib/device-tree/src/arm/synaptics/
H A Dberlin2.dtsi28 #size-cells = <0>;
31 cpu@0 {
35 reg = <0>;
68 #clock-cells = <0>;
78 ranges = <0 0xf7000000 0x1000000>;
82 reg = <0xab0000 0x200>;
91 reg = <0xab0800 0x200>;
100 reg = <0xab1000 0x200>;
104 pinctrl-0 = <&emmc_pmux>;
111 reg = <0xac0000 0x1000>;
[all …]
H A Dberlin2cd.dtsi27 #size-cells = <0>;
29 cpu: cpu@0 {
33 reg = <0>;
53 #clock-cells = <0>;
63 ranges = <0 0xf7000000 0x1000000>;
67 reg = <0xab0000 0x200>;
76 reg = <0xac0000 0x1000>;
83 reg = <0xad0000 0x100>;
88 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
95 reg = <0xad0200 0x20>;
[all …]
H A Dberlin2q.dtsi22 #size-cells = <0>;
25 cpu0: cpu@0 {
29 reg = <0>;
113 #clock-cells = <0>;
122 ranges = <0 0xf7000000 0x1000000>;
127 reg = <0xab0000 0x200>;
136 reg = <0xab0800 0x200>;
145 reg = <0xab1000 0x200>;
154 reg = <0xac0000 0x1000>;
163 reg = <0xad0000 0x58>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-39x.dtsi32 #size-cells = <0>;
35 cpu@0 {
38 reg = <0>;
59 pcie-mem-aperture = <0xe0000000 0x8000000>;
60 pcie-io-aperture = <0xe8000000 0x100000>;
64 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
75 reg = <0x8000 0x1000>;
78 arm,double-linefill-incr = <0>;
79 arm,double-linefill-wrap = <0>;
[all …]
H A Darmada-375.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
80 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
85 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
86 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
[all …]
H A Darmada-38x.dtsi42 pcie-mem-aperture = <0xe0000000 0x8000000>;
43 pcie-io-aperture = <0xe8000000 0x100000>;
47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
66 clocks = <&coreclk 0>;
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300eep.h33 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
34 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
35 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
36 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
37 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
39 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
40 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
51 _compress_none = 0,
64 calibration_data_none = 0,
79 // Yes, the first one is 2. Do not use 0 or 1.
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
144 unsigned addr = 0; in decodeFIOARr()
145 addr |= fieldFromInstruction(Insn, 0, 4); in decodeFIOARr()
157 unsigned addr = 0; in decodeFIORdA()
158 addr |= fieldFromInstruction(Insn, 0, 4); in decodeFIORdA()
171 unsigned b = fieldFromInstruction(Insn, 0, 3); in decodeFIOBIT()
207 unsigned r = fieldFromInstruction(Insn, 0, 3) + 16; in decodeFFMULRdRr()
221 unsigned d = fieldFromInstruction(Insn, 0, 4) * 2; in decodeFMOVWRdRr()
234 unsigned k = 0; in decodeFWRdK()
235 k |= fieldFromInstruction(Insn, 0, 4); in decodeFWRdK()
[all …]
/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DARM.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
52 enum class CodeState { Data = 0, Thumb = 2, Arm = 4 };
55 static DenseMap<InputSection *, SmallVector<const Defined *, 0>> sectionMap{};
70 trapInstr = {0xd4, 0xd4, 0xd4, 0xd4}; in ARM()
78 uint32_t abiFloatType = 0; in calcEFlags()
82 uint32_t armBE8 = 0; in calcEFlags()
218 write32(buf + 0, 0xe52de004); // str lr, [sp,#-4]! in writePltHeaderLong()
219 write32(buf + 4, 0xe59fe004); // ldr lr, L2 in writePltHeaderLong()
220 write32(buf + 8, 0xe08fe00e); // L1: add lr, pc, lr in writePltHeaderLong()
221 write32(buf + 12, 0xe5bef008); // ldr pc, [lr, #8] in writePltHeaderLong()
[all …]
/freebsd/sys/dev/bxe/
H A D57712_int_offsets.h31 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_SIZE
32 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_DATA_SIZE
33 { 0x28, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_SIZE
34 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_DATA_SIZE
35 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_DYNAMIC_HC_CONFIG_SIZE
36 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_MSG_SIZE
37 { 0x8, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_INDEX_SIZE
38 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_INVALID_ASSERT_OPCODE
39 { 0x3d, 0x0, 0x0, 0x0, 0x0}, // COMMON_RAM1_TEST_EVENT_ID
40 …{ 0x3c, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_EVEN…
[all …]

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