Lines Matching +full:0 +full:xd000
33 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
34 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
35 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
36 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
37 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
39 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
40 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
51 _compress_none = 0,
64 calibration_data_none = 0,
79 // Yes, the first one is 2. Do not use 0 or 1.
102 #define reference_current 0
106 #define OSPREY_EEP_VER 0xD000
107 #define OSPREY_EEP_VER_MINOR_MASK 0xFFF
108 #define OSPREY_EEP_MINOR_VER_1 0x1
123 #define OSPREY_CTL_MODE_M 0xF
133 #define OSPREY_BCHAN_UNUSED 0xFF
135 #define OSPREY_OPFLAGS_11A 0x01
136 #define OSPREY_OPFLAGS_11G 0x02
137 #define OSPREY_OPFLAGS_5G_HT40 0x04
138 #define OSPREY_OPFLAGS_2G_HT40 0x08
139 #define OSPREY_OPFLAGS_5G_HT20 0x10
140 #define OSPREY_OPFLAGS_2G_HT20 0x20
141 #define OSPREY_EEPMISC_BIG_ENDIAN 0x01
142 #define OSPREY_EEPMISC_WOW 0x02
157 #define OSPREY_ANT_CHAIN_MASK 0x7
158 #define OSPREY_ANT_COMMON_MASK 0xf
159 #define OSPREY_CHAIN_0_IDX 0
169 #define AR928X_ANT_CHAIN_MASK 0x3
178 #define OSPREY_PWR_TABLE_OFFSET 0
181 #define ENABLE_TEMP_COMPENSATION 0x01
182 #define ENABLE_VOLT_COMPENSATION 0x02
184 #define FLASH_BASE_CALDATA_OFFSET 0x1000
212 0,1,1,1,2,
213 3,4,5,0,1,
215 9,0,1,1,1,
254 //bit5 - enable paprd - default to 0
255 //bit6 - enable TuningCaps - default to 0
256 //bit7 - enable tx_frame_to_xpa_on - default to 0
258 …// bit 1:2 - 0=don't force, 1=force to thermometer 0, 2=force to thermometer 1, 3=force to thermom…
259 // bit 3 - reduce chain mask from 0x7 to 0x3 on 2 stream rates
284 …t8_t xatten1_db_low[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0)
285 …u_int8_t xatten1_margin_low[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa2…
286 …8_t xatten1_db_high[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0)
287 …tten1_margin_high[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12
301 …u_int8_t xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0)
302 …u_int8_t xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c…
323 u_int8_t xLNA_bias_strength; // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2
418 #define AR9300_EEPROM_MAGIC 0x5aa5
419 #define SWAP16(_x) ( (u_int16_t)( (((const u_int8_t *)(&_x))[0] ) |\
423 (((const u_int8_t *)(&_x))[0]) | \
430 #define AR9300_EEPROM_MAGIC 0xa55a
432 ( ( (const u_int8_t *)( &_x ) )[0]<< 8) ) )
438 (((const u_int8_t *)(&_x))[0]<<24)))
444 #define AR_GPIO_IN_OUT 0x4048 // GPIO input / output register
445 #define OTP_MEM_START_ADDRESS 0x14000
446 #define OTP_STATUS0_OTP_SM_BUSY 0x00015f18
447 #define OTP_STATUS1_EFUSE_READ_DATA 0x00015f1c
449 #define OTP_LDO_CONTROL_ENABLE 0x00015f24
450 #define OTP_LDO_STATUS_POWER_ON 0x00015f2c
451 #define OTP_INTF0_EFUSE_WR_ENABLE_REG_V 0x00015f00
453 #define GLB_OTP_LDO_CONTROL_ENABLE 0x00020020
454 #define GLB_OTP_LDO_STATUS_POWER_ON 0x00020028
455 #define OTP_PGENB_SETUP_HOLD_TIME_DELAY 0x15f34
458 #define BTOTP_MEM_START_ADDRESS 0x64000
459 #define BTOTP_STATUS0_OTP_SM_BUSY 0x00065f18
460 #define BTOTP_STATUS1_EFUSE_READ_DATA 0x00065f1c
461 #define BTOTP_INTF0_EFUSE_WR_ENABLE_REG_V 0x00065f00
462 #define BTOTP_INTF2 0x00065f08
463 #define BTOTP_PGENB_SETUP_HOLD_TIME_DELAY 0x65f34
464 #define BT_RESET_CTL 0x44000
465 #define BT_CLOCK_CONTROL 0x44028
469 #define OTP_MEM_START_ADDRESS_WASP 0x00030000
470 #define OTP_STATUS0_OTP_SM_BUSY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1018)
471 #define OTP_STATUS1_EFUSE_READ_DATA_WASP (OTP_MEM_START_ADDRESS_WASP + 0x101C)
472 #define OTP_LDO_CONTROL_ENABLE_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1024)
473 #define OTP_LDO_STATUS_POWER_ON_WASP (OTP_MEM_START_ADDRESS_WASP + 0x102C)
474 #define OTP_INTF0_EFUSE_WR_ENABLE_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1000)
476 #define OTP_PG_STROBE_PW_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1008)
477 #define OTP_RD_STROBE_PW_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x100C)
478 #define OTP_VDDQ_HOLD_TIME_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1030)
479 #define OTP_PGENB_SETUP_HOLD_TIME_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1034)
480 #define OTP_STROBE_PULSE_INTERVAL_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1038)
481 #define OTP_CSB_ADDR_LOAD_SETUP_HOLD_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x103C)
483 #define AR9300_EEPROM_MAGIC_OFFSET 0x0
486 #define AR9300_EEPROM_OFFSET 0x2000
488 #define AR9300_EEPROM_START_ADDR 0x1fff1000
490 #define AR9300_EEPROM_START_ADDR 0x503f1200
492 #define AR9300_FLASH_CAL_START_OFFSET 0x1000
493 #define AR9300_EEPROM_MAX 0xae0
500 #define EEP_RFSILENT_ENABLED 0x0001 /* bit 0: enabled/disabled */
501 #define EEP_RFSILENT_ENABLED_S 0 /* bit 0: enabled/disabled */
502 #define EEP_RFSILENT_POLARITY 0x0002 /* bit 1: polarity */
504 #define EEP_RFSILENT_GPIO_SEL 0x00fc /* bits 2..7: gpio PIN */
506 #define AR9300_EEP_VER 0xE
507 #define AR9300_BCHAN_UNUSED 0xFF
511 CALDATA_AUTO=0,
554 #define AR9300_RATES_OFDM_OFFSET 0
609 * Reserved value 0xFF provides an empty definition both as in fbin2freq()
694 ar9300_noise_floor_cal_or_power_get(ah, frequency, ichain, 0/*use_cal*/)