Lines Matching +full:0 +full:xd000
36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
80 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
85 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
86 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
89 clocks = <&coreclk 0>;
95 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
96 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
99 clocks = <&coreclk 0>;
105 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
106 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
109 clocks = <&coreclk 0>;
115 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
116 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
119 clocks = <&coreclk 0>;
125 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
126 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
129 clocks = <&coreclk 0>;
137 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
141 reg = <0x8000 0x1000>;
144 arm,double-linefill-incr = <0>;
145 arm,double-linefill-wrap = <0>;
146 arm,double-linefill = <0>;
152 reg = <0xc000 0x58>;
157 reg = <0xc600 0x20>;
165 #size-cells = <0>;
167 reg = <0xd000 0x1000>,
168 <0xc100 0x100>;
173 #size-cells = <0>;
175 reg = <0xc0054 0x4>;
182 #size-cells = <0>;
184 reg = <0xf0000 0xa000>, /* Packet Processor regs */
185 <0xc0000 0x3060>, /* LMS regs */
186 <0xc4000 0x100>, /* eth0 regs */
187 <0xc5000 0x100>; /* eth1 regs */
192 eth0: ethernet-port@0 {
194 reg = <0>;
195 port-id = <0>; /* For backward compatibility. */
209 reg = <0x10300 0x20>;
216 reg = <0x10600 0x50>;
218 #size-cells = <0>;
219 cell-index = <0>;
221 clocks = <&coreclk 0>;
228 reg = <0x10680 0x50>;
230 #size-cells = <0>;
233 clocks = <&coreclk 0>;
239 reg = <0x11000 0x20>;
241 #size-cells = <0>;
243 clocks = <&coreclk 0>;
249 reg = <0x11100 0x20>;
251 #size-cells = <0>;
253 clocks = <&coreclk 0>;
259 reg = <0x12000 0x100>;
263 clocks = <&coreclk 0>;
269 reg = <0x12100 0x100>;
273 clocks = <&coreclk 0>;
279 reg = <0x18000 0x24>;
315 reg = <0x18100 0x40>;
329 reg = <0x18140 0x40>;
343 reg = <0x18180 0x40>;
354 reg = <0x18200 0x100>;
359 reg = <0x18220 0x4>;
360 clocks = <&coreclk 0>;
366 reg = <0x18400 0x4>;
372 reg = <0x20000 0x100>, <0x20180 0x20>;
377 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
387 reg = <0x20300 0x30>, <0x21040 0x30>;
394 clocks = <&coreclk 0>, <&refclk>;
400 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
401 clocks = <&coreclk 0>, <&refclk>;
407 reg = <0x20800 0x10>;
412 reg = <0x21010 0x1c>;
417 reg = <0x50000 0x500>;
427 reg = <0x54000 0x500>;
435 reg = <0x58000 0x20000>,<0x5b880 0x80>;
445 reg = <0x60800 0x100
446 0x60A00 0x100>;
465 reg = <0x60900 0x100
466 0x60b00 0x100>;
485 reg = <0x90000 0x10000>;
495 marvell,crypto-sram-size = <0x800>;
500 reg = <0xa0000 0x5000>;
503 clock-names = "0", "1";
509 reg = <0xd0000 0x54>;
511 #size-cells = <0>;
519 reg = <0xd4000 0x200>;
531 reg = <0xe8078 0x4>, <0xe807c 0x8>;
537 reg = <0xe8204 0x04>;
543 reg = <0xe8250 0xc>;
559 bus-range = <0x00 0xff>;
562 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
563 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
564 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
565 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
566 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
567 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
569 pcie0: pcie@1,0 {
571 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
572 reg = <0x0800 0 0 0 0>;
578 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
579 0x81000000 0 0 0x81000000 0x1 0 1 0>;
580 bus-range = <0x00 0xff>;
581 interrupt-map-mask = <0 0 0 7>;
582 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
583 <0 0 0 2 &pcie0_intc 1>,
584 <0 0 0 3 &pcie0_intc 2>,
585 <0 0 0 4 &pcie0_intc 3>;
586 marvell,pcie-port = <0>;
587 marvell,pcie-lane = <0>;
597 pcie1: pcie@2,0 {
599 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
600 reg = <0x1000 0 0 0 0>;
606 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
607 0x81000000 0 0 0x81000000 0x2 0 1 0>;
608 bus-range = <0x00 0xff>;
609 interrupt-map-mask = <0 0 0 7>;
610 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
611 <0 0 0 2 &pcie1_intc 1>,
612 <0 0 0 3 &pcie1_intc 2>,
613 <0 0 0 4 &pcie1_intc 3>;
614 marvell,pcie-port = <0>;
629 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
633 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
638 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
642 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;