3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
144   unsigned addr = 0;  in decodeFIOARr()
145   addr |= fieldFromInstruction(Insn, 0, 4);  in decodeFIOARr()
157   unsigned addr = 0;  in decodeFIORdA()
158   addr |= fieldFromInstruction(Insn, 0, 4);  in decodeFIORdA()
171   unsigned b = fieldFromInstruction(Insn, 0, 3);  in decodeFIOBIT()
207   unsigned r = fieldFromInstruction(Insn, 0, 3) + 16;  in decodeFFMULRdRr()
221   unsigned d = fieldFromInstruction(Insn, 0, 4) * 2;  in decodeFMOVWRdRr()
234   unsigned k = 0;  in decodeFWRdK()
235   k |= fieldFromInstruction(Insn, 0, 4);  in decodeFWRdK()
251   unsigned rr = fieldFromInstruction(Insn, 0, 4) + 16;  in decodeFMUL2RdRr()
264   // address is encoded into 7-bit, in which bits 0-5 are the immediate offset,  in decodeMemri()
265   // and the bit-6 is the pointer register bit (Z=0, Y=1).  in decodeMemri()
271       MCOperand::createReg((Insn & 0x40) ? AVR::R29R28 : AVR::R31R30));  in decodeMemri()
273   Inst.addOperand(MCOperand::createImm(Insn & 0x3f));  in decodeMemri()
281   switch (Insn & 0xf000) {  in decodeFBRk()
282   case 0xc000:  in decodeFBRk()
285   case 0xd000:  in decodeFBRk()
292   int16_t Offset = ((int16_t)((Insn & 0xfff) << 4)) >> 3;  in decodeFBRk()
302       {0x000, AVR::BRLOk}, {0x400, AVR::BRSHk}, {0x001, AVR::BREQk},  in decodeCondBranch()
303       {0x401, AVR::BRNEk}, {0x002, AVR::BRMIk}, {0x402, AVR::BRPLk},  in decodeCondBranch()
304       {0x004, AVR::BRLTk}, {0x404, AVR::BRGEk}};  in decodeCondBranch()
307   int16_t Offset = ((int16_t)((Insn & 0x3f8) << 6)) >> 8;  in decodeCondBranch()
311     return (Insn & 0x407) != I.first;  in decodeCondBranch()
323     Inst.setOpcode(Insn & 0x400 ? AVR::BRBCsk : AVR::BRBSsk);  in decodeCondBranch()
335   unsigned RegVal = GPRDecoderTable[(Insn >> 4) & 0x1f];  in decodeLoadStore()
338   if ((Insn & 0xf000) == 0x8000) {  in decodeLoadStore()
339     unsigned RegBase = (Insn & 0x8) ? AVR::R29R28 : AVR::R31R30;  in decodeLoadStore()
341     if ((Insn & 0x200) == 0) {  // Decode LDD.  in decodeLoadStore()
355   // Decode the following 14 instructions. Bit 9 indicates load(0) or store(1),  in decodeLoadStore()
357   // register (11-X, 10-Y, 00-Z), bits 1~0 indicate the mode (00-basic,  in decodeLoadStore()
373   if ((Insn & 0xfc00) != 0x9000 || (Insn & 0xf) == 0)  in decodeLoadStore()
378   switch (Insn & 0xc) {  in decodeLoadStore()
379   case 0xc:  in decodeLoadStore()
382   case 0x8:  in decodeLoadStore()
385   case 0x0:  in decodeLoadStore()
393   switch (Insn & 0x203) {  in decodeLoadStore()
394   case 0x200:  in decodeLoadStore()
399   case 0x201:  in decodeLoadStore()
402   case 0x202:  in decodeLoadStore()
405   case 0:  in decodeLoadStore()
421   if ((Insn & 0x200) == 0) { // This is a load instruction.  in decodeLoadStore()
439     Size = 0;  in readInstruction16()
444   Insn = (Bytes[0] << 0) | (Bytes[1] << 8);  in readInstruction16()
453     Size = 0;  in readInstruction32()
459       (Bytes[0] << 16) | (Bytes[1] << 24) | (Bytes[2] << 0) | (Bytes[3] << 8);  in readInstruction32()